half adder is a type of adder, an electronic circuit that performs the addition of numbers.

The half adder

is able to add two single binary digits and provide the output plus a carry value. It has two inputs, called
A and B, and two outputs S (sum) and C (carry). The common representation uses a XOR logic gate and
an AND logic gate.

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Techopedia explains Half Adder

A half adder is used to add two single-digit binary numbers and results into a two-digit output. It is
named as such because putting two half adders together with the use of an OR gate results in a full
adder. In other words, it only does half the work of a full adder.

The adder works by combining the operations of basic logic gates, with the simplest form using only a
XOR and an AND gate. This can also be converted into a circuit that only has AND, OR and NOT gates. This
is especially useful since these three simpler logic gate ICs (integrated circuits) are more common and
available than the XOR IC, though this might result in a bigger circuit since three different chips are used
instead of just one.

Half Adder truth table:

A (input) B (input) C (output) S (output)

0 0 0 0

1 0 0 1

0 1 0 1

1 1 1 0
What is an Adder?

An adder is a kind of calculator that is used to add two binary numbers. When I say, calculator, I don’t
mean one with buttons, this one is a circuit that can be integrated with many other circuits for a wide
range of applications. There are two kinds of adders;

Half adder

Full adder

Half Adder

With the help of half adder, we can design circuits that are capable of performing simple addition with
the help of logic gates.

Let us first take a look at the addition of single bits.

0+0 = 0

0+1 = 1

1+0 = 1

1+1 = 10

These are the least possible single-bit combinations. But the result for 1+1 is 10. Though this problem
can be solved with the help of an EXOR Gate, if you do care about the output, the sum result must be re-
written as a 2-bit output.

Thus the above equations can be written as

0+0 = 00

0+1 = 01

1+0 = 01

1+1 = 10

Here the output ‘1’of ‘10’ becomes the carry-out. The result is shown in a truth-table below. ‘SUM’ is the
normal output and ‘CARRY’ is the carry-out.

INPUTS OUTPUTS

A B SUM CARRY

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

From the equation, it is clear that this 1-bit adder can be easily implemented with the help of EXOR Gate
for the output ‘SUM’ and an AND Gate for the carry. Take a look at the implementation below.
For complex addition, there may be cases when you have to add two 8-bit bytes together. This can be
done only with the help of full-adder logic.

Full Adder

This type of adder is a little more difficult to implement than a half-adder. The main difference between a
half-adder and a full-adder is that the full-adder has three inputs and two outputs. The first two inputs
are A and B and the third input is an input carry designated as CIN. When a full adder logic is designed
we will be able to string eight of them together to create a byte-wide adder and cascade the carry bit
from one adder to the next.

The output carry is designated as COUT and the normal output is designated as S. Take a look at the
truth-table.

INPUTS OUTPUTS

A B CIN COUT S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1
1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

From the above truth-table, the full adder logic can be implemented. We can see that the output S is an
EXOR between the input A and the half-adder SUM output with B and CIN inputs. We must also note
that the COUT will only be true if any of the two inputs out of the three are HIGH.

Thus, we can implement a full adder circuit with the help of two half adder circuits. The first will half
adder will be used to add A and B to produce a partial Sum. The second half adder logic can be used to
add CIN to the Sum produced by the first half adder to get the final S output. If any of the half adder
logic produces a carry, there will be an output carry. Thus, COUT will be an OR function of the half-adder
Carry outputs. Take a look at the implementation of the full adder circuit
shown below.

Though the implementation of larger logic diagrams is possible with the

above full adder logic a simpler symbol is mostly used to represent the
operation. Given below is a simpler schematic representation of a one-
bit full adder.
With this type of symbol, we can add two bits together taking a carry from the
next lower order of magnitude, and sending a carry to the next higher order
of magnitude. In a computer, for a multi-bit operation, each bit must be
represented by a full adder and must be added simultaneously. Thus,
to add two 8-bit numbers, you will need 8 full adders which can be formed by
cascading two of the 4-bit blocks. The addition of two 4-bit numbers is shown
below.

Decimal Adder / BCD Adder:

Decimal Adder – The digital systems handles the decimal number in

the form of binary coded decimal numbers (BCD). A BCD adder is a
circuit that adds two BCD digits and produces a sum digit also in BCD. BCD numbers use 10 digits, 0 to 9
which are represented in the binary form 0 0 0 0 to 1 0 0 1, i.e. each BCD digit is represented as a 4-bit
binary number. When we write BCD number say 526, it can be represented as

Here, we should note that BCD cannot be greater than 9

The addition of two BCD numbers can be best understood by considering the three cases that occur
when two BCD digits are added.

Sum Equals 9 or less with carry 0. Let us consider additions of 3 and 6 in BCD.
The addition is carried out as in normal binary addition and the sum is 1 0 0 1,

which is BCD code for 9.

Sum greater than 9 with carry 0

The sum 1 1 1 0 is an invalid BCD number. This has occurred because the sum of the two digits exceeds 9.
Whenever this occurs the sum has to be corrected by the addition of six (0110) in the invalid BCD
number, as shown below

After addition of 6 carry is produced into the second decimal position.

Sum equals 9 or less with carry 1

Let us consider addition of 8 and 9 in BCD

In this, case, result (0001 0001) is valid BCD number, but it is incorrect. To get the correct BCD result
correction factor of 6 has to be added to the least significant digit sum, as shown below
Going through these three cases of BCD addition we can summarise the BCD addition procedure as
follows :

Add two BCD numbers using ordina7 binary addition.

If four-bit sum is equal to or less than 9, no correction is needed. The sum is in proper BCD form.

If the four-bit sum is greater than 9 or if a carry is generated from the four-bit sum, the sum is invalid.

To correct the invalid sum, add 01102 to the four-bit sum. If a carry results from this addition, add it to
the next higher-order BCD digit.

Thus to implement BCD adder we require :

4-bit binary adder for initial addition

Logic circuit to detect sum greater than 9 and

One more 4-bit adder to add 01102 in the sum if sum is greater than 9 or carry is 1.

Another common and very useful combinational logic circuit which can be constructed using just a few
basic logic gates allowing it to add together two or more binary numbers is the Binary Adder.

A basic Binary Adder circuit can be made from standard AND and Ex-OR gates allowing us to “add”
together two single bit binary numbers, A and B.

The addition of these two digits produces an output called the SUM of the addition and a second output
called the CARRY or Carry-out, ( COUT ) bit according to the rules for binary addition. One of the main
uses for the Binary Adder is in arithmetic and counting circuits. Consider the simple addition of the two
denary (base 10) numbers below.

123 A (Augend)

+ 789 B (Addend)

912 SUM
From our maths lessons at school, we learnt that each number column is added together starting from
the right hand side and that each digit has a weighted value depending upon its position within the
columns.

When each column is added together a carry is generated if the result is greater or equal to 10, the base
number. This carry is then added to the result of the addition of the next column to the left and so on,
simple school math’s addition, add the numbers and carry.

The adding of binary numbers is exactly the same idea as that for adding together decimal numbers but
this time a carry is only generated when the result in any column is greater or equal to “2”, the base
number of binary. In other words 1 + 1 creates a carry.

Binary Addition

Binary Addition follows these same basic rules as for the denary addition above except in binary there
are only two digits with the largest digit being “1”. So when adding binary numbers, a carry out is
generated when the “SUM” equals or is greater than two (1+1) and this becomes a “CARRY” bit for any
subsequent addition being passed over to the next column for addition and so on. Consider the single bit
addition below.

Binary Addition of Two Bits

0 0 1 1

+0 +1 +0 +1

0 1 1 (carry) 1←0

When the two single bits, A and B are added together, the addition of “0 + 0”, “0 + 1” and “1 + 0” results
in either a “0” or a “1” until you get to the final column of “1 + 1” then the sum is equal to “2”. But the
number two does not exists in binary however, 2 in binary is equal to 10, in other words a zero for the
sum plus an extra carry bit.

Then the operation of a simple adder requires two data inputs producing two outputs, the Sum (S) of the
equation and a Carry (C) bit as shown.
Binary Adder Block Diagram

For the simple 1-bit addition problem above, the resulting carry bit could be ignored but you may have
noticed something else with regards to the addition of these two bits, the sum of their binary addition
resembles that of an Exclusive-OR Gate. If we label the two bits as A and B then the resulting truth table
is the sum of the two bits but without the final carry.

2-input Exclusive-OR Gate

Symbol Truth Table

2-input exclusive-or gate

2-input Ex-OR Gate

B A S

0 0 0

0 1 1

1 0 1

1 1 0

We can see from the truth table above, that an Exclusive-OR gate only produces an output “1” when
either input is at logic “1”, but not
both the same as for the binary
addition of the previous two bits.
However in order to perform the
addition of two numbers,
microprocessors and electronic
calculators require the extra carry bit to correctly calculate the equations so we need to rewrite the
previous summation to include two-bits of output data as shown below.
00 00 01 01

+ 00 + 01 + 00 + 01

00 01 01 10

From the above equations we now know that an Exclusive-OR gate will only produce an output “1” when
“EITHER” input is at logic “1”, so we need an additional output to produce the carry bit when “BOTH”
inputs A and B are at logic “1”. One digital gate that fits the bill perfectly producing an output “1” when
both of its inputs A and B are “1” (HIGH) is the standard AND Gate.

2-input AND Gate

Symbol Truth Table

2-input AND gate

2-input AND Gate

B A C

0 0 0

0 1 0

1 0 0

1 1 1

By combining the Exclusive-OR gate with the AND gate results in a simple digital binary adder circuit
known commonly as the “Half Adder” circuit.

A Half Adder Circuit

A half adder is a logical circuit that performs an addition operation on two binary digits. The half adder
produces a sum and a carry value which are both binary digits.

Half Adder Truth Table with Carry-Out

Symbol Truth Table

half adder B A SUM CARRY

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

From the truth table of the half adder we can see that the SUM (S) output is the result of the Exclusive-
OR gate and the Carry-out (Cout) is the result of the AND gate. Then the Boolean expression for a half
adder is as follows.

For the SUM bit:

SUM = A XOR B = A ⊕ B

For the CARRY bit:

CARRY = A AND B = A.B

One major disadvantage of the Half Adder circuit when used as a binary adder, is that there is no
provision for a “Carry-in” from the previous circuit when adding together multiple data bits.

For example, suppose we want to add together two 8-bit bytes of data, any resulting carry bit would
need to be able to “ripple” or move across the bit patterns starting from the least significant bit (LSB).
The most complicated operation the half adder can do is “1 + 1” but as the half adder has no carry input
the resultant added value would be incorrect. One simple way to overcome this problem is to use a Full
Adder type binary adder circuit.

A Full Adder Circuit

The main difference between the Full Adder and the previous Half Adder is that a full adder has three
inputs. The same two single bit data inputs A and B as before plus an additional Carry-in (C-in) input to
receive the carry from a previous stage as shown below.

Full Adder Block Diagram

full adder block diagram

Then the full adder is a logical circuit that performs an addition operation on three binary digits and just
like the half adder, it also generates a carry out to the next addition column. Then a Carry-in is a possible
carry from a less significant digit, while a Carry-out represents a carry to a more significant digit.

In many ways, the full adder can be thought of as two half adders connected together, with the first half
adder passing its carry to the second half adder as shown.

Full Adder Logic Diagram

full adder logic diagram

As the full adder circuit above is basically two half adders connected together, the truth table for the full
adder includes an additional column to take into account the Carry-in, CIN input as well as the summed
output, S and the Carry-out, COUT bit.

Full Adder Truth Table with Carry

Symbol Truth Table

full adder C-in B A Sum C-out

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1
1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Then the Boolean expression for a full adder is as follows.

For the SUM (S) bit:

SUM = (A XOR B) XOR Cin = (A ⊕ B) ⊕ Cin

For the CARRY-OUT (Cout) bit:

CARRY-OUT = A AND B OR Cin(A XOR B) = A.B + Cin(A ⊕ B)

An n-bit Binary Adder

We have seen above that single 1-bit binary adders can be constructed from basic logic gates. But what if
we wanted to add together two n-bit numbers, then n number of 1-bit full adders need to be connected
or “cascaded” together to produce what is known as a Ripple Carry Adder.

A “ripple carry adder” is simply “n“, 1-bit full adders cascaded together with each full adder representing
a single weighted column in a long binary addition. It is called a ripple carry adder because the carry
signals produce a “ripple” effect through the binary adder from right to left, (LSB to MSB).

For example, suppose we want to “add” together two 4-bit numbers, the two outputs of the first full
adder will provide the first place digit sum (S) of the addition plus a carry-out bit that acts as the carry-in
digit of the next binary adder.
The second binary adder in the chain also produces a summed output (the 2nd bit) plus another carry-
out bit and we can keep adding more full adders to the combination to add larger numbers, linking the
carry bit output from the first full binary adder to the next full adder, and so forth. An example of a 4-bit
adder is given below.

A 4-bit Ripple Carry Adder

4 bit binary adder

One main disadvantage of “cascading” together 1-bit binary adders to add large binary numbers is that if
inputs A and B change, the sum at its output will not be valid until any carry-input has “rippled” through
every full adder in the chain because the MSB (most significant bit) of the sum has to wait for any
changes from the carry input of the LSB (less significant bit). Consequently, there will be a finite delay
before the output of the adder responds to any change in its inputs resulting in a accumulated delay.

When the size of the bits being added is not too large for example, 4 or 8 bits, or the summing speed of
the adder is not important, this delay may not be important. However, when the size of the bits is larger
for example 32 or 64 bits used in multi-bit adders, or summation is required at a very high clock speed,
this delay may become prohibitively large with the addition processes not being completed correctly
within one clock cycle.

This unwanted delay time is called Propagation delay. Also another problem called “overflow” occurs
when an n-bit adder adds two parallel numbers together whose sum is greater than or equal to 2n

One solution is to generate the carry-input signals directly from the A and B inputs rather than using the
ripple arrangement above. This then produces another type of binary adder circuit called a Carry Look
Ahead Binary Adder where the speed of the parallel adder can be greatly improved using carry-look
ahead logic.

The advantage of carry look ahead adders is that the length of time a carry look ahead adder needs in
order to produce the correct SUM is independent of the number of data bits used in the operation,
unlike the cycle time a parallel ripple adder needs to complete the SUM which is a function of the total
number of bits in the addend.
4-bit full adder circuits with carry look ahead features are available as standard IC packages in the form
of the TTL 4-bit binary adder 74LS83 or the 74LS283 and the CMOS 4008 which can add together two 4-
bit binary numbers and generate a SUM and a CARRY output as shown.

74LS83 Logic Symbol

Summary of Binary Adders

We have seen in this tutorial about Binary Adders that adder

circuits can be used to “add” together two binary numbers
producing a “carry-out”. In its most basic form, adders can be
made from connecting together an Exclusive-OR gate with an
AND gate to produce a Half Adder circuit. Two half adders can the be combined to produce a Full Adder.
There are a number of 4-bit full-adder ICs available such as the 74LS283 and CD4008. which will add two
4-bit binary number and provide an additional input carry bit, as well as an output carry bit, so you can
cascade them together to produce 8-bit, 12-bit, 16-bit, adders but the carry propagation delay can be a
major issue in large n-bit ripple adders.