Beruflich Dokumente
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Radio
GNU Radio and the
USRP
Overview
What is Software Defined Radio?
Advantages of Software Defined Radio
Traditional versus SDR Receivers
SDR and the USRP
Using GNU Radio
Introduction
What is Software Defined Radio (SDR)?
Getting code as close to the antenna as possible
Replacing hardware with software for
modulation/demodulation
Advantages:
Makes communications systems reconfigurable
(adapting to new standards)
Flexible (universal software device - not special
purpose)
Filters/Other Hardware
Cognitive Radio
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Traditional Receiver
|fLO-fc|
RF fc fLO+fc IF Demod-
x
Amplifier Amplifier ulator
fLO
10 KHz
10 KHz
Local
f (KHz)
Oscillator 5
10 KHz
f (KHz)
f (KHz) 455
530 980 1700
f (KHz)
10 KHz 455
fLO=1435 KHz
f (KHz)
530 980 1700
Traditional RF x IF Demod-
/ Hardware Amplifier Amplifier ulator
Receiver Local
Oscillator
Current
SDR Receiver Front End ADC Software
Receiver
Future
SDR
ADC Software
Receiver ?
5
Receiver USB
Front End
ADC FPGA PC
Controller
2
Quadrature Signal
Representation
The received signal, S(t), may be represented as follows:
S(t) = I(t)cos(2! fct) + Q(t)sin(2! fct) 16 KHz
3
USRP Receiver Front End
x LPF I
fc
RF LO
Amplifier
90°
x LPF Q
10
ADC
Decimation
Original sampling rate is 64Msamp/sec
Converts a portion of spectrum 32 MHz wide
Generally we are interested is a narrower portion of the
spectrum requiring a lower sampling rate
USB cannot handle that high data rate
Occurs in the FPGA of the USRP
Downsample
LPF
divide by 128
f f f
32MHz 250KHz 250KHz
64M
= 128
500K 12
4
SDR Receiver with USRP
Daughterboard Motherboard
FPGA
USB
(Decimator,
ADC MUX, etc.) Controller PC
GNU
Radio
Software
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USRP -
Motherboard/Daughterboard
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5
Design of a Receiver
16
f (MHz) f
400 446 500 4KHz
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Design Procedure
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6
NBFM Receiver: Block
Diagram/Parameters
16 KHz 16 KHz 16 KHz
FM
f (MHz) f (MHz) f (KHz)
400 446 500 -32 32 -? -8 8 ?
USRP PC
16 KHz 16 KHz
Audio
f (KHz)
f (MHz) f (MHz) -4 4
-? ?
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16 KHz
Audio
FPGA Channel Filter FM
Dec. factor = cutoff = 8KHz Demodulator
D1 Dec. factor = Dec. factor = f (KHz)
D2 D3 -4 4
-32 32 f (MHz)
64Msamp/sec 8Ksamp/sec
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Channel Filter Specification
16 KHz
Audio
FPGA Channel Filter FM
Dec. factor = cutoff = 8KHz Demodulator
250 Dec. factor = Dec. factor = f (KHz)
D2 D3 -4 4
-32 32 f (MHz)
64Ms/s 16 KHz
Channel Filter
f (KHz) H (dB)
-128 128 0
256Ks/s -0.1
-60
f (KHz)
-16 -9 -8 8 9 16
FM Demodulator
16 KHz
FM
f (KHz)
-16 -8 8 16
32Ks/s
16 KHz
Audio
FPGA Channel Filter FM
Dec. factor = cutoff = 8KHz Demodulator
250 Dec. factor = 8 Dec. factor = f (KHz)
D3 -4 4
-32 32 f (MHz)
64Ms/s 16 KHz
f (KHz)
-128 128
256Ks/s
•Maximum frequency = 4 KHz Reduce sample rate to 8 Ks/s
•32Ks/s / 8Ks/s D3 = 4
•FM Demodulator block “extracts” audio signal from FM waveform by
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operating on I and Q
FM
f (KHz)
-16 -8 8 16
32Ks/s
16 KHz
Audio
FPGA Channel Filter FM
Dec. factor = cutoff = 8KHz Demodulator
250 Dec. factor = 8 Dec. factor = 4 f (KHz)
-4 4
-32 32 f (MHz)
8Ks/s
64Ms/s 16 KHz
f (KHz)
-128 128
256Ks/s
8
Final Application Design
64Ms/s 256Ks/s 32Ks/s 32Ks/s
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9
Channel Filter Design
The following code specifies the channel
filter and computes the coefficients
H (dB)
0
-0.1
-60
f (KHz)
-16 -9 -8 8 9 16
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FM Demodulator
The following code creates the FM demodulator.
The demodulator block also includes a low pass
filter.
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10
Resampler
The following code creates the resampler.
The resampler decimates and/or interpolates the
data to adjust the sample rate.
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Final Thoughts
Demonstration
Storing/creating data
Transmitters
Installing GNU radio
Questions
Where do we go from here?
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