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CXP86541/86549/86561

CMOS 8-bit Single Chip Microcomputer

Description
The CXP86541/86549/86561 are the CMOS 8-bit 52 pin SDIP (Plastic)
microcomputer integrating on a single chip an A/D
converter, serial interface, timer/counter, time-base
timer, on-screen display function, I2C bus interface,
PWM output, remote control reception circuit,
HSYNC counter, watchdog timer, 32kHz timer/counter
besides the basic configurations of 8-bit CPU, ROM,
RAM, I/O ports.
The CXP86541/86549/86561 also provide a sleep
function that enables to lower the power consumption.

Features Structure
• A wide instruction set (213 instructions) which Silicon gate CMOS IC
covers various types of data
– 16-bit operation/multiplication and division/
Boolean bit operation instructions
• Minimum instruction cycle 250ns at 16MHz operation (4.5 to 5.5V)
122µs at 32kHz operation (2.7 to 5.5V)
• Incorporated ROM 40K bytes (CXP86541)
48K bytes (CXP86549)
60K bytes (CXP86561)
• Incorporated RAM 1536 bytes
(Excludes VRAM for on-screen display and sprite RAM)
• Peripheral functions
– A/D converter 8-bit 6-channel successive approximation method
(Conversion time of 3.25µs at 16 MHz)
– Serial interface 8-bit clock sync type, 1 channel
– Timer 8-bit timer
8-bit timer/counter
19-bit time-base timer
32kHz timer/counter
– On-screen display (OSD) function 12 × 16 dots,
512 character types,
15 character colors, 2 lines × 24 characters,
frame background 8 colors/ half blanking,
background on full screen 15 colors/ half blanking
edging/ shadowing/ rounding for every line,
background with shadow for every character,
double scanning,
sprite OSD,
12 × 16 dots, 1 screen, 8 colors for every dot
– I2C bus interface
– PWM output 8 bits, 6 channels
14 bits, 1 channel
– Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO
– HSYNC counter 2 channels
– Watchdog timer
• Interruption 13 factors, 13 vectors, multi-interruption possible
• Standby mode Sleep
• Package 52-pin plastic SDIP
• Piggyback/evaluator CXP86490 64-pin ceramic PSDIP (Supports custom font)
Perchase of Sony's I2C components conveys a licence under the Philips I2C Patent Rights to use these components
in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

–1–
E96Z15B1X-PS
Block Diagram

INT2
MP

EXTAL

INT1
VSS

RST

TX

INT0
VDD

XTAL

TEX
CLOCK GENERATOR
A/D CONVERTER SPC700 CPU CORE
AN0 to AN5 6 /SYSTEM CONTROL 8 PA0 to PA7
6CH

PORT A
RMC REMOCON FIFO ROM
RAM
12K/16K/24K/32K/
352/704/1536 BYTES 8 PB0 to PB7
40K/48K/60K BYTES
PORT B
SI
SERIAL INTERFACE
SO

INTERRUPT CONTROLLER
UNIT
SCK

8BIT TIMER/ 8 PD0 to PD7


EC 2
COUNTER 0
PORT D

TO 8BIT TIMER 1

XLC 2 PE0 to PE1


EXLC 2 PRESCALER/ PE2 to PE3
2
R TIME BASE TIMER

–2–
PORT E

3 PE4 to PE6
G
B ON SCREEN
I DISPLAY WATCHDOG TIMER
YS 8 PF0 to PF7
PORT F

YM
32kHz
HSYNC
TIMER/COUNTER
VSYNC

1 PG7
HS0 HSYNC COUNTER 0
PORT G

2
I2C BUS
8BIT PWM 14BIT PWM
HS1 HSYNC COUNTER 1 INTERFACE UNIT

6
ADJ
PWM

SCL0
SCL1

SDA0
SDA1
PWM0 to PWM5
CXP86541/86549/86561
CXP86541/86549/86561

Pin Assignment (Top View)

EC/PD7 1 52 PF0/PWM0
RMC/PD6 2 51 PF1/PWM1
HS1/PD5 3 50 PF2/PWM2
HS0/PD4 4 49 PF3/PWM3
SI/PD3 5 48 PF4/SCL0
SO/PD2 6 47 PF5/SCL1/PWM4
SCK/PD1 7 46 PF6/SDA0
INT2/PD0 8 45 PF7/SDA1/PWM5
HSYNC/PA7 9 44 PE0/TO/ADJ
VSYNC/PA6 10 43 PE1/PWM
RST 11 42 PE2/TEX/INT0
VSS 12 41 PE3/TX
XTAL 13 40 VSS
EXTAL 14 39 VDD
PA5/AN5 15 38 NC
PA4/AN4 16 37 EXLC
PA3/AN3 17 36 XLC
PA2/AN2 18 35 PE4/YM
PA1/AN1 19 34 PE5/YS
PA0/AN0 20 33 PE6/I
PB7 21 32 B
PB6 22 31 G
PB5 23 30 R
PB4 24 29 PB0
PB3 25 28 PB1
INT1/PG7 26 27 PB2

Note)
1. NC (Pin 38) is left open.
2. Vss (Pins 12 and 40) are both connected to GND.

–3–
CXP86541/86549/86561

Pin Description

Symbol I/O Description


PA0/AN0
I/O/ (Port A) Analog inputs to A/D converter.
to
Analog input 8-bit I/O port. (6 pins)
PA5/AN5
I/O can be set in a
PA6/VSYNC I/O/Input unit of single bits. OSD display vertical sync signal input.
(8 pins)
PA7/HSYNC I/O/Input OSD display horizontal sync signal input.
(Port B)
PB0 to PB7 I/O 8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)
External interruption request input. Active at the
PD0/INT2 I/O/Input
falling edge.
PD1/SCK I/O/I/O (Port D) Serial clock I/O.
PD2/SO I/O/Output 8-bit I/O port. I/O Serial data output.
can be set in a
PD3/SI I/O/Input unit of single bits. Serial data input.
PD4/HS0 I/O/Input Can drive 12mA HSYNC counter (CH0) input.
synk current.
PD5/HS1 I/O/Input (8 pins) HSYNC counter (CH1) input.
PD6/RMC I/O/Input Remote control reception circuit input.
PD7/EC I/O/Input External event input for timer/counter.
I/O/Output/ Rectangular wave output 32kHz oscillation
PE0/TO/ADJ frequency dividing output.
Output for 8-bit timer/counter.
PE1/PWM I/O/Output 14-bit PWM output.
(Port E)
Bits 0 and 1 are I/O External interruption
Input/Input/ Connects a crystal for
PE2/TEX/INT0 port; I/O can be set request input. Active at
Input 32kHz timer/counter
in a unit of single bits. the falling edge.
clock oscillation. When
Bits 2 and 3 are for used as an event
PE3/TX Input/Output input. Bits 4, 5 and counter, input to TEX pin and leave TX pin open.
6 are for output.
PE4/YM Output/Output (7 pins)

PE5/YS Output/Output
PE6/I Output/Output OSD display 6-bit output.
B Output (6 pins)

G Output
R Output

–4–
CXP86541/86549/86561

Symbol I/O Description


PF0/PWM0 to (Port F) 8-bit PWM output.
Output/Output
PF3/PWM3 8-bit output port (4 pins)
and large current
PF4/SCL0 Output/I/O I2C bus interface transfer clock I/O.
(12mA) N-channel
(2 pins)
PF5/SCL1/ Output/I/O/ open drain output.
8-bit PWM output.
PWM4 Output Lower 4 bits are
midium drive voltage
PF6/SDA0 Output/I/O I2C bus interface transfer data I/O.
(12V); upper 4 bits
(2 pins)
PF7/SDA1/ Output/I/O/ are 5V drive.
8-bit PWM output.
PWM5 Output (8 pins)
(Port G) External interruption request input.
PG7/INT1 I/O/Input 1-bit I/O port. Active at the falling edge.
EXTAL Input Connects a crystal for system clock oscillation. When a clock is
supplied externally, input it to EXTAL pin and input a reversed phase
XTAL Output clock to XTAL pin.
RST Input System reset; active at Low level.
EXLC Input OSD display clock oscillation I/O. Oscillation frequency is determined
XLC Output by the external L and C.

NC No connected.
VDD Positive power supply.
Vss GND. Connect two Vss pins to GND.

–5–
CXP86541/86549/86561

Input/Output Circuit Formats for Pins

Pin Circuit format When reset


Port A

Port A data

Port A direction

PA0/AN0 “0” when reset


to
PA5/AN5 Data bus IP Hi-Z
Input
RD (Port A)
protection
circuit
Port A function selection
“0” when reset Input multiplexer
A/D converter

6 pins

Port A
Port A data

Port A direction
PA6/VSYNC “0” when reset
PA7/HSYNC
Data bus Schmitt input Hi-Z
IP

RD (Port A)

HSYNC, VSYNC Input polarity


2 pins “0” when reset

Port B
Ports B, G data
Port G
Ports B, G direction
PB0 to PB7 “0” when reset
PG7/INT1
Schmitt input Hi-Z
Data bus for PB0, PB1, PB2, IP
PG7

RD (Ports B, G)

9 pins INT1

Port F

PWM0 to PWM3
PF0/PWM0
to
Port F function selection
PF3/PWM3 Hi-Z
“0” when reset ∗

Port F data
“1” when reset ∗ 12V drive voltage
Large current 12mA
4 pins

–6–
CXP86541/86549/86561

Pin Circuit format When reset


Port D
Port D data
PD0/INT2
PD3/SI Port D direction
PD4/HS0 “0” when reset ∗
PD5/HS1
Hi-Z
PD6/RMC
Data bus Schmitt input IP
PD7/EC
RD (Port D)

INT2, SI, HS0, ∗ Large current 12mA


HS1, RMC, EC
6 pins

Port D
SCK, SO
SIO output enable

Port D data
PD1/SCK
PD2/SO ∗
Port D direction Hi-Z
“0” when reset
IP
Schmitt input
Data bus only for PD1

RD (Port D)

2 pins SCK only ∗ Large current 12mA

Port E
Internal reset signal

Port E data 00
“1” when reset
TO 01 MPX
ADJ16K∗1 10 ∗2
ADJ2K∗1 11 High level
PE0/TO/ADJ (with
Port E function selection (Upper) approximately
Port E function selection (Lower) 150kΩ
∗1 ADJ signals are frequency resistor when
“00” when reset
dividing outputs for 32kHz reset)
Port E direction oscillation frequency IP
“1” when reset adjustment. ADJ2K provides
usage as buzzer output.
Data bus ∗2 Pull-up resistors approx. 150kΩ

1 pin RD (Port E)

–7–
CXP86541/86549/86561

Pin Circuit format When reset


Port E
PWM
Port E function selection
“0” when reset
Port E data

PE1/PWM “1” when reset


High level
Port E direction
“1” when reset
IP
Data bus

RD (Port E)
1 pin

Port E
32kHz oscillation circuit control
“1” when reset
Schmitt input
INT0

Data bus

RD (Port E)
PE2/TEX/INT0
Data bus Oscillation
PE3/TX
halted
RD (Port E)
PE2/ Schmitt input Port input
TEX/ IP IP
INT0 Clock input

PE3/
2 pins TX

Port E

YM, YS, I
Output polarity
PE4/YM “0” when reset
PE5/YS
PE6/I Port E function selection Hi-Z
“0” when reset

Port E data

Writing data to output polarity


register and port data register
3 pins brings output to active.

–8–
CXP86541/86549/86561

Pin Circuit format When reset


Port F SCL, SDA

I2C bus enable


PF4/SCL0 PWM4, PWM5


PF5/SCL1/PWM4
Port F function selection
PF6/SDA0
“0” when reset Hi-Z
PF7/SDA1/PWM5
Port F data
“1” when reset Schmitt input

SCL, SDA IP
(I2C bus circuit)
BUS SW
4 pins ∗ Large current 12mA To internal I2C pins
(SCL1 for SCL0)

R, G, B

R Output polarity
G “0” when reset
B Hi-Z

Writing data to output


3 pins polarity register brings
output to active.

Oscillation control

EXLC IP OSD display clock


EXLC IP
XLC Oscillation
halted

2 pins XLC

EXTAL EXTAL IP
XTAL • Diagram shows the
circuit composition Oscillation
during oscillation.
• Feedback resistor is
XTAL removed during stop mode.
2 pins (This device does not
enter stop mode.)

Pull-up resistor

RST

AA
OP Mask option Low level
Schmitt input

1 pin

AA
–9–
CXP86541/86549/86561

Absolute Maximum Ratings (Vss = 0V reference)

Item Symbol Ratings Unit Remarks


Supply voltage VDD –0.3 to +7.0 V
Input voltage VIN –0.3 to +7.0∗1 V
Output voltage VOUT –0.3 to +7.0∗1 V
Mid-voltage drive output voltage VOUTP –0.3 to +15.0 V
High level output current IOH –5 mA
High level total output current ∑IOH –50 mA Total of all output pins
Ports excluding large current output
IOL 15 mA
(value per pin)
Low level output current
Large current output ports
IOLC 20 mA
(value per pin∗2)
Low level total output current ∑IOL 130 mA Total of all output pins
Operating temperature Topr –20 to +75 °C
Storage temperature Tstg –55 to +150 °C
Allowable power dissipation PD 375 mW SDIP-52P-01
∗1 VIN and VOUT should not exceed VDD + 0.3V.
∗2 The large current output port is Port D (PD) and Port F (PF).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.

Recommended Operating Conditions (Vss = 0V reference)

Item Symbol Min. Max. Unit Remarks


Guaranteed operation range for 1/2 and 1/4
4.5 5.5 V
frequency dividing modes
Guaranteed operation range for 1/16 frequency
VDD 3.5 5.5 V
Supply voltage dividing mode or sleep mode
2.7 5.5 V Guaranteed operation range for TEX mode
— — V Guaranteed data hold range for stop mode∗5
VIH 0.7VDD VDD V ∗1
High level input ∗2
VIHS 0.8VDD VDD V
voltage
VIHEX VDD – 0.4 VDD + 0.3 V EXTAL pin∗3, TEX pin∗4
VIL 0 0.3VDD V ∗1
Low level input ∗2
VILS 0 0.2VDD V
voltage
VILEX –0.3 0.4 V EXTAL pin∗3, TEX pin∗4
Operating temperature Topr –20 +75 °C
∗1 PA1 to PA5, PB3 to PB7, PD2, PE0, PE1, PE3, SCL0, SCL1, SDA0, SDA1 pins
∗2 VSYNC, HSYNC, INT2, SCK, SI, HS0, HS1, RMC, EC, INT0, INT1, RST, PB0, PB1, PB2 pins
∗3 Specifies only during external clock input.
∗4 Specifies only during external event count input.
∗5 This device does not enter the stop mode.
– 10 –
CXP86541/86549/86561

Electrical Characteristics

DC characteristics (Ta = –20 to +75°C, Vss = 0V reference)

Item Symbol Pins Conditions Min. Typ. Max. Unit


PA, PB, PD, 4.0 V
VDD = 4.5V, IOH = –0.5mA
High level output PE0 to PE1,
VOH
voltage PE4 to PE6, PG7,
VDD = 4.5V, IOH = –1.2mA 3.5 V
R, G, B
PA, PB, PD, PE0 to PE1, VDD = 4.5V, IOL = 1.8mA 0.4 V
PE4 to PE6, PF0 to PF3,
PG7, R, G, B VDD = 4.5V, IOL = 3.6mA 0.6 V
Low level output
VOL PD, PF VDD = 4.5V, IOL = 12.0mA 1.5 V
voltage
PF4 to PF7 VDD = 4.5V, IOL = 3.0mA 0.4 V
(SCL0, SCL1,
SDA0, SDA1) VDD = 4.5V, IOL = 4.0mA 0.6 V
IIHE VDD = 5.5V, VIH = 5.5V 0.5 40 µA
EXTAL
IILE VDD = 5.5V, VIL = 0.4V –0.5 –40 µA
Input current IIHT VDD = 5.5V, VIH = 5.5V 0.1 10 µA
TEX
IILT –0.1 –10 µA
VDD = 5.5V, VIL = 0.4V
IILR RST∗1 –1.5 –400 µA
PA, PB, PD, PE, VDD = 5.5V,
I/O leakage current IIZ ±10 µA
PG7, R, G, B, RST∗1 VI = 0, 5.5V
Open drain I/O PF0 to PF3 VDD = 5.5V, VOH = 12.0V 50 µA
leakage current ILOH
(in N-ch Tr off state) PF4 to PF7 VDD = 5.5V, VOH = 5.5V 10 µA
I2C bus switch VDD = 4.5V
SCL0: SCL1
connection impedance RBS VSCL0 = VSCL1 = 2.25V 120 Ω
SDA0: SDA1
(in output Tr off state) VSDA0 = VSDA1 = 2.25V
1/2 frequency dividing mode
IDD1 VDD = 5.5V, 18 28 mA
16MHz crystal oscillation
(C1 = C2 = 15pF)
VDD = 3.3V,
IDD2 32MHz crystal oscillation 30 80 µA
(C1 = C2 = 47pF)
SLEEP mode
Supply current∗2 IDDS1 VDD VDD = 5.5V, 1.2 2.1 mA
16MHz crystal oscillation
(C1 = C2 = 15pF)
VDD = 3.3V,
IDDS2 32MHz crystal oscillation 12 35 µA
(C1 = C2 = 47pF)
STOP mode∗3
VDD = 5.5V,
IDDS3 — — — µA
termination of 16MHz
and 32MHz oscillation

– 11 –
CXP86541/86549/86561

Item Symbol Pins Conditions Min. Typ. Max. Unit


PA, PB, PD,PE0 to
Clock 1 MHz
PE3, R, G, B, PF4 to
Input capacitance CIN 0V other than the 10 20 pF
PF7 ,PG7 ,EXTAL,
measured pins
TEX, EXLC, RST

∗1 For RST pin, specifies the input current when pull-up resistance is selected, and specifies the leakage
current when non-resistor is selected.
∗2 When all output pins are left open. Specifies only when the OSD oscillation is halted.
∗3 This device does not enter the stop mode.

– 12 –
CXP86541/86549/86561

AC Characteristics

(1) Clock timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item Symbol Pins Conditions Min. Typ. Max Unit
XTAL
System clock frequency fC Fig. 1, Fig.2 8 16 MHz
EXTAL
tXL, Fig. 1, Fig.2
System clock input pulse width EXTAL 28 ns
tXH External clock drive
System clock input rise and fall tCR, Fig. 1, Fig.2
EXTAL 200 ns
times tCF External clock drive
Event count input clock pulse tEH, EC Fig. 3 4tsys∗1 ns
width tEL
Event count input clock rise tER, EC Fig. 3 20 ms
and fall times tEF
VDD = 2.7 to 5.5 V
TEX
System clock frequency fC Fig. 2 (32kHz clock 32.768 kHz
TX
applied conditions)
Event count input clock tTL, TEX Fig. 3 10 µs
pulse width tTH
Event count input clock rise tTR, TEX Fig. 3 ms
20
and fall times tTF
∗1 Indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits
(CPU clock selection).
tsys (ns) = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)

Fig. 1. Clock timing 1/fc

VDD – 0.4V
EXTAL
0.4V

tXH tCF tXL tCR

AAAAA AAAA AAAA


Fig.2. Clock applied conditions

AAAAAAAAA AAAA
Crystal oscillation 32kHz clock applied condition
Ceramic oscillation External clock Crystal oscillation

AAAAAAAAA AAAA
C1
EXTAL XTAL

C2
EXTAL

74HC04
XTAL

C1
TEX TX

C2

Fig. 3. Event count clock timing

TEX 0.8VDD
EC
0.2VDD

tEH tEF tEL tER


tTH tTF tTL tTR

– 13 –
CXP86541/86549/86561

(2) Serial transfer (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pins Conditions Min. Max. Unit


Input mode 1000 ns
SCK cycle time tKCY SCK
Output mode 8000/fc ns

SCK High and Low level tKH SCK input mode 400 ns
SCK
widths tKL SCK output mode 4000/fc – 50 ns

SI input setup time SCK input mode 100 ns


(for SCK ↑)
tSIK SI
SCK output mode 200 ns

SI hold time SCK input mode 200 ns


(for SCK ↑)
tKSI SI
SCK output mode 100 ns
SCK input mode 200 ns
SCK ↓ → SO delay time tKSO SO
SCK output mode 100 ns

Note) The load of SCK output mode and SO output delay time is 50pF + 1TTL.

Fig. 4. Serial transfer timing

tKCY

tKL tKH

0.8VDD
SCK
0.2VDD

tSIK tKSI

0.8VDD
SI Input data

0.2VDD

tKSO

0.8VDD
SO Output data
0.2VDD

– 14 –
CXP86541/86549/86561

(3) A/D converter (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pins Conditions Min. Typ. Max. Unit


Resolution 8 Bits
Linearity error ±3 LSB
Zero transition Ta = 25°C
VZT∗1 –10 10 70 mV
voltage VDD = 5.0V
Vss = 0V
Full-scale transition
VFT∗2 4910 4970 5030 mV
voltage
Conversion time tCONV 26/fADC∗3 µs
Sampling time tSAMP 6/fADC∗3 µs
Analog input voltage VIAN AN0 to AN5 0 VDD V

Fig. 5. Definitions for A/D converter terms

FFh
FEh
Digital conversion value

∗1 VZT: Value at which the digital conversion value changes


from 00h to 01h and vice versa.
∗2 VFT: Value at which the digital conversion value changes
from FEh to FFhand vice versa.
∗3 fADC indicates the below values due to the contents of bit
Linearity error 6 (CKS) of the A/D control register (ADC: 00F6h):

01h
00h
fADC = fc (CKS = “0”), fc/2 (CKS = “1”)
VZT VFT
Analog input

– 15 –
CXP86541/86549/86561

(4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pins Conditions Min. Max. Unit


INT0
External interruption High, tIH 1 µs
INT1
Low level widths tIL
INT2
Reset input Low level width tRSL RST 32/fc µs

Fig. 6. Interruption input timing

tIH tIL

INT0
INT1 0.8VDD
INT2
(falling edge) 0.2VDD

Fig. 7. RST input timing


tRSL

RST
0.2VDD

– 16 –
CXP86541/86549/86561

(5) I2C bus timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pins Conditions Min. Max. Unit


SCL clock frequency fSLC SCL 0 100 kHz
Bus-free time before starting transfer tBUF SDA, SCL 4.7 µs
Hold time for starting transfer tHD; STA SDA, SCL 4.0 µs
Clock Low level width tLOW SCL 4.7 µs
Clock High level width tHIGH SCL 4.0 µs
Setup time for repeated transfers tSU; STA SDA, SCL 4.7 µs
Data hold time tHD; DAT SDA, SCL 0∗1 µs
Data setup time tSU; DAT SDA, SCL 250 ns
SDA, SCL rise time tR SDA, SCL 1 µs
SDA, SCL fall time tF SDA, SCL 300 ns
Setup time for transfer completion tSU; STO SDA, SCL 4.7 µs
∗1 The data hold time should be 300ns or more because the SCL rise time (300ns Max.) is not included in it.

Fig. 8. I2C bus transfer timing

SDA
tBUF
tR tF tHD; STA

SCL
tHD; STA
tSU; STA tSU; STO
P S tLOW tHD; DAT tHIGH tSU; DAT St P

Fig. 9. I2C bus device recommended circuit

I2C bus I2C bus


device device

RS RS RS R S RP RP

SDA0
(or SDA1)
SCL0
(or SCL1)

• A pull-up resistor (Rp) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1).
• The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance can be used to reduce the spike noise caused
by CRT flashover.

– 17 –
CXP86541/86549/86561

(6) OSD timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pins Conditions Min. Max Unit

EXLC
OSD clock frequency fOSC Fig. 11 4 28∗1 MHz
XLC

HSYNC pulse width tHWD HSYNC Fig. 10 2 µs


VSYNC pulse width tVWD VSYNC Fig. 10 1 H∗2
HSYNC afterwrite rise and fall tHCG HSYNC Fig. 10 200 ns
times
VSYNC beforewrite rise and fall Fig. 10
times
tVCG VSYNC 1.0 µs

∗1 The maximum value of fosc is specified with the following equation.


fosc [max] ≤ fc × 1.9
∗2 H indicates 1HSYNC period.

Fig. 10. OSD timing

tHCG
tHWD

HSYNC 0.8VDD
For OSD I/O polarity register
(OPOL: 01FEh)
bit 7 at “0” 0.2VDD

tVCG
tVWD

VSYNC 0.8VDD
For OSD I/O polarity register
(OPOL: 01FEh)
bit 6 at “0” 0.2VDD

Fig. 11. LC oscillation circuit connection

EXLC XLC

R∗1
L

C1 C2

∗1 The series resistor for XLC is used to reduce the frequency of occurrence of the undesired radiation.

– 18 –
CXP86541/86549/86561

Appendix

Fig. 12. Recommended oscillation circuit

AAAA
AAAA
(i) Main clock

AAAA AAAAA
(ii) Main clock

AAAA AAAAA
(iii) Sub clock

AAAA
EXTAL XTAL

AAAA AAAAA
EXTAL XTAL TEX TX

AA
Rd Rd Rd

A
C1 C2 C1 C2

A
C1 C 2

Manufacture Model fc (MHz) C1 (pF) C2 (pF) Rd (Ω) Circuit example


CSA10.0MTZ 10.0
30 30
CSA12.0MTZ 12.0 (i)
CSA16.00MXZ040 16.0 5 5
0 ∗1
MURATA MFG
CO., LTD. CST10.0MTW∗ 10.0
30 30
CST12.0MTW∗ 12.0 (ii)
CST16.00MXW0C1∗ 16.0 5 5
8.0 18 18
RIVER
ELETEC CO., HC-49/U03 12.0 12 12 330 ∗1
LTD.
16.0 10 10
(i)
8.0 10 10
HC-49/U (-S) 12.0 5 5 0 ∗1
KINSEKI LTD.
16.0 Open Open
P3 32.768kHz 30 33 120k (iii)
∗ Models with an astarisk have the built-in ground capacitance (C1, C2).
∗1 The series resistor for XTAL (Rd = 500Ω or less) can reduce the effect of the noise caused by the
electrostatic discharge.

Mask Option Table

Item Content
Reset pin pull-up resistor Non-existent Existent

– 19 –
CXP86541/86549/86561

Fig. 13. Characteristic curve

IDD vs. VDD IDD vs. fc


(fc = 16MHz, Ta = 25°C, Typical) (VDD = 5V, Ta = 25°C, Typical)
100

1/2 dividing mode

10 1/4 dividing mode


15 1/2 dividing mode
1/16 dividing mode

IDD – Supply current [mA]


IDD – Supply current [mA]

Sleep mode
1
10

1/4 dividing mode

0.1
32kHz operation mode 5

32kHz sleep mode


1/16 dividing mode

0.01
Sleep mode
0
1 2 3 4 5 6 7 0 5 10 15
VDD – Supply voltage [mA] Frequency [MHz]

Parameter curve for OSD oscillator L vs. C


(Analytically calculated value)
100

10
L – Inductance [µH]

16MHz
20MHz
1
24MHz
28MHz
30MHz

fOSC = 1 C = C1//C2
2π√ LC
0.1

0.01
0 10 20 30 40 50 60 70 80 90 100
C1, C2 – Capacitance [pF]

– 20 –
CXP86541/86549/86561

Package Outline Unit: mm


52PIN SDIP (PLASTIC)

05
+ 0.1
0.25 – 0.
+ 0.4
47.0 – 0.1

52 27

13.5 – 0.1
+ 0.3
0˚ to 15˚

15.24
1 26
1.778

5.0 MIN
0.51 MIN
0.5 ± 0.1

2.8 MIN
+ 0.1
0.9 – 0.05

PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN
SONY CODE SDIP-52P-01 LEAD TREATMENT SOLDER PLATING

EIAJ CODE P-SDIP52-13.5x47.0-1.778 LEAD MATERIAL COPPER ALLOY


JEDEC CODE PACKAGE MASS 5.6g

52PIN SDIP (PLASTIC)


05
+ 0.1
0.25 – 0.

+ 0.4
47.0 – 0.1

52 27
13.5 – 0.1
+ 0.3

0˚ to 15˚
15.24

1 26
1.778
5.0 MIN
0.51 MIN

0.5 ± 0.1
2.8 MIN

+ 0.1
0.9 – 0.05

PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN
SONY CODE SDIP-52P-01 LEAD TREATMENT SOLDER PLATING

EIAJ CODE P-SDIP52-13.5x47.0-1.778 LEAD MATERIAL COPPER ALLOY


JEDEC CODE PACKAGE MASS 5.6g

LEAD PLATING SPECIFICATIONS

ITEM SPEC.
LEAD MATERIAL COPPER ALLOY
SOLDER COMPOSITION Sn-Bi Bi:1-4wt%
PLATING THICKNESS 5-18µm

– 21 – Sony Corporation