IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-22, NO.

2, APRIL 1987 1

A Versatile Building Block: The CMOS Dierential

Dierence Amplier
Eduard S
ackinger, Student Member, IEEE and Walter Guggenb
uhl Senior Member, IEEE
Abstract | An extension of the op-amp concept featuring of the ideal DDA with negative feedback can be described
two dierential inputs is presented. In a closed-loop envi- by
ronment this circuit forces two oating voltages to the same
value, and thus has many interesting applications in the ana- vPP vPN = vNP vNN : (2)
log circuit domain. The formal description of such a circuit,
its nonidealities and restrictions are given. A monolithic in- Please note that analogous to the normal op amp Eq. (2) is
tegration of this dierential dierence amplier (DDA) in a comparison and therefore the DDA does not require ab-
a double-poly CMOS technology and the measured charac- solutely precise device parameters. The symbol in Fig. 1
teristics are described. Many applications of this circuit,
including a voltage comparator with oating inputs, a volt- might suggest that this circuit can be realized by a combi-
age inverter without resistors and an instrumentation am- nation of three op amps, which is not true for the following
plier with only two external gain determining resistors are reasons. First, an op amp is not designed for a large dier-
discussed.
ential voltage and thus would be overdriven. Second, the
gains of the rst two op amps should exactly match, but it
I. Introduction is not the goal of an usual op amp to provide an accurate

B EFORE discussing the dierential dierence amplier,

a short refresh of the op-amp principle is given. The
classical operational amplier acts as a device which, if
open-loop gain.
In Section II the operating parameters of the DDA are
dened. The realization is discussed in Section III. The
completed with a negative feedback loop, adjusts its out- results of the integrated prototype are presented in Section
put in order to reduce the dierential input voltage to a IV. Examples of nonideal performance are mathematically
negligible value. For an ideal op amp with innite gain analyzed in Section V. Finally, in Section VI this new
this voltage goes to zero. If the voltage at the noninverting circuit is illustrated by many applications which use fewer
input terminal is called vP (for positive) and the voltage at parts than solutions with conventional op amps.
the inverting input vN (for negative) the operating princi-
ple of the ideal op amp can be summarized: II. Definitions
In order to set a basis for the discussion of the charac-
vP = vN : (1) teristics and nonidealities of the DDA, the voltages and
operating parameters describing its operation are dened.
This equation shows that the op-amp operation is mainly The voltage input state of the DDA can be described
based on the comparison of the two input voltages. This by a four-component vector. The most straightforward
comparing character makes it well suited for a monolithic approach is the direct use of the single-ended input ter-
integration despite the strong temperature and process de- minal voltages as vector components. In the case of the
pendence of most device parameters: a good common- ordinary op amp, it is usually more convenient to take the
mode rejection ratio is obtained by a high-impedance cur- dierential- and the common-mode voltages as vector com-
rent source which can be easily realized, while a low oset ponents, thus separating the input signal into a voltage to
voltage results from the good matching and tracking prop- be amplied (dierential mode) and a voltage to be sup-
erties of geometrically equal devices on the same chip. pressed (common mode). We now apply this transforma-
The concept of the op amp will now be extended to a tion procedure to our four-input device. The dierential
circuit which does compare two dierential input voltage voltage reads (vPP vPN ) (vNP vNN ); the three other
signals in contrast to an ordinary op amp which compares vector components should not be amplied and are called
single-ended voltages only. This new circuit is called a common-mode voltages. The denition of this more suit-
dierential dierence amplier or DDA in [1] (see the con- able vector can be best described by specifying the respec-
clusion for more details about the DDA of [1]). As a con- tive transformation matrix:
vention the symbol shown in Fig. 1 will be used for the
DDA with the input-terminal voltages designated as vPP ,
0v 1 0 1 1 1 1
10 v 1
D PP
vPN for the non-inverting input port and vNP , vNN for the B B@ v CA = B@ 0 0 1=2 1=2 CA B@ v CCA : (3)
v CP C B 1 = 2 1 =2 0 0 C B v PN
inverting port. With these denitions the basic property CN NP
vCD 1=2 1=2 1=2 1=2 vNN
Manuscript received February 27, 1986; revised September 19, 1986.
This work was supported by the Swiss National Science Foundation While the rst row describes the dierential voltage vD , the
under a grant from project NFP-13.
The authors are with the Electronics Laboratory, Swiss Federal second, third, and fourth rows assigned to the common-
Institute of Technology, ETH Zentrum, CH-8092 Zurich, Switzerland. mode voltages vCP , vCN , and vCD , respectively, can be
2 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-22, NO. 2, APRIL 1987

chosen arbitrarily to yield any regular transformation ma- In words, the nonlinearity is the maximum deviation of
trix. In Eq. (3), the denition of the common-mode volt- the two port voltages over a given port voltage range
ages is given in order to be compatible with the denition [ VFS : : : VFS ] normalized to this range (always assuming
used for the normal op amp (upper left 2  2 submatrix) an output voltage of zero). Using Eq. (7) and vD  vCD
[2]. the nonlinearity can be rewritten in terms of the oset volt-
The nonideal op amp is usually characterized by the pa- age function:
rameters of its linear model [2]. This means that the non-
NL = max jVOFF (VCP 0 ; VCN 0 ; VCD0 )j ;
linear relation between the input voltages (dierential [vD ]
and common-mode [vCM ] voltage) and the output voltage VFS (9)
vO for VCD0 = VFS : : : VFS :
vO = F (vD ; vCM ) (4)
is linearized at the bias point vO = 0 and vCM = VCM 0 : III. Realization Principle
 1 (v
 In this section the block diagram and the central part of
vO = Ad (vD VOFF ) + CMRR CM VCM 0 ) : (5) the circuit diagram are developed starting from the ideal
DDA's behaviour. The ideal DDA amplies the dierential
Equation (5) contains three well-known parameters: dif- voltage vD by a nearly innite amount, but fully suppresses
ferential gain Ad , oset voltage VOFF and common-mode all common-mode voltages:
rejection ratio CMRR. All three parameters depend on the vO = vD = [(vPP vPN ) (vNP vNN )]
bias point, i.e., VCM 0 . (Note: the CMRR denition given (10)
here has a sign, in contrast to the standard denition which with  ! 1:
uses only the absolute value [2].)
This procedure is now extended to four inputs in a This linear combination of the four input-terminal voltages
straightforward manner. The nonlinear function can be transformed into the more general form
vO = F (vD ; vCP ; vCN ; vCD ) (6) vO = k[fP (vPP vPN ) fN (vNP vNN )]
(11)
is linearized around the point vO = 0, vCP = VCP 0 , vCN = with k ! 1 ;
VCN 0 , vCD = VCD0 . This yields if fP and fN satisfy two conditions. First, both functions
 must be identical, and second they must be invertable.
vO = Ad (vD VOFF ) Written as equations this means
1 (v fP (v) = fN (v) (12a)
+ CMRR CP VCP 0 ) df (v) 6= 0 for all v:
p (12b)
(7) dv
1 (v
+ CMRR CN VCN 0 )
n These functions may be nonlinear and time or temperature
1 (v
 dependent.
+ CMRR CD V CD0 :
) Equation (11) can be modeled by the block diagram in
d
Fig. 2 which may be implemented with standard compo-
The meaning of Ad and VOFF is analogous to the nents like MOSFETs or bipolar transistors. The two volt-
corresponding quantities of the op amp, but here are age dierences (vPP vPN ) and (vNP vNN ) are converted
three CMRR's and all parameters (Ad , VOFF , CMRRp , by two transconductance elements into two current dier-
CMRRn , and CMRRd ) depend on all common-mode volt- ences
iP and
iN . These elements correspond to the
ages (VCP 0 ; VCN 0 , and VCD0 ). The p- and n-common-mode functions fP and fN in Eqs. (11) and (12). The subtrac-
rejection ratios (CMRRp , CMRRn ) describe the eect of tion of the output currents is easily carried out by direct
the common-mode voltages at the two input ports, whereas and cross connection of the two dierential stages to the
the d- common-mode rejection ratio (CMRRd ), not known summing buses (+;  ). Finally the output block am-
from the ordinary op amp, measures the eect of equal plies the dierential current
iD from the bus by a large
oating voltages at the two input ports. value and therefore corresponds to the factor k in Eq. (11).
A further operating parameter which must be introduced In this realization there is no need for linear or stable de-
for the understanding of the later sections is the nonlinear- vices, but only for two matched blocks as well as a high
ity NL. Its denition is given in Eq. (8): gain amplier and it is therefore suitable for monolithic
 integration.
max j(vPP vPN ) (vNP vNN )j  ; The central part of the DDA, the transconductance ele-
NL =
VFS vO =0 (8) ment, can be realized using bipolar [1], [3] or MOS transis-
tors [4]. Circuit diagrams for both possibilities are given in
for (vPP vPN ) = VFS : : : VFS : Fig. 3. Note, that in order to achieve a high input voltage
SA CKINGER AND GUGGENBU HL: CMOS DIFFERENTIAL DIFFERENCE AMPLIFIER 3

Transistor Type Weff Leff 3dB.

T1 ; : : : ; T4 n 6m 34m Figure 5 gives an example for the measured relation be-
T5 ; T6; T11 ; : : : ; T14 n 11m 5m tween the two port voltages. On the right-hand scale the
T7 ; T8 p 65m 19m port voltage dierence divided by 2V and thus the nonlin-
T9 p 417m 5m earity of the particular test device for a full-scale voltage
T10 ; T15 ; T16 n 267m 5m of 2V can be read.
TABLE I The DDA was fabricated on a 4m minimum feature size
Transistor Dimensions guard- ring-isolated CMOS process. It is a double polysil-
icon, p-well, fully implanted ten-mask process. The com-
plete device is shown in Fig. 6. Its size is 0:70:54mm. The
large transistors of the current mirror are placed in the up-
range the bipolar circuit requires an emitter- degeneration per left corner. Below are the two dierential stages. The
resistor, whereas using the MOS approach this is not im- double-poly compensation capacitor is placed to the right
perative. In the latter case the input voltage range can be of the mirror. The output stage and the buer transistors
adjusted by the MOS transistors geometry. can be identied by their serpentine-shaped transistors.
In the following the focus will be on the MOS implemen-
tation only. The transfer function fP (
v) or fN (
v) of V. Examples of Nonideal Performance
the MOS transconductance element is given by In Section III an innite gain of the output stage as well
8 s as a precise matching of the transconductance elements
>
>
v I 2IC were assumed. To understand the performance of a real
>
< j
vj C if j
v j   implementation, like the one discussed in the preceding sec-
s  tion, a more thorough analysis is desirable.

i = >  s Equation (11) rewritten with a nite k and the in-
>
>
2

v I 1 1 
v2 if j
vj  2IC put voltages expressed in their dierential- /common-mode
: j
vj C 2IC  form gives
(13) h  vD  f v vD i : (14)
with  standing for the geometry-dependent amplication vO = k fP v CD + 2 N CD 2
factor of the MOS transistor [4]. For Eq. (13), the in- Assuming both functions are equal (fP = fN = f ) and the
p
vertability condition Eq. (12b) requires
v to stay within output voltage goes to zero for vD = 0, the dierential gain
 2IC =. is obtained to
IV. Monolithic CMOS Integration

@vO 
Ad = @v vO =0  kf (VCD0 ):
D vCD =VCD0
0
(15)
A simple DDA has been designed and integrated in
CMOS technology. The circuit diagram of the realized de- Inserting Eq. (13) for the function f yields
vice is shown in Fig. 4. The transconductance elements 2
are realized with two dierential stages (T1 ; : : : ; T4 ) as de-  VCD
scribed in the last section. The current sources (T5 , T6 , p s IC 2 0
1
T11 , T12 ) are implemented using the cascode technique de- Ad = k IC : (16)
 V 2
scribed in [5]. This provides a good matching of the cur- 1 I CD 0
rents ICP and ICN , since they are essentially independent C 4
on the voltages vCP and vCN . For more details see Section The equation shows that the dierential gain is highest
V. The high-gain stage is composed of a current mirror (T7 , for VCD0 = 0 and degrades with increasing common-mode
T8 ) which converts the dierential current of the bus to a voltage VCD0 (Fig. 7). This is a consequence of the at
single-ended current and a standard integrator (T9 , T10 , shape of function Eq. (13) for large
v. The degradation of
C1 ) followed by a buer stage (T15 , T16 ). The buer stage p its maximum value stays within 3dB if jVCD0j <
Ad against
provides a low-impedance output and makes the operat- 0:85 IC = .
ing point of the amplifying part independent of the output Since matching of the two input blocks is crucical for
current. the performance of this device, two matching errors are
The bias current was chosen IpBIAS = 20A and the input discussed in more detail. They both result in a reduced
transistors were designed for IC = = 2V. All eective common-mode rejection, an oset voltage, and nonlinear-
transistor dimensions are summarized in Table I. ity. To begin with, the case of a  mismatch between the
The measured data are listed in Table II. The power two dierential pairs is considered (the  's within a dier-
supply was chosen as VDD = 6V and VSS = 6V. All bias- ential pair are assumed to be equal). This mismatch shall
dependent parameters were determined at the condition be designated  = N =P . A calculation using Eqs. (7),
VCP 0 = VCN 0 = VCD0 = 0V. All common-mode ranges (13), and (14) gives
were measured in two dierent ways: within the limits 1 )
the dierential gain loss is less than 3dB, whereas in the CMRRd  1p (17)
range 2 ) the common-mode gain Acd increase is less than 1 
4 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-22, NO. 2, APRIL 1987

Parameter Symbol Typ. Value or Range

Dierential gain Ad 63dB
p-Common-Mode Rejection CMRRp 78dB
n-Common-Mode Rejection CMRRn 78dB
d-Common-Mode Rejection CMRRd 49dB
p/n-Common-Mode Range 1 ) VCP 0 , VCN 0 6:0V : : : 5:4V
p-Common-Mode Range 2 ) VCP 0 2:4V : : : 5:1V
n-Common-Mode Range 2 ) VCN 0 1:8V : : : 2:6V
d-Common-Mode Range 1 ) VCD0 1:9V : : : 1:7V
d-Common-Mode Range 2 ) VCD0 1:1V : : : 1:1V
Oset Voltage VOFF 0:7mV
Oset Voltage std. deviation
VOFF 7.7mV
Nonlinearity @ VFS = 1:7V NL 1.3%
Nonlinearity @ VFS = 2:0V NL 1.6%
Output Swing vO 6:0V : : : 4:0V
Output Resistance RO 600

Transition Frequency fT 730kHz

Slew Rate jpSRj 7.1Vp=s
Equiv. Input Noise @ 1kHz Suu 550nV= Hz
TABLE II
Typical Chip Performance

p
VOFF  (  1)VCD0 (18) on the common- mode voltage vCP or vCN is modeled by
p iCP = IC (1 + vCP ) and iCN = IC (1 + vCN ) the charac-
NL  j  1j: (19) teristic parameters can be calculated to
Equation (17) shows that the  mismatch leads to a con-
stant CMRRd, i.e., which is independent of the input volt- 2 I VCD 2
0
ages. In most applications this nonideality will only pro- CMRRp = CMRRn  C (23)
duce a constant closed-loop gain error. VCD0
A deviation between the two tail-current sources has a   2
similar eect. Here
shall stand for the current mismatch 2 I VCD0 2
ICN =ICP : CMRRd  1
C
  2  ( V CP 0 V CN 0 ) 2 + I VCD 2
0
2 C
2 V
IC CD0 (24)
CMRRd  1
(20) V
1
2+  V2 VOFF  (VCN 0 VCP 0 )
CD 0 (25)
IC CD0 2 I VCD 2
0
VOFF  (
1)
VCD0
C
(21) p
2 I VCD 2
0
NL  j ( V CP 0 V CN 0 ) j for V FS = IC =:
C (26)
p
NL  j
1j for VFS = IC = (22) The p- and n-common-mode ranges are limited by the
Plots of Eqs. (20) and (21) are given in Figs. 8 and 9. decrease of CMRRd according to Eq. (24). An ordinary
The dependence of CMRRd on the voltage VCD0 as it was cascode (used in Fig. 4) or regulated cascode current source
p (20)
observed in Table II, is conrmed by Fig. 8. From Eq. (Fig. 10) which provides a low  improves the situation. A
a 3dB reduction of CMRRd results at VCD0 = 0:48 IC = . second limitation occurs when the saturation conditions of
In order to compensate the eects which arise from tail- either the current-source or the current-mirror transistors
current mismatch, one can insert resistors in the source are violated.
leads of T5 and T6 and connect an external trimmer.
Analogous to the simple op-amp case, a nite resistance
of the current sources in the dierential stages also causes
a degradation of p/n-common-mode rejection. Further
dissimilar common-mode voltages on the two input ports
(VCP 0 6= VCN 0 ) leads to a mismatch between the transcon-
ductance elements. If the dependence of the tail-current
VI. Applications
In the following subsections several applications to the
DDA are discussed. The mathematical expressions in this
section were derived assuming that all DDA parameters
have been measured under the condition VCP 0 = VCN 0 =
VCD0 = 0.
SA CKINGER AND GUGGENBU HL: CMOS DIFFERENTIAL DIFFERENCE AMPLIFIER 5

A. Comparator with Floating Inputs op amps and several matched resistors. Figure 14 shows
Equation (10) suggests that the DDA can be directly an alternative utilizing one DDA and two gain-determining
used to compare two oating voltages. The example in Fig. resistors [6]. This amplier is characterized by the equation
11 shows a circuit which compares the oating voltage vI vO = A(vI + BvCM C ), where vCM is the common-mode
from the resistor bridge with a grounded reference voltage voltage at the dierential input. Its properties are
VREF . Depending on the positive feedback provided by R 1 + R 2
 1 + 1
the optional resistors R1 and R2 , a variable hysteresis can A R 1 + CMRR
be added to the transfer function. In this application the 1 d 2 CMRRn
DDA can be further simplied by omitting the compensa- 1 R1 + R2

tion capacitor C1 , since there are no stability problems. An Ad R1 (32)
equivalent circuit without the DDA would require at least
three ordinary op amps (two for an instrumentation am- 1
B  CMRR (33)
plier and one for the single-ended comparator) and many p
resistors. C  VOFF : (34)
B. Level Shifter
It is easily seen that the circuit can be used as a nonin-
verting adder without the use of resistive networks. Fig- E. Voltage-Controlled Current Source
ure 12 shows a circuit which shifts the voltage vI on top A simple voltage-controlled current source (VCCS) em-
of the dc voltage VS . The accurate relation is: vO = ploying only one op amp has the disadvantage that it re-
A(vI + BVS C ) + VS , where A, B , and C are calculated quires the load to be oating. Applying a DDA, this re-
from the DDA parameters: striction is relaxed [1]. In addition, dierential inputs are
available (Fig. 15). The transfer function is
1 +
A  1 + CMRR 1
d 2 CMRRp iO = gm (vI C ) + govO (35)
1
+ 2CMRR 1 (27) where
n Ad 
1
B  CMRR 1 (28) gm  R1 1 + CMRR
1 1
n Ad d 2CMRRp
C  VOFF : (29) 1 1

+ 2CMRR A (36)
n d
Using standard op amps this application requires three op
1
 1 1

amps and three resistors. go  R A CMRR (37)
d n
C. Voltage Inverter without External Resistors
C  VOFF : (38)
The classical voltage inverter employing an ordinary op
amp requires two external matched resistors. With the This VCCS can be extended to an integrator by connecting
DDA, this can be realized with a few additional connec- a capacitor to the output terminal. A gyrator can be built
tions and no further components [6, pp. 44{47]. With by cross-coupling an inverting and noninverting VCCS.
Eq. (2) in mind, the inverter circuit of Fig. 13 can readily
be understood. Of course this inverter can be combined F. Oset Cancellation of an Op Amp
with the level-shifting feature of the Fig. 12 circuit. A The DDA can also be used as a simple op amp with the
detailed analysis shows that the parameters A and C in option to introduce an oset cancellation voltage. In Fig.
vO = A(vI C ) can be expressed by 16 this idea is illustrated. The relation between vO and vD ,
0

vCM is
0

1 +
A  1 CMRR 1  
d 2 CMRRp 1
vO  Ad [vD (VOS + VOFF )] + CMRR vCM : (39)
0 0

1 1 p
2CMRRn + Ad (30)
The formula shows, that VOS can be used to compensate
C  VOFF : (31) the oset voltage VOFF . This voltage can be stored on
a capacitor, which is either dynamically readjusted during
an oset-trimming phase [7], [8] or programmed only once
after the manufacturing of the op amp. The latter possi-
D. Instrumentation Amplier bility presupposes a capacitor with very good charge re-
Ampliers with high-impedance dierential inputs and tention capabilities, like the on-chip Si/SiO2 /Si capacitors
a precise gain factor are often realized with two to three employed in EEPROM cells. In either case it is useful to
6 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-22, NO. 2, APRIL 1987

modify the DDA in order to make the input pair connected [8] M. Degrauwe, E. Vittoz, and I. Verbauwhede. A micropower
to the compensation voltage less sensitive by reducing the CMOS-instrumentation amplier. IEEE J. Solid-State Circuits,
SC-20(3):805{807, June 1985.
 's of the respective dierential stage [4]. This allows to
apply a higher oset compensation voltage.
This oset compensation method can also be applied to
the DDA by using a third low sensitivity dierential pair.
VII. Conclusions
A simple circuit suitable for the analog processing of
oating voltages has been presented. Its simple implemen-
tation makes it suitable as a single universal building block
or as part of a larger integrated circuit. Some nonideali-
Eduard Sackinger (S'84) was born in Basel, Switzerland, on
August 13, 1959. He received the M.S. degree in electrical en-
gineering from Swiss Federal Institute of Technology, Zurich,
Switzerland in 1983.
During 1983 he was employed by Isomat Filmvertonungsgerate,
Switzerland, where he developed several microcomputer-based
tools for sound-movie synchronization. In the fall of 1983 he
joined the Electronics Laboratory of the Swiss Federal Institute
of Technology, where he is currently investigating analog ap-
ties which limit its performance have been identied and plications to
oating-gate devices. His main interest is analog
CMOS integrated circuit design.
treated mathematically. Several applications have been
demonstrated which use fewer components than equivalent Walter Guggenbuhl (SM'60) received the diploma in electrical
solutions with ordinary operational ampliers. engineering in 1950 from the Swiss Federal Institute of Technol-
ogy, Zurich, Switzerland.
The DDA described in this paper has a near relation He was an Assistant in the Department of Electrical Engineer-
to the operating principle of many ordinary instrumenta- ing of the Swiss Federal Institute of Technology for about six
tion ampliers. Two dierences must be pointed out how- years, while pursuing his Ph.D. degree. Thereafter, he joined
Contraves AG, Switzerland, where he was Manager of an R&D
ever: an ordinary instrumentation amplier has an inter-
nally wired feedback and the closed-loop gain is adjusted
by dierent gain factors of the transconductance elements,
i.e., adjustable by the resistor RE in Fig. 3. In contrast
the DDA described here is an open-loop device and hence
Department, involved in the eld of electronic circuit and sub-
system design. Since 1973 he has been a full Professor of Elec-
tronic Circuit Design at the Swiss Federal Institute of Tech-
nology. His main interests are low-noise circuits and computer
hardware for signal processing.
more general than the instrumentation amplier. Further
the gain factors of the transconductance elements are xed
and equal which saves pins for external resistors without
sacricing generality. (Note that the DDA described in [1]
is an open-loop device, but has programmable gain factors.)
A prototype circuit has been integrated and evaluated.
Several improvements over this chip can be made, i.e., the
use of common- centroid techniques to enhance the match-
ing of the two input circuits [5] and trimming of VOFF and
CMRRd . This will be subject of future work.
Acknowledgment
The authors would like to thank `Centre Suisse
d'Electronique et de Microtechnique S. A.' for fabricating
the prototype circuit described, and W. Fichtner for his
helpful suggestions and encouragement. Special thanks go
to the reviewers whose eorts have improved this paper
considerably.
References
[1] Johan H. Huijsing. Instrumentation amplifer: A comparative
study on behalf of monolithic integration. IEEE Trans. Instrum.
Meas., IM-25(3):227{231, September 1976.
[2] Paul R. Gray. Analysis and Design of Integrated Circuits. John
Wiley & Sons, New York, 1977.
[3] B. Gilbert. A high-performance monolithic multiplier using ac-
tive feedback. IEEE J. Solid-State Circuits, SC-9(6):364{373,
December 1974.
[4] R. R. Torrance, T. R. Viswanathan, and J. V. Hanson. CMOS
voltage to current transducers. IEEE Trans. Circuits Syst., CAS-
32(11):1097{1104, November 1985.
[5] Paul R. Gray and R. G. Meyer. MOS operational amplier design
{ a tutorial overview. IEEE J. Solid-State Circuits, SC-17(6):969{
982, December 1982.
[6] E. Nordholt. The Design of High-Performance Negative-Feedback
Ampliers. Delft University of Technology, Delft, NL, June 1980.
[7] Eric A. Vittoz. Dynamic analog techniques. In Y. Tsividis and
P. Antognetti, editors, VLSI Circuits for Telecommunication,
pages 145{170. Prentice-Hall, Inc., Englewood Clis, N.J., 1985.
SA CKINGER AND GUGGENBU HL: CMOS DIFFERENTIAL DIFFERENCE AMPLIFIER 7

Fig. 1. The proposed symbol for the dierential dierence amplier (DDA). The two trapezoids symbolize the transconductance elements;
the triangle stands for the high- gain output stage.

Fig. 2. Block diagram of the DDA. The voltages (vPP vPN ) and (vNP vNN ) are converted to current dierences
iP and
iN . These
currents are subtracted on the buses + and  and amplied by the high-gain stage.

Fig. 3. Bipolar and MOS realization of the transconductance element. To achieve a high input voltage range
v an emitter- degeneration
resistor RE must be inserted in the bipolar circuit.

Fig. 4. The CMOS realization of the DDA which was integrated.

Fig. 5. Measured relation between the two port voltages. The NL for this particular device is 0.9% for a full scale voltage of 2V.

Fig. 6. Photomicrograph of the die containing the circuit of Fig. 4. The chip size including the pads is 0:7  0:54mm.

Fig. 7. A plot of Eq. (16) with Ad (VCD0 = 0) = 1 showing the Ad degradation for high VCD0 .

Fig. 8. A plot of Eq. (20) for = 0:97, 0.98, and 0.99 showing degradation of CMRRd caused by tail-current mismatch.

Fig. 9. Oset voltage as a function of VCD0 for several tail- current mismatches according to Eq. (21).

Fig. 10. A regulated cascode current source. By regulating VDS1 to a constant value determined by T2 and I1 , a high- impedance current
source is obtained. Nevertheless the output voltage swing is not sacriced, i.e., it may go as low as VDS 1 when T3 is driven into its linear
region.

Fig. 11. Floating input comparator. The oating voltage vI is compared to VREF . The optional resistors R1 and R2 provide a hysteresis.

Fig. 12. Level shifter. The input voltage vI is shifted by the voltage VS resulting in vO .

Fig. 13. Voltage inverter. This is an amplier with a gain of 1 and no resistors.

Fig. 14. An instrumentation amplier which is programmable by two external resistors for the gain (R1 + R2 )=R1 .

Fig. 15. Voltage-controlled current source. The output current iO is controlled by the voltage vI through the relation iO = vI =R.

Fig. 16. One of the two ports of the DDA can be used to introduce an oset compensation voltage. In this case the second port behaves
like an ordinary op-amp input.