Comm 471: Digital Circuit Design

Lab1

some slides modified from:

S. Dandamudi, “Fundamentals of Computer Organization and Design”

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Course Outline
• Introduction to VHDL and Modelsim
• VHDL Language Basics
• Combinational circuits
• Sequential circuits
• FPGA Basic Flow
• CMOS Inverter
• Static CMOS Gates
• Dynamic CMOS Gates
• Sequential Circuits
• Semiconductor Memories

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Logistics

• TAs:
Ahmed Hamza
Germin Saeed
Mahitab Farouk
• Tools:
ModelSim
Cadence

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Two HDLs Used Today

• VHDL and Verilog.

• Syntax and “appearance” of the two languages are
very different.
• Capabilities and scope are very similar.
• Both are industrial standards and supported by most
software tools.

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VHDL

• VHDL is a language for describing digital hardware

used by industry worldwide

• VHDL is an acronym for VHSIC (Very High Speed

Integrated Circuit) Hardware Description Language

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Features of VHDL and Verilog

• Technology/vendor independent

• Portable

• Reusable

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VHDL Design Flows

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World of Integrated Circuits

Integrated Circuits

Full-Custom Semi-Custom User

ASICs ASICs Programmable
(std cell)

FPGA

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 ASIC versus FPGA-another lecture

ASIC FPGA
Application Specific Field Programmable
Integrated Circuit Gate Array
• Designs must be sent for • Bought off the shelf
expensive and time and reconfigured by
consuming fabrication designers themselves.
in semiconductor foundry.
• Designed all the way from • No physical layout design;
behavioral description design ends with a bitstream
to physical layout. used to configure a device.

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Which Way to Go?
ASICs FPGAs

Off-the-shelf
High performance
Low development cost
Low power
Short time to market
Low cost in
high volumes Reconfigurability

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 What is an FPGA Chip ? -another lecture
• Field Programmable I/O Block
Gate Array
• A chip that can be
configured by user to
implement different
digital hardware
• Configurable Logic
Blocks (CLB) and
Programmable Switch I/O Block

I/O Block
Matrices
• Bitstream to configure:
I/O Block
function of each block &
the interconnection Source: [Brown99]

between logic blocks

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Levels of Design Description

Algorithmic level
Level of description
Register Transfer Level
most suitable for synthesis
Logic (gate) level

Circuit (transistor) level

Physical (layout) level

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How To Learn By Yourself

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VHDL Fundamentals

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Case Sensitivity

• VHDL is not case sensitive

Example:
Names or labels
databus
Databus
DataBus
DATABUS
are all equivalent

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Naming and Labeling
General rules of thumb (according to VHDL-87)

1. All names should start with an alphabet character (a-z or

A-Z)
2. Use only alphabet characters (a-z or A-Z) digits (0-9) and
underscore (_)
3. Do not use any punctuation or reserved characters within
a name (!, ?, ., &, +, -, etc.)
4. Do not use two or more consecutive underscore
characters (__) within a name (e.g., Sel__A is invalid)
5. All names and labels in a given entity and architecture
must be unique
6. All names should not be from the reserved words list
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 Comments
• Comments in VHDL are indicated with a “double dash”, i.e., “--”
•Comment indicator can be placed anywhere in the line
•Any text that follows in the same line is treated as
• a comment
•Carriage return terminates a comment
•No method for commenting a block extending over a couple of
lines
• Examples:
-- main subcircuit
Data_in <= Data_bus; -- reading data from the input FIFO

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Design Entity

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Example: NAND Gate

a b z
a 0 0 1
z
b 0 1 1
1 0 1
1 1 0

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Example VHDL Code
• 3 sections to a piece of VHDL code
• File extension for a VHDL file is .vhd
• Name of the file is usually the entity name (nand_gate.vhd)
LIBRARY ieee;
USE ieee.std_logic_1164.all; LIBRARY DECLARATION

ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC; ENTITY
z : OUT STD_LOGIC);
END nand_gate;

ARCHITECTURE model OF nand_gate IS

BEGIN
ARCHITECTURE
z <= a NAND b;
END model;

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Fundamental Parts Of A Library
• Library is a collection of commonly used pieces of
code, grouped for reuse.
LIBRARY

PACKAGE 1 PACKAGE 2

TYPES TYPES
CONSTANTS CONSTANTS
FUNCTIONS FUNCTIONS
PROCEDURES PROCEDURES
COMPONENTS COMPONENTS

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Library Declarations

LIBRARY ieee;
USE ieee.std_logic_1164.all;
Library declaration
ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC); Use all definitions from the package
END nand_gate; std_logic_1164

ARCHITECTURE model OF nand_gate IS

BEGIN
z <= a NAND b;
END model;

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Library Declarations - Syntax

LIBRARY library_name;
USE library_name.package_name.package_parts;

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Commonly Used Libraries
• ieee
• Specifies multi-level logic system Needs to be
including STD_LOGIC, and explicitly declared
STD_LOGIC_VECTOR data types
• std
• Specifies pre-defined data types (BIT,
BOOLEAN, INTEGER, REAL, SIGNED,
UNSIGNED, etc.), arithmetic
operations, basic type conversion Visible by default
functions, basic text i/o functions, etc.
• work
• User-created designs after compilation

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Design Entity

design entity

entity declaration • Design Entity - most basic

building block of a design.

architecture 1 • One entity can have many

different architectures.
architecture 2

architecture 3

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Entity Declaration

• Entity Declaration describes the interface of the

component, i.e. input and output ports.

Entity name Port type

Port names
Semicolon

ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
No Semicolon
z : OUT STD_LOGIC after last port
);
END nand_gate;

Reserved words Port modes (data flow directions)

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Entity Declaration – Simplified Syntax

ENTITY entity_name IS
PORT (
port_name : port_mode signal_type;
port_name : port_mode signal_type;
………….
port_name : port_mode signal_type);
END entity_name;

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Architecture

• Entity describes the ports of the module

• Architecture describes the functionality of the
module (i.e. what does the module do)
• Architecture example:

ARCHITECTURE model OF nand_gate IS

BEGIN
z <= a NAND b;
END model;

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Architecture – Simplified Syntax

ARCHITECTURE architecture_name OF entity_name IS

[ declarations ]
BEGIN
code
END architecture_name;

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Entity Declaration & Architecture

• nand_gate.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;

ARCHITECTURE model OF nand_gate IS

BEGIN
z <= a NAND b;
END model;

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Thank you

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