2284 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO.

10, OCTOBER 2006

Direct Digital Synthesizer With Sine-Weighted

DAC at 32-GHz Clock Frequency in
InP DHBT Technology
Steven Eugene Turner, Student Member, IEEE, and David E. Kotecki, Senior Member, IEEE

Abstract—A direct digital synthesizer (DDS) implemented in InP TABLE I

double heterojunction bipolar transistor (DHBT) technology is COMPARISON OF RECENTLY REPORTED INP DDS PERFORMANCE
reported. This DDS uses a sine-weighted digital to analog converter
(DAC) architecture that eliminates the need for a ROM. This en-
ables operation at high frequencies with lower power consumption
compared to traditional approaches. The phase accumulator is
8-bits wide and the sine-weighted DAC uses the five most significant
bits (MSBs) for phase to amplitude conversion. The DDS operates
up to a 32-GHz clock frequency for all frequency control words
(FCWs) and can synthesize sine-wave outputs from 125 MHz to
16 GHz in 125-MHz steps. The spurious free dynamic range (SFDR)
is measured over the Nyquist bandwidth to be 31.00 dBc for the
fundamental output frequency of 125 MHz. Over the full range of
FCWs, the worst case SFDR is 21.56 dBc at an FCW of 95, and Worst SFDR over whole range of FCWs is not specified.
the average SFDR is 26.95 dBc. The circuit is implemented with Result is for worst SFDR provided.
1891 transistors and consumes 9.45 W of power.
Index Terms—Accumulator, digital to analog converter (DAC),
direct digital synthesizer (DDS), emitter coupled logic (ECL),
heterojunction bipolar transistor (HBT), high-speed integrated
circuits, indium phosphide (InP).

I. INTRODUCTION

R ECENT work in InP based heterojunction bipolar tran-

sistor (HBT) technology has led to the development of a
process capable of yielding complex digital and mixed-signal
circuits operating at mm-wave frequencies. The process re-
ported in [1] has demonstrated HBT devices with 0.35 m
emitter widths and with and both over 300 GHz. This
process overcomes traditional HBT processing limitations by
using a self-aligned device structure that enables very small
feature sizes and eliminates manufacturing limitations asso-
ciated with optical lithography. The process uses a double
heterojunction bipolar transistor (DHBT) device structure
with an open-base breakdown voltage over 4 V. The
DHBT devices are integrated in a process with four layers of
metal, precision resistors, and metal–insulator–metal (MIM)
capacitors. These features make the process very well suited for
mixed-signal circuits. The inherent speed of this process was
demonstrated using a series of benchmark circuits, including a
common-mode logic (CML) ring oscillator with 1.95 ps gate
delay and a static frequency divider operating at 152 GHz [1].
Fig. 1. Block diagram of a direct digital synthesizer with the outputs of each
stage illustrated.
In this work, we demonstrate a direct digital synthesizer
(DDS) circuit using the aforementioned process. The goal of this
effort is to demonstrate the ability to yield large-scale mixed-
signal circuits that benefit from the features of the technology.
Design challenges included the development of an efficient
phase accumulator and sine-weighted DAC, and the distribution
of mm-wave clock and data signals across the chip. Measured
results verified proper operation of the DDS at clock rates up to
32 GHz. At such high clock rates, DDS circuits are suitable for
applications in communication systems and radars. A compar-
ison to recently reported DDS circuits is shown in Table I.
II. CIRCUIT DESIGN

Manuscript received December 7, 2005; revised April 21, 2006. This work
The basic DDS architecture [2] consists of a phase accumu-
was supported by the U.S. Army Research Laboratory and by the Defense Ad- lator, phase converter, and digital-to-analog converter (DAC).
vanced Research Projects Agency (DARPA) under Contract DAAD17-02-C- In this design the phase converter and DAC are combined into
0115. a sine-weighted DAC, resulting in the DDS architecture shown
The authors are with the Department of Electrical and Computer Engineering,
University of Maine, Orono, ME 04469 USA. in Fig. 1. The sine-weighted DAC is an alternative to the tradi-
Digital Object Identifier 10.1109/JSSC.2006.881552 tional approach of using ROM look-up tables. This is a similar
0018-9200/$20.00 © 2006 IEEE
TURNER AND KOTECKI: DIRECT DIGITAL SYNTHESIZER WITH SINE-WEIGHTED DAC AT 32-GHZ CLOCK FREQUENCY IN INP DHBT TECHNOLOGY 2285

Fig. 2. Block diagram of the modular, pipelined 8-bit phase accumulator built from 2-bit adder-accumulator blocks and 2-bit register blocks for pipelining.

approach to the cosine-weighted DAC implemented in [3], [4].

Since the phase converter circuitry is eliminated, this approach
allows for a reduction in circuit complexity and a reduction in
power consumption. The accumulator is 8 bits wide, so the DDS
frequency resolution is 1/256 of the clock frequency with
128 steps of frequency control. The sine-weighted DAC uses the
five most significant bits (MSBs) from the accumulator to gen-
erate a full-wave sine output. The DDS uses two power supplies,
with the accumulator circuitry at 3.6 V and the DAC circuitry
at 4.5 V.

A. Phase Accumulator
The 8-bit phase accumulator shown in Fig. 2 uses a modular,
pipelined structure built from four 2-bit adder-accumulators [5].
The individual 2-bit accumulator shown in Fig. 3 is built from
sum, carry, and latch circuits. These circuits are based on an
emitter coupled logic (ECL) topology, which is well-suited for
InP DHBT devices. The sum circuit uses two separate XOR gates
followed by a latch, as shown in Fig. 4(a). Since the first XOR
gate in the sum circuit is driven by the frequency control word
and the sum from the previous state, its output settles shortly
after the clock transition. As a result, the overall propagation
delay of the sum circuit is dominated by the propagation delay
of the second XOR gate, which is dependent on the carry input.
The propagation delay from the carry input to the XOR output is
simulated to be 6.35 ps.
In order to achieve a high-speed accumulator, the parallel-
gated carry circuit [6] shown in Fig. 4(b) is implemented to min-
imize the propagation delay through the carry signal path. This
configuration works as a three-input majority circuit, where the
output is high when either two or three of the inputs are high.
While this carry has a reduced output differential signal for some
states, a full differential signal is recovered by the latch circuit.
Since it uses parallel gates with a single level of logic, the par-
allel-gated carry circuit allows for high-speed operation at a low
supply voltage. Coincidentally, the carry gate also has a simu-
lated propagation delay of 6.35 ps.
Fig. 3. Block diagram of a 2-bit adder-accumulator.
Since the simulated propagation delays for the sum and carry
circuits are equal, the critical path of the accumulator is ei-
ther through one carry gate, one sum gate, and two latches, or
through two carry gates and two latches. Using the total propa-
gation delay of either critical path, the maximum operating fre-
quency of the accumulator can be estimated. The latch circuit
has a simulated propagation delay of 8.37 ps, so the total prop-
agation delay through the critical paths is 29.44 ps. The critical
path propagation delay represents the shortest clock period, or
the maximum operating frequency. In this case, the maximum
estimated operating frequency of the accumulator is approxi-
mately 34 GHz. This is determined from the worst case tran-
sitions. It should be noted that skew in the data paths prevents
the design from improving the speed by tuning the clock delay.
This estimated maximum operating frequency is also optimistic
because it excludes many of the interconnect parasitic capac-
itances. From simulations including the parasitic interconnect
capacitances extracted from the physical layout, the maximum
2286
Fig. 4. Schematics of the (a) sum and (b) parallel-gated carry circuits.
operating frequency of the 8-bit accumulator is 28 GHz, how-
ever, measured results indicate that the accumulator operates up
to 32 GHz.
While it has a similar topology to previously reported
high-speed accumulators [6], [7], this design implements tech-
niques for reduced power consumption. Unlike the previous
designs, the sum and carry gates in this design are not cascaded
with latches. While this reduces the maximum operating speed,
it also allows for the elimination of two diode drops from the
supply voltage compared to the first design [6] and one diode
drop compared to the second design [7]. This leads to a direct
savings in power, particularly in the register circuits. If the
41-GHz design [6] were extended to an 8-bit accumulator,
it is estimated that it would consume 7.86 W, with two 4-bit
accumulator cores at 2.86 W each and one 4-bit register block
at 2.12 W. An extension of the 40-GHz reduced power accumu-
lator [7] to 8 bits is estimated to use 6.39 W, with two 2.38-W
4-bit accumulator cores and a 1.63-W 4-bit register. In this
design, the two 4-bit accumulator cores each consume 1.76 W
and the 4-bit register consumes 1.38 W, for a total of 4.90 W for
the 8-bit accumulator. Compared to the previous designs, this
design has a 30%–32% reduction in operating frequency and a
23%–37.5% reduction in power consumption. The comparison
for speed is pessimistic, because the reduction in operating
frequency due the parasitic interconnection capacitances added
by expanding from a 4-bit accumulator to an 8-bit accumulator
are not taken into account for the two previous designs. Com-
parisons of the accumulator designs are shown in Table II.
B. Sine-Weighted DAC
The sine-weighted DAC uses the five MSBs ( , , , ,
) from the accumulator to generate a full-wave sine output. It
is comprised of a thermometer-coder, a sine-weighted summing
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 10, OCTOBER 2006
TABLE II
COMPARISON OF THE POWER AND SPEED IN 8-BIT
ACCUMULATOR ARCHITECTURES
junction, and a Gilbert multiplier [8]. In the thermometer-coder,
the output from the accumulator complements the lower three
bits to expand the thermometer-coder from a quarter-wave to a
half-wave output. As shown in Fig. 5, the complemented bits are
registered to meet timing requirements, then buffered to drive
the thermometer-coder logic. The thermometer-coder outputs
drive the sine-weighted taps of the summing junction, which has
a tap weighting scheme of . The DAC is driven by
a thermometer coder, thus the weights sum successively to gen-
erate a quarter-wave sine output. The first tap weight of 3 is al-
ways enabled to ensure that the summing junction has non-zero
outputs for all states. This ensures that distinct positive and neg-
ative outputs exist for each state after the analog sum is inverted
by the Gilbert multiplier, and it results in a center step level equal
to 6. The Gilbert multiplier uses the accumulator MSB as a
control signal for inversion, resulting in a full-wave sine output.
The sine-weighted summing junction and the Gilbert multiplier
are shown in Fig. 6.
The DAC in this design is implemented in a different manner
than the DAC presented in [3] and [4]. The DAC in [3] and [4]
uses a combination of a three-bit cosine-weighted DAC and a
slope magnitude DAC to achieve a full sine-wave output. The
DAC in this work uses a 5-bit sine-weighted DAC to achieve
a half sine-wave output, followed by a Gilbert multiplier that
TURNER AND KOTECKI: DIRECT DIGITAL SYNTHESIZER WITH SINE-WEIGHTED DAC AT 32-GHZ CLOCK FREQUENCY IN INP DHBT TECHNOLOGY
Fig. 5. Block diagram of the thermometer-coder portion of the sine-weighted
DAC.
Fig. 6. Block diagram of the summing junction and Gilbert multiplier showing
the [3 5 5 4 4 3 2 1] tap weighting scheme.
performs an analog output inversion to achieve a full sine-wave
output. Overall, the sine-weighted DAC consumes 4.4 W of
power, with 3.3 W due to the thermometer-coder and 1.1 W due
to the summing junction/Gilbert multiplier.
C. Phase Truncation Spur Magnitude and Location
Since this design does not use all of the output bits from the
accumulator, spurs due to phase truncation arise. Fairly simple
formulas for determining the location and magnitude of these
spurs have been developed [9]. The magnitude and locations
of the spurs are a function of the accumulator bit-width ,
the number of bits used for phase conversion , the number
of bits truncated , the frequency control word (FCW), and
the clock frequency . The spurious free dynamic range
(SFDR) (in dBc) is the power magnitude of the worst case phase
truncation spur below the desired output. The analysis in [9]
estimates the upper bound SFDR from phase truncation as
SFDR dBc (1)
The actual SFDR is a function of both and the normalized
output frequency [9], so the upper bound esti-
mate discards the impact from the normalized output frequency.
In reality, the SFDR is reduced by a few dBc for normalized
output frequencies approaching 1/2. In this design, is equal
to 5, so the upper bound on SFDR is about 30 dBc.
Combining terms from [9], the location of the worst case spur
from phase truncation is given by
FCW (2)
2287
where is the value of the truncated LSBs of the frequency
control word. Note that when these spurs are outside of the
Nyquist band (0 to ), they will be aliased back into band.
While (2) gives the location of the worst case phase truncation
spur, other spurs will be located at harmonics of the desired
output and harmonics of the worst case phase truncation spur,
as well as intermodulations of these signals. Additional spurs
occur due to offsets in the Gilbert multiplier and from non-lin-
earities in the DAC.
This design has and , so for the case when
FCW we would expect the worse case phase truncation
spurs (taking aliasing into account) to be located at
. Intuitively, when , the DAC output only
changes every eight clock cycles. Because of this, we would
expect a spurs at a frequency of mixed with the desired
output of .
D. Clock Distribution
In order to achieve high-speed performance, the digital por-
tion of the DDS contains many pipeline registers. Each reg-
ister requires a clock signal, but these clock tree interconnects
start to become electrically long at high frequencies and can not
be modelled by traditional lumped element techniques. A dig-
ital clock interconnect is considered electrically long when its
length exceeds 1/6 of the effective length of a rising edge [10].
This is expressed as
(3)
where is the length where interconnects become electrically
long, is the rise time, and is the interconnect delay per
unit length. For a 30-GHz clock signal with a clock rise time of
11 ps and a delay of approximately 6 fs m, lines longer than
about 300 m would be considered to be electrically long.
In the clock tree, the clock signal is distributed to sub-circuits
where it is buffered and re-distributed to the pipeline registers.
The clock interconnects within the sub-circuits are intention-
ally kept shorter than 300 m, so they can be treated as lumped
element lines. The main clock distribution interconnects, how-
ever, can not be made shorter than 300 m in length and must
be treated as transmission lines. These electrically long inter-
connects are designed to be matched and balanced, so that all
of the clock drivers have the similar loads and all of the clock
interconnects have approximately the same length, run on top
of the same metals layers. This ensures that the clock arrives at
the sub-circuit clock buffers with as close to the same phase and
timing as possible.
In order to further deal with limitations of the lumped ele-
ments, the clock tree is simulated over a range of clock frequen-
cies with the clock distribution interconnects modelled as mi-
crostrip transmission lines with line lengths, characteristic im-
pedances, and loads estimated from the physical layout. These
simulations aid in pinpointing frequencies where the clock sig-
nals feeding the registers are potentially overdamped or under-
damped. Fig. 7 shows the simulation results at register inputs
for a frequency sweep of best case and worse case clock sig-
nals. In these simulations, the clock signal magnitude is nor-
malized so that clock levels above 0 dB are strong enough to
2288
Fig. 7. Simulation of the clock distribution interconnects as microstrip trans-
mission lines with line lengths, characteristic impedances, and loads estimated
from the physical layout. The best case and worst case register inputs are shown
both before and after the addition of series resistors to the clock distribution
paths. Without the series resistors, there is some potential for overdrive in the
worst case register inputs. The series resistors reduce the overdrive while main-
taining a clock bandwidth well above the operating frequency of the accumu-
lator and DDS circuitry.
Fig. 8. Microphotograph of the DDS test chip. The chip has dimensions of
2700 m by 1450 m and contains 1891 transistors.
drive registers. Initially, simulations without series resistors in
the clock distribution path showed that the worst case register
inputs peaked 2.1 dB over the nominal normalized clock signal
magnitude at 30 GHz. This peaking could potentially overdrive
the clock buffers and registers, so resistors were added in series
between the emitter followers of the clock drivers and the long
microstrip transmission lines feeding the registers. These resis-
tors absorb reflections on the microstrip transmission lines and
reduce the clock overshoot to acceptable levels. As can be seen
in Fig. 7, adding series resistors in the clock distribution path
reduces the overshoot down to acceptable levels. The best case
register input has the least clock bandwidth of all the register
inputs after the series resistors are added. However, the addi-
tion of the series resistors does not negatively impact DDS per-
formance because this register clock input still has 36 GHz of
bandwidth, which is well above the accumulator and DDS op-
erating frequency.
III. MEASUREMENT RESULTS
A microphotograph of the fabricated DDS test chip is shown
in Fig. 8. The fabricated DDS test chip has 1891 transistors in
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 10, OCTOBER 2006
Fig. 9. SFDR versus DDS output frequency at a 32-GHz clock rate. The SFDR
is measured within the Nyquist bandwidth. The worst SFDR is 21.56 dBc at an
FCW of 95. Over the whole range of FCWs, the average SFDR is 26.95 dBc.
Fig. 10. Sampling oscilloscope output of the DDS with f = 32 GHz and
f = 125 MHz.
an area of 2700 m by 1450 m. The DDS test chip was imple-
mented using Vitesse’s VIP-2 InP DHBT process [1], which has
both and over 300 GHz. The DDS was tested using a
probe station and high-frequency probes. The DDS clock input
is differential, but it is driven single-ended, with the non-driven
side connected to ground through a 50- termination. The DDS
output is also differential, with one single-ended output driving
a spectrum analyzer and the other single-ended output driving a
high-frequency sampling oscilloscope.
The DDS operates up to a maximum clock frequency of
32 GHz for all frequency control words. A full sweep of all
FCWs at 32 GHz is shown in Fig. 9. For all SFDR measurements,
the SFDR is measured within the full Nyquist bandwidth. The
worst case SFDR over the range of FCWs is 21.56 dBc at an FCW
of 95, which corresponds to an output frequency of 11.875 GHz.
The average SFDR over the whole range of FCWs is 26.95 dBc.
The maximum operation frequency is better than expected from
simulation, since the DDS operates up to a maximum clock
frequency of 32 GHz instead of 28 GHz.
A 125-MHz sine-wave output synthesized from a 32-GHz
clock frequency with FCW is shown in Fig. 10. This output
TURNER AND KOTECKI: DIRECT DIGITAL SYNTHESIZER WITH SINE-WEIGHTED DAC AT 32-GHZ CLOCK FREQUENCY IN INP DHBT TECHNOLOGY
Fig. 11. Frequency spectrum of the DDS output with f = 32 GHz and
f = 125 MHz at FCW = 1. The largest spur is located at 4.125 GHz and
the SFDR is 31.00 dBc.
Fig. 12. Frequency spectrum of the DDS output with f = 32 GHz and
f = 15:875 GHz at FCW = 127. The largest spur is located at 12.125 GHz
and the SFDR is 30.44 dBc.
represents the fundamental output frequency and frequency
resolution of the DDS with a 32-GHz clock. With an output fre-
quency of 125 MHz, the DDS has an SFDR of 31.00 dBc with
the largest in-band spur located at 4.125 GHz. The frequency
spectrum of this output is shown in Fig. 11. The worst spurs
in the output spectrum are due to the truncation of the phase
word from the accumulator to the sine-weighted DAC. They are
located at , which matches the analysis from
(2). The largest of the additional spurs occur at harmonics of the
worst case spurs. The SFDR magnitude is 31.00 dBc, which is
close to the 30 dBc result predicted from (1) for a DDS using
five bits for phase conversion.
To illustrate high output frequency operation of the DDS, the
frequency spectrum of the DDS with FCW is shown
in Fig. 12. At this FCW, the output frequency is 15.875 GHz
and the SFDR is 30.44 dBc. The largest in-band spur is located
2289
at 12.125 GHz, with a similar magnitude spur at 11.875 GHz.
These are truncation spurs located at aliased frequencies of what
would be expected from (2).
Overall, the DDS test chip consumes a total power of 9.45 W,
with 0.15 W due to input buffers, 4.9 W due to the 8-bit accu-
mulator, and 4.4 W due to the sine-weighted DAC. These power
figures are about 10% lower than expected from simulations.
IV. CONCLUSION
A DDS implemented in InP DHBTs and using a sine-
weighted DAC is presented. The sine-weighted DAC approach
eliminates the need for phase converter circuitry, which results
in reduced circuit complexity and lower power consumption
compared to traditional DDS approaches. The DDS is capable
of operation up to a 32-GHz clock frequency for all frequency
control words. It can synthesize sine-wave outputs from 125
MHz to 16 GHz with a frequency resolution of 125 MHz. The
SFDR is 31.00 dBc SFDR for FCW and 30.44 dBc for
FCW . The worst case SFDR over the full FCW range is
21.56 dBc at FCW , and the average SFDR is 26.95 dBc.
This DDS successfully demonstrates the potential for imple-
mentations of moderately complex mixed-signal circuits op-
erating at microwave frequencies. This is enabled by the ad-
vanced InP process. Further work is being done to increase the
frequency resolution and SFDR by extending the accumulator,
modifying the DAC, and increasing its resolution.
ACKNOWLEDGMENT
The authors would like to thank F. Stroili, R. Elder, Jr.,
D. Jansen, and J. Feng at BAE Systems, Dr. J. Zolper and Dr.
S. Pappert at DARPA, and Dr. A. Hung at the Army Research
Laboratory for supporting this work.
REFERENCES
[1] G. He, J. Howard, M. Le, P. Partyka, B. Li, G. Kim, R. Hess, R. Bryie,
R. Lee, S. Rustomji, J. Pepper, M. Kail, M. Helix, R. Elder, D. Jansen,
N. E. Harff, J. Prairie, and E. S. Daniel, “Self-aligned InP DHBT with
f and f over 300 GHz in a new manufacturable technology,” IEEE
Electron Device Lett., vol. 25, no. 8, pp. 520–522, Aug. 2004.
[2] J. Tierney, C. M. Rader, and B. Gold, “A digital frequency synthesizer,”
IEEE Trans. Audio Electroacoust., vol. AU-19, no. 1, pp. 48–57, Mar.
1971.
[3] A. Gutierrez-Aitken, J. Matsui, E. Kaneshiro, B. Oyama, D. Sawdai,
A. Oki, and D. Streit, “Ultra high speed direct digital synthesizer using
InP DHBT technology,” in GaAs IC Symp. Tech. Dig., Oct. 2001, pp.
265–268.
[4] A. Gutierrez-Aitken, J. Matsui, E. N. Kaneshiro, B. K. Oyama, D.
Sawdai, A. K. Oki, and D. C. Streit, “Ultrahigh-speed direct digital
synthesizer using InP DHBT technology,” IEEE J. Solid-State Circuits,
vol. 37, no. 9, pp. 1115–1119, Sep. 2002.
[5] C. G. Eckroot and S. I. Long, “A GaAs 4-bit adder-accumulator circuit
for direct digital synthesis,” IEEE J. Solid-State Circuits, vol. 23, no.
2, pp. 573–580, Apr. 1988.
[6] S. E. Turner, R. B. Elder, Jr, D. S. Jansen, and D. E. Kotecki, “4-bit
adder-accumulator at 41-GHz clock frequency in InP DHBT tech-
nology,” IEEE Microwave Wireless Compon. Lett., vol. 15, no. 3, pp.
144–146, Mar. 2005.
[7] S. E. Turner and D. E. Kotecki, “Benchmark results for high-speed 4-bit
accumulators implemented in indium phosphide DHBT technology,”
Int. J. High Speed Electronics and Devices, vol. 14, no. 3, pp. 646–651,
Aug. 2004.
[8] B. Gilbert, “A precise four-quadrant multiplier with subnanosecond
response,” IEEE J. Solid-State Circuits, vol. SC-3, no. 4, pp. 365–373,
Dec. 1968.
2290 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 10, OCTOBER 2006

[9] V. F. Kroupa, V. Cizek, J. Stursa, and H. Svandova, “Spurious signals David E. Kotecki (S’78–M’88–SM’00) received
in direct digital frequency synthesizers due to the phase truncation,” the B.E.E. degree in electrical engineering from the
IEEE Trans. Ultrason., Ferroelect., Freq. Contr., vol. 47, no. 5, pp. University of Dayton, Dayton, OH, in 1981, and
1166–1172, Sep. 2000. the M.S. and Ph.D. degrees in engineering applied
[10] H. W. Johnson and M. Graham, High-Speed Digital Design. Engle- science from the University of California, Davis, in
wood Cliffs, NJ: PTR Prentice-Hall, 1993. 1984 and 1988, respectively.
[11] K. R. Elliott, “Direct digital synthesis for enabling next generation RF From 1988 to 1999, he was with IBM Microelec-
systems,” in CSIC Dig., Nov. 2005, pp. 125–128. tronics, Hopewell Junction, NY. He is currently an
[12] S. E. Turner and D. E. Kotecki, “Direct digital synthesizer with ROM- Associate Professor in the Electrical and Computer
less architecture at 13-GHz clock frequency in InP DHBT technology,” Engineering Department, University of Maine,
IEEE Microwave Wireless Compon. Lett., vol. 16, no. 5, pp. 296–298, Orono. He has received over 60 U.S. patents for
May 2006. inventions related to semiconductor processing, microelectronic structures and
devices, and has authored or co-authored more than 50 papers in these areas.
Steven Eugene Turner (S’99) received the B.S. de-
gree in electrical and computer engineering, the M.S.
degree in computer engineering, and the Ph.D. de-
gree in electrical engineering, all from the University
of Maine, Orono, in 2001, 2003, and 2006, respec-
tively.
Since September 2001, he has served as a Re-
search Assistant at the University of Maine. During
the summer months, he has served internships at
Tundra Semiconductor in South Portland, ME, and
BAE Systems in Nashua, NH. His current research
interests include high-speed digital and mixed-signal microelectronics design.