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Document Title
256Kx16 bit Low Power full CMOS Static RAM
Revision History
Revision No. History Draft Date Remark
0.0 Initial draft July 26, 2002 Preliminary
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1 Revision 1.0
September 2003
K6X4016C3F Family CMOS SRAM
256Kx16 bit Low Power full CMOS Static RAM
FEATURES GENERAL DESCRIPTION
• Process Technology: Full CMOS The K6X4016C3F families are fabricated by SAMSUNG′s
• Organization: 256Kx16 advanced full CMOS process technology. The families sup-
• Power Supply Voltage: 4.5~5.5V port various operating temperature range and small pack-
• Low Data Retention Voltage: 2V(Min)
age types for user flexibility of system design. The families
• Three state output and TTL compatible
also support low data retention voltage for battery back-up
• Package Type: 44-TSOP2-400F
operation with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product Family Operating Temperature Vcc Range Speed Standby Operating PKG Type
(ISB1, Max) (ICC2, Max)
K6X4016C3F-B Commercial(0~70°C)
20 µA
K6X4016C3F-F Industrial (-40~85°C) 4.5~5.5V 551)/70ns 30 mA 44-TSOP2-400F
Data
cont
Name Function Name Function Column Addresses
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2 Revision 1.0
September 2003
K6X4016C3F Family CMOS SRAM
PRODUCT LIST
Commercial Products(0~70°°C) Industrial Products(-40~85°°C) Automotive Products(-40~125°°C)
Part Name Function Part Name Function Part Name Function
K6X4016C3F-TB55 44-TSOP2-F, 55ns, LL K6X4016C3F-TF55 44-TSOP2-F, 55ns, LL K6X4016C3F-TQ55 44-TSOP2-F, 55ns, L
K6X4016C3F-TB70 44-TSOP2-F, 70ns, LL K6X4016C3F-TF70 44-TSOP2-F, 70ns, LL K6X4016C3F-TQ70 44-TSOP2-F, 70ns, L
FUNCTIONAL DESCRIPTION
CS OE WE LB UB I/O1~8 I/O9~16 Mode Power
H X1) X1) X1) X1) High-Z High-Z Deselected Standby
L H H X 1) X1) High-Z High-Z Output Disabled Active
L X1) X1) H H High-Z High-Z Output Disabled Active
L L H L H Dout High-Z Lower Byte Read Active
L L H H L High-Z Dout Upper Byte Read Active
L L H L L Dout Dout Word Read Active
L X1) L L H Din High-Z Lower Byte Write Active
L X 1) L H L High-Z Din Upper Byte Write Active
L X1) L L L Din Din Word Write Active
1. X means don′t care. (Must be in low or high state)
3 Revision 1.0
September 2003
K6X4016C3F Family CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item Symbol Min Typ Max Unit
Supply voltage Vcc 4.5 5.0 5.5 V
Ground Vss 0 0 0 V
Input high voltage VIH 2.2 - Vcc+0.52) V
Input low voltage VIL -0.5 3) - 0.8 V
Note:
1. Commercial Product: TA=0 to 70°C, otherwise specified
Industrial Product: TA=-40 to 85°C, otherwise specified
Automotive Product TA=-40 to 125°C, otherwise specified
2. Overshoot: VCC+3.0V in case of pulse width ≤ 30ns
3. Undershoot: -3.0V in case of pulse width ≤ 30ns
4. Overshoot and undershoot are sampled, not 100% tested
4 Revision 1.0
September 2003
K6X4016C3F Family CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level: 0.8 to 2.4V
Input rising and falling time: 5ns CL1)
Input and output reference voltage: 1.5V
Output load (See right): CL=100pF+1TTL
CL=50pF+1TTL 1. Including scope and jig capacitance
AC CHARACTERISTICS
( Vcc=4.5~5.5V, Commercial Product: TA=0 to 70°C, Industrial Product: TA=-40 to 85°C, Automotive Product : TA=-40 to 125°C, )
Speed Bins
Parameter List Symbol 55ns 70ns Units
5 Revision 1.0
September 2003
K6X4016C3F Family CMOS SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Out Previous Data Valid Data Valid
tRC
Address
tAA tOH
tCO
CS
tHZ
tBA
UB, LB
tBHZ
tOE
OE
tOLZ
tBLZ tOHZ
tLZ
Data out High-Z Data Valid
6 Revision 1.0
September 2003
K6X4016C3F Family CMOS SRAM
tWC
Address
tWR(4)
tCW(2)
CS
tAW
tBW
UB, LB
tWP(1)
WE
tAS(3)
tDW tDH
tWHZ tOW
tWC
Address
tAS(3) tCW(2)
tWR(4)
CS
tAW
tBW
UB, LB
tWP(1)
WE
tDW tDH
7 Revision 1.0
September 2003
K6X4016C3F Family CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
tWC
Address
tCW(2)
tWR(4)
CS
tAW
tBW
UB, LB
tAS(3)
tWP(1)
WE
tDW tDH
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-
tion when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
2.2V
VDR
CS≥VCC - 0.2V
CS
GND
8 Revision 1.0
September 2003
K6X4016C3F Family CMOS SRAM
PACKAGE DIMENSIONS Units: millimeter(inch)
#44 #23
0.45 ~0.75
0.018 ~ 0.030
0.400
11.76±0.20
10.16
0.463±0.008
( 0.50 )
0.020
#1 #22
1.00±0.10 + 0.1
0
5
0.039±0.004 - 0.0
0.15 04
18.81 1.20 + 0.0
MAX. 6 .002
0.741 0.047
MAX. 0.00 - 0
18.41±0.10
0.725±0.004
0.10
0.004 MAX
MIN.
0.35±0.10 0.80
( 0.805 )
0.002
0.05
9 Revision 1.0
September 2003
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