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6 5 4 3 2 1

REVISION RECORD

LTR ECO NO: APPROVED: DATE:

D D

RF ANT
ANT101
RF TRANSCEIVER
1900008M001 CN102
Impedance be 50ohm 4700023M001 Impedance be 50ohm

[1]
DCS/PCS/TD_IN [1]
ANT102 R101 R102 C101 47pF

UGSM/EGSM_IN
2 1 VDDRF0
ANT_CON[1]
OUT IN

DNP

DNP
1900008M001 0 0

DNP
VDDRF0

4
3
VDDRF VDDRF0
5.1nH
L101

ANT103

L102
DNP
U103

L104

L105
1900008M001

L2
7300094M001

C132

C136
R109
C121 1.2pF
[1] EGSM/GSM_RX C116 47pF 1 3
0

1uF

1uF
4

27nH
L112
27nH
L108

5
C122 1.2pF

C9

D8

C8
A4

B4

A5

A6

A7

A8

A9

B9
VDD_RX

VDD_RXLO

LB1HB1_TX

LB2HB2_TX

HB3_TX

HB4UHB1_TX

UHB2_TX

VDD_TX

VDD_TXLO

PDET_GND

PDET
L118
U104
7300278M001 C123 2.2pF

10
DNP

GND
A3 E8
C150 22pF LB1_RX+ SPI1_LE RF_SPI_LE [4]
DCS_RX 1 9
[1]

5.6nH
BALANCE 8

L113
2 1842.5MHZ A2 E9 RF_SPI_CLK
LB1_RX- SPI1_CLK [4]
3 GND GND 7
C117 22pF 4 GND GND 6 D9
[1] PCS_RX BALANCE SPI1_DATA RF_SPI_DATA [4]
1960MHZ
C124

GND
2.2pF

DNP
A1
LB2_RX+

5
F5
SPI2_LE
B1
LB2_RX-
E4

L109
SPI2_CLK
E5
SPI2_DATA
VRAMP TXEN Ctrl_2 Ctrl_1 Ctrl_0 VDDRF0

C PA MODULE RX1 UGSM/EGSM


RX2 DCS
0
0
0
0
1
1
0
1
0
0
C1

D1
HB1_RX+

HB1_RX-
VDD_DCXO

VDD_DIG
F9

F8
C
VDDRF0
U101
RX3 PCS 0 0 0 1 1 E1 7101369M001
HB2_RX+ C138 1000pF
G9 MCLK_26M [2]
REF1_OUT
RX4 TD_1.9G/2G_RX 0 0 0 0 1 F1
HB2_RX-
H9 R110 0
C142
1uF
REF1_EN
TX LB GSM RAMP 1 0 1 0
C128 1.5pF
TX HB GSM RAMP 1 0 1 1 U105
G1
UHB1_RX+ REF2_OUT
G8

5.6nH
10

L115
7300240M001 H1 H8
UHB1_RX- REF2_EN
TX LB EDGE 1 1 0 0 0

GND
9 VDDRF0
C118 47pF 1.5pF
1 BALANCE_1900M 8 C127
[1] TD_RX
TX HB EDGE 1 1 0 0 1 2
3
UNBALANCE
GND
BALANCE_1900M
E6 C143 1000pF BT/WIFI_26M [7]
C130 1.5pF REF3_OUT
4 GND 7
TD-SCDMA-1.9G/2G HPM X 1 1 0 1 GND BALANCE_2017.5M 6 J1 D5 R111 0

DNP
BALANCE_2017.5M UHB2_RX+ REF3_EN

GND
J2
UHB2_RX-
TD-SCDMA-1.9G/2G LPM X 1 1 0 0

5.6nH
L116
[1] EGSM/GSM_RX

L110

5
[1] DCS_RX J9
REF_IN+ REF_IN+ [1]

VDD_SYNTH
[1] PCS_RX J8
REF_IN- REF_IN- [1]

TRX1_Q+

TRX2_Q+
TRX1_Q-

TRX2_Q-
VDD_BB

TRX1_I+

TRX2_I+
C129

TRX1_I-

TRX2_I-
1.5pF
[1] TD_RX

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND
17

18

19

20

21

22

23

H3

J3

J5

H5

J4

H4

J7

H7

J6

H6

B8

G2

H2

C2

D2

D4

D6

E2

F2

F4

F6

B7

B6

B5

B3

B2
RX3

RX2

RX1

GND

GND

GND

GND

L106
C109 22pF
DCS/PCS/TD_IN [1]
2.4nH
1 VDDRF0
GND
C111 C112
16 2
RX4 RFIN_HB
15 3 3.3pF 3.3pF
[1] ANT_CON ANTENNA U102 GND
14 7101408M001 4 L117
TD_EN RFIN_LB
13 5
GPCTRL3 GND 10nH
GPCTRL2

GPCTRL1

GPCTRL0

6 L120
C120
VRAMP

GND
VBATT

56pF
TX_EN

UGSM/EGSM_IN [1]
5.6nH

C145

C144
C114
12

11

10

C113
VBAT

1uF
3.3pF

100pF
3.3pF
C102

C103

C104
0.1uF

ramp network
10uF

47pF

R103 1.5K
APCOUT [2]

TD_IP
TD_IN
TD_QP
TD_QN
GSM_QP
[2] GSM_QN
R104

C115

GSM_IN

GSM_IP
10M

[4] RFCTRL15_CTRL2 470pF

[2]
[2]
[2]
[4] RFCTRL14_CTRL1

[2]
[2]

[2]

[2]
[4] RFCTRL12_CTRL0
[4] RFCTRL10_PA_TXEN
C105

C106

C107

C108

B B
47pF

47pF

47pF

47pF

26MHz DCXO or TCXO


Y101
26MHz

1
[1] REF_IN+ REF_IN- [1]

4
DCXO,TCXO selection
VALUE R116 R115 R117 R118 C148 C149
DCXO NF NF 0ohm 0ohm 0ohm NF
TCXO 0ohm 0ohm NF 100pF 0.1uF 1000pF

A A

COMPANY:

TITLE:

DRAWN: DATED:

CHECKED: DATED:
CODE: SZE: DRAWING NO: REV:

QUALITY CONTROL: DATED:

RELEASED: DATED:
SCALE: SHEET: OF
6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

ABB_ANALOG ABB_POWER
VBAT VBAT VBAT VBAT

R218
C230

C232

C234
C231

C233

C235

C236
C237
If use TCXO for RF, C201 must be mounted. 0.01uF

4.7uF

4.7uF

4.7uF
0.1uF

0.1uF

0.1uF

4.7uF

0
OSC32KI [2]

[2]

[2]
OSC32KO[2]

[1]
Power Output Voltage (V) Output Current Used Voltage Default

OPTION1

OPTION2

APCOUT
AFCOUT
VDDRTC
VBATBK

C202

C204
C201

C203

N11

D11
P11

K11
VDD1V8 1.2/1.3/1.5/1.8 250mA 1.8V ON

L11

J11
D7
P7

E5
F7
D D

DNP

0.1uF

VBAT_BUCK

VBATD

VBATD

VBATD

VBATD

VBATPA

VBATPA

AVDD36

AVDD36

AVDD36
470pF

470pF
AVDDBB
D12
VDD2V5 2.5/2.75/2.9/3.0 110mA 2.5V ON

D17

D16

E14

E17

E16

E15

A16

A15

A13
F12

F15

F14

F16

B9

B8

B6
VBAT E11
AVDDBB AVDDBB

VDD2V8 1.8/2.65/2.8/3.0 250mA 2.8V ON

OSC32KI

OSC32KO

VBATBK

VDDRTC

OPTION0

OPTION1

OPTION2

OPTION3

OPTION4

OPTION5

AFCREF

AFCOUT

APCOUT

TXREF

TDRXREF

TDTXREF
V8 F11
VBATDRV_CORE AVDDBB
C214 DNP V9
VBAT
VBATDRV_CORE
M16
C215 AVDDVB AVDDVB
4.7uF W8
VDDSIM0 1.8/2.9/3.0/3.1 80mA 1.8/3.0V OFF

DC2DC CORE
VBATDRV_CORE
VDDCORE N17
AVDDAO AVDDA0
Y8
L201 LX_CORE
K2 A11
[4]

[4]
ADI_SCLK

ADI_SYNC
K3
ADI_SCLK

ADI_SYNC RTC Option RF Contrl


TRXIP

TRXIN
B10
GSM_IP [1]

GSM_IN[1]
SPH252012H2R2MT
W9
Y9
LX_CORE AVDDPA
P16 AVDDPA
VDDSIM1 1.8/2.9/3.0/3.1 80mA 1.8/3.0V OFF

C217
LX_CORE
V4
K4 A8 DDR2_BUFOUT DDR2_BUFOUT
[4] ADI_D ADI_D TRXQP GSM_QP[1]

TRXQN
A9
GSM_QN[1]
22uF
C216
Y5
VFB_CORE
H8 VDDCMMB1V8 1.2/1.3/1.5/1.8 250mA 1.8V OFF

0.1uF
VBAT VDD2V5 VDD2V5
D2
[4] AUD_SCLK AUD_SCLK G7
VDD2V5
W11
VBATDRV_ARM
VDDCMMB1V2 1.2/1.3/1.5/1.8 200mA 1.2V OFF

IQ
H3 E8 C218 DNP
[4] AUD_ADSYNC AUD_ADSYNC TDQP TD_QP[1] V11 G8 VDDEFUSE
VBATDRV_ARM VDDEFUSE

DC2DC ARM
E1 C8 C219 4.7uF
[4] AUD_ADD0 AUD_ADD0 TDQN TD_QN[1] Y12
VBATDRV_ARM
W3 VDD1V8
E9 VDDARM VDD1V8

[4]
AUD_DASYNC F1

G3
AUD_DASYNC
TDIP

TDIN
F9
TD_IP [1]

TD_IN [1]
MICBIAS
L202
Y10
LX_ARM
VDD2V8
C5 VDD2V8
VDDRF 1.8/2.5/2.85/2.95 250mA 2.85V ON
[4] AUD_DAD0 AUD_DAD0 Y11
LX_ARM
F2 SPH252012H2R2MT
[4] AUD_DAD1 AUD_DAD1 W10
VDD3V 1.8/2.5/2.8/3.0 200mA 3.0V OFF

C220
K17 LX_ARM
MICBIAS A5 VDD3V
VDD3V

C205

C206
J16 22uF
P2
MICP MICP [6] V5
VFB_ARM
COM_TX_DI0 COM_TX_DI[0] C221 B17

0.1uF
[4] K16 VBAT VDDRF VDDRF
[4] COM_TX_DI1
L3
COM_TX_DI[1]
MICN MICN [6]
VDDSD0 1.8/2.5/2.8/3.0 150mA 2.8V OFF

2.2uF

0.1uF
V12 A6 VDD_A
L16 VBATDRV_MEM VDD_A
AUXMICBIAS
P3 C222 DNP
[4] COM_TX_DQ0 COM_TX_DQ[0] W14
H17 VBATDRV_MEM

DC2DC MEM
[4] COM_TX_DQ1
L4
COM_TX_DQ[1]
AUXMICP
C223 4.7uF W13
VDDCAMCORE
V2 VDDCAMCORE
VDDSD1 1.2/1.3/1.5/1.8 100mA 1.8V OFF

OUTPUT
H16 VBATDRV_MEM

POWER
AUXMICN
VDDMEM A3
N2 VDDCAMMOT
[4] COM_TX_SCLK COM_TX_SCLK R201 1K Y13 U201-B
G17 LX_MEM

[4] COM_TX_SYNC
M2
COM_TX_SYNC
HEADMIC_IN

HEADMICP
G16
HEADMIC_IN [6]

HEADMICP [6]
L203

SPH252012H2R2MT
Y14
LX_MEM
7101496M001
VDDCAMA
D14 VDDCAMA VDDSD3 1.2/1.3/1.5/1.8 100mA 1.8V OFF
W12

C224
G15 LX_MEM
P1
HEADMICN HEADMICN [6] VDDCAMIO
V1
VDDCAMIO
[4] COM_TX_APCD COM_TX_APCD
H15
22uF
C225
W5
VFB_MEM
VDDCAMCORE 1.2/1.3/1.5/1.8 200mA 1.5V OFF
A die To D die

AIL1 FM_AIL [7] N9

0.1uF
VBAT VDDCMMB1V2
U2 H14

AUDIO
[4] COM_RX_DI0 COM_RX_DI[0] AIR1 FM_AIR [7] N10
VDDCMMB1V8
Y7
U1 U201-A VBATDRV_LDO
[4] COM_RX_DI1 COM_RX_DI[1]
7101496M001 AORP
J15 C226 DNP V7
VBATDRV_LDO VDDSD0
B3 VDDSD0 VDDCAMIO 1.2/1.3/1.5/1.8 200mA 1.8V OFF

DC2DC LDO
N3 J14 C227 4.7uF
[4] COM_RX_DQ0 COM_RX_DQ[0] AORN W7 W2 VDDSD1
VBATDRV_LDO VDDSD1
R3 VDDLDO
[4] COM_RX_DQ1

N4
COM_RX_DQ[1]
HEAD_P_L
J12

K12
HEAD_P_L[6]
L204
Y6
LX_LDO
VDDSD3
Y2 VDDSD3
VDDCAMA 1.8/2.5/2.8/3.0 100mA 2.8V OFF
[4] COM_RX_SCLK COM_RX_SCLK HEAD_P_R HEAD_P_R[6] W6 B5 VDDSIM0
LX_LDO VDDSIM0
SPH252012H2R2MT
T2 M15
V6
LX_LDO VDDSIM1
B4
VDDSIM1
VDDCAMMOT 1.8/2.8/3.0/3.3 150mA 2.8V OFF

C228
[4] COM_RX_SYNC COM_RX_SYNC EARP EARP [6]
L14 C229
EARN EARN [6] Y4 A2 VDDUSB
VFB_LDO VDDUSB VDDLDO
B1
[4] XTL_BUF_EN XTL_BUF_EN
VDDUSB 3.1/3.2/3.3/3.4 60mA 3.3V OFF

0.1uF
22uF
C EXT_RST_B
B2
EXT_RST_B
PA_OUTP
M13
PA_OUTP_BB [6]
R17 R5
C
[4] M14 [8] VBAT_SENSE VBAT_SENSE VDCDC_LDOIN
PA_OUTP

CHARGE
VDD2V8 VDD2V8

POWER
R16 U4

INPUT

C239
C3 P14 [8] VBAT_ISENSE ISENSE VDCDC_LDOIN
VDD_A 1.8 80mA 1.8V ON

C238
[4] ANA_INT ANA_INT PA_OUTN PA_OUTN_BB [6]
R15
N1 P15 [8] VDRV VDRV
[4] ANA_INT2 ANA_INT2 PA_OUTN C209 10uF F5
VDD2V8D
R14
VCHG

1uF
VCHG

0.1uF
D3 L17
[4] CHIP_SLEEP CHIP_SLEEP VCOM C210 0.1uF
A1
NC
VIO_0
M9
AVDDBB 2.8/2.9/3.0/3.1 60mA 3.0V ON
H2 B14
[4] TD_TXPD TD_TXPD EXTRSTN A17
NC CURRENT VIBR V15
VIB_CTRL [8]

NC
[4] TD_RXPD
J3
TD_RXPD TESTRSTN
H5
Y1
NC GND SINK KPLED W15
KPLED_CTRL [8] 2.9/3.1/3.2/3.3
SYSTEM

J2
PBINT
E4
PBINT [8] Y17
NC AVDDVB 20mA 3.3V OFF
[4] GSM_TXPD GSM_TXPD
J10
3.4/3.5/3.6/3.8

C263

C265
PBINT2
J1

VSSDRV_CORE

VSSDRV_CORE

VSSDRV_CORE
[4] GSM_RXPD GSM_RXPD

VSSDRV_MEM

VSSDRV_MEM

VSSDRV_MEM

VSSDRV_ARM

VSSDRV_ARM

VSSDRV_ARM
VSSDRV_LDO

VSSDRV_LDO

VSSDRV_LDO
AGNDAFC
G5

AVSSPA

AVSSPA
PRODT

0.1uF
K1
2.9/3.1/3.2/3.3

0.1uF
[4] TD_RX_CLK TD_RX_CLK

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
C15
[4] CLK_32K
E2
CLK_32K
EDCDCEN
AVDDAO 100mA 3.3V OFF

B11

N13

N14

R8

T7

T8

R11

R12

T11

T10

P10

R10

P9

R9

T9

V13

N7

M8

L12

H10

G12

C13

F8

E12

E7

H12

L8
C14

[4] CLK_26M
E3
CLK_26M CLK ADCI T.P. WHTLED
EDCDCARM_EN

EDCDCMEM_EN
C16 3.4/3.5/3.6/3.8
F4
WHTLED_RSET

[4] PTEST
R206 DNP
PTEST
VDDRTC 1.5/1.6/1.7/1.8 0.5mA 1.8V ON
WHTLED_IB0

WHTLED_IB1

WHTLED_IB2

WHTLED_IB3

WHTLED_IB4

WHTLED_IB5

WHTLED_IB6

WHTLED_IB7

WHTLED_IB8

WHTLED_IB9
CLK_SINE
REF26M

TP_XR

TP_YU

TP_YD
MCLKI

ADCI0

ADCI1

ADCI2

ADCI3

TP_XL

These ground pins must be separate. VBATBK 2.6/2.8/3.0/3.2 2.8V ON


C7

B7

H9

B16

B12

B15

B13

K8

L9

J9

K9

T17

T14

T16

V17

W17

U16

U14

U15

Y16

W16

V16

And the circumfluence must be via DC-DC Power input's ground individually.
510

MICBIAS 1.9/2.1/2.3/2.5 2.1V OFF


R205

R202

R203
AUXMICBIAS 1.9/2.1/2.3/2.5 2.1V OFF
DNP

VDDRF
10K

1.7/1.8/1.9/2.0 1.8V(DDR1)
VDDMEM 800mA ON
LCD_ID
MCLK_26M

BAT_TEMP_ADC
CLK_SINE

1.1/1.2/1.3/1.4 1.2V(DDR2)
[9]
[4]

0.65/0.7/0.8/0.9
[1]

VDDARM 1100mA 1.2V ON


[8]

1.0/1.1/1.2/1.3
0.65/0.7/0.8/0.9

B
OPTIONS VDDCORE
1.0/1.1/1.2/1.3
800mA 1.1V ON
B
LDO ouput
VDDRTC

1.8/1.9/2.0/2.1
VDDLDO 800mA 2.2V ON
2.2/2.3/2.4/2.5
RTC VBATBK
R207

R208

BKBT AVDDBB AVDDVB AVDDA0 AVDDPA DDR2_BUFOUT VDD2V5 VDDEFUSE VDD1V8 VDD2V8

[2] OSC32KO VDDRTC


C240

C241

C242

C243

C245

C246

C247

C248
C244
10K
DNP

R215

R216

220K
10M

R217

Y201
0

32.768kHZ
2.2uF

2.2uF

2.2uF

0.1uF

2.2uF

DNP

2.2uF

2.2uF
10uF
[2] OPTION1
[2] OSC32KI C266
[2] OPTION2 0.01uF
C211

C212

C213

C256
BAT201

22uF
22pF

22pF

33pF

DNP
R210

R211

VDD3V VDDRF VDD_A VDDCAMCORE VDDCAMA VDDCAMIO


C250

C251

C252

C255
C249

C254
DNP
10K

2.2uF

2.2uF

2.2uF

2.2uF
1uF

1uF

VDDSD0 VDDSD1 VDDSD3 VDDSIM0 VDDSIM1 VDDUSB

Option Function L H
C262
C258

C259

C260

C261

C264

Option0 DCDC CORE OPTION OUTPUT Internal DCDC External DCDC


2.2uF

2.2uF

2.2uF

1uF

1uF

Option1 LDO POWER ON OPTION OUTPUT LDO POWER ON BY SEQ LDO POWER ON TOGETHER
1uF

Option2 NEW POWER ON RST OPTION OUTPUT NEW POWER ON RST SCHEME(DIGITAL POR) OLD POWER ON RST SCHEME(ANALOG POR)

Option3 DCDC ARM OPTION OUTPUT Internal DCDC External DCDC

A Option4 DCDC MEM OPTION OUTPUT Internal DCDC External DCDC All capacitors must be close to ABB. A
Option5 DCDC MEM OUTPUT SELECT DDR2 application (1.2V) DDR1 application (1.8V) DDR2_BUFOUT must be protected.

COMPANY:

TITLE:

DRAWN: DATED:

CHECKED: DATED:
CODE: SZE: DRAWING NO: REV:

QUALITY CONTROL: DATED:

RELEASED: DATED:
SCALE: SHEET: OF
6 5 4 3 2 1
REVISION RECORD

LTR ECO NO: APPROVED: DATE:

VDD1V8 VDDNF VDDIO12 VDDIO0 VDD2V8

R301 0

R302 0 R304 0

D
DBB_POWER D

VDD2V5 VDD2V5
All capacitors must be close to DBB.
C304 1uF

C305 0.1uF

DBB_MEMORY
C306
0.01uF

C311
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

C310
C312 C313 C314 C315 C316 C317 C318 C319 C320 C321 C322 C323 C324
VDD2V5

1uF
0.1uF
C307 VDDCAMIO
1uF VDDEFUSE VDDIO0 VDDIO12 VDDIO12 VDD1V8 VDD2V8 VDDSD0 VDDSD1 VDDSD3 VDDSIM0 VDDSIM1 VDDNF
C308 0.1uF

AA20

AA19

AA10
AF22

AF24
C309
0.01uF

M24

R30

U24
K24

P29

Y12

Y19

E15

V24

T24
L19

L20

L10

L11

E4

E5
F6
MDSI_AVDD

MDSI_AVDD

MCSI_AVDD

MCSI_AVDD

AVDD_PLL

VDDEFU

VDDIO0

VDDIO1

VDDIO2

VDDIO2

VDDCAMIO

VDDCAMIO

VDDLCM

VDDLCM

VDDIIC

VDDSD0

VDDSD1

VDDSD3

VDDSD3

VDDSIM0

VDDSIM1

VDDNF
VDDCORE

T11
VDDCORE
L12 U5
VDDCORE [3,5] EMD[00:31] CLKDPMEM EMCLKDP [5]
L13 EMD00 AF1 U4
C267

C302

VDDCORE EMD[0] CLKDMMEM EMCLKDM [5]


C334

C333

C332

C301

M12
VSS
L14 EMD01 AF2
VDDCORE EMD[1]
0.01uF M13 N1
VSS EMCKE[0] EMCKE0 [5]
C303 L15 EMD02 AD3
DNP

DNP

DNP

VDDCORE EMD[2]
22uF

0.1uF
10uF

M14 N3
VSS EMCKE[1] EMCKE1 [5]
L16 EMD03 AE3
VDDCORE EMD[3]
M15 P4
VSS EMCS_N[0] EMCSN0 [5]
L17 EMD04 AD2
VDDCORE EMD[4]
POWER VSS
M16
EMCS_N[1]
P3
EMCSN1 [5]

LANE-0
L18 EMD05 AD1
VDDCORE EMD[5]
M17 R4
VSS EMBA[0]
M11 EMD06 AC1
VDDCORE EMD[6]
M18 R3
VSS EMBA[1]
M20 EMD07 AC2
VDDCORE EMD[7]
M19 Y2
VSS EMBA[2]
N11
VDDCORE
N12 AB1 AB2
VSS [5] EMDQM0 EMDQM[0] EMRAS_N
N20
VDDCORE
N13 P2
VSS EMCAS_N
P11 AC3
VDDCORE [5] EMDQS0 EMDQS[0]
N14 Y3
VSS EMWE_N
P20 AC4
VDDCORE [5] EMDQSN0 EMDQS_N[0]
N15 AA4 R306 240
VSS EMZQ
R11 [3,5] 240 1%
VDDCORE EMD[00:31]
N16
VSS EMA00 EMA[00:09] [5]
R20 EMD08 K1 R2
VDDCORE EMD[8] EMA[0]
N17
VSS EMA01
T12 EMD09 M1 W2
VDDCORE EMD[9] EMA[1]
N18
VSS EMA02
T19 EMD10 M2 W3
C T20
VDDCORE
VSS
N19
EMD11 J3
EMD[10] EMA[2]
Y1 EMA03
C
VDDCORE EMD[11] EMA[3]
P12
VSS EMA04
U11 EMD12 K4 R1
VDDCORE EMD[12] EMA[4]

LANE-1
P13
VSS EMA05
U20 EMD13 L1 T4
VDDCORE EMD[13] EMA[5]
P14
VSS EMA06
V11 EMD14 L4 T3
VDDCORE EMD[14] EMA[6]
P15
VSS EMA07
V20 EMD15 H1 T2
VDDCORE EMD[15] EMA[7]
P16
VSS EMA08
W11 V3
VDDCORE EMA[8]
P17 J2
VSS [5] EMDQM1 EMDQM[1] EMA09
Y11 T1
VDDCORE EMA[9]
P18
VSS
AA11 L2 AA3
VDDCORE [5] EMDQS1 EMDQS[1] EMA[10]
P19
VDDARM VSS
W20 L3 W4
VDDCORE [5] EMDQSN1 EMDQS_N[1] EMA[11]
R12
VSS
[3,5] U301-B W1
EMD[00:31] EMA[12]
V14 R13
VDDARM VSS 7101497M001
EMD16 AH4 V2
EMD[16] EMA[13]
C337

C336

C335

C325
C268

C326

V15 R14
VDDARM VSS
EMD17 AJ2 V4
EMD[17] EMA[14]
V16 R15
0.01uF VDDARM VSS
EMD18 AK4
C327 EMD[18] NFD00 NFD[00:03] [5]
W15 R16 AF9
22uF

0.1uF
10uF
DNP

DNP

DNP

VDDARM VSS NFD[0]/GPIO67


EMD19 AG3
EMD[19] NFD01
Y13 R17 AE9
VDDARM
U301-C
VSS
EMD20 AH1
EMD[20]
MEM DDR2 NAND NFD[1]/GPIO68
NFD02

LANE-2
Y14 R18 AK8
VDDARM 7101497M001 VSS (VDDMEM) (VDDNF) NFD[2]/GPIO69
EMD21 AK3
EMD[21] NFD03
Y15 R19 AJ8
VDDARM VSS NFD[3]/GPIO70
EMD22 AJ4
EMD[22]
Y16 T18 AG8
VDDARM VSS NFD[4]/CLK_AUX1/GPIO71
EMD23 AG2
EMD[23]
Y17 T13 AJ7
VDDARM VSS NFD[5]/SD2_D7/GPIO72
Y18 T14 AG1 AH7
VDDARM VSS [5] EMDQM2 EMDQM[2] NFD[6]/SD2_D6/GPIO73
AA13 T15 AF8
VDDARM VSS NFD[7]/SD2_D5/GPIO74
AJ3
[5] EMDQS2 EMDQS[2]
AA14 T16 AF7
VDDARM VSS NFD[8]/SD2_D4/GPIO75
AH3
[5] EMDQSN2 EMDQS_N[2]
AA15 T17 AK6
VDDARM VSS NFD[9]/SD2_D3/GPIO76
AA16 U12 [3,5] EMD[00:31] AG7
VDDARM VSS NFD[10]/SD2_D2/AUD_IIS_DAT_DA1/GPIO77
EMD24 H3
EMD[24]
AA17 U13 AJ6
VDDARM VSS NFD[11]/SD2_D1/AUD_IIS_LRO_DA1/GPIO78
EMD25 G2
VDDMEM EMD[25]
AA18 U14 AF6
VDDARM VSS NFD[12]/SD2_D0/AUD_IIS_CLK_DA1/GPIO79
EMD26 E3
EMD[26]
U15 AG6
VSS NFD[13]/SD2_RST/AUD_IIS_DAT_AD1/GPIO80
EMD27 H2
EMD[27]
U16 AH6
VSS NFD[14]/SD2_CMD/AUD_IIS_LRO_AD1/GPIO81

LANE-3
M10 EMD28 F2
VDDMEM EMD[28]
U17 AJ5
VSS NFD[15]/SD2_CLK/AUD_IIS_CLK_AD1/GPIO82
N10 EMD29 D3
C328
C269

C329

VDDMEM EMD[29]
C339

C338

U18 AH10
VSS NFRB/GPIO61
P10 EMD30 G1
VDDMEM EMD[30]
0.01uF U19 AG10
VSS NFCLE/AMTDI/GPIO62
C330 R10 EMD31 D2
DNP

DNP

VDDMEM EMD[31]
22uF

0.1uF
10uF

V12 AE10
VSS NFALE/AMTCK/GPIO63
T10
VDDMEM
V13 F3 AK9
VSS [5] EMDQM3 EMDQM[3] NFCEN/AMTDO/GPIO64
U10
VDDMEM
V17 AJ9
VSS NFWEN/AMTMS/GPIO66
V10 E1
VDDMEM [5] EMDQS3 EMDQS[3]
V18 AF10
VSS NFREN/AMTRST_N/GPIO65
W10 D1
VDDMEM [5] EMDQSN3 EMDQS_N[3]
V19 AJ10
VREF VSS NFWPN/GPIO60
Y10
VDDMEM
W12
VSS
W13
VSS
M4
VREF
W14
VSS

C331 GND VSS

VSS
W16

W17
0.01uF
B A29
VSS
W18 B
NC
W19
VSS
A30
NC
Y20
VSS
B30
NC
AA12