Celullar ANT

Project : MT6572
REF_SCH TOP LEVEL EMI x32 BPI, APC FEM
EMI
TX RX

Memory
MCP NFI RF IQ
NFI
BSI ctrl
RX
MT6166 balun

MSDC 4-bit MSDC1

26M_BB
micro SD 26M
+ hot-plug 26M_AUD DCXO ctrl

26M_CN
26M_CN
ABB

CMMB
EINT
SPI MT6572 CONN IQ
Connectivity ANT

CONN ctrl
MT6627

32K_BB RTC 32K

Camera IF
Camera CAM
Module (MIPI / Parallel)
Camera IF MT6323 Headset
2nd Camera (HPL, HPR, AU_VIN1)
Module
I2C
i2C_0 Class D/AB

LCD IF
LCD LCD AUD I/F Audio Receiver
module (MIPI / Parallel) Speech

I2C
i2C_1 AU_VIN0
CTP EINT
controller
I2C

Motion EINT
Sensor POWER
I2C
ALS + PXS
EINT
SIM2
SPI SIM2
I2C Power
Management SIM1
Magnetic EINT SIM1
sensor
VIB
I2C
BC1.1
Gyro EINT Charger
sensor

Charger
Battery
Keypad
BJT
JTAG

USB 2.0 micro USB

Debug USB
UART
port

THIS DOCUMENT CONTAINS PROPRIETARY

INFORMATION AND SHALL NOT BE DUPLICATED
OR DISCLOSED TO OTHERS WITHOUT THE PRIOR
WROTTEN PERMISSION OF CK Techfaith
CK Telecom
Communication Technology Limited Communication Technology Limited
DRAWN: DATE: TITLE:

Shouchuang.Zhang2013-3-5 MT6272W
CHECKED: DATE: SIZE: DRAWING NO:
D 1-BLOCK_DIAGRAM
DESIGNED: DATE: SHEET: REV:
SCALE: 1:1 1 OF 11 V1.0
 cap Close to BB IC

C108
0201
U101-H
cap Close to BB IC 100nF

[2,3,4,6,7,8,10] VIO18_PMU VIO18_PMU T25 F1 VTCXO_PMU VTCXO_PMU [4,7]

DVDD18_MIPIRX AVDD28_DAC
U25 DVSS18_MIPIRX
AVDD18_AP E5

R25 U9 VIO18_PMU [2,3,4,6,7,8,10]

VIO18_PMU
DVDD18_MIPITX DVDD18_PLLGP
P25 DVSS18_MIPITX

D3 [2,3,4,6,7,8,10]
VIO18_PMU
[2,3,4,6,7,8,10] AVDD18_MD
VIO18_PMU VIO18_PMU H23 AVDD18_USB AVSS18_MD A1
[4] VUSB_PMU G24 AVDD33_USB AVSS18_MD A4
VUSB_PMU G23 C3 C112 C131 C128
AVSS33_USB AVSS18_MD
E2 0201 0201 0201
AVSS18_MD
100nF 100nF 100nF
C113
C107 C101 C104 1uF
0201 0201 0201 REFP F6 BG
REFP
100nF 100nF 100nF
C109
1uF G6 REFN

IC BASEBAND CHIP(WCDMA) 6572

dedicate VSS ball, must return to cap then to main GND:

1. REFN(G6) => C109
2. DVSS18_MIPIRX(U25) => C107
3. DVSS18_MIPITX(P25) => C101
[3,4] PMIC_SPI_CS
HW trapping PIN
R527

0201
20K 20K: VM=1.8V
NC : VM=1.2V

TP_VMEM

U101-B VIO_EMI [6]

1.8V IO for DDR1 VIO_EMI 0R

VCCIO_EMI W9 R101 VM_PMU [4]
VCC
VCCIO_EMI W12 1.2V IO for DDR2
Memory W14
VCCIO_EMI C129 C130
AC21 GND VCCIO_EMI W16 for eMMC 0201 0201
AD11 GND VCCIO_EMI W19
AF13 GND
100nF 100nF If double-sided SMT, put C405 & C406 below BB.
AB11 GND C124
AC8 If single-sided SMT, put C405 & C406 around memory.
GND DVDD 0201
AB5 GND Peripheral 100nF
AB14 GND
W26 AA1 VIO18_PMU [2,3,4,6,7,8,10]
VIO18_PMU
GND DVDD18_MC0
T15 GND DVDD18_CAM K20 VIO18_PMU
W23 GND DVDD18_VIO_1 L3 VIO18_PMU
T14 GND DVDD18_VIO_2 J19 VIO18_PMU
AF26 GND DVDD18_VIO_3 H13 VIO18_PMU
R119 0R
G3 GND DVDD18_LCD AB24 DVDD18_LCD
K21 GND
L11 GND
L12 GND
L14 GND DVDD3_MC1 K24 VMC_PMU VMC_PMU [4] C126
L15 GND
L16 GND DVDD3_LCD W24 DVDD18_LCD
1uF
M5 GND
VIO28_PMU [4,5,8,10] C121
M11 GND DVDD28_BPI C10 VIO28_PMU
M12 0201
GND
M13 GND C117 NC
M14 GND VCC
M15 GND
M16 CPU P6 1uF
N10
GND
GND
VCCK_CPU
VCCK_CPU T7 Close to BB IC, recommand < 150mil
N8 GND VCCK_CPU P7
N9 GND VCCK_CPU P8
N11 GND VCCK_CPU P9
N12 GND VCCK_CPU R6
N13 GND VCCK_CPU R7
N14 GND VCCK_CPU R8
N15 GND VCCK_CPU R9
N16 GND VCCK_CPU T6 Based on your system level
P10 GND VCCK_CPU U6 design , if better FM performance TP_VCORE
N22 GND VCCK_CPU T9
P11 GND VCCK_CPU T8 is needed on your system ,
P12 GND VCCK_CPU U7
P13 GND
please refer to FM desense
P14 GND performance enhance proposal
P15 GND 120mil VPROC_PMU [4]
P16 GND VCC
R10 GND
R11 Core J9
GND VCCK
R12 GND VCCK J15
R13 GND VCCK M9
R14 GND VCCK K6
R15 GND VCCK K7
R16 K8

2.2uF

2.2uF
GND VCCK

100nF

100nF

100nF

100nF

1uF

1uF

1uF

1uF
T10 K9

4.7uF
GND VCCK
T11 GND VCCK K11
T12 K14

C136

C137
GND VCCK C114

C115

C118

C116

C135

C120

C134

C119
T13 K15

C111
GND VCCK C106 C102 C103
AF1 VSS VCCK M10
VCCK K16 0201 0201 0201 0201
U10 VSS VCCK K17 10uF 10uF 10uF
U11 VSS VCCK U17
V13 VSS VCCK M17
W11 VSS VCCK L7 Vproc remote sense :
Y21 VSS VCCK L8
L9 differential 4mil with good shielding, from the BB to PMIC
VCCK LR101 0R
VCCK L17 0000 GND_VPROC_FB[3]
M6 [4]
VCCK 4mil - defferential - GND shielding
VCCK M7 LR102 0R
M8 0000 VPROC_FB [3]
VCCK [4]
VCCK J17
VCCK J16
VCCK R17
VCCK T16
VCCK L6
VCCK K12
VCCK T17
VCCK J10
VCCK J11
VCCK U12
VCCK U13
VCCK U14
VCCK U15
VCCK U16
VCCK J8
VCCK J14

A26 DUMMY

IC BASEBAND CHIP(WCDMA) 6572 THIS DOCUMENT CONTAINS PROPRIETARY

INFORMATION AND SHALL NOT BE DUPLICATED
OR DISCLOSED TO OTHERS WITHOUT THE PRIOR
WROTTEN PERMISSION OF CK Techfaith
CK Telecom
Communication Technology Limited Communication Technology Limited
DRAWN: DATE: TITLE:

Shouchuang.Zhang 2013-3-5 MT6272W

CHECKED: DATE: SIZE: DRAWING NO:
D 2-BB-POWER
DESIGNED: DATE: SHEET: REV:
SCALE: 1:1 2 OF 11 V1.0
 U101-A

[7] RX_I_P D2 DL_I_P BPI_BUS0 B12 ASM_VCTRL_A [7]

[7] RX_I_N C2 DL_I_N BPI_BUS1 B11 ASM_VCTRL_B [7]
[7] RX_Q_P B1 DL_Q_P BPI_BUS2 C12 ASM_VCTRL_C [7] U101-D
[7]RX_Q_N C1 DL_Q_N BPI_BUS3 A11 WG_GGE_PA_ENABLE[7]
[4] AUD_MISO J1
D11 PWM_BL_CTRL [8] [4] AUD_DAT_MISO
[7] TX_I_P BPI_BUS4 AUD_CLK K5 [4,8] VCAMD_IO_PMU
A2 C11 EINT0_HP [5] [4] AUD_CLK_MOSI
[7] TX_I_N UL_I_P BPI_BUS5 AUD_MOSI K1
B2 A13 GPIO_GPS_LNA_EN[9] AUD_DAT_MOSI
[7] TX_Q_P UL_I_N BPI_BUS6
B4 UL_Q_P [4] PMIC_SPI_MOSI
[7] TX_Q_N [7] L2 PMIC_SPI_MOSI
B3 UL_Q_N BPI_BUS7 A10 W_PA_B1_EN [4] PMIC_SPI_MISO [2,3,4,6,7,8,10] VIO18_PMU
[7] L5 PMIC_SPI_MISO
BPI_BUS8 B10 W_PA_B2_EN [4] PMIC_SPI_SCK
[7] L4 PMIC_SPI_SCK
BPI_BUS9 D10 W_PA_B5_EN [2,4] PMIC_SPI_CS K2 PMIC_SPI_CSN
BPI_BUS10 E9 R208 R204 R205

0201

0201
0201
BPI_BUS11 E8 [4,6] 20K_NC 2.2K 2.2K
WATCHDOG G2 WATCHDOG
BPI_BUS12 B9 [4,7]
[7] VM0 A8 B8 EINT4_ALS
SRCLKENA H4 SRCLKENA
VM0 BPI_BUS13 [10] [4] EINT_PMIC J2 [3,8] SCL_0
A7 VM1 BPI_BUS14 E7 EINT5_G_SENSOR [10]
EINTX [3,4] SIM1_SCLK Power by CAM_IO
[7] VM1 D7 [3,8] SDA_0
BPI_BUS15
[3,4] SIM1_SCLK H5 SIM1_SCLK Normal : NC
[7] TXBPI D5 TXBPI BSI_DATA2 D6 BSI-A_DAT2 [7] SIM1_SIO M3
C7 BSI-A_DAT1 [4] SIM1_SIO [2,3,4,6,7,8,10] VIO18_PMU
BSI_DATA1 [7] JTAG : 20K
[7]WG_GGE_PA_VRAMP F2 APC BSI_DATA0 F9 BSI-A_DAT0 [7]
BSI_EN F11 BSI-A_EN [7]
[4] SIM2_SCLK J5 SIM2_SCLK
F3 VBIAS BSI_CLK G11 BSI-A_CK [7]
[4] SIM2_SIO M1 SIM2_SIO Reserve R footprint
for JTAG debugging R206 R207

0201

0201
2.2K 2.2K

IC BASEBAND CHIP(WCDMA) 6572 [3,8,10]

IC BASEBAND CHIP(WCDMA) 6572 SCL_1
[3,8,10] SDA_1 Power by CTP, sensor

U101-E

[7] CLK1_BB E1 CLK26M PWM_A D12

SYSTEM PWM E12 EINT1_CTP [8]
[4] PWM_B
CLK32K_BB H2 CLK32K_IN
LCD
[4,10] RESETB M2 SYSRSTB LPD17 N1
Based on your system level design , if better Parallel N2
LPD16
G4 N3
desense performance is needed on your TESTMODE LPD15
P2
LPD14
system , please refer to desense AC24 FSOURCE LPD13 N4
R2
performance enhance proposal LPD12
N5
LPD11
[4] CHD_DP J26 CHD_DP LPD10 R1 MC1_INS [3]
[4] CHD_DM J25 BC 1.1 P5
CHD_DM LPD9
LPD8 T1
LPD7 R5
C209 [10] USB_DM 90-ohm differential G26 USB_DM LPD6 T2
U101-G [10] USB_DP G25 USB 2.0 T5
0201 USB_DP LPD5
100nF_NC 0201 H25 USB_VRT LPD4 U2
MIPI_2nd_CAM R203 5.11K LPD3 T3
L25 CMPDN2 Parallel 8-bit LPD2 U5
K25 CMRST2 [3,8] i2C
[8] SCL_0 C25 SCL_0 LPD1 T4
GPIO_CMPDN H22 CMPDN
[8] GPIO_CMRST J22 CMRST close to BB [3,8]
[3,8,10]
SDA_0
SCL_1
C26
B24
SDA_0
SCL_1
LPD0 V2
MT6572 support JTAG from below :
[3,8,10] SDA_1 B23 SDA_1
Y22 CMMCLK [8]
R24
CMMCLK 1. KP (recommand)
RDN0 MIPI_CAM
R23 Y23 CMPCLK [8]
R22
RDP0 CMPCLK
LPCE0B AD25
[8]
2. MC1
RDN1 F24 AB26 LPTE
R21 V25 CMVSYNC [8] SPI_MISO LPTE
R26
RDP1 RCN_A
W25 CMHSYNC [8] F25 SPI_MOSI
SPI
LRSTB AC26 GPIO_LRSTB [8] 3. CAM
RCN RCP_A F23 AA22
T26 V24 CMDAT7 [8] SPI_SCK LPRDB
RCP RDN1_A
V23 CMDAT6 [8] E23 SPI_CS LPA0 AB23 for JTAG pin out from MC1/CAM, refer
RDP1_A AC25
P19 U22 CMDAT5 [8] LPWRB
[8] MIPI_TDN0
P20
TDN0 MIPI_LCD RDN0_A
U21 CMDAT4 [8]
GPIO57_CTP_RSTB
[8] to HW design notice
[8] MIPI_TDP0 TDP0 RDP0_A
N25 TDN1 [3]
[8] MIPI_TDN1
[8] MC1CMD K23 MC1_CMD KROW0 B25
N26 TDP1 CMDAT3 Y26 CMDAT3 [3] T-flash KP
[8] MIPI_TDP1
[8] MC1CK L21 MC1_CK KROW1 A24
P23 TDN2 CMDAT2 Y25 CMDAT2 [3]
[8] MC1DAT0 K22 MC1_DAT0 KROW2 B26 MCU_JTMS[10]
P24 TDP2 CMDAT1 AA25 CMDAT1 [3]

T FLASH CARD
MC1DAT1 M22 MC1_DAT1 KCOL0 C24 KCOL0 [10]
N20 AB25 CMDAT0 [8] [3]
[8] MIPI_TCN
N19
TCN CMDAT0 MC1DAT2 M25 MC1_DAT2 KCOL1 D24 KCOL1 [10] VMC max current = 200mA,Only for single TF
MIPI_TCP TCP [3] MC1DAT3 L26 A25 MCU_JTCK[10]
[8] MC1_DAT3 KCOL2
close to BB
B7 AUX_IN0 UTXD1 E25 UTXD1 [10]
MIPI_VRT P26 VRT [8] ADC UART [10]
ADC4_LCD_ID B6 AUX_IN1 URXD1 D25 URXD1
C5 AUX_IN2_XP UTXD2 E26 1
UTXD2 [10] [3] R517 0201 0R DAT2
B5 AUX_IN3_YP URXD2 F26 MC1DAT2
2
URXD2 [10] [3] R518 0201 0R DAT3
C4 AUX_IN4_XM MC1DAT3
3
[3] R519 0201 0R CMD
R202 A5 MC1CMD
0201

IC BASEBAND CHIP(WCDMA) 6572 AUX_IN5_YM

ͬINSTANTÏîÄ¿
[4] L501 0R 4
VMCH_PMU VDD
1.5K_1% [3] R522 0201 0R 5
MC1CK CLK
6
VSS
[3] R520 0201 0R 7
MC1DAT0 DAT0
R521 0201 0R 8
[3] MC1DAT1 DAT1

MCINS
GND1
GND2
GND3
IC BASEBAND CHIP(WCDMA) 6572
C540
C533 C534 C535 C536 C537 C538

G1
G2
G3
G4
2.2uF J501
0201 0201 0201 0201 0201 0201
CAF11-08373-S107
NC NC NC NC NC NC CONN T-FLASH ¿¨×ù H3.7

+ -
T501

[3] MC1_INS

µ×²¿°´¼üµÆ L522
SZ1005G750T

SIM CARD [4,7,8,10] VBAT

D501 D502 D503

20

19

SIM1 SIM2
SIM1 SIM2
8 16
GND CLOSE GND
4 12
[4] VSIM1_PMU 7
VCC VCC
15 VSIM2_PMU [4]
VPP VPP
[4] 3 11 [4]
SRST RST RST SRST2
[4] 6 14 [4] R533 R532 R534
SIO I/O I/O SIO2
[4] 2 10 [4] 100R
SCLK CLK CLK SCLK2 100R 100R
5 13
NC NC
1 9
NC NC

J502
17

18

[4] ISINK3

C517 C518 C519 C520 C521

0201 0201 0201 0201
NC NC NC NC 1uF

C526 C525 C522 C523 C524

0201 0201 0201 0201
1uF NC NC NC NC

THIS DOCUMENT CONTAINS PROPRIETARY

INFORMATION AND SHALL NOT BE DUPLICATED
OR DISCLOSED TO OTHERS WITHOUT THE PRIOR
WROTTEN PERMISSION OF CK Techfaith
CK Telecom
Communication Technology Limited Communication Technology Limited
DRAWN: DATE: TITLE:

Shouchuang.Zhang 2013-3-5 MT6272W

CHECKED: DATE: SIZE: DRAWING NO:
D 2-MT6572_BASEBAND/TF/SIM/LED/FPC
DESIGNED: DATE: SHEET: REV:
SCALE: 1:1 3 OF 11 V1.0
 Charger
1. Close to Battery Connector.
[10] (Rsense (R328) <10mm)
VBUS 2. Main path should be 40mil.
OVP: 12V (VBUS -> U301's E, -> U301's C -> R328 -> VBAT)
3. Star connection from R328 to BAT Connector
VCDT rating: 1.268V
R305 330K
VCDT [4]
25V rating
C329 R309
2.2uF
39K

U301
R310 3.3K
CHR_LDO [4]
[3,4,7,8,10] VBAT

4
C

E
U303 K1 [5] AU_SPKP
SPK_P
C313 L1 [5] AU_SPKN
SPK_N
2.2uF P1 VBAT_SPK
C

B
L2 H1 [5] AU_HSP
GND_SPK AU_HSP

1
1

3
G1 [5] AU_HSN
AU_HSN
32 VDRV [4] H4 [5] AU_HPL
U302 AU_HPL
[5] MICBIAS0 F2 J4 [5] AU_HPR
PNM723T703E0-2 AU_MICBIAS0 AU_HPR
[5] MICBIAS1 G2 AU_MICBIAS1
C312
0201
ISENSE [4] [5] AU_VIN0_P E4 E9
100nF AU_VIN0_P AUDIO DRIVER ISINK0
[5] AU_VIN0_N F4 C9
AU_VIN0_N ISINK1
ISINK2 E10
R328 [5] AU_VIN1_P G3 C10 ISINK3 [3]
ISENSEÓëVBAT²î·Ö×ßÏß AU_VIN1_P ISINK3
0.2R Rsense [5] AU_VIN1_N G4 AU_VIN1_N Based on your system level design , if
[4] VA_PMU D2 AU_VIN2_P lower LX voltage swing is needed on
D1 AU_VIN2_N
VBAT [3,4,7,8,10] your system, please refer to Buck LX

1uF
J2 voltage swing enhance proposal
D3
AVDD28_ABB Please use inductor recommand by MTK
AVDD28_AUXADC
H2 Refer to MT6323 design notice

C314
GND_ABB

[5] ACCDET E2 VPROC_SW 0.68uH

ACCDET BUCK OUTPUT
VPROC C14 VPROC_SW
[7]CLK4_AUDIO [4] L301 0.68uH [2]
E1 CLK26M VPROC D14 VPROC_PMU
E14

BATTERY CONNECTOR
VPROC C345 1nF_NC

0201
VPROC_SW
[4,7]
AUXADC_REF ISENSE/BSTSNS 4mil [4]
differential to Rsense B12 VPROC_FB [2]
CHARGER VPROC_FB
C12 GND_VPROC_FB [2]
R334 GND_VPROC_FB
0201

[3,4,7,8,10] VBAT VBAT P13 RB521CS-30 D305

BATSNS L304 2.2uH
16.9K [4] ISENSE ISENSE P12 A14 VPA_PMU [7] C358
ISENSE VPA 1nF_NC

0201
[4] VPA_SW VBAT
BAT_ON BAT_ON K3 BATON VPA B14 [3,4,7,8,10]
J301 [4] VCDT VCDT A12 [4] C357 RB521CS-30 D307
VCDT
[4] VDRV VDRV M13 D12 2.2uF VPA_SW
VDRV VPA_FB
1 near-end cap [4] RB521CS-30 D306
VBAT VBAT [3,4,7,8,10]
R326 [4]
2 CHR_LDO CHR_LDO N13 CHRLDO 0.68uH
DET 0201 BAT_ON [4]
1K VSYS_SW L303 0.68uH VSYS_SW RB521CS-30 D304
3 H14 VSYS_PMU [4]
HOLE

HOLE

GND VSYS [4]

1uF
VSS

C315 C317 CONTROL SIGNAL VSYS_SW C344

0201
1nF_NC
R335 1K R316 [4]
0201

[10] PWRKEY M2
+ -

+ -

KBC23S1W10R
Close to PMIC PWRKEY
6

C316
0201 0201 T303 T304 0201
27K [3,6]WATCHDOG A1
33pF 33pF SYSRSTB
[3,10] RESETB K4 RESETB ALDO OUTPUT
A9 M3 VA_PMU [4]
FSOURCE VA
[3] EINT_PMIC A7 INT
N12 EXT_PMIC_EN VCN28 N3 VCN_2V8_PMU[9]
VTCXO L4 VTCXO_PMU[2,7]
N2 PMU_TESTMODE
VCAMA P3 VCAMA_PMU [8]
[3] AUD_MOSI E7 M6 VCN_3V3_PMU[9]
AUD_MOSI VCN33
[3] AUD_CLK E8 C3 VRTC [4] C355
AUD_CLK AVDD33_RTC
[3] AUD_MISO B6 AUD_MISO
[3,7] SRCLKENA 1uF
A2 SRCLKEN DLDO OUTPUT
TP301 FCHR_ENB[4] [4] FCHR_ENB M1 FCHR_ENB
J13 VM_PMU [2]
VM
PMIC_SPI_SCK D9 H11 VRF18_PMU [7]
[3] SPI_CLK VRF18
[2,3] PMIC_SPI_CS B7 SPI_CSN VIO18 L12 VIO18_PMU[2,3,4,6,7,8,10]
[3] PMIC_SPI_MOSI D8 SPI_MOSI VIO28 M4 VIO28_PMU [2,5,8,10]
[3] PMIC_SPI_MISO B8 J12 VCN_1V8_PMU [9]
SPI_MISO VCN18
K14 VCAMD_PMU [8]
VCAMD
VCAM_IO L13 VCAMD_IO_PMU [3,8]
F13 VBAT INPUT
[3,4,7,8,10] VBAT_VPROC
VBAT 80mil 30mil F14 VBAT_VPROC [4]
G13 P7 VEMC_3V3_PMU [4] VEMC_3V3_PMU
VBAT_VPROC VEMC_3V3
4mil (VPA no use) A13 L6 VMC_PMU [2]
VBAT_VPA VMC
C310 VMCH P4 VMCH_PMU [3]
D301 L
15mil H13 VBAT_VSYS VUSB N6 VUSB_PMU [2] C354
P8 VBAT_LDOS3 VSIM1 P9 VSIM1_PMU [3] 0201
PZ5D4V2H 20mil P6 N9 VSIM2_PMU [3]
22uF VBAT_LDOS3 VSIM2
20mil P5 L8 100nF
VBAT_LDOS2 VGP1 VGP1 [8]
20mil P2 VBAT_LDOS1
M7 VIBR_PMU [4] VIBR_PMU B305
VIBR [4]
[4] VSYS_PMU 20mil J14 N8 VGP2
AVDD22_BUCK VGP2 [8] PZ1608U221-1R4TF
M14 AVDD22_BUCK VGP3 L14
VCAM_AF N7

1
MOTOR301
+
DVDD18_DIG_PMIC A8 C350
DVDD18_DIG

M
[2,3,4,6,7,8,10] VIO18_PMU A5 100pF
DVDD18_IO C302

-
WG_GGE_PA_ENABLE
AUXADC_REF

2
[4,7] AUXADC_REF C2 AUXADC 1uF
AUXADC_VREF18
[7]AUXADC_TSX B1 AUXADC_AUXIN_GPS VREF P14 VREF
C340 C323 B2 AVSS28_AUXADC C320
0201 0201 [7]GND_AUXADC 0201 dedicate VSS ball, must return to cap then to main GND:
LR339 100nF 100nF
0000 BC 1.1
100nF 1. GND_VREF(N14) => C320
0R
[3] CHD_DM A10 N14
1uF

1uF

CHG_DM GND_VREF
[3] CHD_DP A11 CHG_DP
C304 1uF_NC

C305 1uF_NC

RTC 32K : X301+C324+C319=> mount, R333=> NC

C307

C308

C301 C303
C306 C309
RTC_32K1V8 D5 CLK32K_BB [3] 32K-less: X301+C324=> remove, C319+R333=> 0R
SIM LVS RTC C4
RTC_32K2V8
10uF 10uF [3] SIM1_SCLK B5 A3 32K_IN
10uF 10uF SIM1_AP_SCLK XIN
[3] SIM1_SIO M11 A4 32K_OUT
SIMLS1_AP_SIO XOUT SSP-T7-F
E6 SIM1_AP_SRST X301
[3] SIM2_SCLK
[3] SIM2_SIO
C5 SIM2_AP_SCLK GND_ISINK B10
RTC

4
K11 G11

1
SIMLS2_AP_SIO GND_VSYS
D6 SIM2_AP_SRST GND_VPA E13 C324 C319
E11

2
GND_VPROC 0201 0201
[3] SCLK M9 F11
SIMLS1_SCLK GND_VPROC
[3] SIO N11 F10 18pF 18pF
SIMLS1_SIO GND_VPROC
[3] SRST M10 [4] VRTC
SIMLS1_SRST
GND_LDO K6
[3] SCLK2 K9 K8
SIMLS2_SCLK GND_LDO
[3] SIO2 L11 SIMLS2_SIO
[3] SRST2 K10 F5 Close to chip

0201
SIMLS2_SRST GND_LDO R307
GND_LDO F6 1K
F7 0R_NC R333 DCXO_32K [7] C318
GND_LDO 0201
F8

GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
refer to system analog LDO GND_LDO F9
100nF

1
1
GND_LDO G5
performance improve proposal GND_LDO G6
BAT302
BAT301
PAS414HR-VE5R XH414HG

J10
J9
J8
J7
J6
H10
H9
H8
H7
H6
H5
G9
G8
G7
Refer to MT6323 design notice

2
2
for Buck GND layout rule MT6323GA

==> for longer RTC time sustain after battery remove,

please refer to RTC design notice

THIS DOCUMENT CONTAINS PROPRIETARY

INFORMATION AND SHALL NOT BE DUPLICATED
OR DISCLOSED TO OTHERS WITHOUT THE PRIOR
WROTTEN PERMISSION OF CK Techfaith
CK Telecom
Communication Technology Limited Communication Technology Limited
DRAWN: DATE: TITLE:
Shouchuang.Zhang
2013-3-5 MT6272W
CHECKED: DATE: SIZE: DRAWING NO:
D 3-MT6323_POWER
DESIGNED: DATE: SHEET: REV:
SCALE: 1:1 4 OF 11 V1.0
 EXTERIOR AUDIO AMPLIFIER
R401 1K
[4] MICBIAS0 0201 Close to BB Close to MIC

R405
¿¿½üMIC¡£

0201
1.5K

[4] AU_VIN0_P
C405 100nF
B402 SZ1005G750T
B415
0R
MIC401 [4] AU_SPKP
B406

PZ1608U221-1R4TF
1115
C431 100pF C445 C430
1
0201 2 + 0201 0201
4.7uF C455 C450 +
NC 33pF
C406 100nF B416 0R 0201
B407 SZ1005G750T -
[4] AU_VIN0_N 100pF

SPK401
B409
C457
0201
R406 C456
C458 C459 [4] AU_SPKN

+ -

+ -
1.5K 0201 PZ1608U221-1R4TF
0201 T415 T416
0201 0201
33pF 33pF C429 C444 C460 C461
NC NC
0201 0201

+ -

+ -
0201 0201 T418 T419
NC 33pF NC NC

R412
0201

1K

Close Baseband IC

Microphone
Earphone MICOPHONE
Earphone Receiver Earphone Audio
[2,4,8,10]
MICBIAS1[4] VIO28_PMU

close to BB MIC Spec. : L-R-G-M

C422 R404
Close to BB Close to MIC

0201
R422

0201
0201 1K
C421 Close to J401 470K
NC
B411 C432 22uF 100nF C421 4.7uF
R408 33R C415 J401
[4] AU_HPL HP_MP3L [5] [4] AU_VIN1_N CONN 3.5MM AUDIO JACK ÆÆ°åʽ
L

0R B413
6 MIC PJES-050-1-G-BLK
GND of C421(4.7uF) and headset [5] HP_MIC
R407

0201
C419 should tie together and single SZ1608K252TF SDV1005E140C101NPT£¨100pf£© 5
T420 MIC
0201 1.5K via to GND plane + -
33pF
C417 B410 SZ1608K252TF 4 EAR_R
C433 22uF [5] HP_MP3R
B412 33R
R409 0201 47K
[4] AU_HPR HP_MP3R [5] DET
L

R410 1
0R [3] EINT0_HP 0201
100pF
C424
C420 ͬINSTANTÏîÄ¿

SDV1005E140C101NPT£¨100pf£©

SDV1005E140C101NPT£¨100pf£©

SDV1005E140C101NPT£¨100pf£©

SDV1005E140C101NPT£¨100pf£©
0201 0201
33pF
NC
C416 100nF B408 0R SZ1608K252TF EAR_L
[5] B417 2
[4] AU_VIN1_P HP_MIC [5] HP_MP3L
3 GND
R402 C401
[4] ACCDET 0201 1K R427

0201
R426

0201
0201
470R 470R
33pF C425 C426

+ -

+ -

+ -

+ -
0201 0201
33pF 33pF T404 T403 T405 T412 C <= 1pF

0R
0201 FM_ANT
R445 [9]

100nH L421
SDV1005H260C030YPT (3pf) To FM ANT

+ -
T422

0R
0201 FM_RX_N_6572
R443 [9]

Single via to GND plane

SPEECH Receiver
close to IC
close to connector
B403
B401 SZ1005G750T
[4] AU_HSN
0R
1
+
C412 2
0201 100pF -
B405
B404 SZ1005G750T
[4] AU_HSP
0R REC401

C413 C414 T413 T414

C428 C438

+ -

+ -
0201 0201
0201 0201
33pF 33pF
NC NC

Ë«¼«ÐÔTVS

THIS DOCUMENT CONTAINS PROPRIETARY

INFORMATION AND SHALL NOT BE DUPLICATED
OR DISCLOSED TO OTHERS WITHOUT THE PRIOR
WROTTEN PERMISSION OF CK Techfaith
CK Telecom
Communication Technology Limited Communication Technology Limited
DRAWN: DATE: TITLE:
Shouchuang.Zhang
2013-3-5 MT6272W
CHECKED: DATE: SIZE: DRAWING NO:
D 4-AUDIO
DESIGNED: DATE: SHEET: REV:
SCALE: 1:1 5 OF 11 V1.0
 NAND-LPDDR1
[2] VIO_EMI

U401
C9 VDDQ CLK G8 EDCLK [6]
4.7uF D10 VDDQ CLK# H8 EDCLK_B [6]
U101-F C501
E9 VDDQ CKE0 E3 ECKE [6]

2
F10 VDDQ CS0# J2 ECS0_B [6]
[6] ED31 AF6 G9 VDDQ RAS# G2 ERAS_B [6]
ED31_(DDR1)
[6] ED30 AE6 AF22 [6] Put C402 & C403 between BB & memory. J10 VDDQ CAS# H2 ECAS_B [6]
ED30_(DDR1) ECS0_B_(DDR1) ECS0_B
[6] ED29 AF8 AF19 K9 VDDQ WE# K1 EWR_B [6]
ED29_(DDR1) ECS1_B_(DDR1) ECS1_B [6]
[6] ED28 AE7 L9 VDDQ BA0 J3 EBA0 [6]
ED28_(DDR1)
[6] ED27 AE8 AF21 EWR_B [6] C502 100nF M10 VDDQ BA1 K2 EBA1

0201 0201
ED27_(DDR1) EWR_B_(DDR1) [6]
AC9 AD21 ERAS_B N9 VDDQ DM0 J8 EDQM0 BA[1:0] = EA[15:14] (LPDDR1)

2
[6] ED26 ED26_(DDR1) ERAS_B_(DDR1) [6] [6]
[6] ED25 AC7 AB20 ECAS_B [6] C503 100nF DM1 G6 EDQM1 [6]
ED25_(DDR1) ECAS_B_(DDR1)
AB9 AD24 ECKE H10 VDDD DM2 F8 EDQM2

2
[6] ED24 ED24_(DDR1) ECKE_(DDR1) [6] [6]
[6] ED23 AF5 H1 VDDD DM3 E7 EDQM3 [6]
ED23_(DDR1)
[6] ED22 AE5 AB13 M1 VDDD DQS0 J7 EDQS0 [6]
ED22_(DDR1) EDQM0_(DDR1) EDQM0 [6]
[6] ED21 AD5 AD12 B8 VDDD DQS1 G5 EDQS1 [6]
ED21_(DDR1) EDQM1_(DDR1) EDQM1 [6]
[6] ED20 AC5 AD8 D1 VDDD DQS2 H7 EDQS2 [6]
ED20_(DDR1) EDQM2_(DDR1) EDQM2 [6]
[6] ED19 AE4 AE12 P8 VDDD DQS3 E5 EDQS3 [6]
ED19_(DDR1) EDQM3_(DDR1) EDQM3 [6]
[6] ED18 AF3 ED18_(DDR1)
[6] ED17 AF2 AA14 C504 1uF C1 VSSD DQ0 L4 ED0 [6]
ED17_(DDR1) EDQS0_(DDR1) EDQS0 [6]
AB6 Y13 J1 VSSD DQ1 L5 ED1

2
[6] ED16 ED16_(DDR1) EDQS1_(DDR1) EDQS1 [6]
AE11 Y8 [6] B9 VSSD DQ2 L6 ED2
[6] ED15 ED15_(DDR1) EDQS2_(DDR1) EDQS2 C505 4.7uF [6]
AD15 AA9 [6] H9 VSSD DQ3 L7 ED3
[6] ED14 ED14_(DDR1) EDQS3_(DDR1) EDQS3 [6]

2
AE10 [6] P9 VSSD DQ4 K8 ED4
[6] ED13 ED13_(DDR1) [6]
[6] ED12 AE9 Y14 M2 VSSD DQ5 L8 ED5 [6]
ED12_(DDR1) EDQS0_B
[6] ED11 AF12 AA13 DQ6 K7 ED6 [6]
ED11_(DDR1) EDQS1_B
[6] ED10 AF11 AA8 N10 VSSQ DQ7 K5 ED7 [6]
ED10_(DDR1) EDQS2_B
[6] ED9 AF9 Y9 M9 VSSQ DQ8 K6 ED8 [6]
ED9_(DDR1) EDQS3_B
[6] ED8 AC13 J9 VSSQ DQ9 G7 ED9 [6]
ED8_(DDR1)
[6] ED7 AE16 Y18 EDCLK_B [6] G10 VSSQ DQ10 J6 ED10 [6]
ED7_(DDR1) EDCLK0_B
[6] ED6 AE13 AA18 EDCLK [6] F9 VSSQ DQ11 J5 ED11 [6]
ED6_(DDR1) EDCLK0
[6] ED5 AE15 E10 VSSQ DQ12 H6 ED12 [6]
ED5_(DDR1)
[6] ED4 AE14 AA19 L10 VSSQ DQ13 H5 ED13 [6]
ED4_(DDR1) EDCLK1_B
[6] ED3 AF15 Y19 K10 VSSQ DQ14 J4 ED14 [6]
ED3_(DDR1) EDCLK1
[6] ED2 AF16 D9 VSSQ DQ15 G3 ED15 [6]
ED2_(DDR1)
[6] ED1 AC15 C10 VSSQ DQ16 G4 ED16 [6]
ED1_(DDR1)
[6] ED0 AB16 AA2 NLD0 DQ17 F4 ED17 [6]
ED0_(DDR1) ND0_(DDR1)
Y2 NLD1 [6] [6] EA0 K4 A0 DQ18 E4 ED18 [6]
ND1_(DDR1)
AB17 W1 NLD2 [6] [6] EA1 L1 A1 DQ19 F5 ED19 [6]
VREF1 ND2_(DDR1)
AC11 W3 NLD3 [6] [6] EA2 L2 A2 DQ20 H3 ED20 [6]
VREF0 ND3_(DDR1)
AB1 NLD4 [6] [6] EA3 L3 A3 DQ21 H4 ED21 [6]
ND4_(DDR1)
AD2 NLD5 [6] [6] EA4 C2 A4 DQ22 E6 ED22 [6]
ND5_(DDR1)
AB18 W4 NLD6 [6] [6] EA5 D2 A5 DQ23 F7 ED23 [6]
EA18_(DDR1) ND6_(DDR1)
AE18 AE1 NLD7 [6] [6] EA6 E1 A6 DQ24 F6 ED24 [6]
EA17_(DDR1) ND7_(DDR1)
AE17 W2 NLD8 [6] [6] EA7 D3 A7 DQ25 D5 ED25 [6]
[6] EBA1 EA16_(DDR1) ND8_(DDR1)
AE21 Y3 NLD9 [6] [6] EA8 E2 A8 DQ26 E8 ED26 [6]
[6] EBA0 EA15_(DDR1) ND9_(DDR1)
AB19 AC2 NLD10[6] [6] EA9 D4 A9 DQ27 D6 ED27 [6]
EA14_(DDR1) ND10_(DDR1)
[6] EA13 AE22 AC1 NLD11 [6] [6] EA10 K3 A10 DQ28 D8 ED28 [6]
EA13_(DDR1) ND11_(DDR1)
[6] EA12 AC23 Y4 NLD12 [6] [6] EA11 F2 A11 DQ29 D7 ED29 [6]
EA12_(DDR1) ND12_(DDR1)
[6] EA11 AD22 V5 NLD13 [6] [6] EA12 F1 A12 DQ30 C8 ED30 [6]
EA11_(DDR1) ND13_(DDR1) VIO18_PMU [2,3,4,6,7,8,10]
[6] EA10 AD18 AE2 NLD14 [6] DQ31 C7 ED31 [6]
EA10_(DDR1) ND14_(DDR1)
BA[1:0] = [6] EA9 AE25 V1 NLD15 [6] R1 DNU
EA9_(DDR1) ND15_(DDR1) [6]
EA[15:14] [6] EA8 AE23 [6] R2 DNU NLD8 P2 NLD8
EA8_(DDR1) [6]
[6] EA7 AF25 R9 DNU NLD9 P3 NLD9
(LPDDR1) EA7_(DDR1) [6]
[6] EA6 AE24 R10 DNU NLD10 N4 NLD10
EA6_(DDR1) 2 [6]
[6] EA5 AF24 W5 NCEB [6] B5 VCCN NLD11 P4 NLD11
EA5_(DDR1) NCEB_(DDR1) [6]
[6] EA4 AE26 Y5 N5 VCCN NLD12 P5 NLD12
EA4_(DDR1) NWRB_(DDR1) NWRB [6] [6]
[6] EA3 AC18 AB2 C5 VSSN NLD13 N7 NLD13
EA3_(DDR1) NREB_(DDR1) NREB [6] 1uF [6]
[6] EA2 AE19 AC3 P6 VSSN NLD14 M7 NLD14
EA2_(DDR1) NCLE_(DDR1) NCLE [6] C506 [6]
[6] EA1 AE20 AD3 B1 NC NLD15 N8 NLD15
EA1_(DDR1) NALE_(DDR1) NALE [6]
[6] EA0 AF18 AE3 [6] ECKE B2 NC DNU A2 VIO18_PMU[2,3,4,6,7,8,10]
EA0_(DDR1) NRNB_(DDR1) NRNB [6] 1 B10 NC NC P1
[6] ECS1_B F3 NC NC G1
AC22 AB3 NC M3 EA13 EA13 [6]
ERESET NWPB_(DDR1)
[6] NLD0 N1 NLD0
NLD1 N2 B4 NCLE [6]
[6] NLD1 CLE
N3 C4

2 0201 1
[6] NLD2 NLD2 ALE NALE [6]

R501
M5 B6

47K
[6] NLD3 NLD3 /CE NCEB [6]
[6] NLD4 P7 NLD4 /RE B3 NREB [6]
[6] NLD5 M6 NLD5 /WE B7 NWRB [6]
DO NOT use this pin, Please use [6] NLD6 N6 NLD6 /WP C3 WATCHDOG [3,4]
[6] NLD7 M8 NLD7 R/#B C6 NRNB [6]
WATCHDOG as write-protect signal
P10 NC NC M4
@ NAND boot A10 A9
DNU DNU
H9DA4GH2GJAMCR-4EM

Please make sure the ball map is

match to the MCP type you selected

For other memory pin mux, please refer

to Design Notice "DDR1/DDR2 Pin Mux"
and "NAND/eMMC Pin Mux"

THIS DOCUMENT CONTAINS PROPRIETARY

INFORMATION AND SHALL NOT BE DUPLICATED
OR DISCLOSED TO OTHERS WITHOUT THE PRIOR
WROTTEN PERMISSION OF CK Techfaith
CK Telecom
Communication Technology Limited Communication Technology Limited
DRAWN: DATE: TITLE:
Shouchuang.Zhang
2013-3-5 MT6272W
CHECKED: DATE: SIZE: DRAWING NO:
D 5-MEM
DESIGNED: DATE: SHEET: REV:
SCALE: 1:1 6 OF 11 V1.0
 ANT602 ANT600 ANT601
ECT818000376
ECT818000376ECT818000376

CN600
C606 18pF 0R
50 ohm M603 M601

0201
GGE_PA_HB_IN 0201
[7] 0R 0R
R603 33pF C659 1 2

0201
TX_HB 50R IN OUT
[7] W_PA_VCC

BAND2 PA MODULE

R607
0201

R605
0201
NC

NC

3
4
C658 M602 M600 C617

02 01
L601
0201 0201 100nF
NC 39nH [3,4,7,8,10] VBAT
NC NC

C615 C616
C607 56pF 0R 0201 82pF 0201 100nF
0201

[7] GGE_PA_LB_IN 0201

R609
TX_LB 50R

R610
0201
R611
0201

NC
NC

3GB2_RXP
[7] C624 3.9pF
C626
50R TRXB2 [7]

0201
01 02 0R

PA / SKY77590

U601
8
7
6
5
4
3
2
1
1 10
50R
VBAT VCC
L603
50R

2
4
5
7
9
R616 U602

GND
GND
GND
GND
GND
GND
GND
GND

01 02
C618

0201
ASM_VCTRL_A R606 L607 [7] W_PA_B2_IN
18pF 2 9
[3] 0201 GND NC
0201 RF_IN RF_OUT 02 01 W_PA_BAND2 [7]

G
G
G
G
G
29 0R 1.2nH
1K C605 8

0201

01 02
RX

02 01
NC L608 L605 3 VMODE2 SKY77762-11 CPL_IN 8

02 01
R602 9 TX_HB_IN GND 1 RX L609 C619

SKY77590
28 2.4nH R617 C610
0201
10 TX_LB_IN GND 27 3 TX ANT 6 3.9nH
NC 4 7 0201 NC

0201
ASM_VCTRL_B 1K VMODE1 GND 0201

01 02
22pF BS2 ANT L604 NC 0.5pF
[3] 22pF [3,4,7,8,10] VBAT 11 26
0201 0201 12 BS1 GND 25 3GB2_RXN NC 5 6
[7] C625 3.9pF SAYRF1G88CA0B0A VEN CPL_OUT R619

GND
C611 C612 13 VBATT TRX_6 24 TRXB2 [7]
VCC TRX_5 TRXB5 [7] 01 02 F606

0201
14 23 NC

VRAMP
TRX_1
TRX_2
TRX_3
TRX_4

11
MODE
R618
50R

TXEN
C620 C648 C649

GND
C644 B1_CPL_OUT [7]

0201
L 0201 0201 0201 NC
W_PA_BAND2
22uF 100nF 27pF 10pF 50R [7] [3,7]
50R

15
16
17
18
19
20
21
22
VM1
R614 3GB5_RXP [3,7] B2_CPL_OUT [7]
ASM_VCTRL_C R608 0201 [7] C661 1.8nH
C660
50R TRXB5 [7] VM0

0201
[3] 51R 01 02 33pF
0201 [3] W_PA_B2_EN
1K TRXB1 [7]

2
4
5
7
9
R615 2G_LB [7]
WG_GGE_PA_ENABLE

G
G
G
G
G
0201
[3]
1K close to PA 2G_HB[7] 8

01 02
RX

01 02

02 01
22pF 22pF L613 L612 L614

02 01
0201 NC 33nH 1 RX L610
0201 3 6 27nH
C613 C614 TX ANT 5.6nH

3GB5_RXN
[7] C650 1.8nH SAYFH836MCC0F0A
01 02 F602

WG_GGE_PA_VRAMP 0201
[3] R612 10K
W_PA_BAND5
50R [7]

R613 50R
0201

C608 0201
24K 220pF
3GB1_RXP W_PA_BAND1
[7] C662 F604 [7]

0201
4.7pF
SAYRF1G95HN0F0A
L606 0R
3 TX ANT 6 01 02 TRXB1

01 02
L620 1 RX [7]
NC 8 RX 50R [7] W_PA_VCC

BAND5 PA MODULE

G
G
G
G
G
01 02
C663

0201
8.2pF L617
4.3nH C603

2
4
5
7
9
C671

02 01
L602 0201
NC 0201 100nF
[3,4,7,8,10] VBAT

01 02
L621 2nH
NC
3GB1_RXN
2G_LB [7]
0201

C664

0201
01 02
01 02 LB_RX_P 4.7pF C668 C669
C600

[7]
22pF

L618
L600 12nH [7] 0201 0201
2nH 82pF 100nF
10

W_PA_B1_IN [7]

W_PA_B2_IN[7]

W_PA_B5_IN [7]
02 01
GND

GND

C665 L616
02 01

C656 L615
9

GGE_PA_HB_IN [7]

GGE_PA_LB_IN [7]
0201 0201 F1_OUT 39nH VRF18-1
NC

3GB1_RXP [7]
NC VRF18-1

3GB1_RXN [7]
NC

3GB5_RXP[7]

3GB5_RXN[7]

3GB2_RXP [7]

3GB2_RXN [7]
[7]
LB C685
1 VBAT VCC 10
1
F1_IN 01 02 LB_RX_N C679 C651 R652 50R U604 56pF 50R
56pF

0201
8 [7] W_PA_BAND5

0201
L619 12nH [7] W_PA_B5_IN 2 SKY77765 RF_OUT 9
F1_OUT 0201 RF_IN
0R [7]
7 470NF 3 8
F2_OUT VMODE2 CPL_IN C686
4 0201
F2_IN NC C673
4 7
0201

0201
2G_HB HB PDET [7] R651 VMODE1 GND 0201
NC
C622

01 02 HB_RX_P
22pF

01 02
[7] L623 6.2nH NC
L632 3.3nH [7] 5 6
VEN CPL_OUT

2nH

GND
2nH
6
F2_OUT

01 02
GND

GND

01 02
B2_CPL_OUT [7]

L627

L628
02 01

11
C670 L635
50R
02 01

0201
C688 L624 R635
2

0201

0201
0201
1.5pF
F600 NC
7.5nH R653
NC
NC
NC
BD2012-20L0820TLF [3,7] VM1 50R R660 R665

A10

A11

D11
PDET [7]

C10
B11

B10
[3,7] VM0 0201 0201

D3

A2

A3

A5

A6

A8

A9
C3

C2

C7

C8

C9
E3

B3

B4

B5

B6

B8
J2

J7

J8
U600 24R 24R
01 02 HB_RX_N
L626 6.2nH

GND
GND
GND
GND
GND

3GB1_RXP

3GB1_RXN

3GB5_RXP

3GB5_RXN

3GB2_RXP

3GB2_RXN

3GB8_RXP

3GB8_RXN

2GHB_TX

3GH1_TX

3GH2_TX

3GL5_TX

2GLB_TX

VTXHF

DET

GND
GND

GND
GND
GND
GND
GND
[7] [3] W_PA_B5_EN

0201
F3 D9 R668
GND GND 33R
G3 GND GND E9
H3 GND GND F9
J3 GND GND G9
C4 FDD RX TXO H9
GND GND
D4 GND GND J9
VRF18-1
Two Application Circuit Conditions, [7] A1 B40_RXP DETGND D10

1.TSX Circuit : OSC600=TSX, R658=R656=NC, R659=100K+-1%, R655=R657=0ohm B1 B40_RXN TMEAS C11 TMEAS
[7] LB_RX_P C1 E10
2.XTAL Circuit :OSC600=Mobile XTAL, R658=R656=0ohm, R659=R655=R657=NC LB_RXP
TDD RX V28
C675 [7] LB_RX_N D1 G10 VTCXO28-1
LB_RXN 3GTX_IP TX_I_P [3]

R639
connect to main GND [7]

0201
0R
470NF C674
[7] HB_RX_P E1 G11
HB_RXP 3GTX_IN TX_I_N [3]
Route AUXADC_REF with 4mil trace width TX(I/Q)
[4] AUXADC_REF [7] HB_RX_N F1 F10 470NF
HB_RXN 3GTX_QP TX_Q_P [3] [7] W_PA_VCC
C689
VRF18-1 F2
MT6166 F11
BAND1 PA MODULE
R659

R656

1uF VRXHF 3GTX_QN TX_Q_N [3]

0201

0201
NC

0R

NCP15WF104F03RC
VRF18-1
XTAL1 G2 L11 [7] R645 C678
RFVCO_MON TXVCO_MON
OSC600 0201 100nF
Route AUXADC_TSX with 4mil trace width R657 7V26000028 [3,4,7,8,10] VBAT
AUXADC_TSX XTAL2 J1 XTAL1 VTXLF J11
[4]
0201
NC 1 3 R645 close to 3G PA
H2 XTAL2 TXBPI H10
XO TXBPI C676
C695 C696
2

[3]
VTCXO28_IC K1 J10 RCAL 0201 82pF 0201 100nF
VTCXO28 RCAL
Test pin 470NF
Route AUXADC_GND with 24mil trace width R655
GND_AUXADC 0201 G1 32K_EN TST2 K11
[4]
under AUXADC_REF/AUXADC_TSX trace NC
SRCLKENA L1 L10
VTCXO28-1 C677 EN_BB TST1
Connect TSX/XTAL GND BSI
R658

BSI-A_DAT2 [3]
0201

[7]
0R

R600
to GND_AUXADC first 470NF

0201
SRCLKENA K2 G8

2K
R646 0R CLK_SEL BSI_DATA2
Close to each other and nearby OSC600 26M output 1 10
than connect to main GND L2 H8 50R
VBAT VCC
50R
XO3 BSI_DATA1 C694 R678 U606 L636

0201
[7] W_PA_B1_IN 18pF 2 9 W_PA_BAND1
BSI-A_DAT1 [3] 0201 RF_IN RF_OUT 02 01
[7]
E4 GND GND B7 0R SKY77761 0R
connect to main GND [7]DCXO_32K_EN
AVDD_VIO18

F4 GND GND J6 3 VMODE2 CPL_IN 8

BSI_DATA0

G4 RX(I/Q) D8 C639
GND GND C680
OUT32K

BSI_CLK

H4 02010.5pF
VXODIG

[3,4,7] SRCLKENA E8 4 7
XMODE

BSI_EN

GND GND

0201
RX_QN

VMODE1 GND 0201 0.5pF

RX_QP

R637
VRXLF

RX_IN
RX_IP
GND
GND
GND
GND
GND
GND

GND
GND

GND
GND
GND
GND
XO4

XO2

XO1

NC 5 6
Route AUXADC_REF/AUXADC_TSX as differential trace with well GND shielding VEN CPL_OUT

GND
[3,4,7] SRCLKENA
MT6166
J4
C5
D5
E5
F5
D7

K4

K3

L4

K5

L5

K6

K7

L7

L8

K8

K10

K9

G6

H6

F8

E7
J5

C6
D6
E6
F6
and route AUXADC_GND with 24mil trace width under

11
B1_CPL_OUT

R629
[7]

51R
0201
AUXADC_TSX/AUXADC_REF trace to provide return current path. [4] CLK4_AUDIO
CLK4_AUDIO [3,7] VM1
VIO18_VGPIO

SYSCLK_WCN BSI-A_DAT0 [3]

[9] SYSCLK_WCN
CLK1_BB [3,7] VM0
[3] CLK1_BB BSI-A_CK [3]
DCXO_32K
VRF18-1

[4] DCXO_32K
[3] W_PA_B1_EN
BSI-A_EN [3]
[7] XMODE XMODE
[3] RX_I_P

[3] RX_I_N

[3]RX_Q_P

[3]RX_Q_N
R650
0201

VIO18_PMU
NC

[2,4] VTCXO_PMU
VTCXO28-1 [7]
[2,3,4,6,8,10] L630 0R VRF18-1
[7] R633 0R
C682 [4] VRF18_PMU
1uF VRF18-1 [7]
Logic VTCXO28-1 R641 R634 0R
MODE XMODE VXODIG [7] 0201 DCXO_32K_EN Reserved LC filter
DCXO_ NC [7] C684
32K_EN R642 470NF
0201
[7] VIO18_VGPIO

0R

DCXO + 32K XO 0(GND) 1(VIO18) 1(VIO18)

R643
VIO18_VGPIO 0201
XMODE
DCXO + 32K-Less 1(VTXCO28) 1(VTXCO28) 1(VTXCO28)
[7] 0R [7]
VXODIG [4] VPA_PMU W_PA_VCC [7]
R644
VTCXO28-1 0201 [7] R621 0R
[7] NC
THIS DOCUMENT CONTAINS PROPRIETARY
CK Telecom

2.2uF
R647
INFORMATION AND SHALL NOT BE DUPLICATED
VIO18_VGPIO 0201 VXODIG OR DISCLOSED TO OTHERS WITHOUT THE PRIOR
WROTTEN PERMISSION OF CK Techfaith

C630
[7]
VTCXO28-1
0R
R648
0201
[7]
Communication Technology Limited Communication Technology Limited
[7] NC DRAWN: DATE: TITLE:
Mo Haihua 2013-3-5 MT6272W
CHECKED: DATE: SIZE: DRAWING NO:
D 6-RF_MT6166_SKY77590_3G_PA
DESIGNED: DATE: SHEET: REV:
SCALE: 1:1 7 OF 11 V1.0
 4.0" WVGA LCD
Backlight LED Driver
F801
0R

VIO18_PMU
[2,3,4,6,7,8,10]
R813 0R
LCD_IOVCC
[8]
[3] MIPI_TDN0

[3] MIPI_TDP0
16 LR801
D0+ 0000
15 LR802
D0- 0000
0R
D0+
0R
D0-
1

2
´ý¸üвÎÊý
14
GND GND
3 VOUT max. : 38V
C806 LR803 1 Switch Frequency : 5KHz~100KHz
13 0R 4 GND
[3] MIPI_TCN D1+ 0000 D1+ 2
D0- VFB : 200mV
3
1uF 12 LR804 0R 5 4
NC
[3] MIPI_TCP D1- 0000 D1- D0+
5
11 6 GND
GND GND 6
CLK-
LR805 0R 7
10 7 NC
[3] MIPI_TDN1 D2+ 0000 D2+ 8
CLK+
9
9 LR806 0R 8 10
GND
D2- 0000 D2- D1-
[3] MIPI_TDP1 11

10uH
NC

L803
12
D1+
13
GND
14 L801 0R
NC

LVS303012
15 [3,4,7,10] VBAT
LED_PWM
16
[3] R821 GND
R811 NC GPIO_LRSTB 0201
1K 17 RESET C827
[4] VGP2 LCD_VCC [8] LPTE 18
[3] TE D801
19 NC
LCD_IOVCC 20 4.7uF
[8] IOVCC 2 8 1 2 L804 0R
0R C807 C808 [8] LCD_VCC 21 VDD SW VLED_P [8]
VIO28_PMU R812 VCI
22 GND
[2,4,5,8,10] 23 PSBD3D60V1H C831 C832 C833
[8] VLED_P

0201
2.2uF LED+ U801 R805
100nF [8] 24
VLED_N LED- 330K_1%
R801 1K 25 SGM3729
[3] ADC4_LCD_ID 0201
26
LCM_ID
R816
1uF(50V) 1nF(50V) 33pF(50V)
GND 0R 3 7 VOP=35.3V
C822 27 J801 [3] PWM_BL_CTRL 0201 EN OVP
C825 C826
GND 35.3V

FH26-25S-0.3SHW(Y320U_LCD)
NC 4
R817 NC

0201
NC NC 6
FB VLED_N [8]
10K
CLOSE TO LCD POWER PIN

GND_PAD
1 5
GND RSET

0201
R808
12K

9
R818
15R

L803µç¸ÐÁϺţº(4.7uH)SWPA3010S4R7MT
C831µçÈÝÁϺţº£¨1uF 50V£©CL10A105KA8NNNC

CTP
camera DOVDD must=1.8V ×¢Ò⣺CTP¹¤×÷µçѹ2.8V£¬µ«ÊÇI2CµçѹÐèΪ1.8V,ÐèҪȷÈÏCTP ICÊÇ·ñÖ§³Ö
MAIN CAMERA 2M CAMERA CONNECOR
[3] SDA_0 1 VIO18_PMU
SIO_D
[3] SCL_0 2 [2,3,4,6,7,8,10]
SIO_C
[3] CMVSYNC 3
VSYNC

10K R851

R850
0201
0201
[3] CMHSYNC 4
HREF
[3,4] VCAMD_IO_PMU 5
DOVDD
6

10K
[3] CMMCLK XCLK
7 [4] VGP1 NC R852
DGND 0201
[3] CMPCLK 8
PCLK 0R
9 [2,4,5,8,10] VIO28_PMU R853 1
Y0 0201 VDD
10 2 0201
R810 10R 2
Y1 [3] EINT1_CTP INT
[3] CMDAT0 11 [3,10] 2 0201
R809 10R 3
Y2 SCL_1 SCL
[3] CMDAT1 12 [3,10] 2 0201
R806 10R 4
Y3 SDA_1 SDA
13 2 0201
R804 10R 5
DGND [3]GPIO57_CTP_RSTB RESET
[3] CMDAT2 14 6
Y4 GND

GND
GND
[3] CMDAT3 15
Y5
[3] CMDAT4 16 C830
Y6
17

+ -
[3] CMDAT5

+ -

+ -

+ -
Y7 T805

7
8
T803 T806 T804
[3] CMDAT6 18 J804
Y8 1uF
[3] CMDAT7 19 Y9
[4] VCAMD_PMU B804 0R 20 DVDD
[3] GPIO_CMPDN 21 PWDN
B801 0R 22 AVDD
[4] VCAMA_PMU
[3] GPIO_CMRST 23
RESET
24
µ¥¶ÀÏÂÖ÷µØ¡£ AGND

0201
C834
J805 CTPµØµ¥¶À¸î¿ª
NC(or 330pF)
C812 C810 C816 C815
C813

NC 2.2uF
2.2uF NC
2.2uF

THIS DOCUMENT CONTAINS PROPRIETARY

INFORMATION AND SHALL NOT BE DUPLICATED
OR DISCLOSED TO OTHERS WITHOUT THE PRIOR
WROTTEN PERMISSION OF CK Techfaith
CK Telecom
Communication Technology Limited Communication Technology Limited
DRAWN: DATE: TITLE:
Shouchuang.Zhang 2013-3-5 MT6272W
CHECKED: DATE: SIZE: DRAWING NO:
D 7-LCD/CAM/CTP
DESIGNED: DATE: SHEET: REV:
SCALE: 1:1 8 OF 11 V1.0
1
 U101-C

[9]GPS_RX_IN B16 A14

GPS_RXIN GND_WBG
[9] GPS_RX_IP A16 D18
GPS_RXIP GND_WBG
GND_WBG B22
GND_WBG C16
[9]GPS_RX_QN B14 C17
GPS_RXQN GND_WBG
[9]GPS_RX_QP B15 C18
GPS_RXQP GND_WBG
GND_WBG C19
GND_WBG C20
[9] WB_TXIN A19 C15
WB_TXIN GND_WBG
[9] WB_TXIP B19 D16
WB_TXIP GND_WBG
GND_WBG D17
7L26002015 U1006 [9]WB_TXQN

2
B18 WB_TXQN GND_WBG D19
[9] WB_TXQP A18 D20
WB_TXQP GND_WBG

EN
GND_WBG C21
3 1 [9] WB_RXIN A21
GND VREF WB_RXIN
[9] WB_RXIP A22 WB_RXIP
E20 WB_CTRL0 [9]

TSENS
CONN_WB_CTRL0
4 6 VCN_2V8_PMU [9]WB_RXQN B20 F20 WB_CTRL1 [9]
OUT VCC WB_RXQN CONN_WB_CTRL1
[9] WB_RXQP B21 D22 WB_CTRL2 [9]
[4,9] WB_RXQP CONN_WB_CTRL2
CONN_WB_CTRL3 E22 WB_CTRL3[9]

5
CONN_WB_CTRL4 C22 WB_CTRL4[9]
CONN_XO_IN C1022 CONN_WB_CTRL5 C23 WB_CTRL5[9]
[9]
1uF [9]AVDD18_WBG F18 C14 CONN_RSTB [9]
AVDD18_WBG CONN_RSTB
CONN_SEN E15 CONN_SEN [9]
R1014 CONN_SDATA E14 CONN_SDATA[9]
0201 CONN_SCLK G12 CONN_SCLK [9]
SYSCLK_WCN
NC [7]
E13 FM_DATA [9]
CONN_F2W_DAT [9]
CONN_F2W_CLK F12 FM_CLK

CONN_XO_IN F14 CONN_XO_IN[9]

IC BASEBAND CHIP(WCDMA) 6572

WIFI/BT/GPS Single ANT Ref. WB_CTRL3

[9]
Based on your system level design , if WB_CTRL2
R1007
ANT1002 ANT1001 0201 50 Ohm better WiFi TX performance is needed on WB_CTRL4 [9]
0R
Close to MT6572
ECT818000376 101266-1 [9]
your system, please refer to WiFi WB_CTRL1
WB_CTRL5 [9]
F1002 performance enhance proposal
[9]
1

C1043 NC

0201
6 GND WIFI 1 WB_CTRL0
R1001
AVDD18_WB [9] VCN_1V8_PMU
[9] AVDD18_WBG 0201 [4,9]
M1001 50 Ohm [9] 0R
5 2 WB_RXIP
ANT GND
50 Ohm 50 Ohm [9]
0R L1055

02 01
C1001
NC WB_RXIN 0201 100nF
4 GND GPS 3 C1044 18pF
Same pad

0201
M1000 M1002 50 Ohm [9]
NC NC U1000
DP1608-V1524AA C1066 0201

30

29

28

27

26

25

24

23

22

21
NC

W_LNA_EXT

AVDD18_WBT

WB_CTRL5

WB_CTRL4

WB_CTRL3

WB_CTRL2

WB_CTRL1

WB_CTRL0

WB_RX_IP

WB_RX_IN
Optional: M1002 for better ESD performance 50 Ohm R1002
WBG_ANT 31 WB_GPS_RF_IN WB_RX_QP 20 WB_RXQP [9] AVDD18_WB VCN_1V8_PMU
0201 [4,9]
[9] 0R
R1003
R1016 [9] AVDD18_GPS 0201
VCN_1V8_PMU
[4,9]
50 Ohm 0201 32 GPS_DPX_RFOUT WB_RX_QN 19 WB_RXQN 0R
0R [9]

WB_TXIP
Star Conn
AVDD33_WB 33 AVDD33_WBT WB_TX_IP 18
[9] [9] C1007 C1008 for WB/GPS/WBG 1V8
0201 100nF 0201

34 17 WB_TXIN C1005 100pF

NC WB_TX_IN 0201 4.7nF
50 Ohm [9] C1006
×ßÏß¾¡Á¿¶Ì
1uF
35 NC WB_TX_QP 16 WB_TXQP

VCN_2V8_PMU
B1003
36 AVDD28_FM
MT6627PN WB_TX_QN 15
[9]

WB_TXQN
SZ1005G750T
[4,9] [9]

FM [5]
FM_RX_N_6572
FM_RX_N_6572
37 FM_LANT_N GPS_RX_IP 14 GPS_RX_IP
[9]
L1011
[5] FM_ANT 01 02
82nH 38 FM_LANT_P GPS_RX_IN 13 GPS_RX_IN
[9]
Same pad
L1012
01 02
NC

R1010
50 Ohm 39 12 GPS_RX_QP
0201
0R
GPS_RFIN GPS_RX_QP
[9]
refer to FM desense performance
R1010¿¿PIN39·ÅÖÃ
AVDD18_GPS enhance proposal
Based on your system level design , if [9] 40 AVDD18_GPS GPS_RX_QN 11 GPS_RX_QN VCN_2V8_PMU VCN_2V8_PMU
[4,9]
R1015

better GPS performance is needed on 0201

NC
[9] [4,9]

AVDD28_FSOURCE
C1002
your system, please refer to GPS 41 DVSS
0201 10nF

F2W_DATA
performance enhance proposal

F2W_CLK
FM_DBG
HRST_B

SDATA

XO_IN
CEXT
Close to ANT

SCLK

SEN
GPS MT6627 SMD QFN40

10
[4,9]
VCN_2V8_PMU

Close to MT6627

R1018 0R
AVDD33_WB VCN_3V3_PMU
[9] [4]
CONN_RSTB
[9] CONN_XO_IN
C1004 C1003 C1009 C1010
C1051 [9] 0201
U1010 1uF C1011 2.2uF 2.2uF 220nF
U1005 C1012
BGU7005 0201 100pF
SAFEB1G57KE0F00 C1037 18pF FM_DATA 1uF
50 Ohm L1006 3 RFIN VCC 4 100pF
0201

1 IN OUT 4 02 01 [9]
7.5nH 2 5
GND SHDN
G
G
G

GPIO_GPS_LNA_EN
[3] FM_CLK
2
3
5

1 GND RFOUT 6 [9]

C1050
0201
NC(10pF) MAX2659* 50 Ohm
C1016 33pF
0201

CONN_SCLK
[9]
C1018
0201
2.2pF CONN_SDATA
Infineon LNA [9]
CONN_SEN
[9]

THIS DOCUMENT CONTAINS PROPRIETARY

INFORMATION AND SHALL NOT BE DUPLICATED
OR DISCLOSED TO OTHERS WITHOUT THE PRIOR
WROTTEN PERMISSION OF CK Techfaith
CK Telecom
Communication Technology Limited Communication Technology Limited
DRAWN: DATE: TITLE:
Mo Haihua 2013-3-5 MT6272W
CHECKED: DATE: SIZE: DRAWING NO:
D 9-MT6627_GPS_BT/WIFI
DESIGNED: DATE: SHEET: REV:
SCALE: 1:1 9 OF 11 V1.0
1

1
 ²âÊÔµã

G-sensor
ÏÂÔØÓòâÊÔµã DEBUG
[4,10] VBUS TP_VUSB

[3,10] KCOL0 TP_KCOL0

[3] MCU_JTCK C1606
TP_MCU_JTCK

[3] 4.7uF
MCU_JTMS TP_MCU_JTMS
RESETB VIO28_PMU [2,4,5,8,10]
[3,4] TP_RESET
C1605 C1604

16

15

14
[3,10] KCOL0 TP1_KCOL0
0201
Ambient Light and Proximity Sensor

GND

C1

VDD
[3] UTXD2 TP_TXD2 100nF 10uF
[3] VIO18_PMU [2,3,4,6,7,8,10]
URXD2 TP_RXD2
[3,10] USB_DP TP_USB_DP1 1 13
[2,3,4,6,7,8,10] VIO18_PMU VDD_IO GND

0201
R1610
[3,10] USB_DM TP_USB_DM1 2 12 47K
C1608 C1601 SETC GND
C1603 U1604
0201 3 11 TMD27723

5
SETP INT1 EINT5_G_SENSOR [3]
1uF
100nF 220nF [3,4,7,8,10]

LEDR

LEDK
4 10 0R
SCL/SPC RESERVED 1 4
VIO28_PMU 0201 VDD LEDA VBAT
5 9 R1628

SDA/SDI
GND INT2 [2,4,5,8,10]

¶¨Î»¿×

SDA
3 C1644
дIMEIºÅ²âÊÔµã

INT

SCL
SDO
[3,8,10]
GND

CS
SCL_1
C1633

8
10uF

8
U1603
[3,10] URXD1 TP_URXD1
2.2uF
[3,10] UTXD1 TP_UTXD1 [3,8,10] SDA_1
HOLE5 R1619 1K
[4,10] PWRKEY TP_PWR HOLE3 [2,3,4,6,7,8,10] VIO18_PMU 0201 EINT4_ALS [3] SCL_1 SDA_1
[3,8,10] [3,8,10]
[3,4,7,8,10] VBAT TP_VBAT HOLE1 IC G SENSOR CHIP ¡À8g 12/8bit 3*3mm

[2,3,4,5,6,7,8,9,10] GND TP_GND

[4,10] BAT_TEMP TP_VTEMP

HOLE6 VIO18_PMU R1601 0201 10K
HOLE4 [2,3,4,6,7,8,10]
[3,10] URXD1 TP1_URXD1

[3,10] UTXD1 TP1_UTXD1

HOLE2
[4,10] PWRKEY TP_PWR1

[3,4,7,8,10] VBAT TP_VBAT1

[2,3,4,5,6,7,8,9,10] GND TP_GND1

ÌùƬÍ-ÂÝĸ TMD27723
[4,10] BAT_TEMP TP_VTEMP1

USB I/O
¿ª»ú¼üÓëÒôÁ¿¼ü
1
[4,10] VBUS VCHG/USB_PWR
2
[3,10] USB_DM D-

[3,10] USB_DP
3
D+ ͬINSTANTÏîÄ¿ [3,10] KCOL0
R524
0201
1K
1
2 KCOL0=VOL UP
4
ID
[4,10]
[3] KCOL1
R523
0201
1K 3
4 KCOL1=VOL DOWN
PWRKEY 5
5
GND
+ -

+ -

+ -

T1607 T1608 T1609

<1pF <1pF T516 T519
6
7
8
9

12V J1104
KIU90511S1M1R T1606

J1603

×ö²à¼üFPCʱ£¬Domesheet¶ÔÓ¦µÄÍâȦΪGND

ÆÁ±Î¿ò PCB¼°¸¨ÁÏ

ÆÁ±Î¿ò ÆÁ±Î¿ò ÆÁ±Î¿ò

PCB Label Label

LABEL_SMALL LABEL_BIG
PCB С¸ßαêÇ©¿Õ°×ÌùÖ½(ÎÞǦ) ´ó¸ßοհױêÇ©ÌùÖ½(ÎÞǦ)
SH_BB 5*18MM Ä͸ßÎÂ150¡æ(Á½±ß¸÷Áôµ×Ö½5MM) 5*32MM Ä͸ßÎÂ300¡æ (Á½±ß¸÷Áôµ×Ö½2MM)
1

SH_RF
1

SH_GPS
1

THIS DOCUMENT CONTAINS PROPRIETARY

INFORMATION AND SHALL NOT BE DUPLICATED
OR DISCLOSED TO OTHERS WITHOUT THE PRIOR
WROTTEN PERMISSION OF CK Techfaith
CK Telecom
Communication Technology Limited Communication Technology Limited
DRAWN: DATE: TITLE:

Shouchuang.Zhang2013-3-5 MT6272W
CHECKED: DATE: SIZE: DRAWING NO:
D 12-SENSOR/KEY/F_LED/BTB
DESIGNED: DATE: SHEET: REV:
SCALE: 1:1 10 OF 11 V1.0