Jordan University of Science and Technology

Faculty of Computer and Information Technology

Department of Computer Engineering

CPE 352 – Computer Architecture

First Semester (2007/2008)

Second Exam - Wednesday, December 05, 2007

Instructor: Dr. Abdulla Bataineh and Dr. Mazen Kharbutli

Student’s Name:
Student’s ID: Section #:

Exam Instructions:
ƒ This exam consists of 5 pages and 3 questions.
ƒ The total points for this exam are 30 points.
ƒ This exam’s duration is 90 minutes.
ƒ This is a closed-book and closed-notes exam.
ƒ Cheating is prohibited.
ƒ Answer all questions on the questions' sheets.

1
Question #1: [10 points]
Consider two implementations A and B of the MIPS instruction set, both built using the same technology.
Machine A uses a simple single cycle datapath design and has a CPI of 1.0 with a cycle time of 1ns.
Machine B uses a pipelined datapath to reduce the cycle time to 0.5 ns and has a CPI of 1.0 in the absence
of control and data hazards. However, taken branch instructions incur 2 stall cycles and loads followed by
a dependent instruction incur 1 stall cycle.

Part 1: (4 points)
For the two workloads below, assume that 80% of branches are taken and 50% of loads are followed by a
dependent instruction. Compute the CPI for the pipelined datapath (CPIB).

Workload % Branches % Loads % Stores % Other CPIB

W1 25% 20% 10% 45%
W2 15% 16% 8% 61%

Part 2: (6 points)
An alternative Machine C uses a pipeline design that reduces the cycle time to 0.4 ns, but requires
increasing the taken branch penalty to 4 stall cycles and the load-use delay to 2 stall cycles. Which machine
has the best performance? Show your work.

Workload CPIC Which Machine

is Better
(A or B or C)
W1
W2

2
 Question #2: [8 points]
Consider a pipelined datapath similar to the one in the book. Assume register writes occur in the first half
of the cycle, reads in the second half. There is a bypass from the output of the EX/MEM latch to the inputs
of the ALU. Assume that the control logic bypasses the data as soon as possible using the given
forwarding data paths, and stalls in decode otherwise. You may NOT add additional data paths. In this
problem, you will look at how a program snippet performs on this pipeline.

Use the table below to show how the given instruction sequence flows through the pipeline
and where stalls are necessary to resolve hazards.

Cycle
Instruction 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
add $1, $2, $3 IF ID EX MEM WB

sub $4, $1, $5 IF

or $6, $1, $4
and $7, $4, $8
lw $9, 4($7)
add $1, $2, $4
sw $1, 4($7)

3
Question #3: [12 points]
We wish to add the instruction INCRBEQ (increment and branch if zero). This instruction has a 6 bit
opcode (bits 26-31), a 5-bit Rs register field (bits 21-25), a 5-bit Rt register field (bits 16-20), and a 16-bit
displacement field (bits 0-15). The semantics of the instruction are as follows: the Rs register is
incremented by 1 and the new value is stored in the Rs register. If the new value is zero, the branch is
taken, else it is not. The branch target address is calculated by adding the 16-bit displacement, sign
extended and shifted left by 2 bits, to PC+4 (i.e, the PC of the next instruction). The Rt register field of
the instruction is not used.

Part 1: (5 points)
Modify the multi-cycle datapath and control signals to make this new instruction work. You cannot make
any changes to the instruction register, register file, ALU, or memory.
The changes are mainly: adding new multiplexers or modifying existing ones, adding new datapaths, and
adding control signals or expanding current control signals. Points will be taken off for solutions that
require more hardware, or take more time steps, than necessary.

PCWrite + (PCWriteCond•zero) RegDst PCSource

2
IorD MemRead MemWrite IRWrite RegWrite ALUsrcA PC+4
0
Branch
1 Target
26 <<2 28
2

I[25:0] 0
Read Read 1
I[25:21] Reg1 Data1 A
PC 0 zero
Address Read Read
1 Read I[20:16] ALUout
Data Reg2 Data2 B 0
Write I[15:11]
0 1
ALU
Data Write 4
I[15:0] 1
Reg 2
Memory IR
0 Write RF 3
1 Data ALUcontrol
MDR
16 sign 32 <<2 2
extend

MemtoReg ALUsrcB

4
Part 2: (7 points)

Fill in the list of control signals needed to implement the above new increment and branch if zero
(INCRBEQ) instruction.

Clock Function Description Signals

Cycle
1 Instruction -> IR MemRd=1, ALUSrcA=0, IorD=0, IRWrite=1, ALUSrcB=01
and PC=PC+4 ALUOp=add, PCWrite=1, PCSource=00