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Topstar Digital technologies Co.,LTD


D D

Board name: Mother Board Schematic 1. System Block Diagram & Schematic page description;
Project name: N01 2. Power Block Diagram & Discription;
Version: VerA 3. Annotations & information;
initial Date: 4. Schematic modify Item and history;
New update: 5. Power on & off Sequence;
6. ACPI Mode Switch Timings;
7. Power On Sequence Map;
8. CLOCK Distribution;
C C
9. Power Distribution;

Topstar Confidential

Hardware drawing by: Hardware check by: EMI Check by:

Power drawing by: Power check by:

B B

Manager Sign by:

A A
TOPSTAR TECHNOLOGY
Swain Xu
Page Name Title
Size Project Name Rev
A3 N01
A
Date: Wednesday, July 16, 2008 Sheet 1 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1

CONTENT

Topstar Confidential 1 Title


ShenZhen Topstar Industry Co.,LTD 2 System Block & Sch Page
3 PWR Block & description
D D
4 NOTE and Annotations
N01 SYSTEM BLOCK Ver:A 5 Sch Modify and history
6 CK-505M
7 Diamondvill (1of2)(Host BUS)
8 Diamondvill (2of2)(Power &GND)
Diamondville SC CK505M
9 Calistoga(HOST)
Clocking
10 Calistoga(Graphic)
FCBGA 437PIN CY28548 11 Calisoga(DDRII& NCTF)
+VCC_CORE,+VCCP
+VCCA1.5 +V3.3S PG 6 12 Calisoga(Power)
13 Calistoga(VSS&NC)
PG 7,8 14 DDRII SODIMM0
Backlight
Connector 15 LVDS Inverter CONN
+VDC
16 CRT CONN
PG 15 17 ICH7_M(1 of 4)
FSB
533MHz 18 ICH7_M(2 of 4)
19 ICH7_M(3 of 4)
LVDS 20 ICH7_M(4 of 4
10.21' TFT
C +V3.3S 21 SATA HDD C
Calistoga GSE DDR2
PG 15 DDR2 SODIMM1 22 Card Reader(UB6232 USB)
400/533
998 FCBGA 400/533 23 PCIE MINI SLOT 1
VGA +V0.9S,+V1.8,+V3.3S 24 PCIE MINI SLOT 2
R/G/B +V3.3S,+V1.5S, PG 14
+V1.05S,+V1.8 25 USB Port & FAN
+V5S +V2.5S
PG 16 26 Audio (ALC662)
PG 9,10,11, 27 LED
12,13 28 OTP
PCIE mini Card PCIE mini Card
10/100M 29 KBC(W83L951DG)
PG 24 PG 23 LAN 30 LAN(RTL8101E)
DMI PCIE X1 RTL8101E RJ45 31 ADAPTER IN
x2 +V5S,+V3.3S
32 BATTERY JACK
PG 30 33 V3.3AL/+V5AL POWER
34 DDR V1.8/+V0.9S POWER
PCIE 1X
ICH7-M 35 V1.5S/+V1.05S POWER
82801GBM 652 BGA 36 Power Good Logic_OVP
USB1.1/2.0
+V1.05S,+V3.3S S-ATA 37 Power Discharge Circuit
+V3.3AL,+V5AL 2.5" HHD 38 System 2.5V
BIOS +V1.5S,+V5S SATAO(R1.0) +V5S,+V3.3S
B 8Mbit +V3.3A_RTC 39 VCORE POWER B
+V3.3AL PG 21 40 CHARGER
PG 17,18,19,20
PG 18 41 Power On Secquence & Reset M
42 Power ON/OFF

Speaker

USB PORT1 HDA AMP L


+V5AL TPS6017A2
PG 25 +V5S
KB Matrix PG 26 R
KB Controller/EC
USB PORT2 W83L951DG
+V5AL MiC
+V3.3AL AZALIA
PG 29 LED & TouchPAD
ALC662 PG 26
+V5S,+V3.3S Audio Jack
USB PORT3
+V5AL PG 26

Daught Board
A TOPSTAR TECHNOLOGY A

Swain Xu
Page Name System Block & Index
SD/MMC/MS/XD CARD
Size Project Name Rev
PG 22 A3 N01
A
Date: Wednesday, July 16, 2008 Sheet 2 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

N01 POWER BLOCK Ver:A


D D

Charger power Battery


ISL6251 7.4V-8.4V
PU9 4A

Adapter VCC_CORE +VCC_CORE


Power +VDC ISL6545
12V 2.5A 1.1V,5A
Switch PU8
C C

Chipset Power
Always power DDR Power
ISL6545
ISL6545 TPS51116
PU4/PU5 PU3
PU1/PU2

+V3.3AL,2A +V1.8
+V1.5S,3A +V0.9S
/+V5AL,3A
/+V1.05S,3A
MOSFET
B
Switch B

+V3.3S,2A
/+V5S,3A
LDO

+V2.5S,0.5A

A A
TOPSTAR TECHNOLOGY

Swain Xu
Page Name PWR Block & description
Size Project Name Rev
A3 N01
A
Date: Wednesday, July 16, 2008 Sheet 3 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1

Voltage Rails
I2C SMB Address
+VDC Primary DC system power supply (6V-9.5V)
Device Address Hex Master
+VBATTERY Battery Power supply (6-8.4V) Clock Generator 1101 001x D2 ICH7-M
D D
+VCC_CORE Core Voltage for CPU
SO-DIMM0 1010 000x A0 ICH7-M
CPU Thermal Sensor 1001 100x 98 KBC
+V1.05S 1.05V for Calistoga & ICH7M core / FSB VTT Smart Battery 0001 011x 16 KBC
+V1.8 1.8V power rail for DDR2
PCIE Slot TBD TBD ICH7-M

+V0.9S 0.9V DDR2 Termination voltage

+V3.3AL 3.3V always on power rail


Power States
+V5AL 5V for ICH7-M's VCC5 Refsus
Signal SLP_S3# SLP_S4# SLP_S5# +V*ALW +V* +V*S Clock
+V3.3S 3.3V main power rail
S0(Full On) HIGH HIGH HIGH ON ON ON ON
+V5S 5V main power rail
S3(STM) LOW HIGH HIGH ON ON OFF OFF
+V2.5S 2.5V power rail for 945GMS
S4(STD) LOW LOW HIGH ON OFF OFF OFF
C C
Board stack up description S5(SoftOff) LOW LOW LOW ON OFF OFF OFF

PCB Layers
Top(Signal1)

VCC 2
Wake up Events
Signal 3 Trace Impedence:55ohm +/-15%
LID switch from EC
Signal4
Power switch from EC
Ground 5

Bottom(Signal6)

B B
PCB Footprints
3 5 4
USB Table
SOT23 SOT23_5
USB Port# Function Description
1 2 1 2 3
0 Standard USB2.0 Port
1 Standard USB2.0 Port
2 Standard USB2.0 Port
3 MINICARD_USB ns: Component marked "ns" is not stuff
4 CAM_USB
5 MINICARD_USB
A 6 CR_USB TOPSTAR TECHNOLOGY A
Swain Xu
7 NC Page Name
NOTE
Size Project Name Rev
A3 N01
A
Date: Wednesday, July 16, 2008 Sheet 4 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1

Schematic modify Item and history:

D D

C C

B B

A A
TOPSTAR TECHNOLOGY
Swain Xu
Page Name Sch Modify and history
Size Project Name Rev
A3 A
A
Date: Wednesday, July 16, 2008 Sheet 5 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1

+V3.3S 7,10,11,12,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,35,36,37,39

+V1.05S 7,8,9,11,12,17,20,28,35,36,37

+V3.3S FB28 U36


FB0805 CY28548
100ohm@100MHz,3A TSSOP64_0D5_6D1
1 2
D
2 VDD_PCI
SMBUS ADD:1101 001X D

C390 C391 C389 +V3.3S_CK_VDD 9 48


0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R VDD_48 IO_VOUT
16 VDD_PLL3
C0402 C0402 C0402 61 63 R345 0 R0402
VDD_REF SMB_DATA SMB_DATA_S 14,19,23,24
64 R347 0 R0402
SMB_CLK SMB_CLK_S 14,19,23,24
+V3.3S_CK_VDD 39 VDD_SRC
55 VDD_CPU
C388 C392 C393 C398 C397 38
SRC5/PCI_STOP# PM_STP_PCI# 19
10UF/6.3V,X5R 4.7UF/10V,Y5V 0.047uF/16V,X7R 0.047uF/16V,X7R 0.1UF/25V,Y5V +VDDIO_CLK 12 37
VDD_IO SRC5#/CPU_STOP# PM_STP_CPU# 19
C0805 C0805 C0402 C0402 C0402 +VDDIO_CLK 20
+VDDIO_CLK VDD_PLL3_IO CPU0 RN7
26 VDD_SRC_IO_1 CPU0 54 1 2 33 CLK_CPU_BCLK 7
36 53 CPU#0 3 4 RA0402_4
VDD_SRC_IO_2 CPU0# CLK_CPU_BCLK# 7
45 VDD_SRC_IO_3
+VDDIO_CLK 49 51 CPU1 RN8 1 2 33
VDD_CPU_IO CPU1 CLK_MCH_BCLK 9
50 CPU#1 3 4 RA0402_4
CPU1# CLK_MCH_BCLK# 9
1 PCI0/OE#_0/2_A
+V3.3S 47 RN18 1 2 33
SRC8/CPU2_ITP CLK_PCIE_EXPCARD2 24
3 PCI1/OE#_1/4_ASRC8#/CPU2#_ITP 46 3 4 RA0402_4 CLK_PCIE_EXPCARD2# 24
TME 4 34 RN10 3 4 33
PCI2/TME SRC10 CLK_PCIE_EXPCARD 23
1

FB29 35 1 2 RA0402_4
SRC10# CLK_PCIE_EXPCARD# 23
100ohm@100MHz,3A R631 22 R0402 5
29 PCI_CLK_EC PCI3/FSD
FB0805 33 MPCIE_CLKREQ R643 475,1% R0402 ns
SRC11/OE#_10 PCIE_CLKREQ# 23,24
R632 22 R0402 27M_SEL 6 32 MCH_CLKREQ R634 475,1% R0402 ns
23 PCI_CLK_DEBUG MCH_CLKREQ# 10
2

PCI4/SRC5_SEL SRC11#/OE#_9
R635 22 R0402 PCIF_ITP_EN 7 30 3 4
18 PCI_CLK_ICH PCIF5/ITP_EN SRC9 CLK_MCH_3GPLL 10
+VDDIO_CLK 31 1 2
SRC9# CLK_MCH_3GPLL# 10
C395 C396 CLK_XTAL_IN 60 RN11
C C394 10UF/6.3V,X5R 0.1uF/10V,X5R R640 10K R0402 XTAL_IN 33 C
SRC7/OE#_8 44
10UF/6.3V,X5R C0805 C0402 CLK_XTAL_OUT 59 43 RA0402_4
C0805 Set to SRC8 No more than 500 milXTAL_OUT SRC7#/OE#_6

SRC6 41 1 2 RN16 DREFSSCLK 10


+VDDIO_CLK R636 33 R0402 10 40 3 4 33
19 CLK_USB48 USB_48/FSA SRC6# DREFSSCLK# 10
C399 C400 RA0402_4
10UF/6.3V,X5R 0.1uF/10V,X5R CLK_BSEL0 R637 2.2K R0402 27 RN17 3 4 33
SRC4 CLK_PCIE_ICH 18
C0805 C0402 CLK_BSEL1 57 28 1 2 RA0402_4
FSB/TEST_MODE SRC4# CLK_PCIE_ICH# 18
CLK_BSEL2 R639 10K R0402 62 REF0/FSC/TEST_SEL RN12 3
SRC3/OE#_0/2_B 24 4 33 CLK_PCIE_LAN 30
R638 33 R0402 25 1 2 RA0402_4
19 CLK_ICH14 SRC3#/OE#_1/4_B CLK_PCIE_LAN# 30
+VDDIO_CLK
C401 C402 C403 C404 8 21 RN13 3 4 33
VSS_PCI SRC2/SATA CLK_ICH_SATA 17
10UF/6.3V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 11 22 1 2 RA0402_4
VSS_48 SRC2#/SATA# CLK_ICH_SATA# 17
C0805 C0402 C0402 C0402 15 VSS_IO
19 VSS_PLL3 SRC1/SE1 17
52 VSS_CPU SRC1#/SE2 18
23 VSS_SRC_1
+VDDIO_CLK 29 13 RN14 3 4 33
VSS_SRC_2 SRC0/DOT96 DREFCLK 10
C405 C406 58 14 1 2 RA0402_4
VSS_REF SRC0#/DOT96# DREFCLK# 10
10UF/6.3V,X5R 0.1uF/10V,X5R 42
C0805 C0402 VSS_SRC3 R734 0 R0402
CK_PWRGD/PWRDWN# 56 VR_PWRGD_CLK_EN 19
ns

C407
27pF/50V,NPO CLK_XTAL_IN
C0402 1
B B
Y5
14.318180MHz
XS2
C408
2

27pF/50V,NPO CLK_XTAL_OUT
C0402 +V3.3S
CLK_ICH14 C410 10PF/50V,NPO ns
BUS FREQUENCE SELECT C0402
MCH_CLKREQ R675 10K R0402 CLK_USB48 C411 10PF/50V,NPO ns
+V1.05S C0402
MPCIE_CLKREQ R646 10K R0402 PCI_CLK_DEBUG C412 10PF/50V,NPO ns
C0402
PCI_CLK_EC C413 10PF/50V,NPO ns
C409 C0402
R641 R650 R649 0.1UF/25V,Y5V TME R648 10K R0402 PCI_CLK_ICH C414 10PF/50V,NPO ns
56 1K 1K C0402 C0402
R0402 R0402 R0402 0:Normal mode
ns ns +V3.3S
1:No Overclocking
R642 0 R0402 ns CLK_BSEL0 R670 1K R0402
7 CPU_BSEL0 MCH_BSEL0 10
R651 0 R0402 ns CLK_BSEL1 R671 1K R0402
7 CPU_BSEL1 MCH_BSEL1 10
R647
R652 0 R0402 ns CLK_BSEL2 R672 1K R0402 10K
7 CPU_BSEL2 MCH_BSEL2 10
R0402

R645 R653 R655 27M_SEL


A
1K 0 0
FSC FSB FSA HOST Clock TOPSTAR TECHNOLOGY
A

R0402
ns
R0402 R0402 BSEL2 BSEL1 BSEL0 frequency Swain Xu
R654 Page Name CK505M
10K
0 0 1 133MHz R0402 Size Project Name Rev
ns A3 A A
Date: Wednesday, July 16, 2008 Sheet 6 of 42
1 0 1 100MHz PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1

+V1.05S +V1.05S 6,8,9,11,12,17,20,28,35,36,37


+V3.3S
+V3.3S 6,10,11,12,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,35,36,37,39

9 H_D#[63:0]
U22B
H_D#[63:0] 9
U22A ICTP H_D#0 Y11 R3 H_D#32
9 H_A#[31:3] T1 +V1.05S D[0]# D[32]#
H_A#3 P21 V19 H_D#1 W10 R2 H_D#33
A[3]# ADS# H_ADS# 9 D[1]# D[33]#
H_A#4 H20 Y19 H_D#2 Y12 P1 H_D#34
A[4]# BNR# H_BNR# 9 D[2]# D[34]#
H_A#5 N20 U21 H_D#3 AA14 N1 H_D#35
A[5]# BPRI# H_BPRI# 9 D[3]# D[35]#

DATA GRP 0
H_A#6 R20 H_D#4 AA11 M2 H_D#36
A[6]# D[4]# D[36]#

0
GROUP
ADDR
H_A#7 J19 T21 H_D#5 W12 P2 H_D#37
A[7]# DEFER# H_DEFER# 9 D[5]# D[37]#
H_A#8 N19 T19 R63 R64 H_D#6 AA16 J3 H_D#38
A[8]# DRDY# H_DRDY# 9 D[6]# D[38]#

DATA GRP 2
D H_A#9 G20 Y18 56 330 H_D#7 Y10 N3 H_D#39 D
A[9]# DBSY# H_DBSY# 9 D[7]# D[39]#
H_A#10 M19 R0402 R0402 H_D#8 Y9 G3 H_D#40
H_A#11 A[10]# H_D#9 D[8]# D[40]# H_D#41
H21 A[11]# BR0# T20 H_BREQ#0 9 Y13 D[9]# D[41]# H2
H_A#12 L20 H_D#10 W15 N2 H_D#42
A[12]# D[10]# D[42]#

CONTROL
H_A#13 M20 F16 H_IERR# H_D#11 AA13 L2 H_D#43
H_A#14 A[13]# IERR# R65 1K,1% R0402 H_D#12 D[11]# D[43]# H_D#44
K19 A[14]# INIT# V16 H_INIT# 17 Y16 D[12]# D[44]# M3
H_A#15 J20 H_D#13 W13 J2 H_D#45 H_DSTBN#/H_DSTBP# should route
H_A#16 A[15]# H_D#14 D[13]# D[45]# H_D#46 as differential pair
L21 A[16]# LOCK# W20 H_LOCK# 9 AA9 D[14]# D[46]# H1
K20 Place testpoint on H_D#15 W9 J1 H_D#47
9 H_ADSTB#0 ADSTB[0]# T3 ICTP H_IERR# with a GND D[15]# D[47]#
T2 ICTP D17 D15 Y14 K2
9 H_REQ#[4:0] AP0 RESET# H_CPURST# 9 0.1" away 9 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 9
H_REQ#0 N21 W18 Y15 K3
REQ[0]# RS[0]# H_RS#0 9 9 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 9
H_REQ#1 J21 Y17 W16 L1
REQ[1]# RS[1]# H_RS#1 9 9 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 9
H_REQ#2 G19 U20 T4 ICTP V9 M4 ICTP
REQ[2]# RS[2]# H_RS#2 9 DP#0 DP#2 T5
H_REQ#3 P20 W19
REQ[3]# TRDY# H_TRDY# 9 9 H_D#[63:0] H_D#[63:0] 9
H_REQ#4 R19 H_D#16 AA5 C2 H_D#48
REQ[4]# H_D#17 D[16]# D[48]# H_D#49
9 H_A#[31:3] HIT# AA17 H_HIT# 9 Y8 D[17]# D[49]# G2
H_A#17 C19 V20 H_D#18 W3 F1 H_D#50
A[17]# HITM# H_HITM# 9 D[18]# D[50]#
H_A#18 F19 H_D#19 U1 D3 H_D#51
H_A#19 A[18]# H_BPM#0 ICTP H_D#20 D[19]# D[51]# H_D#52
E21 A[19]# BPM[0]# K17 T7 W7 D[20]# D[52]# B4

DATA GRP 1
H_A#20 A16 J18 H_BPM#1 ICTP H_D#21 W6 E1 H_D#53
A[20]# BPM[1]# T6 D[21]# D[53]#
H_A#21 D19 H15 H_BPM#2 ICTP H_D#22 Y7 A5 H_D#54
A[21]# BPM[2]# T8 D[22]# D[54]#
H_A#22 C14 J15 H_BPM#3 ICTP H_D#23 AA6 C3 H_D#55

DATA GRP 3
A[22]# BPM[3]# T9 D[23]# D[55]#
ADDR GROUP 1

H_A#23 C18 K18 H_BPM#4 T10 ICTP H_D#24 Y3 A6 H_D#56


XDP/ITP SIGNALS

H_A#24 A[23]# PRDY# H_BPM#5 ICTP H_D#25 D[24]# D[56]# H_D#57


C20 A[24]# PREQ# J16 T11 W2 D[25]# D[57]# F2
H_A#25 E20 M17 H_TCK H_D#26 V3 C6 H_D#58
H_A#26 A[25]# TCK H_TDI H_D#27 D[26]# D[58]# H_D#59
D20 A[26]# TDI N16 U2 D[27]# D[59]# B6
H_A#27 B18 M16 H_TDO H_D#28 T3 B3 H_D#60
H_A#28 A[27]# TDO H_TMS +V1.05S H_D#29 D[28]# D[60]# H_D#61
C15 A[28]# TMS L17 AA8 D[29]# D[61]# C4
H_A#29 B16 K16 H_TRST# H_D#30 V2 C7 H_D#62
C H_A#30 A[29]# TRST# H_DBR# R674 0 R0402 ns H_D#31 D[30]# D[62]# H_D#63 C
B17 A[30]# BR1# V15 PM_SYSRST# 19 W4 D[31]# D[63]# D2
H_A#31 C16 Y4 E2
A[31]# 9 H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 9
H_A#32 A17 G17 R104 22 R0402 VR_PROCHOT# Y5 F3
H_A#33 B14
A[32]# PROCHOT#
E4 H_THERMDA R66 Layout Note: Z=55ohm, 9 H_DSTBP#1
Y6
DSTBP[1]# DSTBP[3]#
C5
H_DSTBP#3 9
THERM

A[33]# THRMDA 0.5" max for GTLREF 9 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 9
H_A#34 B15 E5 H_THERMDC 1K,1% T12 ICTP R4 D4
A[34]# THRMDC R0402 DP#1 DP#3 T13ICTP
H_A#35 A14 A[35]# COMP0 R68 27.4,1% R0402
9 H_ADSTB#1 B19 ADSTB[1]# THERMTRIP# H17 PM_THRMTRIP# 10,17,28 A7 GTLREF COMP[0] T1
T14 ICTP M18 R67 1K,1% R0402 ns ACLKPH U5 T2 COMP1 R70 54.9,1% R0402 Layout note:
AP1 R69 1K,1% R0402 ns DCLKPH ACLKPH COMP[1] COMP2 R72 27.4,1% R0402 Comp0,2 connec with Zo=27.4ohm,make
V5 DCLKPH COMP[2] F20
U18 R71 C19 T15 ICTP T17 F21 COMP3 R73 54.9,1% R0402 trace length shorter than 0.5"
17 H_A20M# A20M# BINIT# COMP[3]
T16 V11 2K,1% 0.1uF/10V,X5R T16 ICTP R6 MISC Comp1,3 connec with Zo=55ohm,make
17 H_FERR# FERR# BCLK[0] CLK_CPU_BCLK 6 R0402 EDM
J4 V12 C0402 EXTBGREF M6 R18 trace length shorter than 0.5"
17 H_IGNNE# IGNNE# BCLK[1] CLK_CPU_BCLK# 6 EXTBGREF DPRSTP# H_DPRSTP# 17
T17 ICTP N15
H CLK

17 H_STPCLK# R16 STPCLK# FORCEPR# DPSLP# R17 H_DPSLP# 17


T15 T18 ICTP N6 U4
17 H_INTR LINT0 HFPLL DPWR# H_DPWR# 9
R15 T20 ICTP P17 V17
17 H_NMI LINT1 MCERR# PWRGOOD H_PWRGD 17
U17 T19 ICTP T6 N18
17 H_SMI# SMI# RSP# SLP# H_CPUSLP# 9,17
6 CPU_BSEL0 J6 BSEL[0] CORE_DET A13 T21ICTP
D6 C21 H5 B7 CPU_CMREF
R74 R75 NC1 RSVD3 +V1.05S 6 CPU_BSEL1 BSEL[1] CMREF[1]
G6 C1 G5
NC

1K,1% 1K,1% NC2 RSVD2 6 CPU_BSEL2 BSEL[2]


H6 NC3 RSVD1 A3
R0402 R0402 K4 Diamondville
ns ns NC4
K5 NC5
M15 Layout Note: Z=55ohm, +V1.05S
NC6 R76 0.5" max for GTLREF
L16 NC7 1K,1%
+V1.05S R0402
Diamondville EXTBGREF
R77 Layout Note: Zo=55ohm,
+V1.05S 1K,1% 0.5" max for GTLREF
B R78 C20 R0402 B
R79 1K,1% R0402 H_A#32 2K,1% 0.1uF/10V,X5R CPU_CMREF
R82 1K,1% R0402 H_A#33 R0402 C0402
R81 1K,1% R0402 H_A#34 R80 56 R0402 H_TCK
R84 1K,1% R0402 H_A#35 R83 56 R0402 H_TRST# R85 C21
2K,1% 0.1uF/10V,X5R
R89 +V3.3S R0402 C0402
R150 56 R0402 H_TDO 220
R87 56 R0402 H_BPM#5 R0402
R86 56 R0402 H_TMS +V1.05S
R88 56 R0402 H_TDI
C23
R90 1K,1% R0402 ns H_NMI 0.1uF/10V,X5R
R92 1K,1% R0402 ns H_SMI# R94 C0402
R91 1K,1% R0402 ns H_INTR 1K,1%
R93 1K,1% R0402 ns H_STPCLK# For defensive design R0402 H_THERMDA
1

reservation only in this ns


R99 1K,1% R0402 ns H_DPSLP# initial release H_DPWR#
EC SMBUS ADD:1001 100X
VCC

R96 1K,1% R0402 ns H_DPRSTP# C22 2 8


DXP SMBCLK I2C_CLK 29
R95 1K,1% R0402 ns H_PWRGD 2200pF/25V,X7R
R97 C0402 3 7
+V3.3S DXN SMBDATA I2C_DATA 29
1K,1%
R0402 H_THERMDC G781
ns ADM1032AR 6
LM86CIM ALERT# OVT_SHUTDOWN# 28
R98 MAX6657MSA 4 THERM#
GND

330 SOIC-8 THERM#


R0402 C24 C25
A
U4 R100 R101 27pF/50V,NPO 27pF/50V,NPO A
5

F75383S 10K 10K C0402 C0402 TOPSTAR TECHNOLOGY


EC_PROCHOT# 29
SO8_50_150 R0402 R0402
+V1.05S Swain Xu
R102 Q4 R147 NOTE Page Name Diamondville(1of2)(Host BUS)
1K MMBT3904-F 1K
3

R0402 Q1 SOT23 R0402 1.H_THERMDA/C线宽10 MILS,并配对走线, Size Project Name Rev


MMBT3904-F R103 +V3.3S A3 A
+V1.05S 1
SOT23 56
1 +V1.05S 然后再包地处理. A
R0402 2.H_THERMDA/C走线远离19V及VGA或高速线走线 Date: Wednesday, July 16, 2008 Sheet 7 of 42
2

PROPERTY NOTE: this document contains information confidential and property to


VR_PROCHOT# TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1

+VCC_CORE 36,39
U22D
A2 VSS1 VSS162 N5 +V1.5S 10,11,12,20,23,24,35,36,37
A4 VSS2 VSS161 N7
A8 VSS4 VSS160 N9 +V1.05S 6,7,9,11,12,17,20,28,35,36,37
A15 VSS5 VSS159 N13
A18 VSS6 VSS158 N17
A19 P3 U22C +V1.05S
VSS7 VSS157
A20 VSS8 VSS156 P4
B1 VSS9 VSS155 P5 VTT1 C9
B2 VSS10 VSS154 P6 VTT2 D9

1
B5 P7 E9 C26 C27 C28 C29 C30 C31 C32 C33
VSS11 VSS153 +V1.05S VTT3 0.1uF/10V,X7R 0.1uF/10V,X7R 0.1uF/10V,X7R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R
D B8 P9 F8 + C34 D

1
VSS12 VSS152 VTT4 C0402 C0402 C0402 C0402 C0402 C0402 C0805 C0805 220uF/2.5V,POSCAP
B13 VSS13 VSS151 P13 VTT5 F9
B20 P15 G8 ns ns ns CT7343_19

2
VSS14 VSS149 VTT6 ns
B21 VSS15 VSS148 P16 V10 VCCF VTT7 G14
C8 VSS16 VSS147 P18 VTT8 H8
C17 VSS17 VSS146 P19 A9 VCCQ1 VTT9 H14
D1 VSS18 VSS145 R1 B9 VCCQ2 VTT10 J8
D5 VSS19 VSS144 R5 VTT11 J14
D8 VSS20 VSS143 R7 VTT12 K8
D14 VSS21 VSS142 R9 VTT13 K14
D18 VSS22 VSS141 R13 VTT14 L8
D21 VSS23 VSS140 R21 VTT15 L14
E3 VSS24 VSS139 T4 VTT16 M8
E6 VSS25 VSS138 T5 VTT17 M14
E7 VSS26 VSS137 T7 VTT18 N8
E8 T9 +VCC_CORE N14
VSS27 VSS136 VTT19
E15 VSS28 VSS135 T10 VTT20 P8
E16 VSS29 VSS134 T11 A10 VCCP1 VTT21 P14
E19 VSS30 VSS133 T12 A11 VCCP2 VTT22 R8
F4 VSS31 VSS132 T13 A12 VCCP3 VTT23 R14
F5 VSS32 VSS131 T18 B10 VCCP4 VTT24 T8
F6 VSS33 VSS130 U3 B11 VCCP5 VTT25 T14
F7 VSS34 VSS129 U6 B12 VCCP6 VTT26 U8
F17 VSS35 VSS128 U7 C10 VCCP7 VTT27 U9
F18 VSS36 VSS127 U15 C11 VCCP8 VTT28 U10
G1 VSS37 VSS126 U16 C12 VCCP9 VTT29 U11
G4 VSS38 VSS125 U19 D10 VCCP10 VTT30 U12
G7 VSS39 VSS124 V1 D11 VCCP11 VTT31 U13
G9 VSS41 VSS123 V4 D12 VCCP12 VTT32 U14
C G13 V6 E10 C
VSS42 VSS122 VCCP13
G21 VSS45 VSS121 V7 E11 VCCP14
H3 VSS46 VSS120 V8 E12 VCCP15
H4 VSS48 VSS119 V13 F10 VCCP16 VCCPC64 F14
H7 VSS49 VSS118 V14 F11 VCCP17 VCCPC63 F13
H9 VSS51 VSS117 V18 F12 VCCP18 VCCPC62 E14
H13 VSS52 VSS116 V21 G10 VCCP19 VCCPC61 E13
H16 W1 G11 +V1.5S
VSS53 VSS115 VCCP20
H18 VSS54 VSS114 W5 G12 VCCP21
H19 VSS55 VSS113 W8 H10 VCCP22
J5 VSS56 VSS112 W11 H11 VCCP23
J7 W14 H12 C35 C36
VSS57 VSS111 VCCP24 0.1uF/10V,X5R 10uF/6.3V,X5R
J9 VSS58 VSS110 W17 J10 VCCP25
J13 W21 J11 C0402 C0805
VSS59 VSS109 VCCP26 ns
J17 VSS60 VSS108 Y1 J12 VCCP27
K1 VSS61 VSS107 Y2 K10 VCCP28
K6 VSS62 VSS106 Y20 K11 VCCP29
K7 Y21 K12 Place near PIN D7
VSS63 VSS105 VCCP30
K9 VSS64 VSS104 AA2 L10 VCCP31 VCCA D7
K13 VSS65 VSS103 AA3 L11 VCCP32
K15 VSS66 VSS102 AA4 L12 VCCP33
K21 VSS67 VSS101 AA7 M10 VCCP34 VID[0] F15
L3 AA10 M11 D16 +VCC_CORE
VSS68 VSS100 VCCP35 VID[1]
L4 VSS69 VSS99 AA12 M12 VCCP36 VID[2] E18
L5 VSS70 VSS98 AA15 N10 VCCP37 VID[3] G15
L6 VSS71 VSS97 AA18 N11 VCCP38 VID[4] G16
L7 AA19 N12 E17 R106
VSS72 VSS96 VCCP39 VID[5] 100,1%
L9 VSS73 VSS95 AA20 P10 VCCP40 VID[6] G18
L13 P11 R0402
B VSS74 VCCP41 B
L15 VSS75 P12 VCCP42
L18 VSS76 R10 VCCP43 VCCSENSE C13
L19 VSS77 R11 VCCP44
M1 VSS78 R12 VCCP45
M5 VSS79 VSSSENSE D13
M7 VSS80
M9 Diamondville Layout Note: VCCSENSE
VSS81 and VSSSENSE lines R107
M13 VSS82
M21 should be of equal 100,1%
VSS83 R0402
N4 VSS84
length

Route VCCSENSE and VSSSENSE


traces at 27.4 Ohms with 50
Diamondville mil spacing

+VCC_CORE

C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52
0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R
C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402

A A
+VCC_CORE TOPSTAR TECHNOLOGY
Swain Xu
Page Name Diamondville (PWR&GND)(2of2)
C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64
10uF/6.3V,X5R Size Project Name Rev
10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R C0805 A3 N01
A
C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805
Date: Wednesday, July 16, 2008 Sheet 8 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1

+V1.05S
+V1.05S 6,7,8,11,12,17,20,28,35,36,37

+V1.05S
D D
U23A
7 H_D#[63:0] H_A#[31:3] 7
H_D#0 C4 F8 H_A#3
R108 H_D#1 HD0# HA3# H_A#4
F6 HD1# HA4# D12
221,1% H_D#2 H9 C13 H_A#5
R0603 H_D#3 HD2# HA5# H_A#6
H6 HD3# HA6# A8
H_D#4 F7 E13 H_A#7
H_D#5 HD4# HA7# H_A#8
E3 HD5# HA8# E12
H_XSWING Trace should be 10mil H_D#6 C2 J12 H_A#9
H_D#7 HD6# HA9# H_A#10
wide with 20mil C3 HD7# HA10# B13
H_D#8 K9 A13 H_A#11
spacing! H_D#9 F5
HD8# HA11#
G13 H_A#12
H_D#10 HD9# HA12# H_A#13
J7 HD10# HA13# A12
R109 C65 H_D#11 K7 D14 H_A#14
100,1% 0.1uF/10V,X5R H_D#12 HD11# HA14# H_A#15
H8 HD12# HA15# F14
R0402 C0402 H_D#13 E5 J13 H_A#16
H_D#14 HD13# HA16# H_A#17
K8 HD14# HA17# E17
H_D#15 J8 H15 H_A#18
H_D#16 HD15# HA18# H_A#19
J2 HD16# HA19# G15
H_D#17 J3 G14 H_A#20
H_D#18 HD17# HA20# H_A#21
N1 HD18# HA21# A15
H_D#19 M5 B18 H_A#22
H_D#20 HD19# HA22# H_A#23
K5 HD20# HA23# B15
+V1.05S H_D#21 J5 E14 H_A#24
H_D#22 HD21# HA24# H_A#25
H3 HD22# HA25# H13
H_D#23 J4 C14 H_A#26
H_D#24 HD23# HA26# H_A#27
N3 HD24# HA27# A17
R110 H_D#25 M4 E15 H_A#28
221,1% H_D#26 HD25# HA28# H_A#29
M3 HD26# HA29# H17
C R0603 H_D#27 N8 D17 H_A#30 C
H_D#28 HD27# HA30# H_A#31
N6 HD28# HA31# G17
H_D#29 K3
H_YSWING H_D#30 HD29#
Trace should be 10mil N9 HD30#
wide with 20mil H_D#31 M1 F10 +V1.05S
HD31# HADS# H_ADS# 7
H_D#32 V8 C12
spacing! HD32# HADSTB0# H_ADSTB#0 7
H_D#33 V9 H16
HD33# HADSTB1# H_ADSTB#1 7
R111 H_D#34 R6 E2
100,1% C66 H_D#35 HD34# H_AVREF R112
T8 HD35# HBNR# B9 H_BNR# 7
R0402 0.1uF/10V,X5R H_D#36 R2 C7 100,1%
HD36# HBPRI# H_BPRI# 7

HOST
C0402 H_D#37 N5 G8 R0402
HD37# HBREQ0# H_BREQ#0 7
H_D#38 N2 B10
HD38# HCPURST# H_CPURST# 7
H_D#39 R5 E1
H_D#40 HD39# HDVREF
U7 HD40#
H_D#41 R8 AA6
HD41# HCLKN CLK_MCH_BCLK# 6
H_D#42 T4 AA5 C67 C68 R113
HD42# HCLKP CLK_MCH_BCLK 6
H_D#43 T7 C10 0.1uF/10V,X5R 0.1uF/10V,X5R 200,1%
HD43# HDBSY# H_DBSY# 7
H_D#44 R3 C6 C0402 C0402 R0402
HD44# HDEFER# H_DEFER# 7
H_D#45 T5 H5 ns
HD45# HDINV0# H_DINV#0 7
H_D#46 V6 J6
HD46# HDINV1# H_DINV#1 7
+V1.05S H_D#47 V3 T9
HD47# HDINV2# H_DINV#2 7
H_D#48 W2 U6
HD48# HDINV3# H_DINV#3 7
H_D#49 W1 G7
HD49# HDPWR# H_DPWR# 7
H_D#50 V2 E6
HD50# HDRDY# H_DRDY# 7 Place close to PIN-E1/E2
H_D#51 W4 F3
HD51# HDSTBN0# H_DSTBN#0 7
R114 R115 H_D#52 W7 M8
HD52# HDSTBN1# H_DSTBN#1 7
54.9,1% 54.9,1% H_D#53 W5 T1
HD53# HDSTBN2# H_DSTBN#2 7
R0402 R0402 H_D#54 V5 AA3
HD54# HDSTBN3# H_DSTBN#3 7
H_D#55 AB4 F4
B HD55# HDSTBP0# H_DSTBP#0 7 B
H_D#56 AB8 M7
HD56# HDSTBP1# H_DSTBP#1 7
H_XSCOMP H_D#57 W8 T2
HD57# HDSTBP2# H_DSTBP#2 7
H_D#58 AA9 AB3
HD58# HDSTBP3# H_DSTBP#3 7
H_YSCOMP H_D#59 AA8
H_D#60 HD59#
AB1 HD60#
H_D#61 AB7
H_D#62 HD61#
AA2 HD62# HHIT# C8 H_HIT# 7
H_XRCOMP H_D#63 AB5 B4
HD63# HHITM# H_HITM# 7
HLOCK# C5 H_LOCK# 7 H_REQ#[4:0] 7
H_YRCOMP G9 H_REQ#0
HREQ0# H_REQ#1
HREQ1# E9
H_XRCOMP A10 G12 H_REQ#2
H_XSCOMP HXRCOMP HREQ2# H_REQ#3
Trace should be 10mil A6 HXSCOMP HREQ3# B8
R116 R117 wide with 20mil H_XSWING C15 F12 H_REQ#4
24.9,1% 24.9,1% H_YRCOMP HXSWING HREQ4#
J1 A5 H_RS#0 7
R0402 R0402 spacing! H_YSCOMP K1
HYRCOMP HRS0#
B6
HYSCOMP HRS1# H_RS#1 7
H_YSWING H1 G10
HYSWING HRS2# H_RS#2 7
HCPUSLP# E8 H_CPUSLP# 7,17
HTRDY# E10 H_TRDY# 7

945GMS

A A
TOPSTAR TECHNOLOGY
Swain Xu
Page Name Calistoga(HOST)
Size Project Name Rev
A3 N01 A
Date: Wednesday, July 16, 2008 Sheet 9 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

+V3.3S 6,7,11,12,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,35,36,37,39

+V1.5S_PCIE 12

+V1.5S 8,11,12,20,23,24,35,36,37
+V1.8 +V1.8 12,14,34,36,37

+V1.5S_PCIE
U23F
U23B
D D
H27 SDVOCTRL_DATA EXP_COMPI R28
18 DMI_TXN0 Y29 DMI_RXN0 CFG0 C18 MCH_BSEL0 6 J27 SDVOCTRL_CLK EXP_ICOMPO M28
Y32 E18 Y26 R123
18 DMI_TXN1 DMI_RXN1 CFG1 MCH_BSEL1 6 6 CLK_MCH_3GPLL# GCLKN
Y28 G20 AA26 N30 24.9,1%
18 DMI_TXP0 DMI_RXP0 CFG2 MCH_BSEL2 6 6 CLK_MCH_3GPLL GCLKP SDV0_TVCLKIN# R0402

MISC
18 DMI_TXP1 Y31 DMI_RXP1 CFG3 G18 SDVO_INT# R30
J20 GMS_CFG5 T29
CFG5 SDVO_FLDSTALL#
18 DMI_RXN0 V28 DMI_TXN0 CFG6 J18
18 DMI_RXN1 V31 DMI_TXN1
18 DMI_RXP0 V29 DMI_TXP0 16 CRT_DDC_CLK H20 DDCCLK SDVO_TVCLKIN M30
V32 R130 R131 R132 H22 P30

DMI
18 DMI_RXP1 DMI_TXP1 16 CRT_DDC_DATA DDCDATA SDVO_INT
2.2K 2.2K 2.2K A24 T30
R0402 R0402 R0402 16 CRT_BLUE BLUE SDVO_FLDSTALL
A23 BLUE#
ns ns E25
16 CRT_GREEN GREEN
14 M_CLK_DDR0 AF33 SM_CK0 MCH_RSVD1 K32 F25 GREEN#

SDVO
AG1 K31 C25

VGA
14 M_CLK_DDR1 SM_CK1 MCH_RSVD2 16 CRT_RED RED
MCH_RSVD7 C17 D25 RED#
AJ1 F18 16 CRT_VSYNC R125 39 R0402 F27
SM_CK2 MCH_RSVD8 R120 39 R0402 VSYNC
AM30 SM_CK3 MCH_RSVD9 A3 16 CRT_HSYNC D27 HSYNC

CFG/RSVD
R121 255,1%R0603 H25 P28
REFSET SDVOB_RED#
14 M_CLK_DDR#0 AG33 SM_CK0# SDVOB_GREEN# N32
14 M_CLK_DDR#1 AF1 SM_CK1# 15 LVDS_BKLTCTL H30 LBKLT_CTRL SDVOB_BLUE# P32
15,29 LVDS_BKLTEN G29 LBKLT_EN SDVOB_CLKN T32
AK1 LCTLA_CLK F28
SM_CK2# LCTLB_DATA LCTLA_CLK
AN30 SM_CK3# E28 LCTLB_CLK

DDR2 MUXING
L_DDC_CLK G28 N28
L_DDC_DATA LDDC_CLK SDVOB_RED
14 M_CKE0 AN21 SM_CKE0 H28 LDDC_DATA SDVOB_GREEN M32
14 M_CKE1 AN22 SM_CKE1 15 LVDS_VDDEN K30 LVDD_EN SDVOB_BLUE P33
AF26 R122 1.5K,1% R0402 K27 R32
C SM_CKE2 LIBG SDVOB_CLKP C
AF25 SM_CKE3 J29 LVBG
J30 LVREFH
AG14 K29 +V1.5S
14 M_CS#0 SM_CS0# LVREFL
14 M_CS#1 AF12 SM_CS1#
AK14 SM_CS2# 15 MCH_LVDS_CLKAN D30 LACLKN TVDAC_A A21
AH12 SM_CS3# 15 MCH_LVDS_CLKAP C30 LACLKP TVDAC_B C20
A30 LBCLKN TVDAC_C E20

LVDS
AJ21 SMOCDCOMP0 A29 LBCLKP TV_REFSET G23

TV
AF11 SMOCDCOMP1 ICHSYNC# E31 MCH_ICH_SYNC# 18 TV_IRTNA B21
BM_BUSY# G21 PM_BMBUSY# 19 15 MCH_LVDS_YAN0 G31 LADATAN0 TV_IRTNB C21
PM

+V1.8 AE12 F26 R_PM_EXTTS#0 F32 D21


14 M_ODT0 SM_ODT0 EXT_TS0# 15 MCH_LVDS_YAN1 LADATAN1 TV_IRTNC
AF14 H26 PM_EXTTS#1 15 MCH_LVDS_YAN2 D31
14 M_ODT1 SM_ODT1 EXT_TS1#/DPRSLPVR LADATAN2
1

AJ14 SM_ODT2 THRMTRIP# J15 PM_THRMTRIP# 7,17,28


R140 AJ12 AB29 15 MCH_LVDS_YAP0 H31
SM_ODT3 PWROK IMVP_PWRGD 19,29,39 LADATAP0
10K,1% W27 R141 100 R0402 15 MCH_LVDS_YAP1 G32 G26
RSTIN# BUF_PLT_RST# 18,19,23,24,29,30 LADATAP1 TV_DCONSEL0
M_RCOMPN AN12 15 MCH_LVDS_YAP2 C31 J26
M_RCOMPP SMRCOMPN LADATAP2 TV_DCONSEL1
AN14
2

SMRCOMPP
AA33 SMVREF0 F33 LBDATAN0
CLK

AE1 SMVREF1 DREF_CLKN A27 DREFCLK# 6 D33 LBDATAN1


DREF_CLKP A26 DREFCLK 6 F30 LBDATAN2
1

C69 C70 C71 J33


DREF_SSCLKN DREFSSCLK# 6
R142 2.2uF/10V,X7R 0.1uF/10V,X5R 0.1uF/10V,X5R H33 E33
DREF_SSCLKP DREFSSCLK 6 LBDATAP0
10K,1% C0805 C0402 C0402 J22 D32
CLKREQB MCH_CLKREQ# 6 LBDATAP1
F29 LBDATAP2
2

945GMS
945GMS
Close to GMCH
ONE PIN, ONE CAP
B B
R733 SM_VREF_L 14,34
0
R0402 +V3.3S

R118 150,1% R0402 CRT_BLUE

R119 150,1% R0402 CRT_GREEN


+V3.3S R126 R127 R128 R129
R124 150,1% R0402 CRT_RED 10K 10K 10K 10K
+V1.8 R0402 R0402 R0402 R0402
150ohm电阻到GMCH LCTLA_CLK
R133 R134 R151 走线阻抗37.5ohm
R136
80.6,1%
10K
R0402
10K
R0402
10K
R0402
150ohm电阻到VGA口 LCTLB_DATA

R0603 ns 走线阻抗50ohm 15 L_DDC_CLK


MCH_CLKREQ# PLACE 150 OHM
M_RCOMPN
15 L_DDC_DATA
R_PM_EXTTS#0 R138 0 R0402
PM_EXTTS#0 14
RESISTORS CLOSE TO
M_RCOMPP GMCH
PM_EXTTS#1 R139 0 R0402
PM_DPRSLPVR 19
R137
80.6,1%
R0603

A A
TOPSTAR TECHNOLOGY
Swain Xu
Page Name Calistoga(Graphic)
Size Project Name Rev
A3 N01 A

Date: Wednesday, July 16, 2008 Sheet 10 of 42


PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1

+V1.05S 6,7,8,9,12,17,20,28,35,36,37

+V1.5S 8,10,12,20,23,24,35,36,37

+V3.3S 6,7,10,12,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,35,36,37,39

+V1.05S +V1.5S
U23H

U23C T25 VCC_NCTF1 VCCAUX_NCTF1 AD25


D 14 MA_DATA[63:0] R25 VCC_NCTF2 VCCAUX_NCTF2 AC25 D
MA_DATA0 AC31 AK12 P25 AB25
SA_DQ0 SA_BS_0 MA_A_BS#0 14 VCC_NCTF3 VCCAUX_NCTF3
MA_DATA1 AB28 AH11 N25 AD24
SA_DQ1 SA_BS_1 MA_A_BS#1 14 VCC_NCTF4 VCCAUX_NCTF4
MA_DATA2 AE33 AG17 M25 AC24
SA_DQ2 SA_BS_2 MA_A_BS#2 14 VCC_NCTF5 VCCAUX_NCTF5
MA_DATA3 AF32 P24 AD22
SA_DQ3 MA_DM[7:0] 14 VCC_NCTF6 VCCAUX_NCTF6
MA_DATA4 AC33 AB30 MA_DM0 N24 AD21
MA_DATA5 SA_DQ4 SA_DM0 MA_DM1 VCC_NCTF7 VCCAUX_NCTF7
AB32 SA_DQ5 SA_DM1 AL31 M24 VCC_NCTF8 VCCAUX_NCTF8 AD20
MA_DATA6 AB31 AF30 MA_DM2 Y22 AD19
MA_DATA7 SA_DQ6 SA_DM2 MA_DM3 VCC_NCTF9 VCCAUX_NCTF9
AE31 SA_DQ7 SA_DM3 AK26 W22 VCC_NCTF10 VCCAUX_NCTF10 AD18
MA_DATA8 AH31 AL9 MA_DM4 V22 AD17
MA_DATA9 SA_DQ8 SA_DM4 MA_DM5 VCC_NCTF11 VCCAUX_NCTF11
AK31 SA_DQ9 SA_DM5 AG7 U22 VCC_NCTF12 VCCAUX_NCTF12 AD16
MA_DATA10 AL28 AK5 MA_DM6 T22 AD15
MA_DATA11 SA_DQ10 SA_DM6 MA_DM7 VCC_NCTF13 VCCAUX_NCTF13
AK27 SA_DQ11 SA_DM7 AH3 R22 VCC_NCTF14 VCCAUX_NCTF14 AD14
MA_DATA12 AH30 P22 K14
SA_DQ12 MA_DQS[7:0] 14 VCC_NCTF15 VCCAUX_NCTF15
MA_DATA13 AL32 AC28 MA_DQS0 N22 AD13
MA_DATA14 SA_DQ13 SA_DQS0 MA_DQS1 VCC_NCTF16 VCCAUX_NCTF16
AJ28 SA_DQ14 SA_DQS1 AJ30 M22 VCC_NCTF17 VCCAUX_NCTF17 Y13
MA_DATA15 AJ27 AK33 MA_DQS2 Y21 W13
MA_DATA16 SA_DQ15 SA_DQS2 MA_DQS3 VCC_NCTF18 VCCAUX_NCTF18
AH32 SA_DQ16 SA_DQS3 AL25 W21 VCC_NCTF19 VCCAUX_NCTF19 V13
MA_DATA17 AF31 AN9 MA_DQS4 V21 U13
MA_DATA18 SA_DQ17 SA_DQS4 MA_DQS5 VCC_NCTF20 VCCAUX_NCTF20
AH27 SA_DQ18 SA_DQS5 AH8 U21 VCC_NCTF21 VCCAUX_NCTF21 T13
MA_DATA19 AF28 AM2 MA_DQS6 T21 R13
MA_DATA20 SA_DQ19 SA_DQS6 MA_DQS7 VCC_NCTF22 VCCAUX_NCTF22
AJ32 SA_DQ20 SA_DQS7 AE3 R21 VCC_NCTF23 VCCAUX_NCTF23 P13
MA_DATA21 AG31 P21 N13
SA_DQ21 MA_DQS#[7:0] 14 VCC_NCTF24 VCCAUX_NCTF24
MA_DATA22 AG28 AC29 MA_DQS#0 N21 M13
MA_DATA23 SA_DQ22 SA_DQS0# MA_DQS#1 VCC_NCTF25 VCCAUX_NCTF25
AG27 SA_DQ23 SA_DQS1# AK30 M21 VCC_NCTF26 VCCAUX_NCTF26 AD12
MA_DATA24 AN27 AJ33 MA_DQS#2 Y20 Y12
MA_DATA25 SA_DQ24 SA_DQS2# MA_DQS#3 VCC_NCTF27 VCCAUX_NCTF27
AM26 AM25 W20 W12

DDR2 SYSTEM MEMORY


MA_DATA26 SA_DQ25 SA_DQS3# MA_DQS#4 VCC_NCTF28 VCCAUX_NCTF28
AJ26 SA_DQ26 SA_DQS4# AN8 V20 VCC_NCTF29 VCCAUX_NCTF29 V12
MA_DATA27 AJ25 AJ8 MA_DQS#5 U20 U12
C MA_DATA28 SA_DQ27 SA_DQS5# MA_DQS#6 VCC_NCTF30 VCCAUX_NCTF30 C
AL27 SA_DQ28 SA_DQS6# AM3 T20 VCC_NCTF31 VCCAUX_NCTF31 T12
MA_DATA29 AN26 AE2 MA_DQS#7 R20 R12
MA_DATA30 SA_DQ29 SA_DQS7# VCC_NCTF32 VCCAUX_NCTF32
AH25 SA_DQ30 MA_A_A[13:0] 14 P20 VCC_NCTF33 VCCAUX_NCTF33 P12
MA_DATA31 AG26 AJ15 MA_A_A0 N20 N12
MA_DATA32 SA_DQ31 SA_MA0 MA_A_A1 VCC_NCTF34 VCCAUX_NCTF34
AM12 SA_DQ32 SA_MA1 AM17 M20 VCC_NCTF35 VCCAUX_NCTF35 M12
MA_DATA33 AL11 AM15 MA_A_A2 Y19 AD11
MA_DATA34 SA_DQ33 SA_MA2 MA_A_A3 VCC_NCTF36 VCCAUX_NCTF36
AH9 SA_DQ34 SA_MA3 AH15 P19 VCC_NCTF37 VCCAUX_NCTF37 AD10
MA_DATA35 AK9 AK15 MA_A_A4 N19 K10
MA_DATA36 SA_DQ35 SA_MA4 MA_A_A5 VCC_NCTF38 VCCAUX_NCTF38
AM11 SA_DQ36 SA_MA5 AN15 M19 VCC_NCTF39 VSS_NCTF1 AN33
MA_DATA37 AK11 AJ18 MA_A_A6 Y18 AA25
MA_DATA38 SA_DQ37 SA_MA6 MA_A_A7 VCC_NCTF40 VSS_NCTF2
AM8 AF19 P18 V25
MA_DATA39
MA_DATA40
MA_DATA41
AK8
AG9
AF9
SA_DQ38
SA_DQ39
SA_DQ40
SA_MA7
SA_MA8
SA_MA9
AN17
AL17
AG16
MA_A_A8
MA_A_A9
MA_A_A10
N18
M18
Y17
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
NCTF VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
U25
AA22
AA21
MA_DATA42 SA_DQ41 SA_MA10 MA_A_A11 VCC_NCTF44 VSS_NCTF6
AF8 SA_DQ42 SA_MA11 AL18 P17 VCC_NCTF45 VSS_NCTF7 AA20
MA_DATA43 AK6 AG18 MA_A_A12 N17 AA19
MA_DATA44 SA_DQ43 SA_MA12 MA_A_A13 VCC_NCTF46 VSS_NCTF8
AF7 SA_DQ44 SA_MA13 AL14 M17 VCC_NCTF47 VSS_NCTF9 AA18
MA_DATA45 AG11 Y16 AA17
MA_DATA46 SA_DQ45 VCC_NCTF48 VSS_NCTF10
AJ6 SA_DQ46 SA_CAS# AJ17 MA_A_CAS# 14 P16 VCC_NCTF49 VSS_NCTF11 AA16
MA_DATA47 AH6 AK18 N16 AA15
SA_DQ47 SA_RAS# MA_A_RAS# 14 VCC_NCTF50 VSS_NCTF12
MA_DATA48 AN6 AN28 TP_MA_RCVENIN# M16 AA14 +V3.3S
SA_DQ48 SA_RCVENINB T23 ICTP ns VCC_NCTF51 VSS_NCTF13
MA_DATA49 AM6 AM28 TP_MA_RCVENOUT# Y15 AA13
SA_DQ49 SA_RCVENOUTB T22 ICTP ns VCC_NCTF52 VSS_NCTF14
MA_DATA50 AK3 AH17 P15 A4
SA_DQ50 SA_WEB MA_A_WE# 14 VCC_NCTF53 VSS_NCTF15
MA_DATA51 AL2 N15 A33
MA_DATA52 SA_DQ51 VCC_NCTF54 VSS_NCTF16 R143
AM5 SA_DQ52 SB_BS_0 AH21 M15 VCC_NCTF55 VSS_NCTF17 B2
MA_DATA53 AL5 AJ20 Y14 AN1 1K
MA_DATA54 SA_DQ53 SB_BS_1 VCC_NCTF56 VSS_NCTF18 R0402
AJ3 SA_DQ54 SB_BS_2 AE27 W14 VCC_NCTF57 VSS_NCTF19 C1
MA_DATA55 AJ2 V14 ns
MA_DATA56 SA_DQ55 VCC_NCTF58 GMS_CFG19
AG2 SA_DQ56 SB_MA0 AN20 U14 VCC_NCTF59 CFG19 K28
B MA_DATA57 B
AF3 SA_DQ57 SB_MA1 AL21 T14 VCC_NCTF60
MA_DATA58 AE7 AK21 R14 K25
MA_DATA59 SA_DQ58 SB_MA2 VCC_NCTF61 MCH_RSVD10
AF6 SA_DQ59 SB_MA3 AK22 P14 VCC_NCTF62 MCH_RSVD11 K26
MA_DATA60 AH5 AL22 N14 R24
MA_DATA61 SA_DQ60 SB_MA4 VCC_NCTF63 MCH_RSVD12
AG3 SA_DQ61 SB_MA5 AH22 M14 VCC_NCTF64 MCH_RSVD13 T24
MA_DATA62 AG5 AG22 K21
MA_DATA63 SA_DQ62 SB_MA6 MCH_RSVD14
AF5 SA_DQ63 SB_MA7 AF21 T10 VTT_NCTF1 MCH_RSVD15 K19
SB_MA8 AM21 R10 VTT_NCTF2 MCH_RSVD16 K20
SB_MA9 AE21 P10 VTT_NCTF3 MCH_RSVD17 K24
AG19 SB_CAS# SB_MA10 AL20 N10 VTT_NCTF4 MCH_RSVD18 K22
AG21 SB_RAS# SB_MA11 AE22 L10 VTT_NCTF5 MCH_RSVD19 J17
AG20 SB_WE# SB_MA12 AE26 D1 VTT_NCTF6 MCH_RSVD20 K23
SB_MA13 AE20 MCH_RSVD21 K17
M10
A18
MCH_RSVD3 MCH_RSVD22 K12
K13
LOW=Normal
MCH_RSVD4 MCH_RSVD23
AB10 MCH_RSVD5 MCH_RSVD24 K16 High=LANES
945GMS AA10 K15
MCH_RSVD6 MCH_RSVD25 REVERSED(945GMS no
945GMS support.

A A
TOPSTAR TECHNOLOGY
Swain Xu
Page Name
Calisoga(DDRII&NCTF)
Size Project Name Rev
A3 N01
A
Date: Wednesday, July 16, 2008 Sheet 11 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1

+V3.3S 6,7,10,11,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,35,36,37,39

+V1.05S 6,7,8,9,11,17,20,28,35,36,37
+V1.05S
3A
+V1.5S 8,10,11,20,23,24,35,36,37
+V1.5S
U23D +V1.5S_PCIE 10
C72 C520 C73 C522
10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R T26 B20
120mA
VCC0 VCCA_TVDACA0 +V2.5S 37,38
C0805 C0805 C0805 C0805 R26 A20
VCC1 VCCA_TVDACA1
P26 VCC2 VCCA_TVDACB0 B22 +V1.8 10,14,34,36,37
N26 VCC3 VCCA_TVDACB1 A22
D M26 VCC4 VCCA_TVDACC0 D22 D
V19 VCC5 VCCA_TVDACC1 C22
U19 VCC6 VCCA_TVBG D23
C77 C78 C74 T19 E23
10uF/6.3V,X5R 4.7uF/10V,X5R 1uF/10V,X7R VCC7 VSSA_TVBG +V1.5S
W18 VCC8 VCCD_TVDAC F20
C0805 C0805 C0603 FB8
V18
T18
VCC9 VCCDQ_TVDAC F22
C28
20mA +V1.5S 100ohm@100MHz,3A +V1.5S_DPLLA
VCC10 VCCD_LVDS0 C79 FB0805
R18
W17
VCC11 VCCD_LVDS1 B28
A28 0.1uF/10V,X5R C80 1 2
50mA
VCC12 VCCD_LVDS2 C0402 10uF/6.3V,X5R
U17 VCC13 VCCHV0 E26
R17 D26 C0805 C84 C86
C81 C82 C75 VCC14 VCCHV1 10uF/6.3V,X5R 0.1uF/10V,X5R
W16 VCC15 VCCHV2 C26
0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R C0805 C0402
C0402 C0402 C0402
V16
T16
VCC16 VCCSM0 AB33
AM32
40mA
VCC17 VCCSM1 +V3.3S
R16 VCC18 VCCSM2 AN29
V15 VCC19 VCCSM3 AM29
U15 AL29 FB10
VCC20 VCCSM4 C76 100ohm@100MHz,3A +V1.5S_DPLLB
T15 VCC21 VCCSM5 AK29
0.1uF/10V,X5R C83 FB0805
AD33
VCCSM6 AJ29
AH29 C529 C530 C0402 10uF/6.3V,X5R 1 2
50mA
VCC_AUX1 VCCSM7 1uF/10V,X7R 1uF/10V,X7R C0805
AD32 VCC_AUX2 VCCSM8 AG29
AD31 AF29 C0603 C0603 C88 C89
VCC_AUX3 VCCSM9 10uF/6.3V,X5R 0.1uF/10V,X5R
AD30 VCC_AUX4 VCCSM10 AE29
AD29 AN24 C0805 C0402
VCC_AUX5 VCCSM11
AD28 VCC_AUX6 VCCSM12 AM24
AD27 VCC_AUX7 VCCSM13 AL24
AC27 AK24 C521 +V1.5S_MPLL
VCC_AUX8 VCCSM14 10uF/6.3V,X5R
+V1.5S
AD26
AC26
VCC_AUX9 VCCSM15 AJ24
AH24 C0805 1 2
45mA
C VCC_AUX10 VCCSM16 C
TBD AB26
AE19
VCC_AUX11 VCCSM17 AG24
AF24 C87 FB3 C95 C96
VCC_AUX12 VCCSM18 1uF/10V,X7R 100ohm@100MHz,3A 10uF/6.3V,X5R 0.1uF/10V,X5R
AE18 VCC_AUX13 VCCSM19 AE24
AF17 AN18 C0603 FB0805 C0805 C0402
C85 VCC_AUX14 VCCSM20
AE17 VCC_AUX15 VCCSM21 AN16
0.1uF/10V,X5R AF16 AM16 +V1.8 +V1.5S_HPLL
C0402 VCC_AUX16 VCCSM22
AE16
AF15
VCC_AUX17 VCCSM23 AL16
AK16 1 2
45mA
VCC_AUX18 VCCSM24
AE15 VCC_AUX19 VCCSM25 AJ16
J14 AN13 FB4 C99 C100 C101
VCC_AUX20 VCCSM26 C90 C91 C92 C93 100ohm@100MHz,3A 10uF/6.3V,X5R 10uF/6.3V,X5R 0.1uF/10V,X5R
J10 VCC_AUX21 VCCSM27 AM13
H10 AL13 1uF/10V,X7R 4.7uF/10V,Y5V 4.7uF/10V,Y5V 10uF/6.3V,X5R FB0805 C0805 C0805 C0402
VCC_AUX22 VCCSM28 C0603 C0805 C0805 C0805
AE9 VCC_AUX23 VCCSM29 AK13
AD9 VCC_AUX24 VCCSM30 AJ13
U9 VCC_AUX25 VCCSM31 AH13
AD8 VCC_AUX26 VCCSM32 AG13
C97 AD7 AF13 C98 FB5
0.47uF/25V,Y5V VCC_AUX27 VCCSM33 1uF/10V,X7R +V1.5S 100ohm@100MHz,3A +V1.5S_PCIE
AD6 VCC_AUX28 VCCSM34 AE13
C0603 C0603 FB0805
A14
VCCSM35 AN4
AM10 1 2
400mA
+V1.05S VTT0 VCCSM36 C102
D10 VTT1 VCCSM37 AL10
1uF/10V,X7R C156 C105 C106
780mA P9
L9
VTT2 VCCSM38 AK10
AH1 C0603 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R
VTT3 VCCSM39 C0805 C0805 C0805
D9 VTT4 VCCSM40 AH10
C477 C478 P8 AG10
4.7uF/10V,X5R 4.7uF/10V,X5R VTT5 VCCSM41
L8 VTT6 VCCSM42 AF10
C0805 C0805 D8 AE10
VTT7 VCCSM43 +V1.5S_3GPLL
P7 VTT8 VCCSM44 AN7
+V1.5S_MPLL
B
L7
D7
VTT9 VCCSM45 AM7
AL7 1 2
400mA B
VTT10 VCCSM46 +V1.5S_HPLL
A7 VTT11 VCCSM47 AK7
P6 AJ7 +V1.5S_DPLLA FB6
VTT12 VCCSM48 100ohm@100MHz,3A
L6 VTT13 VCCSM49 AH7
POWER

C276 G6 AN10 +V1.5S_DPLLB FB0805


10uF/6.3V,X5R C103 VTT14 VCCSM50 +V2.5S
C0805 0.47uF/25V,Y5V
D6 VTT15 VCCSM51 AJ10 45mA
C0603
U5 VTT16 VCCA_MPLL AD1 45mA +V1.5S +V2.5S D1
P5 VTT17 VCCA_HPLL AD2 50mA 1N4148WS +V1.05S
L5
G5
VTT18 VCCA_DPLLA B26
J32
50mA C107 C108 SOD323
VTT19 VCCA_DPLLB 0.1uF/10V,X5R 4.7uF/10V,Y5V R144 10 R0402
D5
Y4
VTT20 VCCD_HMPLL1 AE5
AD5
150mA C0402 C0805
1
VTT21 VCCD_HMPLL2 +V1.5S_3GPLL +V2.5S_CRTDAC
U4 VTT22 VCCTX_LVDS0 D29 60mA
P4 VTT23 VCCTX_LVDS1 C29 70mA
L4 VTT24 VCC3G0 U33 400mA 1 2
G4
D4
VTT25 VCC3G1 T33
V26
+V1.5S_PCIE 400mA C109 C110 FB7 C111
VTT26 VCCA_3GPLL 0.1uF/10V,X5R 10uF/6.3V,X5R 100ohm@100MHz,3A 10uF/6.3V,X5R
Y3 VTT27 VCCA_3GBG N33
U3 M33 C0402 C0805 FB0805 C0805
VTT28 VSSA_3GBG
P3 VTT29 VCC_SYNC J23
L3 C24 +V2.5S
VTT30 VCCA_CRTDAC0
G3
D3
VTT31 VCCA_CRTDAC1 B24
B25
10mA
VTT32 VSSA_CRTDAC
Y2 VTT33 VCCA_LVDS B31
U2 B32 +V2.5S +V2.5S_CRTDAC +V2.5S C118
VTT34 VSSALVDS 0.1uF/10V,X5R
P2
L2
VTT36
P1
10mA 70mA 70mA C0402
VTT35 VTT41
G2 VTT37 VTT42 L1
A D2 G1 C112 C113 C114 C115 C116 C117 A
VTT38 VTT43 0.01uF/25V,X7R
0.1uF/10V,X5R 0.022uF/16V,X7R0.1uF/10V,X5R0.1uF/10V,X5R10uF/6.3V,X5R
AA1 VTT39 VTT44 U1 TOPSTAR TECHNOLOGY
F1 Y1 C0402 C0402 C0402 C0402 C0402 C0805
VTT40 VTT45 Swain Xu
Page Name Calistoga(POWER)
C119 C120 945GMS +V1.05S
0.47uF/25V,Y5V 0.47uF/25V,Y5V Size Project Name Rev
C0603 C0603 A3 N01
A
Date: Wednesday, July 16, 2008 Sheet 12 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
A
B
C
D

5
5

VSS110 U16
VSS109 AH16
VSS108 B17
VSS107 F17
VSS106 T17
VSS105 V17
VSS104 AK17
VSS103 D18
VSS102 H18
VSS101 U18
VSS100 AF18
VSS99 AH18
NC60 AM1 VSS98 AM18
NC59 AE4 VSS97 R19
NC58 AG4 VSS96 W19
NC57 AH4 VSS95 D20
NC56 AJ4 VSS94 AF20
AB17 MCH_RSVD42 NC55 W31 VSS93 AH20
AB12 MCH_RSVD41 NC54 AK4 VSS92 AK20
AB13 MCH_RSVD40 NC53 AL4 VSS91 AM20
AB15 MCH_RSVD39 NC52 AD4 VSS90 F21
AB18 MCH_RSVD38 NC51 AF4 VSS89 H21
AB20 MCH_RSVD37 NC50 AM4 VSS88 J21
AB24 MCH_RSVD36 NC49 Y7 VSS87 E22
AA24 MCH_RSVD35 NC48 A16 VSS86 G22
W24 MCH_RSVD34 NC47 AN2 VSS85 AF22
AA12 MCH_RSVD33 NC46 B16 VSS84 AJ22
AB14 MCH_RSVD32 NC45 C16 VSS83 AM22
AB16 MCH_RSVD31 NC44 D16 VSS82 B23
AB19 MCH_RSVD30 NC43 E16 VSS81 F23
AB21 MCH_RSVD29 NC42 F16 VSS80 H23
AB22 G16 A25

4
4

MCH_RSVD28 NC41 VSS79


Y24 MCH_RSVD27 NC40 Y8 VSS78 G25
Y25 MCH_RSVD26 NC39 A19 VSS77 J25
NC38 B19 R1 VSS185 VSS76 AE25
NC37 C19 V1 VSS184 VSS75 AG25
NC36 D19 F2 VSS183 VSS74 AK25
NC35 E19 H2 VSS182 VSS73 AN25
NC34 F19 K2 VSS181 VSS72 U26
NC33 G19 M2 VSS180 VSS71 W26
NC32 H19 AB2 VSS179 VSS70 AH26
NC31 J19 AF2 VSS178 VSS69 AL26
NC30 Y9 AH2 VSS177 VSS68 B27
AN3 AK2 C27

NC
NC29 VSS176 VSS67
NC28 AH19 B3 VSS175 VSS66 E27
NC27 AJ19 T3 VSS174 VSS65 G27
NC26 AK19 W3 VSS173 VSS64 M27
NC25 AL19 AD3 VSS172 VSS63 N27
NC24 AM19 AL3 VSS171 VSS62 P27
NC23 AN19 E4 VSS170 VSS61 R27
NC22 C23 H4 VSS169 VSS60 T27
NC21 E21 K4 VSS168 VSS59 U27
NC20 A31 N4 VSS167 VSS58 Y27
NC19 K33 R4 VSS166 VSS57 AA27
NC18 D24 V4 VSS165 VSS56 AB27
NC17 E24 AA4 VSS164 VSS55 AF27
NC16 F24 B5 VSS163 VSS54 AM27
NC15 G24 AJ5 VSS162 VSS53 D28
NC14 W32 AN5 VSS161 VSS52 J28
NC13 H24 K6 VSS160 VSS51 T28
VSS

K18 NC72 NC12 J24 M6 VSS159 VSS50 U28


U10 NC71 NC11 W29 T6 VSS158 VSS49 AA28
V10 NC70 NC10 V27 W6 VSS157 VSS48 AE28
U24 NC69 NC9 W28 AB6 VSS156 VSS47 AH28

3
3

V24 NC68 NC8 AN31 AE6 VSS155 VSS46 AK28


W25 NC67 NC7 A32 AG6 VSS154 VSS45 B29
W10 NC66 NC6 AN32 AL6 VSS153 VSS44 E29
Y10 NC65 NC5 B33 B7 VSS152 VSS43 H29
Y5 NC64 NC4 C33 E7 VSS151 VSS42 M29
AL1 NC63 NC3 AL33 H7 VSS150 VSS41 N29
Y6 NC62 NC2 AM33 N7 VSS149 VSS40 P29
W30 NC61 NC1 W33 R7 VSS148 VSS39 R29
V7 VSS147 VSS38 U29
AA7 VSS146 VSS37 AA29
U8 VSS145 VSS36 B30
AE8 VSS144 VSS35 E30
U23G

AG8 VSS143 VSS34 G30


945GMS

AL8 VSS142 VSS33 U30


A9 VSS141 VSS32 V30
C9 VSS140 VSS31 Y30
F9 VSS139 VSS30 AA30
J9 VSS138 VSS29 AC30
M9 VSS137 VSS28 AE30
R9 VSS136 VSS27 AG30
W9 VSS135 VSS26 AL30
AB9 VSS134 VSS25 F31
AJ9 VSS133 VSS24 J31
AM9 VSS132 VSS23 M31
AE11 VSS131 VSS22 N31
AJ11 VSS130 VSS21 P31
AN11 VSS129 VSS20 R31
B12 VSS128 VSS19 T31
H12 VSS127 VSS18 U31
AG12 VSS126 VSS17 AA31
AL12 VSS125 VSS16 AJ31
D13 VSS124 VSS15 AM31
F13 VSS123 VSS14 C32
2
2

B14 VSS122 VSS13 E32


H14 VSS121 VSS12 H32
AE14 VSS120 VSS11 U32
AH14 VSS119 VSS10 AA32
AM14 VSS118 VSS9 AC32
D15 VSS117 VSS8 AE32
F15 VSS116 VSS7 AG32
R15 VSS115 VSS6 AK32
W15 VSS114 VSS5 G33
AG15 VSS113 VSS4 R33
AL15 VSS112 VSS3 V33
J16 VSS111 VSS2 Y33
VSS1 AH33
A3
Size

Date:
U23E
945GMS

Page Name

Project Name

Wednesday, July 16, 2008


N01

the expressed written consent of TOPSTAR


Swain Xu

1
1

Calistoga (VSS NC)

Sheet 13
TOPSTAR TECHNOLOGY

of 42

to others or used for any purpose other than that for which it was obtained without
PROPERTY NOTE: this document contains information confidential and property to
A
Rev

TOPSTAR and shall not be reproduced or transferred to other documents or disclosed


A
B
C
D
5 4 3 2 1

+V0.9S 34,37

+V1.8 10,12,34,36,37
DIM1
+V1.8 DDR2_SODIMM200
DDR200STD_5D2 SO-DIMM 0 +V3.3S 6,7,10,11,12,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,35,36,37,39

+V1.8

112
111
117

118

103

104

187
178
190

155

132
144
156
168

149
161

138
150
162
96
95

81
82
87

88

21
33

34

15
27
39

28
40
9

2
3
11 MA_A_A[13:0]
C527 C121 C528

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12

VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
MA_DATA[63:0] 11
D 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R C122 C123 C124 D
MA_A_A0 102 5 MA_DATA0 C0805 C0805 C0805 0.1uF/10V,X5R 2.2uF/10V,X7R 2.2uF/10V,X7R
MA_A_A1 A0 D0 MA_DATA1 C0805 C0805
101 A1 D1 7 C0402
MA_A_A2 100 17 MA_DATA2
MA_A_A3 A2 D2 MA_DATA3
99 A3 D3 19
MA_A_A4
MA_A_A5
98
97
A4
A5
D4
D5
4
6
MA_DATA4
MA_DATA5 +V1.8 Layout note:电容靠近DDR slot VDD PIN
MA_A_A6 94 14 MA_DATA6
MA_A_A7 A6 D6 MA_DATA7
92 A7 D7 16
MA_A_A8 93 23 MA_DATA8
MA_A_A9 A8 D8 MA_DATA9 C125 C126 C127 C128 C129
91 A9 D9 25
MA_A_A10 105 35 MA_DATA10 0.1uF/10V,X5R 2.2uF/10V,X7R 0.1uF/10V,X5R 2.2uF/10V,X7R 0.1uF/10V,X5R
MA_A_A11 A10/AP D10 MA_DATA11 C0402 C0805 C0402 C0805 C0402
90 A11 D11 37
MA_A_A12 89 20 MA_DATA12
MA_A_A13 A12 D12 MA_DATA13
116 A13 D13 22
86 36 MA_DATA14
A14 D14 MA_DATA15 +V1.8
84 A15 D15 38
85 43 MA_DATA16
11 MA_A_BS#2 A16_BA2 D16
45 MA_DATA17
D17 MA_DATA18
11 MA_A_BS#0 107 BA0 D18 55
106 57 MA_DATA19 C130 C131 C132 C133 C134
11 MA_A_BS#1 BA1 D19
44 MA_DATA20 2.2uF/10V,X7R 0.1uF/10V,X5R 2.2uF/10V,X7R 0.1uF/10V,X5R 2.2uF/10V,X7R
D20 MA_DATA21 C0805 C0402 C0805 C0402 C0805
10 M_CS#0 110 CS0 D21 46
115 56 MA_DATA22
10 M_CS#1 CS1 D22 MA_DATA23
D23 58
MA_DM0 10 61 MA_DATA24
MA_DM1 DQM0 D24 MA_DATA25
26 DQM1 D25 63
MA_DM2 52 73 MA_DATA26
MA_DM3 DQM2 D26 MA_DATA27
67 DQM3 D27 75
C MA_DM4 130 62 MA_DATA28 C
MA_DM5 DQM4 D28 MA_DATA29
147 DQM5 D29 64
MA_DM6 170 74 MA_DATA30 +V0.9S
11 MA_DM[7:0] MA_DM7 DQM6 D30 MA_DATA31 RN1 56x4 RA0402_8
185 DQM7 D31 76

DDRII
123 MA_DATA32 1 2
D32 MA_DATA33 MA_A_A6
11 MA_A_WE# 109 WE D33 125 3 4
113 135 MA_DATA34 5 6 MA_A_A11
11 MA_A_CAS# CAS D34
108 137 MA_DATA35 7 8 MA_A_A7
11 MA_A_RAS# RAS D35
124 MA_DATA36
D36 MA_DATA37 RN2 56x4 RA0402_8
10 M_CKE0 79 CKE0 D37 126
80 134 MA_DATA38 1 2 MA_A_A12
10 M_CKE1 CKE1 D38 MA_DATA39
D39 136 3 4 MA_A_BS#2 11
30 141 MA_DATA40 5 6 MA_A_A9
10 M_CLK_DDR0 CK0 D40 MA_DATA41 MA_A_A8
10 M_CLK_DDR#0 32 CK0 D41 143 7 8
164 151 MA_DATA42
10 M_CLK_DDR1 CK1 D42 MA_DATA43 RN3 56x4 RA0402_8
10 M_CLK_DDR#1 166 CK1 D43 153
140 MA_DATA44 1 2
D44 MA_A_WE# 11
114 142 MA_DATA45 3 4
10 M_ODT0 ODT0 D45 MA_A_BS#1 11
119 152 MA_DATA46 5 6 MA_A_A13
10 M_ODT1 ODT1 D46
154 MA_DATA47 7 8
D47 MA_A_CAS# 11
MA_DQS0 13 157 MA_DATA48
MA_DQS1 DQS0 D48 MA_DATA49 RN4 56x4 RA0402_8
31 DQS1 D49 159
MA_DQS2 51 173 MA_DATA50 1 2 MA_A_A3
MA_DQS3 DQS2 D50 MA_DATA51 MA_A_A1
70 DQS3 D51 175 3 4
MA_DQS4 131 158 MA_DATA52 5 6 MA_A_A10
MA_DQS5 DQS4 D52 MA_DATA53 MA_A_A5
148 DQS5 D53 160 7 8
MA_DQS6 169 174 MA_DATA54
11 MA_DQS[7:0] MA_DQS7 DQS6 D54 MA_DATA55 RN5 56x4 RA0402_8
188 DQS7 D55 176
179 MA_DATA56 1 2
B D56 MA_A_RAS# 11 B
181 MA_DATA57 3 4 MA_A_A0
D57 MA_DATA58 MA_A_A2
6,19,23,24 SMB_DATA_S 195 SDA D58 189 5 6
197 191 MA_DATA59 7 8 MA_A_A4
6,19,23,24 SMB_CLK_S SCL D59 MA_DATA60
D60 180
R145 10K R0402 198 182 MA_DATA61
R146 10K R0402 SA0 D61 MA_DATA62 R149 56 R0402
+V3.3S
200 SA1 1010 000x D62 192
MA_DATA63 R148 56 R0402
M_CS#1 10
D63 194 M_ODT1 10
R152 56 R0402
M_CKE0 10
199 11 MA_DQS#0 R154 56 R0402
VDDSPD DQS#0 M_CKE1 10
29 MA_DQS#1 R155 56 R0402
DQS#1 MA_A_BS#0 11
1 49 MA_DQS#2 R157 56 R0402
10,34 SM_VREF_L VREF1 DQS#2 M_ODT0 10
C136 68 MA_DQS#3 R159 56 R0402
DQS#3 M_CS#0 10
C137 129 MA_DQS#4
0.1uF/25V,Y5V 2.2UF/10V,X7R C135 C138 DQS#4 MA_DQS#5
83 NC1 DQS#5 146
C0402 C0805 2.2UF/10V,X7R 120 167 MA_DQS#6
0.1uF/25V,Y5V NC2 DQS#6 MA_DQS#7
50 NC3 DQS#7 186
C0402 C0805 69
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33

NC4 MA_DQS#[7:0] 11
GND0
GND1
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

163 NCTEST
close to DDR pin
47
133
183
77
12
48
184
78
71
72
121
122
196
193
8
18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177

201
202

10 PM_EXTTS#0

A
+V0.9S 每4个电阻两个0.1UF电容 TOPSTAR TECHNOLOGY
A

Swain Xu
Page Name DDRII SODIMM0
C139 C140 C141 C142 C143 C144 C145 C146 C147 C148 C149 C150 C151
Size Project Name Rev
0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R
A3 N01
C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 A
Date: Wednesday, July 16, 2008 Sheet 14 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1

+V3.3AL 17,18,19,20,23,24,25,27,29,30,31,32,33,34,35,36,37,39
+V3.3S 6,7,10,11,12,14,16,17,18,19,20,21,23,24,25,26,27,28,29,30,35,36,37,39
+V5AL 20,22,25,33,34,36,37
+VDC 23,25,31,33,34,35,37,39
+V5S 16,19,20,21,25,26,27,29,35,37,38,39

High : Enable R160 +V3.3S


Low : Disable 100K
R0402
D2 R161 LCDVDD
D
2 1 1N4148WS 1K 500mA D
10,29 LVDS_BKLTEN
SOD323 R0402 CLOSE TO INTCON
D3
25,29 LIDR# 2 1 1N4148WS BKLT_ON LCDCON
SOD323 88242-4001
D4 CNS40_LCD_R1
29 HW_OFF_BKLT# 2 1 1N4148WS C152
41 41
SOD323 1000pF/50V,X7R LCDVDD 1 2
D5 C0402 1 2
3 3 4 4
19,29 PM_SUS_STAT# 2 1 1N4148WS 10 MCH_LVDS_YAN1 5 5 6 6 MCH_LVDS_YAN0 10
SOD323 7 8
10 MCH_LVDS_YAP1 7 8 MCH_LVDS_YAP0 10
ns 9 10
9 10
10 MCH_LVDS_CLKAP 11 11 12 12 MCH_LVDS_YAN2 10
10 MCH_LVDS_CLKAN 13 13 14 14 MCH_LVDS_YAP2 10
15 15 16 16
EDID_PWR 17 18
17 18 L_DDC_CLK 10
+V5AL_CAM 19 19 20 20 L_DDC_DATA 10
BKLT_PWM 21 22
BKLT_ON 21 22
23 23 24 24 USB_CAM_PN5 18
29 IVT_I_ADJ 25 25 26 26 USB_CAM_PP5 18
27 27 28 28
Q2 +VDC FB34 0 R0805 INVT_VDD 29 30 R714 0 R0805
+V5S
+V3.3AL +V3.3S AO6409 29 30
31 31 32 32
TSOP6_0D95_1D6 33 34
C275 33 34
35 35 36 36
0.1UF/25V,Y5V 37 38
37 38
4
5
6

LCDVDD C0402 39 40
39 40
S

C R162 500mA 42 42
C
100K C153
D

R0402 0.047uF/16V,X7R
G

C0402 C154 C155 R163


3
2
1

R164 0.1uF/10V,X5R 10UF/6.3V,X5R 2.2K R727 +VDC


100K C0402 C0805 R0402 100
R0402 ns R0603

ns
SPWG Require LCDVDD rising time
3

PQ75 PQ76 R728

3
2N7002 2N7002 100K
is 0.5-10ms,1-10ms is better SOT23 ns SOT23 ns
1 Q3
10 LVDS_VDDEN
2N7002E-T1 LVDS_VDDEN 1

100pF/50V,NPO
1
SOT23
2

R165 ns C515 R729

2
100K 100K
R0402 ns ns +V5AL

R712 0 R0805
+V5AL_CAM

2 3
500mA
R204
10K Q15 C313 C296
R0402 SOT23 0.1uF/10V,X5R 10UF/6.3V,X5R
ns AO3415 C0402 C0805

1
B ns B
R730 10K
R0402
29 EC_BKLT_PWM R696 0 R0402 ns ns

3
R697 0 R0402 BKLT_PWM
10 LVDS_BKLTCTL

R168 C158 1
10K 100pF/50V,NPO 29 CAM_PWRON
R0402 C0402 Q16

2
R213 2N7002E-T1
100K SOT23
R0402 ns
ns

+V3.3AL R699 0 R0402 ns

+V3.3S R700 0 R0402 EDID_PWR

C182
100pF/50V,NPO
C0402

A A
TOPSTAR TECHNOLOGY
Swain Xu
Page Name
LVDS
Size Project Name Rev
A3 N01
A
Date: Wednesday, July 16, 2008 Sheet 15 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1

+V5S 15,19,20,21,25,26,27,29,35,37,38,39
+V3.3S 6,7,10,11,12,14,15,17,18,19,20,21,23,24,25,26,27,28,29,30,35,36,37,39

Cross moat Cross moat place


D D
place
+V5S FB11 +V5_VGA
75ohm@100MHz,500mA
D6 FB0603
1 2 1 2
FB12 GND_VGA
47ohm@100MHz,500mA 1N5819HW-F
10 CRT_RED 1FB0603 2 ROUT SOD123 C163 R182
0.1uF/10V,X5R 100K
VGA

3
C0402 R0402

17
R172 C164 C162 D7
150,1% BAT54S
R0402 5.6pF/50V NPO 5.6pF/50V NPO SOT23 GND_VGA GND_VGA 6 GND
CONNECTOR TOP VIEW
C0402 C0402 ROUT 1 R NC
11
7 GND

2
GOUT SDA 5VDDCDA
2 G 12
FB13 GND_VGA 8 GND
47ohm@100MHz,500mA GND_VGA+V5_VGA BOUT 3 B HSYNC 13 HSYNC
10 CRT_GREEN 1FB0603 2 GOUT 9 NC
4 NC VSYNC 14 VSYNC

3
10 GND
R173 GND CLK 5VDDCCK
C165 C166 5 15
150,1% D8 shell
R0402 5.6pF/50V NPO 5.6pF/50V NPO BAT54S shell
C0402 C0402 SOT23 D-Sub
VGADMA

16
C167 C168 C169 C170

2
15PF/50V,NPO 15PF/50V,NPO 15PF/50V,NPO 15PF/50V,NPO
GND_VGA C0402 C0402 C0402 C0402
C GND_VGA+V5_VGA ns ns C

10 CRT_BLUE 1 2 FB14 FB0603 BOUT


47ohm@100MHz,500mA

3
GND_VGA
R174 C171 C172 +V3.3S GND_VGA
150,1% D9
R0402 5.6pF/50V NPO 5.6pF/50V NPO BAT54S
C0402 C0402 SOT23 C173
0.1uF/10V,X5R
1

2
C0402
GND_VGA
150ohm电阻前 +V5_VGA
走线阻抗50ohm GND_VGA
GND_VGA
+V3.3S +V5_VGA

+V5_VGA
R175 R176
2.2K Q5 2.2K
R0402 BSS138 R0402

C174 C175 2 3 5VDDCCK


10 CRT_DDC_CLK
0.1uF/10V,X5R 0.1uF/10V,X5R

3
C0402 C0402
U6
1 5 +V3.3S D26

1
OE# VCC +V3.3S +V5_VGA BAT54S
B SOT23 B
10 CRT_HSYNC 2 A GND_VGA

2
3 GND Y 4
R179 R177
74AHCT1G125 Near U11/U12 ASAP 2.2K Q6 2.2K +V5_VGA
SOT23_5 R0402 BSS138 R0402 GND_VGA
U7 R178 39 R0402 HSYNC 5VDDCDA
10 CRT_DDC_DATA 2 3
1 OE# VCC 5

3
R180 39 R0402 VSYNC
10 CRT_VSYNC 2 A +V3.3S D27

1
3 4 BAT54S
GND Y SOT23
74AHCT1G125

2
SOT23_5

GND_VGA +V5_VGA
GND_VGA

R731
+V5_VGA 0
+V5_VGA R0805
D10 R732
D11 0
2
C176 2 R0805
HSYNC 3 0.1uF/10V,X5R
A
C0402 VSYNC 3 C177 A
1 0.1uF/10V,X5R TOPSTAR TECHNOLOGY
1 C0402
GND_VGA Swain Xu
BAT54S Page Name CRT CONN & S TV OUT & LIDR SWITCH
SOT23 GND_VGA BAT54S
SOT23 GND_VGA Size Project Name Rev
A3 N01
A
Date: Wednesday, July 16, 2008 Sheet 16 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1

+V3.3A_RTC 332K 1% PULL HIGH


+V3.3AL TO VBAT_RTC FOR
ICH7 INTRNAL VR +V1.05S 6,7,8,9,11,12,20,28,35,36,37
ENABLE(PULL LOW
DISABLE) +V3.3A_RTC 20
1 +V3.3A_RTC R198
C179 332K,1%
15pF/50V,NPO R0402 +V3.3AL 15,18,19,20,23,24,25,27,29,30,31,32,33,34,35,36,37,39
3
C0402 +V3.3S 6,7,10,11,12,14,15,16,18,19,20,21,23,24,25,26,27,28,29,30,35,36,37,39
2 D12 C178 ICH_INTVRMEN
D BAT54C 1uF/10V,X7R D
SOT23 C0603 Y2
CMOS Settings J1 2 1 R190
Clear CMOS Shunt 3 4 R184 0
R186 Keep CMOS Open 10M R0402
RTCBAT1 R183 20K 32.768KHz R0402 ns
CONN2_R 1K R0402 XS4_8038 +V3.3S
CNS2_R R0402

1
ns
3

C180 J1
R185 1uF/10V,X7R JOPEN C181 U24A R187 R196
1
3

1 1M C0603 RESISTOR_1 15pF/50V,NPO 10K 10K


2 2 AB1 RTCX1 LAD0 AA6 LPC_AD0 23,29
4

R0402 ns C0402 AB2 AB5 R0402 R0402


LPC_AD1 23,29

2
RTCX2 LAD1
AC4 LPC_AD2 23,29
4

RTC_RST# LAD2
AA3 RTCRST# LAD3 Y6 LPC_AD3 23,29

LPC
RTC
SM_INTRUDER# Y5 AC3
ICH_INTVRMEN INTRUDER# LDRQ0#
W4 INTVRMEN LDRQ1#/GPIO23 AA5

W1 EE_CS LFRAME# AB3 LPC_FRAME# 23,29 +V1.05S


Y1 EE_SHCLK
Y2 AE22 R200 R188
EE_DOUT A20GATE H_A20GATE 29
W3 AH28 56 56
EE_DIN A20M# H_A20M# 7
R0402 R0402
V3 AG27 R199 0 R0402 ns ns ns
LAN_CLK CPUSLP# H_CPUSLP# 7,9
R189 0 R0402
SPONGE_RTC1
U3 LAN_RSTSYNC TP1/DPRSTP# AF24
AH25 R191 0 R0402
Place near H_DPRSTP# 7
TP2/DPSLP# H_DPSLP# 7
RTCBAT GLUE U5 to ICH7-M

LAN
CPU
C ns LAN_RXD0 C
V4 LAN_RXD1 FERR# AG26 H_FERR# 7
T5 LAN_RXD2
AG24 +V3.3S
+ U7
GPIO49/CPUPWRGD H_PWRGD 7
R201
LAN_TXD0
- V6 LAN_TXD1
56
RTC_BAT1 V7 AG22 R0402
LAN_TXD2 IGNNE# H_IGNNE# 7
RTCBAT with Cable AG21 R192
ns R193 39 R0402 INIT3_3V# 10K
26 HDA_BITCLK U1 ACZ_BIT_CLK INIT# AF22 H_INIT# 7
R203 39 R0402 R6 AF25 R0402
26 HDA_SYNC ACZ_SYNC INTR H_INTR 7
根据机构 +V1.05S

AC-97/AZALIA
+V3.3S R195 39 R0402 R5 AG23
26 HDA_RST# H_RCIN# 29
定Cable尺寸 ACZ_RST# RCIN#

26 HDA_SDATA_IN0 T2 ACZ_SDIN0 NMI AH24 H_NMI 7


T3 ACZ_SDIN1 SMI# AF23 H_SMI# 7
R197 T1
10K ACZ_SDIN2
STPCLK# AH22 H_STPCLK# 7
R0402 R206 39 R0402 T4
26 HDA_SDOUT ACZ_SDOUT R210 24.9,1% R0402
THERMTRIP# AF26 PM_THRMTRIP# 7,10,28
27 HDD_LED# AF18 SATALED#
AF3 AB15 R209
21 SATA_RXN0 SATA0RXN DD0
AE3 AE14 56
21 SATA_RXP0 SATA0RXP DD1
C505 3300pF/50V,X7R C0402AG2 AG13 R0402
21 SATA_TXN0 SATA0TXN DD2
C506 3300pF/50V,X7R C0402AH2 AF13
21 SATA_TXP0 SATA0TXP DD3
DD4 AD14
AF7 SATA2RXN DD5 AC13
AE7 AD12 +V1.05S
SATA2RXP DD6 R209 NEEDS BE PLACE WITHIN
AG6 SATA2TXN DD7 AC12
AH6 AE12 2" OF ICH7, R210NEEDS BE
B SATA2TXP DD8 PLACED WITHIN 2" OF R230 B
DD9 AF12
AF1 AB13 WITHOUT STUB
6 CLK_ICH_SATA# SATA_CLKN DD10
6 CLK_ICH_SATA AE1 SATA_CLKP DD11 AC14
AF14

SATA
R211 24.9,1% R0402 DD12
AH10 SATARBIASN DD13 AH13
within 500 mils AG10 AH14
of the ICH7-M SATARBIASP DD14
DD15 AC15

+V3.3S
AF15
AH15
DIOR# IDE DA0 AH17
AE17
DIOW# DA1
AF16 DDACK# DA2 AF17
R194 10K R0402 AH16
R205 10K R0402 IDEIRQ
AG16 IORDY DCS1# AE16
AE15 DDREQ DCS3# AD16
ICH7M

A A
TOPSTAR TECHNOLOGY
Swain Xu
Page Name ICH7_M(1 of 4)
Size Project Name Rev
A3 N01
A
Date: Wednesday, July 16, 2008 Sheet 17 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1

+V1.5S_PCIE_ICH 20

+V3.3S 6,7,10,11,12,14,15,16,17,19,20,21,23,24,25,26,27,28,29,30,35,36,37,39

+V3.3AL 15,17,19,20,23,24,25,27,29,30,31,32,33,34,35,36,37,39

D D

RN22
10K +V3.3S
RA0402_8
U24B PCI_STOP# 1 2
E18 D7 PCI_REQ#0 PCI_REQ#1 3 4 U24D
AD0 REQ0# PCI_REQ#2
C18
A16
AD1 PCI GNT0# E7
C16 PCI_REQ#1 PCI_FRAME#
5
7
6
8
30 PCIE_RXN0_LAN F26
F25
PERn1 DMI0RXN V26
V25
DMI_RXN0 10
AD2 REQ1# 30 PCIE_RXP0_LAN PERp1 DMI0RXP DMI_RXP0 10
C184 0.1UF/10V,X7R C0402 E28

Direct Media Interface


F18 AD3 GNT1# D16 30 PCIE_TXN0_LAN PETn1 DMI0TXN U28 DMI_TXN0 10
E16 C17 PCI_REQ#2 C185 0.1UF/10V,X7R C0402 E27 U27
AD4 REQ2# 30 PCIE_TXP0_LAN PETp1 DMI0TXP DMI_TXP0 10
A18 D17 RN21
AD5 GNT2# PCI_REQ#3 10K +V3.3S
E17 AD6 REQ3# E13 23 PCIE_RXN1_SLOT H26 PERn2 DMI1RXN Y26 DMI_RXN1 10
A17 F13 PCI_GNT#3 RA0402_8 H25 Y25
AD7 GNT3# 23 PCIE_RXP1_SLOT PERp2 DMI1RXP DMI_RXP1 10
A15 A13 PCI_REQ#4 PCI_DEVSEL# 1 2 C186 0.1UF/10V,X7R C0402G28 W28
AD8 REQ4#/GPIO22 23 PCIE_TXN1_SLOT PETn2 DMI1TXN DMI_TXN1 10
C14 A14 PCI_GNT#4 PCI_REQ#4 3 4 C187 0.1UF/10V,X7R C0402G27 W27
AD9 GNT4#/GPIO48 23 PCIE_TXP1_SLOT PETp2 DMI1TXP DMI_TXP1 10
E14 C8 PCI_REQ#5 PCI_REQ#3 5 6
AD10 REQ5#/GPIO1

PCI-Express
D14 D8 PCI_GNT#5 PCI_TRDY# 7 8 K26 AB26
AD11 GNT5#/GPIO17 24 PCIE_RXN2_SLOT PERn3 DMI2RXN
B12 AD12 24 PCIE_RXP2_SLOT K25 PERp3 DMI2RXP AB25
C13 B15 C225 0.1UF/10V,X7R C0402 J28 AA28
AD13 C/BE0# 24 PCIE_TXN2_SLOT PETn3 DMI2TXN
G15 C12 R226 R227 R280 R228 RN23 C226 0.1UF/10V,X7R C0402 J27 AA27
AD14 C/BE1# BIOS strap pin 24 PCIE_TXP2_SLOT PETp3 DMI2TXP
G13 D12 1K 1K 1K 1K 10K +V3.3S
AD15 C/BE2# R0402 R0402 R0402 R0402 RA0402_8 +V1.5S_PCIE_ICH
E12 AD16 C/BE3# C15 M26 PERn4 DMI3RXN AD25
C11 ns ns ns 1 2 M25 AD24
AD17 PCI_IRDY# INT_PIRQB# Place AC coupling caps PERp4 DMI3RXP Place within 500
D11 AD18 IRDY# A7 3 4 L28 PETn4 DMI3TXN AC28
A11 E10 INT_PIRQC# 5 6 need to be within L27 AC27 mils of ICH
AD19 PAR INT_PIRQD# 250mils of the driver. PETp4 DMI3TXP
A10 AD20 PCIRST# B18 7 8
F11 A12 PCI_DEVSEL# P26 AE28
AD21 DEVSEL# PERn5 DMI_CLKN CLK_PCIE_ICH# 6
C F10 C9 PCI_PERR# P25 AE27 C
AD22 PERR# PERp5 DMI_CLKP CLK_PCIE_ICH 6
E9 E11 PCI_LOCK# RA0402_8 N28
AD23 PLOCK# PCI_SERR# 10K +V3.3S PETn5
D9 AD24 SERR# B10 N27 PETp5 DMI_ZCOMP C25
B9 F15 PCI_STOP# RN19 D25 DMI_IRCOMP_RR240 24.9,1% R0402
AD25 STOP# PCI_TRDY# PCI_LOCK# DMI_IRCOMP
A8 AD26 TRDY# F14 7 8 T25 PERn6
A6 F16 PCI_FRAME# PCI_SERR# 5 6 T24 F1
AD27 FRAME# PERp6 USBP0N USB_PORT_PN1 25
C7 INT_PIRQG# 3 4 R28 F2
AD28 PETn6 USBP0P USB_PORT_PP1 25
B6 C26 PLT_RST# PCI_PERR# 1 2 R27 G4
AD29 PLTRST# PETp6 USBP1N USB_PORT_PN0 25
E6 AD30 PCICLK A9 PCI_CLK_ICH 6 USBP1P G3 USB_PORT_PP0 25
D6 B19 SPI_SCK_ICH R2 H1
AD31 PME# SPI_CLK USBP2N USB_PORT_PN2 25
RN20 SPI_CE#_ICH P6 H2
SPI_CS# USBP2P USB_PORT_PP2 25
10K +V3.3S
Interrupt I/F P1 SPI_ARB USBP3N J4 MINICARD_USB_PN3 24

SPI
INT_PIRQA# A3 G8 INT_PIRQE# RA0402_8 J3 MINICARD_USB_PP3 24
INT_PIRQB# PIRQA# GPIO2/PIRQE# INT_PIRQF# INT_PIRQH# SPI_SI_ICH USBP3P
B4 PIRQB# GPIO3/PIRQF# F7 1 2 P5 SPI_MOSI USBP4N K1
INT_PIRQC# C5 F8 INT_PIRQG# INT_PIRQE# 3 4 SPI_SO_ICH P2 K2 USB_CAM_PN5 15
PIRQC# GPIO4/PIRQG# SPI_MISO USBP4P USB_CAM_PP5 15

USB
INT_PIRQD# B5 G7 INT_PIRQH# PCI_IRDY# 5 6 L4 MINICARD_USB_PN4 23
PIRQD# GPIO5/PIRQH# PCI_REQ#5 USBP5N
7 8 25 USB_PORT_OC1# D3 OC0# USBP5P L5 MINICARD_USB_PP4 23

AE5
MISC AE9
25 USB_PORT_OC0# C4
D5
OC1# USBP6N M1
M2 USB_CR_PN6 22
RSVD[1] RSVD[6] RN24 OC2# USBP6P USB_CR_PP6 22
AD5 RSVD[2] RSVD[7] AG8 D4 OC3# USBP7N N4
AG4 AH8 10K +V3.3S R455 E5 N3
RSVD[3] RSVD[8] T33 ICTPns RA0402_8 10K OC4# USBP7P
AH4 RSVD[4] TP3 F21 C3 OC5#/GPIO29
AD9 AH20 1 2 R0402 A2 D2
RSVD[5] MCH_SYNC# MCH_ICH_SYNC# 10 OC6#/GPIO30 USBRBIAS#
INT_PIRQF# 3 4 +V3.3AL B3 D1 USB_RBIAS_PN R245 22.6,1% R0402
ICH7M INT_PIRQA# OC7#/GPIO31 USBRBIAS
5 6
PCI_REQ#0 7 8 ICH7M Place within 500
mils of ICH

B B

+V3.3AL R238
+V3.3AL 10K
R0402

C188
0.1uF/10V,X5R U9
C0402 W25X40
SO8_50_150 ns
5

SPI_SI R239 22 R0402 SPI_SI_ICH


VCC 1 PLT_RST#
8 VDD SI 5
2 SPI_SO R242 22 R0402 SPI_SO_ICH
GNT5# GNT4# Boot BIOS
SO
10,19,23,24,29,30 BUF_PLT_RST# 4 R241 3.3K R0402 SPI_WP# 3
WP# CE# 1 SPI_CE#
SPI_SCK R244 22
SPI_CE#_ICH
R0402 SPI_SCK_ICH
0 1 SPI
2 SCK 6
GND R243 3.3K R0402 SPI_HD# 7
HOLD#
1 0 PCI
U11 4
3

R713 SN74AHC1G08DBV VSS 1 1 LPC


100K SOT23_5 C499
R0402 0.1uF/10V,X5R +V3.3AL
C0402
8 1 SPI_CE#
SPI_HD# VCC CS# SPI_SO
7 HOLD# Q 2
SPI_SCK 6 3 SPI_WP#
SPI_SI CLK W#
5 D VSS 4
U10
A
W25X80A A
SOIC8_50_208 TOPSTAR TECHNOLOGY
Swain Xu
Page Name ICH7_M(2 of 4)
Size Project Name Rev
A3 N01
A
Date: Wednesday, July 16, 2008 Sheet 18 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1

+V3.3S 6,7,10,11,12,14,15,16,17,18,20,21,23,24,25,26,27,28,29,30,35,36,37,39
+V3.3AL 15,17,18,20,23,24,25,27,29,30,31,32,33,34,35,36,37,39
+V5S 15,16,20,21,25,26,27,29,35,37,38,39

+V3.3AL +V3.3S

D R262 R263 R266 R265 D


2.2K 2.2K 2.2K 2.2K
R0402 R0402 Q7 R0402 R0402
2N7002
SOT23

SMB_DATA 3 2 SMB_DATA_S 6,14,23,24


Q8 +V3.3S
2N7002
SOT23

1
SMB_CLK 3 2 SMB_CLK_S 6,14,23,24
R246 R247 R248 R249
8.2K 8.2K 8.2K 8.2K
R0402 R0402 R0402 R0402
1

U24C
SMB_CLK C22 AF19 +V3.3AL
SMB_DATA SMBCLK GPIO21/SATA0GP
B22 SMBDATA GPIO19/SATA1GP AH18
SMB_LINK_ALERT# A26 AH19

SATA
SMB

GPIO
+V5S SMLINK0 LINKALERT# GPIO36/SATA2GP PC_BEEP R250 1K ns R0402
B25 SMLINK0 GPIO37/SATA3GP AE19
SMLINK1 A25 SMLINK1 PM_RI# R251 10K R0402
CLK14 AC1 CLK_ICH14 6
PM_RI# A28 B2

Clocks
RI# CLK48 CLK_USB48 6
SMB_ALERT# R252 10K R0402
A19 C20 ICH_SUSCLK T24 ICTPns
26 PC_BEEP SPKR SUSCLK
A27 SMB_LINK_ALERT# R253 10K R0402
15,29 PM_SUS_STAT# SUS_STAT#
7 PM_SYSRST# A22 SYS_RST# SLP_S3# B24 PM_SLP_S3# 29,36
C D23 SMLINK0 R254 10K R0402 C
SLP_S4# PM_SLP_S4# 29,37
AB18 F22 PM_SLP_S5# T30 ICTPns
10 PM_BMBUSY# GPIO0/BM_BUSY# SLP_S5# SMLINK1 R255 10K R0402
SMB_ALERT# B23 AA4 PM_ICH_PWROK
GPIO11/SMBALERT# PWROK PM_SLP_S3# R257 10K R0402
PM_STPPCI# AC20 AC22

Power MGT
6 PM_STP_PCI# GPIO18/STPPCI# GPIO16/DPRSLPVR PM_DPRSLPVR 10
PM_STPCPU# AF21 PM_BATLOW# R258 8.2K R0402
6 PM_STP_CPU# GPIO20/STPCPU#
+V3.3S C21 PM_BATLOW#

GPIO
TP0/BATLOW# PM_SYSRST# R260 10K R0402
A21

SYS
GPIO26
PWRBTN# C23 PM_PWRBTN# 29
B21 PCIE_WAKE# R264 1K R0402
R256 GPIO27
E23 GPIO28
10K C19 R293 0 R0402 PM_CLKRUN# R301 10K R0402
LAN_RST# BUF_PLT_RST# 10,18,23,24,29,30
R0402 AG18
29 PM_CLKRUN# GPIO32/CLKRUN#
RSMRST# Y4 PM_RSMRST# 29,36
VR_PWRGD_CLK_EN 6 AC19 GPIO33/AZ_DOCK_EN#
U2 GPIO34/AZ_DOCK_RST# GPIO9 E20
3

R261 Q9 A20 R344


1K 2N7002 GPIO10
23,24,29,30 PCIE_WAKE# F20 WAKE# GPIO12 F19 10K
R0402 SOT23 C504 AH21 E19 R0402
29 INT_SERIRQ SERIRQ GPIO13
1 0.1uF/10V,X5R PM_THRM# AF20 R4
39 CK505_CLK_EN# THRM# GPIO14
C0402 E22
ns VR_PWRGD_CLK_EN GPIO15
AD22 R3
2

VRMPWRGD GPIO24
GPIO25 D20
AC21 GPIO6 GPIO35 AD21
29 EC_RUNTIME_SCI# AC18
E21
GPIO7 GPIO GPIO38 AD20
AE20
29 EXT_SMI# GPIO8 GPIO39
ICH7M
B B
+V3.3AL PM_RSMRST#

3
R389 100K 1 Q25
+V3.3S 2N2222
ns SOT23

2
ns
EC_PWROFF# 29
R298 10K R0402 EC_RUNTIME_SCI#

R294 10K R0402 EXT_SMI#

R267 10K R0402 ns PM_STPPCI#

R268 10K R0402 ns PM_STPCPU# R269 0 R0402 PM_ICH_PWROK


10,29,39 IMVP_PWRGD
R270 10K R0402 INT_SERIRQ
R272
R271 8.2K R0402 PM_THRM# 10K
R0402
R274 100KR0402 PM_DPRSLPVR

A A
TOPSTAR TECHNOLOGY
Swain Xu
Page Name ICH7_M(2 of 3)
Size Project Name Rev
A3 N01
A
Date: Wednesday, July 16, 2008 Sheet 19 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1

+V3.3AL 15,17,18,19,23,24,25,27,29,30,31,32,33,34,35,36,37,39 +V5S 15,16,19,21,25,26,27,29,35,37,38,39 A4 VSS[1] VSS[98] P28


+V3.3S 6,7,10,11,12,14,15,16,17,18,19,21,23,24,25,26,27,28,29,30,35,36,37,39
+V1.5S 8,10,11,12,23,24,35,36,37 A23 VSS[2] VSS[99] R1
+V1.05S 6,7,8,9,11,12,17,28,35,36,37 +V3.3A_RTC 17 B1 VSS[3] VSS[100] R11
+V5AL 15,22,25,33,34,36,37 +V1.5S_PCIE_ICH 18 B8 VSS[4] VSS[101] R12
+V5S +V3.3S B11 R13
VSS[5] VSS[102]
B14 VSS[6] VSS[103] R14
B17 VSS[7] VSS[104] R15
D13 Layout note: Layout note:Distribute near +V1.05S B20 R16
R276 1N4148WS 0.1uF needs be placed pin ICH7 Package edge VSS[8] VSS[105]

1
B26 VSS[9] VSS[106] R17
100 SOD323 within 100mils of U24F
R0402 ICH7M PIN AD17
6mA G10 L11
860mA B28
C2
VSS[10] VSS[107] R18
T6
V5REF[1] Vcc1_05[1] VSS[11] VSS[108]
Vcc1_05[2] L12 C6 VSS[12] VSS[109] T12
AD17 L14 C189 C190 C223 C224 C27 T13
V5REF[2] Vcc1_05[3] VSS[13] VSS[110]

1
D L16 0.1UF/10V,X7R 1UF/10V,X7R 10UF/6.3V,X5R 10UF/6.3V,X5R D10 T14 D
C204 Vcc1_05[4] C0402 C0603 C0805 C0805 VSS[14] VSS[111]
F6 L17 + C524 D13 T15

1
1uF/10V,X7R V5REF_Sus Vcc1_05[5] 220UF/6.3V,OSCON VSS[15] VSS[112]
Vcc1_05[6] L18 D18 VSS[16] VSS[113] T16
C0603 +V5AL +V3.3AL AA22 M11 CAP6_6x7_3 D21 T17

2
Vcc1_5_B[1] Vcc1_05[7] VSS[17] VSS[114]
AA23 Vcc1_5_B[2] Vcc1_05[8] M18 D24 VSS[18] VSS[115] U4
AB22 P11 E1 U12

CORE
D14 Vcc1_5_B[3] Vcc1_05[9] ns VSS[19] VSS[116]
AB23 Vcc1_5_B[4] Vcc1_05[10] P18 E2 VSS[20] VSS[117] U13
Layout note: R275 1N4148WS

1
AC23 Vcc1_5_B[5] Vcc1_05[11] T11 E4 VSS[21] VSS[118] U14
0.1uF needs be placed 10 SOD323 AC24 T18 +V3.3S E8 U15
R0402 Vcc1_5_B[6] Vcc1_05[12] VSS[22] VSS[119]
within 100mils of pin AC25 U11 E15 U16
Place above cap Vcc1_5_B[7] Vcc1_05[13] VSS[23] VSS[120]
F6 of ICH7M AC26 Vcc1_5_B[8] Vcc1_05[14] U18 F3 VSS[24] VSS[121] U17
with 100milof
10mA ICH on the
AD26
AD27
Vcc1_5_B[9] Vcc1_05[15] V11
V12
F4
F5
VSS[25] VSS[122] U24
U25
bottom or 140 Vcc1_5_B[10] Vcc1_05[16] C192 VSS[26] VSS[123]
AD28 Vcc1_5_B[11] Vcc1_05[17] V14 F12 VSS[27] VSS[124] U26
mil on the top 0.1UF/10V,X7R
D26 Vcc1_5_B[12] Vcc1_05[18] V16 F27 VSS[28] VSS[125] V2
C191 near D28 T28 C0402
AD28 D27 Vcc1_5_B[13] Vcc1_05[19] V17 F28 VSS[29] VSS[126] V13
0.1uF/10V,X5R D28 V18 G1 V15
C0402 Vcc1_5_B[14] VCC PAUX Vcc1_05[20] +V3.3S +V3.3AL VSS[30] VSS[127]
E24
E25
Vcc1_5_B[15]
V5
30mA G2
G5
VSS[31] VSS[128] V24
V27
+V1.5S Vcc1_5_B[16] VccSus3_3/VccLAN3_3[1] VSS[32] VSS[129]
100 OHM@100MHz BEAD E26 Vcc1_5_B[17] VccSus3_3/VccLAN3_3[2] V1 G6 VSS[33] VSS[130] V28
+V1.5S_PCIE_ICH F23 W2 G9 W6
IN INTEL DEMO CIRCUIT Vcc1_5_B[18] VccSus3_3/VccLAN3_3[3] VSS[34] VSS[131]
FB15 0 R0805
770mA F24 Vcc1_5_B[19] VccSus3_3/VccLAN3_3[4] W7
C193 C194
G14 VSS[35] VSS[132] W24
G22
G23
Vcc1_5_B[20]
U6
50mA 0.1UF/10V,X7R 0.1UF/10V,X7R
G18
G21
VSS[36] VSS[133] W25
W26
C523 C525 C526 C195 C197 Vcc1_5_B[21] Vcc3_3/VccHDA C0402 C0402 VSS[37] VSS[134]
10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R 0.1UF/10V,X7R C196
H22
0.1UF/10V,X7R H23 Vcc1_5_B[22]
R7
10mA +V1.05S
G24
G25
VSS[38] VSS[135] Y3
Y24
C0805 C0805 C0805 C0402 0.1UF/10V,X7R C0402 Vcc1_5_B[23] VccSus3_3/VccSusHDA VSS[39] VSS[136]
C0402
J22
J23
Vcc1_5_B[24]
AE23
14mA G26
H3
VSS[40] VSS[137] Y27
Y28
Vcc1_5_B[25] V_CPU_IO[1] VSS[41] VSS[138]
K22 Vcc1_5_B[26] V_CPU_IO[2] AE26 H4 VSS[42] VSS[139] AA1
C K23 AH26 +V3.3S Place within 100 H5 AA24 C

VCCA3GP
Vcc1_5_B[27] V_CPU_IO[3] C199 VSS[43] VSS[140]

IDE
mils on the C198 C205
L22
L23
Vcc1_5_B[28]
AA7
330mA bottom or 140 mil 0.1UF/10V,X7R 0.1UF/10V,X7R 4.7UF/10V,Y5V
H24
H27
VSS[44] VSS[141] AA25
AA26
Vcc1_5_B[29] Vcc3_3[3] on the top of ICH C0402 C0402 C0805 VSS[45] VSS[142]
M22 Vcc1_5_B[30] Vcc3_3[4] AB12 H28 VSS[46] VSS[143] AB4
M23 Vcc1_5_B[31] Vcc3_3[5] AB20 J1 VSS[47] VSS[144] AB6
N22 AC16 C200 J2 AB11
Vcc1_5_B[32] Vcc3_3[6] 0.1UF/10V,X7R VSS[48] VSS[145]
N23 Vcc1_5_B[33] Vcc3_3[7] AD13 J5 VSS[49] VSS[146] AB14
C0402 +V3.3S

IDE
P22 Vcc1_5_B[34] Vcc3_3[8] AD18 J24 VSS[50] VSS[147] AB16
P23 Vcc1_5_B[35] Vcc3_3[9] AG12 J25 VSS[51] VSS[148] AB19
R22 Vcc1_5_B[36] Vcc3_3[10] AG15 J26 VSS[52] VSS[149] AB21
R23 Vcc1_5_B[37] Vcc3_3[11] AG19 K24 VSS[53] VSS[150] AB24

PCI
Place within 100
R24
R25
Vcc1_5_B[38]
A5
330mA C201 C202 C203
K27
K28
VSS[54] VSS[151] AB27
AB28
mils on the Vcc1_5_B[39] Vcc3_3[12] 0.1UF/10V,X7R 0.1UF/10V,X7R 0.1UF/10V,X7R VSS[55] VSS[152]
R26 Vcc1_5_B[40] Vcc3_3[13] B13 L13 VSS[56] VSS[153] AC2
+V1.5S bottom or 140 mil T22 B16 C0402 C0402 C0402 L15 AC5
on the top of ICH +V3.3S Vcc1_5_B[41] Vcc3_3[14] VSS[57] VSS[154]
T23 Vcc1_5_B[42] Vcc3_3[15] B7 L24 VSS[58] VSS[155] AC9
FB16 0 R0805 T26 C10 +V3.3A_RTC L25 AC11
Vcc1_5_B[43] Vcc3_3[16] VSS[59] VSS[156]

PCI
270mA T27
T28
Vcc1_5_B[44] Vcc3_3[17] D15
F9
L26
M3
VSS[60] VSS[157] AD1
AD3
Vcc1_5_B[45] Vcc3_3[18] VSS[61] VSS[158]
U22 Vcc1_5_B[46] Vcc3_3[19] G11 M4 VSS[62] VSS[159] AD4
C207 U23 G12 C209 C210 M5 AD7
0.01uF/25V,X7R Vcc1_5_B[47] Vcc3_3[20] 0.1UF/10V,X7R 0.1UF/10V,X7R VSS[63] VSS[160]
V22 Vcc1_5_B[48] Vcc3_3[21] G16 M12 VSS[64] VSS[161] AD8
C206 C0402 C208 C0402 C0402
10UF/6.3V,X5R 0.1UF/10V,X7R
V23
W22
Vcc1_5_B[49]
W5
6uA M13
M14
VSS[65] VSS[162] AD11
AD15
C0805 C0402 Vcc1_5_B[50] VccRTC +V3.3AL VSS[66] VSS[163]
W23 Vcc1_5_B[51] M15 VSS[67] VSS[164] AD19
Y22
Y23
Vcc1_5_B[52] VccSus3_3[1] P7 52mA M16
M17
VSS[68] VSS[165] AD23
AE2
Vcc1_5_B[53] VSS[69] VSS[166]
VccSus3_3[2] A24 M24 VSS[70] VSS[167] AE4
+V1.5S B27 C24 C211 C212 M27 AE8
B Vcc3_3[1] VccSus3_3[3] 0.1UF/10V,X7R 0.1UF/10V,X7R VSS[71] VSS[168] B
50mA AG28
VccSus3_3[4] D19
D22 C0402 C0402
M28
N1
VSS[72] VSS[169] AE11
AE13
Place within 100 +V1.5S VccDMIPLL VccSus3_3[5] +V3.3AL VSS[73] VSS[170]
VccSus3_3[6] G19 N2 VSS[74] VSS[171] AE18
mils on the Place within 100
bottom or 140 mil C213 mils on the 1.01A AB7
AC6
Vcc1_5_A[1]
K3
52mA N5
N6
VSS[75] VSS[172] AE21
AE24
on the top of ICH 0.1UF/10V,X7Rbottom or 140 mil Vcc1_5_A[2] VccSus3_3[7] VSS[76] VSS[173]
AC7 Vcc1_5_A[3] VccSus3_3[8] K4 N11 VSS[77] VSS[174] AE25
C0402 on the top of ICH AD6 K5 N12 AF2
near AG5 Vcc1_5_A[4] VccSus3_3[9] VSS[78] VSS[175]
ARX

C214 AE6 K6 C215 C216 N13 AF4


0.1UF/10V,X7R Vcc1_5_A[5] VccSus3_3[10] 0.1UF/10V,X7R 0.1UF/10V,X7R VSS[79] VSS[176]
AF5 Vcc1_5_A[6] VccSus3_3[11] L1 N14 VSS[80] VSS[177] AF8
C0402 AF6 L2 C0402 C0402 N15 AF11
Vcc1_5_A[7] VccSus3_3[12] VSS[81] VSS[178]
USB

AG5 Vcc1_5_A[8] VccSus3_3[13] L3 N16 VSS[82] VSS[179] AF27


AH5 Vcc1_5_A[9] VccSus3_3[14] L6 N17 VSS[83] VSS[180] AF28
+V3.3S
50mA AD2
VccSus3_3[15] L7
M6
N18
N24
VSS[84] VSS[181] AG1
AG3
VccSATAPLL VccSus3_3[16] VSS[85] VSS[182]
270mA AH11
VccSus3_3[17] M7
N7 +V1.5S
N25
N26
VSS[86] VSS[183] AG7
AG11
Vcc3_3[2] VccSus3_3[18] VSS[87] VSS[184]
Place within 100 +V1.5S AB10 AB17
1.01A P3
P4
VSS[88] VSS[185] AG14
AG17
mils on the C217 Vcc1_5_A[10] Vcc1_5_A[19] VSS[89] VSS[186]
bottom or 140 mil 0.1UF/10V,X7R
1.01A AB9
AC10
Vcc1_5_A[11] Vcc1_5_A[20] AC17 P12
P13
VSS[90] VSS[187] AG20
AG25
on the top of ICH C0402 Place within 100 Vcc1_5_A[12] VSS[91] VSS[188]
AD10 Vcc1_5_A[13] Vcc1_5_A[21] T7 P14 VSS[92] VSS[189] AH1
mils on the C218 AE10 F17 P15 AH3
Vcc1_5_A[14] Vcc1_5_A[22] VSS[93] VSS[190]
ATX

bottom or 140 mil 0.1UF/10V,X7R AF10 G17 P16 AH7


on the top of ICH C0402 Vcc1_5_A[15] Vcc1_5_A[23] VSS[94] VSS[191]
AF9 Vcc1_5_A[16] P17 VSS[95] VSS[192] AH12
near AG9
AG9 Vcc1_5_A[17] Vcc1_5_A[24] AB8 P24 VSS[96] VSS[193] AH23
+V3.3AL AH9 AC8 P27 AH27
Vcc1_5_A[18] Vcc1_5_A[25] VSS[97] VSS[194]
45mA E3 K7 T25 ICTP ns C220 U24E
+V1.5S VccSus3_3[19] VccSus1_05[1] 0.1UF/10V,X7R ICH7M
A 10mA C1 C28 T28 ICTP ns C0402 TOPSTAR TECHNOLOGY
A

C219 VccUSBPLL VccSus1_05[2] T27 ICTP ns


VccSus1_05[3] G20
0.1UF/10V,X7R ns ICTP T26 AA2 +V1.5S Swain Xu
C0402 ns ICTP T29 VccSus1_05/VccLAN1_05[1]
Y7 VccSus1_05/VccLAN1_05[2]Vcc1_5_A[26] A1 Page Name ICH7_M(3 of 3)
C222
0.1UF/10V,X7R Vcc1_5_A[27] H6
H7
1.01A C221 Place within 100 Size
USB CORE

Vcc1_5_A[28] Project Name Rev


C0402 J6 0.1UF/10V,X7R mils on the A3 N01
Vcc1_5_A[29] C0402 bottom or 140 mil A
Vcc1_5_A[30] J7
on the top of ICH Date: Wednesday, July 16, 2008 Sheet 20 of 42
ICH7M PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1

+V5S 15,16,19,20,25,26,27,29,35,37,38,39

+V3.3S 6,7,10,11,12,14,15,16,17,18,19,20,23,24,25,26,27,28,29,30,35,36,37,39

D D
SATA HDD
+V5S V_HDD
SATA_HDD
FB32 0 R0805 Close to connector as possible SATA_HDD CONN
the same distance to connector SATA_S_50E
C444 C301 C300 P2
17 SATA_TXP0 TX
4.7uF/10V,Y5V 0.1uF/25V,Y5V 0.1uF/25V,Y5V P3 P1
17 SATA_TXN0 TX# GND0
C0805 C0402 C0402 C508 3300pF/50V,X7RC0402 P5 P4
17 SATA_RXN0 RX# GND1
C507 3300pF/50V,X7RC0402 P6 P7
17 SATA_RXP0 RX GND2

V3.3_SATA P8 VCC3_0 GND3 P11


P9 VCC3_1 GND4 P12
P10 VCC3_2 GND5 P13

V_HDD P14 VCC5_0 GND6 P17


+V3.3S V3.3_SATA P15 VCC5_1
P16 VCC5_2 GND7 P19
FB31 0 R0805 ns P18 REEVE
C
GND8 23 C
C441 C295 C294 P20 24
4.7uF/10V,Y5V 0.1UF/16V,Y5V 0.1UF/16V,Y5V VCC12_0 GND9
P21 VCC12_1
C0805 C0402 C0402 P22
ns ns ns VCC12_2

B B

TOPSTAR TECHNOLOGY
Swain Xu
Page Name SATA HDD
A A
Size Project Name Rev
A4 N01
A
Date: Wednesday, July 16, 2008 Sheet 21 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1

+V5AL 15,20,25,33,34,36,37

FB19
VCC3V 600ohm@100MHz,1.5A
FB0805
VCC3VA
D D
C230 C231 C232 CFD2/SMD2/SDD2
0.1UF/25V,Y5V 4.7UF/10V,Y5V 0.1UF/25V,Y5V CFD3/SMD3/SDD3
C0402 C0805 C0402
OLD 3IN1 CONN.

VCC3V
MSD1 MSINS

VREF
MSCLK1 CFD1/SMD1/SDD1
CFA0/SMALE/MSBS CFD0/SMD0/SDD0 J6A
R278 CFD2/SMD2/SDD2 2
0 CFD3/SMD3/SDD3 DAT2_SD CARD_3V3
3 DAT3_SD VDD_SD 6
R0603 U25 CFA1/SMCLE/SDCMD 4
VCC18 UB6232 CMD_SD

48
47
46
45
44
43
42
41
40
39
38
37
QFPS48_0D5_1D6 SDCLK 7 SD+MMC C516
CLK_SD 0.1uF/10V,X7R

SMALE/MSBS
MSCLK

VREF

MSINSZ
MSD1
SMREZ/MMCD4
SMD3/SDD3
SMD2/SDD2

GND_4
VCC33_3

SMD1/SDD1
SMD0/SDD0
CFD0/SMD0/SDD0 9 8
C236 C237 CFD1/SMD1/SDD1 DAT0_SD VSS_SD2
10 DAT1_SD
0.1UF/25V,Y5V 4.7UF/10V,Y5V SDCD# 1 5 C517
C0402 C0805 EROM15/SDWPD CD_SD# VSS_SD1 1uF/10V,X7R
11 WP_SD#
CFD4/SMD4/MSD0 1 C0603
SMD4/MSD0 CFD6/SMD6/MSD2 3IN1
2 SMD5/MMCD6 SMD6/MSD2 36
SDCLK 3 35 CFD7/SMD7/MSD3
SDCLK SMD7/MSD3 CFA1/SMCLE/SDCMD J6B
4 SMWEZ/MMCD5 SMCLE/SDCMD 34
5 33 VCC3V MSCLK1 14 13 CARD_3V3
VREF GND_1 VCC33_2 SDCD# CLK_MS VCC_MS
6 SMCDZ SDCDZ 32
VCC3V 7 31 CFD7/SMD7/MSD3 15
C229 CARD_3V3 8
VCC33_1 GND_3
30 EROM15/SDWPD MSINS 16
DAT3_MS MS
0.1UF/25V,Y5V VBUS_5V VCC18 CRDVCC SDWPD CFD6/SMD6/MSD2 INS_MS
9 29 17 12

LEDZ/TESTEN/UATX
C0402 VCC3V REG18_O SMWPZ VCC18 CFD4/SMD4/MSD0 DTA2_MS VSS_MS1
10 REG33_O VCC18 28 18 DTA0_MS VSS_MS2 21
VCC5V MSD1

SMWPDZ/TEST0
11 VBUS SMBSYZ/MMCD7 27 19 DTA1_MS GND1 22
12 26 CFA0/SMALE/MSBS 20 23
C C234 GND_2 SDA/TEST3/UARX BS_MS GND2 C
SCL/TESTINTR 25

VCC33A_1

VCC33A_2
10uF/10V,Y5V C235 3IN1 C518 C519

GNDA_1

GNDA_2
C1206 0.1UF/25V,Y5V 0.1uF/10V,X7R 1uF/10V,X7R

SMCEZ

REXT
CARD_3V3 ns C0402 C0603

DM
XO

DP
XI
C233
13
14
15
16
17
18
19
20
21
22
23
24
1uF/25V,Y5V
C0805
XI
USB_CR_PP6 18
VCC3VA
USB_CR_PN6 18

VCC3VA
REXT
R282
0 Y3
R0402 12.000MHz
+V5AL R279 VBUS_5V XS2
0 1 2 XO R281
R0805 12.1K,1%
R0402
C238 C239
27pF/50V,NPO27pF/50V,NPO
C0402 C0402
PWR SW

4
5
6
S
R735 0 R0805 Q27
CR_Nops +V5AL AO6409 VBUS_5V

D
TSOP6_0D95_1D6

G
CR_PS

3
2
1
B SDCD_D# B
1
D37
SDCD# 3 BAT54C
SOT23 R736 C531 C532
2 4.7K C0402 C0402
CR_PS R0402 0.01uF/25V,X7R 0.01uF/25V,X7R
CR_PS CR_PS CR_PS
R737
2
D38
MSINS 3 BAT54C
SOT23 100K
1 MSINS_D# R0402
CR_PS CR_PS

R738 0 R0805
CR_Nops

A A
TOPSTAR TECHNOLOGY
Swain Xu
Page Name Card Reader(UB6232 USB)
Size Project Name Rev
A3 N01
A
Date: Wednesday, July 16, 2008 Sheet 22 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1

+V3.3S 6,7,10,11,12,14,15,16,17,18,19,20,21,24,25,26,27,28,29,30,35,36,37,39
+V3.3AL 15,17,18,19,20,24,25,27,29,30,31,32,33,34,35,36,37,39
+V1.5S 8,10,11,12,20,24,35,36,37
+VDC 15,25,31,33,34,35,37,39
+DATA4

D -DATA4 D

+V3.3AL

1
D15 D16 +V3.3S PCIE_NUT1
ESDPAD_R0603 ESDPAD_R0603 Hole+Dowel
EGA1-0603-V05 EGA1-0603-V05 TH_200_132_112
ns ns R283

2
0 R284 R285
R0603 0 0 +V1.5S
ns R0603 R0603

+V3.3S_PCIE +V3.3AL_PCIE

1
MPCIE1
MINIPCIE_TEMP1

52

24

48
28
2

6
Keep USB2.0 Signal stub short

+3.3VAUX
+3.3V0
+3.3V1

+1.5V0
+1.5V1
+1.5V2
R288 0 R0402 +V3.3S +V3.3AL
R289 0 R0402

CHK1
90ohm@100MHz,0.5A
L4_0805 ns ICTP R286 R287
3 4 -DATA4 36 46 ns 10K 10K
18 MINICARD_USB_PN4 USB_D- LED_WPAN# T31
2 1 +DATA4 38 44 R0402 R0402
18 MINICARD_USB_PP4 USB_D+ LED_WLAN# Wireless_LED# 27
42 ns ns
T32

PCIE mini Card


LED_WWAN# ICTP minicard_CLKREQ#
C ns C
11 22 minicard_Wake#
6 CLK_PCIE_EXPCARD# REFCLK- PERST# BUF_PLT_RST# 10,18,19,24,29,30
13 1 minicard_Wake# R290 0 R0402 ns
6 CLK_PCIE_EXPCARD REFCLK+ WAKE# PCIE_WAKE# 19,24,29,30
7 minicard_CLKREQ# R299 0 R0402 ns
CLKREQ# PCIE_CLKREQ# 6,24

18 PCIE_TXN1_SLOT 31 PETN0
33 32 R292 0 R0402 ns
18 PCIE_TXP1_SLOT PETP0 SMB_DATA SMB_DATA_S 6,14,19,24
30 R291 0 R0402 ns
SMB_CLK +V3.3AL SMB_CLK_S 6,14,19,24

18 PCIE_RXN1_SLOT 23 PERN0
18 PCIE_RXP1_SLOT 25 PERP0
CHANNEL_CLK 5
3 R0402
R296 0 R0402 Debug CHANNEL_DATA 10K
+VDC 17 RESERVED0
R302 0 R0402 Debug 19 R300
10,18,19,24,29,30 BUF_PLT_RST# RESERVED1
20 R297 0 R0402
RESERVED_DISABLE HW_RATIO_OFF1# 29
R323 0 R0402 Debug 37
6 PCI_CLK_DEBUG RESERVED_PCIE0
+V3.3AL R295 0 R0603 39 RESERVED_PCIE1 R333 0 R0402 Debug
41 RESERVED_PCIE2 RESERVED_SIM0 16 EC_DEBG_Enable 29
R304 0 R0402 Debug 43 14 R338 0 R0402 Debug
17,29 LPC_FRAME# RESERVED_PCIE3 RESERVED_SIM1 PWR_SW_VCC2 25,31
R322 0 R0402 Debug 45 12 R339 0 R0402 Debug
17,29 LPC_AD0 RESERVED_PCIE4 RESERVED_SIM2 EC_DEBG_UTXD 29
R330 0 R0402 Debug 47 10 R340 0 R0402 Debug
17,29 LPC_AD1 RESERVED_PCIE5 RESERVED_SIM3 EC_DEBG_URXD 29
R331 0 R0402 Debug 49 8 ns
17,29 LPC_AD2 RESERVED_PCIE6 RESERVED_SIM4 T37
R332 0 R0402 Debug 51 ICTP
17,29 LPC_AD3 RESERVED_PCIE7

GND10
GND11
GND12
GND13
B
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9 +V3.3S_PCIE +V3.3AL_PCIE B

C243 C244 C245 C246


PCIE MINI CARD 10UF/6.3V,X5R 0.1UF/25V,Y5V 10UF/6.3V,X5R 0.1UF/25V,Y5V
9
15
21
27
29
35
4
18
26
34
40
50
53
54
C0805 C0402 C0805 C0402

+V1.5S

C247 C248 C249 C250 C251


10UF/6.3V,X5R 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V
C0805 C0402 C0402 C0402 C0402

A A
TOPSTAR TECHNOLOGY
Swain Xu
Page Name
PCIE MINI SLOT 1
Size Project Name Rev
A3 N01
A
Date: Wednesday, July 16, 2008 Sheet 23 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1

+V3.3S 6,7,10,11,12,14,15,16,17,18,19,20,21,23,25,26,27,28,29,30,35,36,37,39
+V1.5S 8,10,11,12,20,23,35,36,37
+V3.3AL 15,17,18,19,20,23,25,27,29,30,31,32,33,34,35,36,37,39

D D

+DATA8

-DATA8
+V3.3S +V3.3AL +V3.3AL

1 1
D36 D35
EGA10603V05A1-B EGA10603V05A1-B R500 R506 R504
ESDPAD_R0603 ESDPAD_R0603 0 0 0
ns ns R0603 R0603 R0603 +V1.5S
2 2 ns

MPCIE2
MINIPCIE_TEMP1 +V3.3S +V3.3AL
Keep USB2.0 Signal stub short

52

24

48
28
2

6
+3.3VAUX
+3.3V0
+3.3V1

+1.5V0
+1.5V1
+1.5V2
R495 0
R496 0
R540 R502 R539
10K 10K 10K
CHK6 ns ns ns
90ohm@100MHz,0.5A
L4_0805
C
18 MINICARD_USB_PN3 3 4 -DATA8 36 46 T148 ns C
+DATA8 38 USB_D- LED_WPAN# T155 ns MiniPCIE_REQ#
18 MINICARD_USB_PP3 2 1 USB_D+ LED_WLAN# 44
42

PCIE mini Card


ns LED_WWAN# T147 ns
HW_RATIO_OFF2#
6 CLK_PCIE_EXPCARD2# 11 REFCLK- PERST# 22 BUF_PLT_RST# 10,18,19,23,29,30
6 CLK_PCIE_EXPCARD2 13 1 WAKE# R538 0 ns WAKE#
REFCLK+ WAKE# PCIE_WAKE# 19,23,29,30
7 MiniPCIE_REQ#
CLKREQ# PCIE_CLKREQ# 6,23

18 PCIE_TXN2_SLOT 31 PETN0
33 32 R402 0 ns
18 PCIE_TXP2_SLOT PETP0 SMB_DATA SMB_DATA_S 6,14,19,23
30 R394 0 ns
SMB_CLK SMB_CLK_S 6,14,19,23

18 PCIE_RXN2_SLOT 23 PERN0
18 PCIE_RXP2_SLOT 25 PERP0
CHANNEL_CLK 5
CHANNEL_DATA 3
ns ICTP T150
17 RESERVED0
ns ICTP T146
19 RESERVED1
+V3.3AL
20 R503 0
RESERVED_DISABLE HW_RATIO_OFF2# 29
R532 0 37
R533 0 R0603 RESERVED_PCIE0
39 RESERVED_PCIE1
41 RESERVED_PCIE2 RESERVED_SIM0 16 T152ICTP ns
R0603 43 14 R491 R492
RESERVED_PCIE3 RESERVED_SIM1 T151ICTP ns
45 12 10K 10K
RESERVED_PCIE4 RESERVED_SIM2 T149ICTP ns
47 10 ns ns
RESERVED_PCIE5 RESERVED_SIM3 T154ICTP ns
49 RESERVED_PCIE6 RESERVED_SIM4 8 T153ICTP ns
51 RESERVED_PCIE7
B B
+V3.3S +V3.3AL
GND10
GND11
GND12
GND13
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9

PCIE MINI CARD


9
15
21
27
29
35
4
18
26
34
40
50
53
54

+V1.5S +V3.3S
+V3.3AL

C458 C459 C450 C445 C449 C452 C469


10UF/6.3V,X5R 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 10UF/6.3V,X5R 0.1UF/25V,Y5V C457 C460
C0805 C0402 C0402 C0402 C0402 C0805 C0402 10UF/6.3V,X5R 0.1UF/25V,Y5V
C0805 C0402

A A
TOPSTAR TECHNOLOGY
Swain Xu
Page Name
USB Port
Size Project Name Rev
A3 N01 A
Date: Wednesday, July 16, 2008 Sheet 24 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1

+V3.3S 6,7,10,11,12,14,15,16,17,18,19,20,21,23,24,26,27,28,29,30,35,36,37,39
+V3.3AL 15,17,18,19,20,23,24,27,29,30,31,32,33,34,35,36,37,39
+V5S 15,16,19,20,21,26,27,29,35,37,38,39
+V5AL 15,20,22,33,34,36,37
+VDC 15,23,31,33,34,35,37,39

S3 FUSE 1.1A FUSE1812


1 2 +V5AL

C288 C289 R483 560K R0402 +V3.3AL


D 330PF/50V,X7R + 100uF/10V,TAN R484 D
C0402 CT7343_28 300K C429
R0402 1000pF/50V,X7R
C0402 ns PR161
USB1 GND_USB 20K
R0402
VCC1 1 Keep USB2.0 Signal USB_PORT_OC0#
ns 18
5 HOLE0 GND_USB PWRSW# 29

3
6 HOLE1 -DATA1 2 -DATA0 stub short 4 3 USB_PORT_PN0 18 +V3.3AL
7 3 +DATA0 1 2 PQ59
HOLE2 +DATA1 USB_PORT_PP0 18
8 L4_0805 2N7002E-T1
HOLE3 SWVCC2_SW_1 SOT23
GND 4 1
90ohm@100MHz,0.5A

1
SINGLE USB PORT D30 D29 CHK4 PC133

2
USB1 ESDPAD_R0603 ESDPAD_R0603 R335 0 R0603 PR163 1000pF/50V,X7R
EGA1-0603-V05 EGA1-0603-V05 GND_USB 1M C0402 PD32
R334 0 R0603 R0402 BAT54S

2
3 SOT23
GND_USB
GND_USB GND_USB

1
PWR_SW_VCC2 23,31

C C

+V5S +V3.3AL +V3.3S

R359 R135 R357


10K 10K 10K
ns
ns
FAN_BACK 29

3
R351 1K FAN_TACH_ON 1 Q23
2N2222 R352
+V5S C286 ns SOT23

2
ns 0
1000pF/50V,X7R

Q13 ns
BCP69-16
SOT223
4
3 2 Vfan
1

B B
R35
1

1K R24
1

10
R0603 R346 FAN_FB
USBCONN1
2

VCC_358 5.11K,1% 21 21
1

C161 Vfan 2 1 USB_PORT_PP2 18


2

R36 U1A 2 1
4 4 3 3 USB_PORT_PN2 18
1K 0.1UF/25V,Y5V LM358 FAN_FB 6 5
6 5
8

so8_50_150 Shut-Down +VDC 8 7 +V5AL


+V3.3S SWVCC2_SW_1 10 8 7
+ 3 9
2

10 9
1 12 12 11 11
1

- 2 Throttling/ 18 USB_PORT_OC1# 14 14 13 13
R349 Un-throttling +V3.3AL 16 15
16 15 USB_PORT_PP1 18
R22 18 17
15,29 LIDR# USB_PORT_PN1 18
4

C183 10K,1% 18 17
4.7K 20 20 19 19
R0402 22
2

0.1UF/25V,Y5V 22
R26 R25
High-5V 88242_2001
1 100K 2
FAN1_V 29 CNS2x10_1_R
200K R0402
Middle-4V

Low-3V
C94
C104
A
FAN1_V=3.30V,Vfan=5V 4.7UF/10V,Y5V 0.1uF/25V,Y5V
A
C0805 C0402
FAN1_V=2.65V,Vfan=4V 50 55 60 65 70 75 80 85 90 95 100
TOPSTAR TECHNOLOGY
Swain Xu
FAN1_V=1.98V,Vfan=3V Page Name Output Board
Size Project Name Rev
A3 N01
A
Date: Wednesday, July 16, 2008 Sheet 25 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1

VCC5CDC +V5S
FB20
+V3.3S 6,7,10,11,12,14,15,16,17,18,19,20,21,23,24,25,27,28,29,30,35,36,37,39
+V3.3S 1 2300ohm@100MHz,1.5A +V5S 15,16,19,20,21,25,27,29,35,37,38,39
FB0805
C252 C253 C254 C255 C256 C257 C258
C0402 C0402 C0805 C0402 C0402 C0805
0.1UF/25V,Y5V 0.1UF/25V,Y5V 10UF/6.3V,X5R 0.1UF/25V,Y5V 0.1UF/25V,Y5V 10UF/6.3V,X5R 0.1UF/25V,Y5V Headphone Jack
C0402
INPUT:HEADPHONE/LINE-OUT
U26
ALC662
Cross moat place OUTPUT:FRONT L/R

25
38
GND_AUD

1
9
QFPS48_0D5_1D6

VDD1
VDD2

AVDD1
AVDD2
LINE_OUT1
T39 ICTP ns A_GPIO0 2 35 C264 4.7uF/10V,X5R C0805 HP_OUT_L
GPIO0 FRONT-OUT-L HP_OUT_L R319 75 R0402 FB23 1
D
2300ohm@100MHz,1.5A 2 L D
ns A_GPIO1 3 36 C266 4.7uF/10V,X5R C0805 HP_OUT_R FB0805
T40 ICTP GPIO1 FRONT-OUT-R HP_OUT_R R320 75 R0402 FB24 1 2300ohm@100MHz,1.5A 3
37 FB0805 4 R
LINE1-VREFO-R C259 0.1UF/25V,Y5V C0402 HP_JD
GND_AUD 5
1
27 C265 10UF/6.3V,X5R C0805
VREF

1
D18 0.1UF/25V,Y5V D32 D31
11 28 VREFOUT R303 4.7K R0402 INT_MIC_L_R ESDPAD_R0603 C277 C278 C279 ESDPAD_R0603 ESDPAD_R0603 AZALIAJACK
17 HDA_RST# REST# MIC1-VREFO-L ns EGA1-0603-V05 C0402 EGA1-0603-V05 EGA1-0603-V05 AUDIO5A
6 ?? 100pF/50V,NPO 100pF/50V,NPO
17 HDA_BITCLK

2
BITCLK C0402 C0402
LINE1-VREFO-L 29
17 HDA_SYNC 10 SYNC
30 R317 2.2K R0402 MIC2_REF
MIC2-VREFO
17 HDA_SDOUT 5 SDOUT
LINE2-VREFO 31
R305 33 R0402 8
17 HDA_SDATA_IN0 SDIN
32 R306 4.7K R0402 INT_MIC_L_R GND_AUD
R307 51K R0402 C260 1uF/10V,Y5V C0603 C261 10pF/50V,NPO C0402 MIC1-VREFO-R
12 33 R308 10K R0402
29 BTL_BEEP PC-BEEP DCVOL VCC5CDC
ns
JACK_DET_A 13 34 JACK_DET_B
R309 75K R0402 C262 1uF/10V,Y5V C0603 JD1 JD2
C263
14 43
19 PC_BEEP 100pF/50V,NPO LINE2-L CEN-OUT Stereo Microphone Jack
C0402 15 LINE2-R LFE-OUT 44 INPUT:STEREO MIC-IN
R312
4.7K
R311
4.7K
MIC2_L C272 4.7uF/10V,X5R C0805 16
MIC2-L
ALC662 SIDESURR-OUT-L 45 D20
1N4148WS
OUTPUT:CENT/LFE
R0402 R0402 MIC2_R C273 4.7uF/10V,X5R C0805 17 46 MIC2_REF 1 2
MIC2-R SIDESURR-OUT-R SOD323
D24
18 47 EAPD R721 0 R0402 SHUTDOWN# 1N4148WS
CD-L SPDIFI/EAPD ns 1 2
REMOVE SHUTDOWN# 20 48 SOD323
CD-R SPDIFO
INT_MIC_L C267 1uF/10V,X7R C0603 21 R202 R220
MIC1-L SURR_OUT_L 4.7K 4.7K
SURR-OUT-L 39
update internal MIC circuit C268 1uF/10V,X7R C0603 22 R0402 R0402 MIC_IN1
MIC1-R R315 20K,1% R0402
C
JDREF 40 GND_AUD C
23 MIC2_L R310 75 R0402 FB21
1 2300ohm@100MHz,1.5A 2 L
LINE1-L SURR_OUT_R FB0805
Layout Note: SURR-OUT-R 41

CD-GND
24 MIC2_R R313 75 R0402 FB22
1 2300ohm@100MHz,1.5A 3

AGND1
AGND2
All of JD resistors should be LINE1-R R

GND1
GND2
FB0805 4
placed as close as possible to MIC2_JD 5
the sense pin of codec. 1

4
7

19

26
42

1
D17 C269 C270 C271 D33 D34
ESDPAD_R0603 ESDPAD_R0603 ESDPAD_R0603 AZALIAJACK
EGA1-0603-V05 C0402 100pF/50V,NPO 100pF/50V,NPO EGA1-0603-V05 EGA1-0603-V05 AUDIO5A
0.1UF/25V,Y5V C0402 C0402

2
GND_AUD

GND_AUD
HP_OUT_L GND_AUD HP_OUT_R GND_AUD

Q11 Q10 JACK_DET_B R314 20K,1% R0402 MIC2_JD


6

3
VCC5CDC VCC5CDC 2N7002DW 2N7002DW
SC70_6 SC70_6 JACK_DET_A R318 5.11K,1% R0402 HP_JD
AMP_SHDW 2 5 AMP_SHDW 2 5
GAIN0 GAIN1 Av(inv)
1

4
R722 R723
10K 10K 0 0 6dB
R0402 R0402
ns 0 1 10dB
GAIN0
GAIN1 Adjust Gain to 10dB 1 0 15.6dB
BY K' 080118 VCC5CDC
1 1 21.6dB D25
R724 R725
B B
10K 10K 1 2 JOPEN_3
R0402 R0402 R325 ns
ns 10K
R0402

SHUTDOWN# C291 C0402 ns


GND_AUD GND_AUD De-pop Solution
3

0.1UF/25V,Y5V
Q12 C287 C0402 ns
2N7002
R327 1K R0402 1 0.1UF/25V,Y5V
29 AMP_SHDW
R329
Layout Note: FB26 1 2 FB0805 ns
2

R328 100K Tied at three points under the 300ohm@100MHz,1.5A


10K R0402
R0402 codec and near the codec C285 C0402 ns

0.1UF/25V,Y5V

GND_AUD

GND_AUD
Onboard Amp
C290 R336 U27
0.22uF/10V,X7R
20K TPA6017A2
onboard stereo
SURR_OUT_R
C0603 R0402 sop20_0d65_4d4g
INTSPR+
INTSPK1
INT_spkR 4Pin INT_MIC_L_R
microphone
17 RIN- ROUT+ 18
20K CNS4_R
R726 R0402 7 14 INTSPR- INTSPL- 4 4 6 6 MIC1
RIN+ ROUT- INTSPL+ Microphone
3 3
GND_AUD
C282 0.22uF/10V,X7R R326 10K R0402
C0603
9 LIN+ LOUT+ 4 INTSPL+ INTSPR+
INTSPR-
2 2
INT_MIC_L
R321
1K R0402 FB25 300ohm@100MHz,1.5A
+ BZ_D6027
ASSY
1 1 5 5 1 2 1
C283 0.22uF/10V,X7R 10 8 INTSPL- FB0805 2
GND_AUD BYPASS LOUT-
C0603 VCC5CDC
1

A SURR_OUT_L R324 20K R0402 ns 5 16 GND_AUD C319 D23 A


LIN- VDD C284 100pF/50V,NPO ESDPAD_R0603
12 NC PVDD1 6
C281 15 C513 C514 C0805 C0402 EGA1-0603-V05
0.22uF/10V,X7R SHUTDOWN# PVDD2 C0402 C0402 ns
19 1
2

C0603 SHDWN# GND1 4.7uF/10V,Y5V


GND2 11
GAIN0 2 13 0.1UF/10V,X7R TOPSTAR TECHNOLOGY
GAIN0 GND3 0.1UF/10V,X7R
GND4 20
GAIN1 Swain Xu
3 GAIN1 GND5 21
Page Name
GND_AUD Audio
GND_AUD Size Project Name Rev
C N01 A
Date: Wednesday, July 16, 2008 Sheet 26 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1

LED
D D

+V3.3S +V5S 15,16,19,20,21,25,26,29,35,37,38,39


+V3.3S 6,7,10,11,12,14,15,16,17,18,19,20,21,23,24,25,26,28,29,30,35,36,37,39
WIRELS +V3.3AL 15,17,18,19,20,23,24,25,29,30,31,32,33,34,35,36,37,39
R677 220 R0402 WIRE+ 1 2 TP_WIRELESS_LED#
WIRELESS_LED# 23
BL-HB335A-TRB
R678 220 R0402 IDE+ 1 2 TP_HDD_LED#
HDD_LED# 17
HDD
BL-HB335A-TRB

TCHARGE

+V3.3AL LED4_1210B
HA1B333B AMP&BLUE
Blue Color
B
R680 220 R0402 CHARGE_LED 4 2 TP_CHG_LED#
CHG_LED# 29
R
R682 220 R0402 BAT_STATE_LED 3 1 TP_BTL_LED#
BTL_LED# 29
C470 Orange color
0.1UF/25V,Y5V
C0402 TP
R684 220 R0402 PWR+ 1 2 TP_POWERLED# INT_spkR 6Pin
POWERLED# 29
CNS6_0D5_RA1
POWER
BL-HB335A-TRB 6 +V5S
6
8 8 5 5
C 4 C
4 TPCLK 29
7 7 3 3 TPDAT 29
TP_WIRELESS_LED#TESD11 1 2 EGA1-0603-V05 2
ns ESDPAD_R0603 2
1 1
+V3.3AL
TP_HDD_LED# TESD8 1 2 EGA1-0603-V05
ns ESDPAD_R0603 TP_CHG_LED# R709 10K R0402
ns
TP_CHG_LED# TESD9 1 2 EGA1-0603-V05
ns ESDPAD_R0603 TP_BTL_LED# R710 10K R0402
ns
TP_BTL_LED# TESD10 1 2 EGA1-0603-V05
ns ESDPAD_R0603 TP_POWERLED# R711 10K R0402
ns
TP_POWERLED# TESD12 1 2 EGA1-0603-V05
ns ESDPAD_R0603

WIRE+ C472 1000pF/50V,X7R C0402

IDE+ C473 1000pF/50V,X7R C0402

CHARGE_LED C474 1000pF/50V,X7R C0402

BAT_STATE_LED C475 1000pF/50V,X7R C0402

PWR+ C476 1000pF/50V,X7R C0402

H8
H1 H2 H4 H6 H9 H7
B B

HOLE

1
HOLE HOLE HOLE HOLE HOLE HOLE TH_256_118

1
TH_256_118 TH_256_118 TH_256_118 TH_256_118 TH_256_118 TH_256_118

ns ns CASE_GND ns
ns ns ns ns
GND_USB
GND_BAT

H3 H5

HOLE HOLE
1

1
TH_200_118 TH_200_118
A A
TOPSTAR TECHNOLOGY
ns ns
Swain Xu
Page Name
MDC/SSD
Size Project Name Rev
A3 N01 A
Date: Wednesday, July 16, 2008 Sheet 27 of 42
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1

+V1.05S 6,7,8,9,11,12,17,20,35,36,37