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AN 883: Intel Arria 10 DisplayPort

TX-only Design

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Contents

Contents

1.1. Design Components............................................................................................... 4


1.2. Clocking Scheme................................................................................................... 5
1.3. Top Level Interface Signals..................................................................................... 6
1.4. Quick Start Guide ................................................................................................. 6
1.4.1. Hardware and Software Requirements.......................................................... 7
1.4.3. Running the Hardware................................................................................8
1.4.4. Design Debug Features...............................................................................9
1.5. Creating the TX-only Design with Bitec FMC Daughter Card....................................... 10
1.5.1. Generating the Design.............................................................................. 10
1.5.2. Removing Irrelevant Blocks....................................................................... 11
1.5.3. Instantiating Video and Image Processing (VIP) Intel FPGA IPs...................... 12
1.5.4. Generated Clocks.....................................................................................14
1.5.5. Making a Direct Connection to the TX Transceiver Block................................ 14
1.5.6. Modifying the Software............................................................................. 15
1.6. Document Revision History for AN 883: Intel Arria 10 DisplayPort TX-only Design.........16

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1. Intel® Arria® 10 DisplayPort TX-only Design


The Intel® Arria® 10 DisplayPort TX-only design demonstrates how the DisplayPort
source (TX) transmits 4Kp60 video output generated by the Test Pattern Generator II
Intel FPGA IP.

This design uses the Bitec FMC daughter card to transmit the video output.

Figure 1. Intel Arria 10 DisplayPort TX-only Design Block Diagram


Computer

OC RAM Avalon-MM
Nios II Processor
SYSID Interconnect TX AUX Transaction
Debug FIFO Monitoring
Timer Avalon-MM
JTAG UART Source Interconnect
Clocked Video TX AUX Debug Management
Output II Stream
Test Pattern
Generator II Avalon-ST DisplayPort TX DisplayPort TX
Video with Sync Management Bridge
Video Signals
TX Sub-system (Platform Designer)
Core System (Platform Designer)

TX Reconfiguration
148.5 MHz
160 MHz
16 MHz

Locked

TX Reconfiguration Transceiver PHY


Management Rest Controller

Reset Generator
Video PLL
Transceiver Native
PHY
TX PLL
TX PHY Top
Top

100 MHz Bitec FMC


Reference Clock Daughter Card
Reset Button
Intel FPGA IP components
outside Platform Designer system
Intel FPGA IP components
inside dp_core Platform Designer system
Intel FPGA IP components
inside DisplayPort TX Platform Designer system
Custom logic component

Related Information
• Intel Design Store
Provides the design files.
• DisplayPort Intel Arria 10 FPGA IP Design Example User Guide
Provides more information about the Intel Arria 10 design examples.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in ISO
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services 9001:2015
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any Registered
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
1. Intel® Arria® 10 DisplayPort TX-only Design
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1.1. Design Components


The DisplayPort Intel FPGA IP core design example requires these components.

Table 1. Core System Components


Module Description

Core System (Platform Designer) The core system consists of the Nios II processor and its necessary components,
DisplayPort TX core sub-system and the Video and Image Processing (VIP) FPGA
IPs.
This system provides the infrastructure to interconnect the Nios II processor with
the DisplayPort Intel FPGA IP core (TX instance) through Avalon Memory Mapped
(Avalon-MM) interface within a single Platform Designer system to ease the
software build flow.
This system consists of:
• CPU Sub-System
• TX Sub-System
• VIP FPGA IPs

TX Sub-System (Platform Designer) The TX sub-system consists of:


• Clock Source—The clock source to the DisplayPort TX core. This sub-system
has two clock sources integrated: 100 MHz and 16 MHz.
• Reset Bridge—The bridge that connects the external signal to the sub-system.
This bridge synchronizes to the respective clock source before it is used.
• DisplayPort TX Core—DisplayPort Source IP core, VESA DisplayPort Standard
version 1.4.
• Debug FIFO—This FIFO captures all DisplayPort TX auxiliary cycles, and prints
out in the Nios II Debug terminal. This component is only used when the
TX_AUX_DEBUG parameter is turned on.
• PIO—The parallel IO that triggers the DPTX register update in software
(tx_utils.c).
• Avalon-MM Pipeline Bridge—This Avalon-MM bridge interconnects the Avalon-
MM interface between components within the TX sub-system to the Nios II
processor in the Core sub-system.

Table 2. DisplayPort TX PHY Top Components


Module Description

TX PHY Top The TX PHY top level consists of the components related to the transmitter PHY
layer.
• Transceiver Native PHY(TX)—The transceiver block that receives 20-bit or
40-bit parallel data from the DisplayPort Intel FPGA IP core and serializes the
data before transmitting it. This block supports up to 8.1 Gbps (HBR3) data
rate with 4 channels.
Note: You must set the TX channel bonding mode to PMA and PCS
bonding and the PCS TX Channel bonding master parameter to 0
(default is auto).
• Transceiver PHY Reset Controller—The TX Reconfiguration Management
module triggers the reset input of this controller to generate the
corresponding analog and digital reset signals to the Transceiver Native PHY
block according to the reset sequencing.
• TX Reconfiguration Management—This block reconfigures and recalibrates the
Transceiver Native PHY and TX PLL blocks to transmit serial data in the
required data rates (RBR, HBR, HBR2, and HBR3).
• TX PLL—The transmitter PLL block provides a fast serial fast clock to the
Transceiver Native PHY block. For the DisplayPort Intel FPGA IP core design
example, Intel uses transmitter fractional PLL (FPLL).
Note: 8.1 Gbps is available only in the Intel Quartus® Prime Pro Edition
software.

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Table 3. Top-Level Common Blocks


Module Description

IOPLL IOPLL generates three common source clocks:


• 160 MHz—Used as main clock for Clocked Video Output II and Test Pattern
Generator II FPGA IPs.
• 16 MHz—Used as DisplayPort TX auxiliary clock.
• 148.5 MHz—Used as video clock for DisplayPort Intel FPGA source and
Clocked Video Output II FPGA IP

1.2. Clocking Scheme


The clocking scheme illustrates the clock domains in the DisplayPort Intel FPGA IP core
design example.

Table 4. Clocking Scheme Signals


Clock Signal Name in Design Description

TX PLL Refclock tx_pll_refclk 135 MHz TX PLL reference clock, that is divisible by the
transceiver for all DisplayPort data rates (1.62 Gbps, 2.7
Gbps, and 5.4 Gbps).
Note: The reference clock source of the TX PLL refclock is
located at the HSSI refclk pin.

TX Transceiver Clockout gxb_tx_clkout TX clock recovered from the transceiver, and the frequency
varies depending on the data rate and symbols per clock.

Data Rate Symbols per Frequency


Clock (MHz)

RBR (1.62 Gbps) 2 (dual) 81

4 (quad) 40.5

HBR (2.7 Gbps) 2 (dual) 135

4 (quad) 62.5

HBR2 (5.4 Gbps) 2 (dual) 270

4 (quad) 135

HBR3 (8.1 Gbps) 4 (quad) 202.5

Management Clock tx_rcfg_mgmt_clk A free running 100 MHz clock for both Avalon-MM interfaces
for reconfiguration and PHY reset controller for transceiver
reset sequence.

Component Required
Frequency
(MHz)

Avalon-MM reconfiguration 100 – 125

Transceiver PHY reset controller 1 – 500

16 MHz Clock clk_16 16 MHz clock used to encode and decode auxiliary channel in
the DisplayPort Intel FPGA source and sink IP cores.

Calibration Clock dp_tx_clk_cal A 50 MHz calibration clock input that must be synchronous to
the Transceiver Reconfiguration module's clock. This clock is
used in the DisplayPort Intel FPGA IP core's reconfiguration
logic.
continued...

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Clock Signal Name in Design Description

TX Video Clock tx_vid_clk Recovered video clock from the PCR module that reflects the
actual video clock frequency.
Used when DisplayPort source's TX_SUPPORT_IM_ENABLE =
0.

CVO Video Clock tx_vid_clk Fixed video clock generated by the video PLL (148.5 MHz) to
the DisplayPort Intel FPGA source.

VIP Clock vip_clk 160 MHz clock generated by the video PLL.

1.3. Top Level Interface Signals


The tables list the signals for the TX-only design example.

Table 5. Top-Level Signals


Signal Direction Width Description

On-board Oscillator Signal

refclk1_p Input 1 100 MHz clock source used as IOPLL reference clock and
Avalon-MM management clock

User Push Button

cpu_resetn Input 1 Global reset

DisplayPort FMC Daughter Card Pins on FMC Port A

fmca_gbtclk_m2c_p Input 1 135 MHz dedicated transceiver reference clock from FMC
port A

fmca_dp_c2m_p Output N DisplayPort TX serial data


Note: N = TX maximum lane count

fmca_la_rx_n_9 Input 1 DisplayPort TX HPD


• 1 = HPD asserted
• 0 = HPD deasserted

fmca_la_tx_p_12 Input 1 DisplayPort TX Aux In

fmca_la_rx_p_10 Output 1 DisplayPort TX Aux Out

fmca_la_rx_n_10 Output 1 DisplayPort TX Aux OE

fmca_la_tx_n_12 Output 1 FMC card TX CAD

1.4. Quick Start Guide


The reference design features a hardware design that supports compilation and
hardware testing.

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1.4.1. Hardware and Software Requirements


To test the design, ensure that you have the appropriate hardware and software.

Hardware
• Intel Arria 10 GX FPGA Development Kit (10AX115S2F45I1SG)
• Bitec FMC daughter card revision 5.0 or later
• DisplayPort sink (monitor)
• DisplayPort cables

Software
• Intel Quartus Prime (for hardware testing)

2. Compiling and Testing the Design


You can download the DisplayPort TX-only design file (A10_DP_TX_FMC_PRO.par)
from the Intel Design Store. To compile and run a demonstration test on the hardware
example design, follow these steps.

The .par file contains includes pre-compiled .sof and .elf files that you can run to
test the design.
1. Unzip the Additional_Files.zip file from the A10_DP_TX_FMC_PRO.par file,
and move the Script and Software folder to the main project directory.
2. Launch the Intel Quartus Prime Pro Edition software and open <project
directory>/quartus/top.qpf.
Note: Bitec DisplayPort FMC daughter card revision 10 has schematic changes
compared to revisions 8 and earlier. Revision 8 has lane reversal and
polarity inversion at TX. To support all revisions, the design example top
level RTL file at <project directory>/rtl/top.v file include a local
parameter for you to select the FMC revision.
localparam BITEC_DP_CARD_REV = 0;

// 0 = Bitec FMC DP card rev.4 - 8,

// 1 = rev.9 or later

3. Open Nios II Command Shell and navigate to the Script folder.


4. Run the build_sw_sh script in the Nios II terminal to build the software.
5. In the Intel Quartus Prime Pro Edition software, click Processing ➤ Start
Compilation.
6. After successful compilation, the Intel Quartus Prime Pro Edition software
generates a .sof file in your specified directory.

Related Information
Intel Design Store
Provides the design files.

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1.4.2.1. Regenerating ELF File

By default, the ELF file is generated when you generate the dynamic design example.

Note: In some cases, you need to regenerate the ELF file if you modify the software file or
modify and regenerate the dp_core.qsys file. Regenerating the dp_core.qsys file
updates the .sopcinfo file, which requires you to regenerate the ELF file.

1. Go to <project directory>/software and edit the code if necessary.


2. Go to <project directory>/script and execute the following build script:
source build_sw.sh
• On Windows, search and open Nios II Command Shell. In the Nios II
Command Shell, go to <project directory>/script and execute source
build_sw.sh.
• On Linux, launch the Platform Designer, and open Tools ➤ Nios II Command
Shell. In the Nios II Command Shell, go to <project directory>/script
and execute source build_sw.sh.
3. Make sure an .elf file is generated in <project directory>/software/
dp_demo.
4. Download the generated .elf file into the FPGA without recompiling the .sof file
by running the following script:
nios2-download <project directory>/software/dp_demo/*.elf
5. Push the reset button on the FPGA board for the new software to take effect.

1.4.3. Running the Hardware


Set up the hardware before you run the design on the Intel Arria 10 development kit.

Figure 2. Arria 10 Development Kit Hardware Setup


DisplayPort TX
to sink device

Bitec FMC
daughter card

USB to
computer

Power supply

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1. Install the Bitec FMC daughter card at the FMC port A on the Intel Arria 10
development kit.
2. Connect the DisplayPort TX connector on the Bitec FMC daughter card to a video
analyzer or DisplayPort sink device such as a monitor.
3. Ensure all switches on the development board are in default position.
4. Power up and connect the development board to your PC using a micro USB cable.
5. Download the .sof file into the FPGA device using Intel Quartus Prime
Programmer.
6. Push the Reset button on the Intel Arria 10 development kit.
7. The DisplayPort sink device displays the video.

Figure 3. DisplayPort TX-only Design Output Video

Note: The hardware setup below uses ASUS MG28UQ monitor with Bitec FMC daughter card revision 8 connected to
Intel Arria 10 FPGA development kit. The monitor runs 4Kp60 color bar video generated by the Video and
Image Processing Intel FPGA IPs.

1.4.4. Design Debug Features


This design also offers debugging features that are useful for debugging link up and no
video output issues.

1.4.4.1. Main Stream Attribute (MSA) Information


This debug feature enables you to check the MSA information.

This feature is a part of the DisplayPort TX-only design example. To display the (MSA
of the DisplayPort TX core, type ‘S’ on the keyboard while in the Nios II terminal. The
TX stream MSA values will appear on the Nios II terminal.

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Figure 4. MSA Values on Nios II Terminal

1.4.4.2. Auxiliary Channel Traffic Monitor


This debug feature enables you to check the auxiliary channel transaction.

This feature is also a part of the DisplayPort TX-only design example. To display the
auxiliary channel transaction on the Nios II terminal, set the BITEC_AUX_DEBUG flag
in the config.h file in the project folder to 1.
#define BITEC_AUX_DEBUG 1 // Set to 1 to enable AUX CH traffic monitoring
Rebuild the Nios II software and download the ELF image into the FPGA.

1.5. Creating the TX-only Design with Bitec FMC Daughter Card
You can create the DisplayPort TX-only design by making certain software and
hardware modifications to the already provided DisplayPort SST parallel loopback with
PCR design example.

1.5.1. Generating the Design


Before you make the modifications, first you need to generate the DisplayPort SST
Parallel Loopback design example in the Intel Quartus Prime Pro Edition.

1. Instantiate the DisplayPort Intel FPGA IP and specify the parameters as listed
below.

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Table 6.
Parameters Value Description

Maximum video output color depth (Source) 10 bpc This design supports GPU and monitors up to a
maximum of 10 bit-per-color depth.

Maximum link rate 5.4 Gbps The bandwidth requirement for 4Kp60 and 10
bpc video stream through serial link:
Maximum lane count 4 • Active video resolution = 3840 × 2160
pixels/frame
• Total resolution (including reduced blanking)
= 4000 × 2222 pixels/frame
• Refresh rate = 60 Hz or 60 frames per
second
• Bits per pixel = 10 bpc × 3 colors = 30 bits
per pixel
• Total bandwidth = (4000 × 2222) pixel/
frame × 60 frame/s × 30 bits/pixel =
15.9984 Gbits/s
With 8b/10b encoding scheme, the actual
bandwidth required = 15.9984 × 10/8 =
19.998 Gbps. With 4 lanes at 5.4 Gbps, the
aggregated bandwidth of 21.6 Gbps is sufficient
to support the 4K video stream at 60 Hz
refresh rate.

Symbol output mode (Source) Quad Symbol mode affects the transceiver parallel
bus width and the DisplayPort IP core clock
Symbol input mode (Sink) frequency. The DisplayPort IP core synchronizes
with the transceiver parallel clock. The parallel
clock frequency is link rate/transceiver parallel
bus width.
Frequency for HBR2 (5.4 Gbps) is 5400/20 or
270 MHz for dual (20 bits) and 5400/40 or 135
MHz for quad (40 bits) mode.

Pixel input mode (Source) Quad Pixel mode affects the video clock frequency
and video port width of the IP core.
Pixel output mode (Sink) For 4Kp60 video stream, the bandwidth
requirement is 4000 × 2222 × 60 pixel/s =
533280000 pixels/s. Because of the high
bandwidth requirement, the design requires
dual or quad pixel mode for timing closure.
• Single (1 pixel/clock) 533.28 MHz
• Dual (2 pixels/clock) 266.64 MHz
• Quad (4 pixels/clock) 133.32 MHz

Support analog reconfiguration On Enable analog reconfiguration interface. Used


to reconfigure vod and pre-emphasis value.

Enable AUX debug stream On Enable AUX source traffic output to Avalon-ST
port

DisplayPort SST Parallel Loopback With PCR On Enable Pixel Clock Recovery in the design.

2. Click Generate Example Design.

1.5.2. Removing Irrelevant Blocks


Modify the generated design example by removing the irrelevant blocks from the top-
level design and from the dp_core.qsys file.

Remove the RX sub-system, RX PHY top. Pixel Clock Recovery (PCR), and Transceiver
Arbiter components (in gray), as shown in the diagram below. These blocks are not
needed for the TX-only design.

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Figure 5. Components Required for the DisplayPort TX-only Design

Top

Core System (Platform Designer)


RX Sub-system (Platform Designer) TX Sub-system (Platform Designer)
PIO Avalon-MM Avalon-MM PIO
Interconnect Interconnect
Debug CPU Sub-system
FIFO Debug
FIFO
DisplayPort RX DisplayPort TX
EDID
RAM

Audio Data

Video Data Video Data


Pixel Clock
Recovery
(PCR)
RX PHY Top Video TX PHY Top
Transceiver IOPLL Pattern Transceiver
PHY Reset Transceiver Generator PHY Reset
Native PHY TX PLL
Controller Controller
Transceiver
RX Arbiter TX
Transceiver Reconfiguration
Reconfiguration Native PHY
Management Management

Control/Sataus Parallel Data TX only component


Serial Data Avalon-MM Component to be removed

1.5.3. Instantiating Video and Image Processing (VIP) Intel FPGA IPs
After generating the design, instantiate the relevant Video and Image Processing FPGA
IPs.

1. Instantiate the Clocked Video Output (CVO) II and Test Pattern Generator (TPG) II
Intel FPGA IPs and specify the parameters as listed in the table below.
Note: The Test Pattern Generator (TPG) II Intel FPGA IP generates video stream
that displays color bars video pattern. The Clocked Video Output II Intel
FPGA IP converts the Avalon-ST video format received from the TPG II Intel
FPGA IP to standard clocked video format.

Table 7. Clocked Video Output (CVO) II and Test Pattern Generator (TPG) II
Parameter Settings
FPGA IP Parameters Value

Clocked Video Output II Image width / Active pixels 3840


Note: The CVO II parameter setting is
Image height / Active lines 2160
specific for 4K video resolution.
For other video resolution, refer
Bits per pixel per color plane 8
to VESA monitor timing
standard specifications. Number of color planes 3

Number of pixels in parallel 4


continued...

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FPGA IP Parameters Value

Separate syncs only - Frame/ Field 1 32


Horizontal sync

Separate syncs only - Frame/ Field 1 48


Horizontal front porch

Separate syncs only - Frame/ Field 1 80


Horizontal back porch

Separate syncs only - Frame/ Field 1 5


Vertical sync

Separate syncs only - Frame/ Field 1 3


Vertical front porch

Separate syncs only - Frame/ Field 1 54


Vertical back porch

Pixel FIFO size 3840

FIFO level at which to start output 3839

Use control port 4

Test Pattern Generator II Bits per color sample 10

Number of pixels in parallel 4

Color planes transmitted in parallel Yes

Output format 4:4:4

Maximum frame width 3840

Maximum frame height 2160

Default Interlacing Progressive output

Number of test patterns 1

Pattern Color bars

Subsampling & Colorspace RGB

2. Connect the CVO II and TPG II Intel FPGA IP instances in the Platform Designer.

Figure 6. Connecting the CVO II and TPG II in the Platform Designer

Main Clock VIP Clock Bridge

Main Reset VIP Reset Bridge

Dout

Test Pattern Generator II

Din
Main Clock
Main Reset
Clocked Video

Clocked Video Output II

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Note: The CVO II and TPG II Intel FPGA IPs share the reset input from the reset
generator output.
3. Ensure the CVO II FPGA IP signals are exported out from Platform Designer and
connected to the signals in the DisplayPort TX sub-system as shown below.

Figure 7. Connecting CVO II Intel FPGA IP to the DisplayPort TX Sub-system

Vid_v_sync Tx_vid_v_sync
Vid_h_sync Tx_vid_h_sync
Tx_vid_clk Vid_datavalid Tx_vid_de Tx_vid_clk
Vid_data Tx_vid_data

Clocked Video 0utput II DisplayPort TX

Note: The CVO II and TPG II Intel FPGA IPs share the reset input from the reset
generator output.

1.5.4. Generated Clocks


Apart from the default clocking scheme in the generated design example, you need to
generate an additional output clock from the video PLL.

Table 8. DisplayPort TX-only Design Generated Clocks


Clocks Description

outclk_0 (default) 160 MHz output clock that acts as the main clock for CVO II
and TPG II FPGA IP instances.

outclk_1 (default) 16 MHz output clock for DisplayPort Source 1 Mbps AUX
channel interface.

outclk_2 (user-generated) 148.5 MHz output clock for DisplayPort TX and CVO II video
clocks.
Note: The 148.5 MHz clock frequency supports the native
4K or UHD resolution video output. Other video
formats may run at different clock frequency.

1.5.5. Making a Direct Connection to the TX Transceiver Block


The existing dynamic DisplayPort parallel SST loopback with PCR design example uses
the Transceiver Arbiter to share between an RX and TX transceiver within the same
channel. As the TX-only design only requires the TX transceiver, you need to remove
the Transceiver Arbiter and make a direct connection to the TX transceiver.

1. Before you make the connection, in the Platform Designer turn on the Shared
Reconfiguration Interface parameter in the Transceiver Native PHY block to
allow for single Avalon-MM slave interface for dynamic reconfiguration of all
channels.
2. Update the transceiver signal width as shown below in the design top-level and
the tx_phy_top.v files.

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Table 9. TX Transceiver Signals


Signal Direction Width (Bit)

gxb_tx_rcfg_write Input 1

gxb_tx_rcfg_read Input 1

gxb_tx_rcfg_address Input 12

gxb_tx_rcfg_writedata Input 32

gxb_tx_rcfg_readdata Input 32

gxb_tx_rcfg_waitrequest Input 1

3. Make a direct connection from the Bitec Reconfig block to the TX transceiver block
in the tx_phy_top.v file as shown in the diagram below..

Figure 8. Bitec Reconfig and TX Transceiver Block Connection

Tx_rcfg_writedata

Tx_rcfg_address

Tx_rcfg_write
Bitec_reconfig_alt_a10

Tx_rcfg_read

Tx_rcfg_readdata

Tx_rcfg_waitrequest

Tx_rcfg_cal_busy

Gxb_tx_rcfg_writedata

Gxb_tx_rcfg_address

Gxb_tx_rcfg_write

Gxb_tx_rcfg_read
Gxb_tx

Gxb_tx_rcfg_readdata

Gxb_tx_rcfg_waitrequest
_

Gxb_tx_rcfg_cal_busy

Tx_phy_top

1.5.6. Modifying the Software


After removing the irrelevant blocks and reconnecting the remaining blocks with the
newly instantiated FPGA IPs, modify the software.

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1. First, modify the software's config.h file. Navigate to the design example folder
and change the values of the following parameter settings in the file.

Table 10. Config.h Parameter Settings


Parameter Value Description

BITEC_AUX_DEBUG 0 Set to 1 to enable AUX channel traffic


monitoring.

BITEC_STATUS_DEBUG 1 Set to 1 to enable MSA and link status


monitoring.

DP_SUPPORT_RX 0 Set to 1 if the DisplayPort supports RX.

BITEC_RX_GPUMODE 0 Set to 1 to enable Sink GPU mode.

BITEC_RX_CAPAB_MST 0 Set to 1 to enable MST support.

BITEC_RX_FAST_LT_SUPPORT 0 Set to 1 to enable Fast Link Training support.

BITEC_RX_LQA_SUPPORT 0 Set to 1 to enable Link Quality Analysis


support.

BITEC_EDID_800X600_AUDIO 0 Set to 1 to use an EDID with maximum


resolution 800 x 600

BITEC_DP_0_AV_RX_CONTROL_BITEC_CFG_R 0 Set to 1 to enable MST support


X_SUPPORT_MST

DP_SUPPORT_TX 1 Set to 1 if DisplayPort supports TX

BITEC_TX_CAPAB_MST 0 Set to 1 to enable MST support

TX_VIDEO_IM_ENABLE 0 Set to 1 to enable TX Video IM interface

DP_SUPPORT_EDID_PASSTHRU 0 Set to 1 to enable EDID passthrough from sink


to source.

BITEC_DP_CARD_REV 0 • Set to 0 = Bitec FMC DisplayPort daughter


card revision 4 – 8 (without Paradetech
Retimer)
• Set to 1 = Bitec FMC DisplayPort daughter
card revision 9 or later (with Paradetech
Retimer)

MST_RX_STREAMS 0 RX MST number of streams

MST_TX_STREAMS 0 TX MST number of streams

2. Next, for debugging purposes, modify the debug.c file located in the software/
dp_demo folder. Open the debug.c file and remove the void
bitec_dp_dump_sink_msa() and void bitec_dp_dump_sink_config()
functions.
Note: Any modifications you make in the debug.c script will be overwritten each
time you rebuild the software. To prevent this, place a copy of the debug.c
file in the main software folder before you modify.

1.6. Document Revision History for AN 883: Intel Arria 10


DisplayPort TX-only Design
Document Changes
Version

2019.02.20 Initial release.

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