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A 0.1�2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation
Circuits in 130-nm CMOS 24 OCTOBER 2017 by: JPINFOTECH PROJECTS in: BLOGTags: VLSI
IEEE PROJECTS 2017note: NO COMMENTS
A 0.1�2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation
Circuits in 130-nm CMOS ABSTRACT: A 100-MHz�2-GHz closed-loop analog in-
phase/quadrature correction circuit for digital clocks is presented. The proposed
circuit consists of a phase-locked loop- type architecture for quadrature error
correction. The circuit corrects the phase error to within
a1.5�upto1GHzandtowithin3�at2GHz. It consumes 5.4 mA [�]

Read More � A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit

Prediction Algorithm for the Successive-Approximation Register 16 SEPTEMBER 2016
by: VARADAN in: BLOGTags: BULK IEEE PROJECTS, IEEE PROJECTS FOR ECE, IEEE PROJECTS
IN PONDICHERRY, VLSI IEEE PROJECTS 2016note: NO COMMENTS
A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit Prediction
Algorithm for the Successive-Approximation Register ABSTRACT: This brief presents
a fast-acquisition 11-bit all-digital delay-locked loop (ADDLL) using a novel
starting-bit prediction algorithm for the successive-approximation register (SBP-
SAR). It can effectively eliminate the harmonic lock and the false lock. The
achievable acquisition time is within 17.5�23.5 or [�]

Read More � An All-Digital Approach to Supply Noise Cancellation in Digital Phase-

Locked Loop 15 SEPTEMBER 2016 by: VARADAN in: BLOGTags: BULK IEEE PROJECTS, IEEE
PROJECTS FOR ECE, IEEE PROJECTS IN PONDICHERRY, VLSI IEEE PROJECTS 2016note: NO
COMMENTS
An All-Digital Approach to Supply Noise Cancellation in Digital Phase-Locked Loop
ABSTRACT: With increased levels of integration in modern system-on-chips, the
coupling of supply noise in a phase locked loop (PLL) has become the dominant
source of performance degradation in many systems. In this paper, an all-digital
approach to canceling the effects of supply noise [�]

Read More � A Robust Energy/Area-Efficient Forwarded-Clock Receiver with All-

Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects 14
SEPTEMBER 2016 by: VARADAN in: BLOGTags: BULK IEEE PROJECTS, IEEE PROJECTS FOR ECE,
IEEE PROJECTS IN PONDICHERRY, VLSI IEEE PROJECTS 2016note: NO COMMENTS
A Robust Energy/Area-Efficient Forwarded-Clock Receiver with All-Digital Clock and
Data Recovery in 28-nm CMOS for High-Density Interconnects ABSTRACT: This paper
presents a robust energy/area-efficient receiver fabricated in a 28-nm CMOS
process. The receiver consists of eight data lanes plus one forwarded-clock lane
supporting the hyper transport standard for high-density chip-to-chip links. The
proposed all-digital clock [�]

Read More �
A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator
A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator 24 SEPTEMBER 2015
by: VARADAN in: BLOGnote: NO COMMENTS
A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator ABSTRACT: In this
brief, a low-cost low-power all-digital spread spectrum clock generator (ADSSCG) is
presented. The proposed ADSSCG can provide an accurate programmable spreading ratio
with process, voltage, and temperature variations. To maintain the frequency
stability while performing triangular modulation, the fast-relocked mechanism is
proposed. The proposed fast-relocked [�]

Read More � A Novel Digital-Intensive Hybrid Polar-I/Q RF Transmitter Architecture

24 DECEMBER 2018 by: JPINFOTECH PROJECTS in: PROJECTS 2018Tags: IEEE PROJECTS
2018note: NO COMMENTS
A Novel Digital-Intensive Hybrid Polar-I/Q RF Transmitter Architecture ABSTRACT A
novel digital-intensive hybrid transmitter (TX) architecture is presented,
combining conventional inphase and quadrature (I/Q) with constrained phase
modulation. The proposed architecture utilizes an RF-DAC with phase modulated RF
clock and adjusted I/Q components. By incorporating phase modulation the quadrature
component is kept small while [�]

Read More � Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power

Fused Multiply-Add 11 OCTOBER 2018 by: JPINFOTECH PROJECTS in: PROJECTS 2018Tags:
IEEE PROJECTS 2018, VLSI IEEE PROJECTSnote: NO COMMENTS
Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused
Multiply-Add ABSTRACT: The need for power efficiency is driving a rethink of design
decisions in processor architectures. While vector processors succeeded in the
high-performance market in the past, they need a retailoring for the mobile market
that they are entering now. Floating-point (FP) fused multiply-add (FMA), being [�]

Read More � Multilevel Half-Rate Phase Detector for Clock and Data Recovery
Circuits 11 OCTOBER 2018 by: JPINFOTECH PROJECTS in: PROJECTS 2018Tags: IEEE
PROJECTS 2018, VLSI IEEE PROJECTSnote: NO COMMENTS
Multilevel Half-Rate Phase Detector for Clock and Data Recovery Circuits ABSTRACT:
In this brief, a half-rate (HR) bang-bang (BB) phase detector (PD) with multiple
decision levels is proposed for clock and data recovery (CDR) circuits. The
combination allows the oscillator to run at half the input data rate while
providing information about the sign and [�]

Read More � A Fast-Locking, Low-Jitter Pulsewidth Control Loop for High-Speed ADC
11 OCTOBER 2018 by: JPINFOTECH PROJECTS in: PROJECTS 2018Tags: IEEE PROJECTS 2018,
VLSI IEEE PROJECTSnote: NO COMMENTS
A Fast-Locking, Low-Jitter Pulsewidth Control Loop for High-Speed ADC ABSTRACT: A
fast-locking, high-precision, and low-jitter pulsewidth control loop (PWCL) for
high-speed high-resolution analog-to-digital converter is presented. Only through
controlling the delay of rising edge to adjust duty cycle, the clock jitter could
be suppressed greatly. An improved charge pump with a follower circuit and self-
biased [�]

Read More � A 100-mA, 99.11% Current Efficiency, 2-mVppRipple Digitally Controlled

LDO with Active Ripple Suppression 24 OCTOBER 2017 by: JPINFOTECH PROJECTS in:
BLOGTags: VLSI IEEE PROJECTS 2017note: NO COMMENTS
A 100-mA, 99.11% Current Efficiency,2-mVpp Ripple Digitally Controlled LDO with
Active Ripple Suppression ABSTRACT: Digital low-dropout (DLDO) regulators are
gaining attention due to their design scalability for distributed multiple voltage
domain applications required in state-of-the-art system on-chips. Due to the
discrete nature of the output current and the discrete-time control loop, the
steady-state response [�]

Read More �
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