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by Fred Harris

How to Pack
Professor
San Diego State University
fred.harris@sdsu.edu

Dragan Vuletic

a Room of Analog Director of Engineering


Signum Concepts
dragan.vuletic@signumconcepts.com

Wade Lowdermilk

FM Modulators CEO
Signum Concepts
wade.lowdermilk@signumconcepts.com

into a Xilinx FPGA


You are likely familiar with the way that dig-
ital television is transmitted from satellites as
multi-channel MPEG (Motion Picture
Experts Group) compressed video to a cable
head end where the multiple channels are
demodulated. The MPEG streams are
decoded and then remodulated as channel-

DSP techniques replace a legacy ized analog NTSC (National Television


Standards Committee) or PAL (Phase

multi-channel analog modulator. Alternating Lines) television signals for inser-


tion in a cable distribution plant.
Similarly, high-quality stereo audio is
transmitted from a satellite as multi-channel
MP3 (MPEG Layer-3) compressed audio to
a cable head end where the multiple channels
are demodulated. The MP3 streams are
decoded and then remodulated as channel-
ized analog FM signals for insertion in a
cable distribution plant.

Figure 1 – Equipment bay containing


legacy transceiver equipment

16 DSP magazine Copyright © 2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. April 2007
WIRELESS

PCM
L-Band IQ MP3
RF-Tuner De-Mod DSP
Decoder
Digital
L-Band IQ MP3 PCM DBX To

Data Mux
RF-Tuner De-Mod

De-Mux
FM DAC
DSP Modulator and
L-Band IQ MP3 Decoder Channelizer Smoothing
RF-Tuner De-Mod and Filter
PCM
Interpolator
L-Band IQ MP3 DSP
RF-Tuner De-Mod Decoder

Figure 2 – High-level block diagram of transceiver

The device that combines a transmitter FPGA. The FPGA outputs a single sampled through a high-speed output bus to the
and receiver in a single unit is called a trans- data stream of channelized FDM signal span- FPGA modulation module. Figure 2 is a
ceiver, while the device that performs ning approximately the 20- to 80-MHz fre- high-level block diagram of the system.
demodulation of a collection of channels in quency band. The MP3 decoding is
one format and remodulates them in a sec- performed by 48 Blackfin processors from System Considerations
ond format is called a transmultiplexer. We Analog Devices. We designed the digital FM modulator and
will resist the temptation to coin a new noun The all-DSP-based transceiver that replaces channelizer to replace an existing analog
from pieces of the words transmitter, receiv- the bay of analog equipment was recently modulator system. The output of the modu-
er, translator, and multiplexer and refer to the fielded by X-Digital Systems, a San Diego- lator is demodulated by legacy analog
system we describe here as a transceiver. based satellite communications company. receivers. These receivers contain a standard
In this article, we’ll describe the imple- The emphasis of this article is on the channelizer, a set of conventional FM
mentation of a unique digital transceiver sys- processing tasks performed in the FPGA- demodulators, and analog dbx decoders. The
tem. The system decodes 384 MP3 stereo based modulator, designed and imple- digital modulator is required to seamlessly
audio signals received from a satellite down- mented by Signum Concepts, another San interact with the analog receiver, which
link. It digitally remodulates the multiple Diego-based communication systems means that the design parameters of the dig-
sampled data signal sets as a single analog sig- development company. ital modulator have to match the design
nal made up of 384 frequency-division mul- parameters of the legacy analog modulator.
tiplexed (FDM) channels. Each channel High-Level Description Thus, the gain and phase of the digital filters
contains a pair of stereo signal components The transceiver comprises four subsystems: in the digital dbx encoders have to match
as well as a third component similar to the the demodulator block, the demultiplexer those of the analog dbx encoders. This is
commercial FM broadcast signal known as a block, the decoder block, and the FM modu- required to assure that the analog dbx
subsidiary carrier authorization (SCA). lator block. The demodulator block accepts decoders perform as well with the digital
The three signals are pre-processed by a four L-Band input signals as inputs to four encoder as they do with the analog encoder.
dbx (noise reduction system) and standard RF tuners, which down-convert selected Similarly, the gain and phase of the pre-
pre-emphasis filters before FM modulation QPSK RF bands to IQ (in-phase and quadra- emphasis filters used in the digital FM modu-
and channelization. The entire transceiver ture phase) baseband signals. The baseband lator must match the gain and phase of the
occupies a 2U rack-mount chassis (436-mm IQ signals are processed by the demodulator analog pre-emphasis filters. Here too, the
wide [17.16”], 350-mm deep [13.78”], and block to form MP3 (MPEG audio) data or requirement ensures that the receiver perform-
87.1-mm [3.4”] high) – replacing a legacy transport streams. ance is the same when receiving signals
hardware rack containing 192 analog modula- These demodulated streams enter the formed in the digital modulator as signals
tor circuit boards. Figure 1 shows the bay of demultiplexer block, which merges the streams formed in the analog modulator. For the same
legacy equipment that previously performed with optional local asynchronous digital MP3 reason, the modulation index and the modu-
the 384 channels of MP3 decoding, dbx pre- transport streams and partitions the composite lated bandwidths of the digital FM modulator
coding, pre-filtering, and FM modulation. transport stream for delivery to the 48 Blackfin chain must match the corresponding values of
The dbx encoding, digital pre-emphasis processors in the decoder block. The decoder the analog FM modulator chain.
system-specific stereo FM modulation, and block forms 16-bit pulse-coded modulation This is an unusual design constraint.
resampling channelizer are performed in a (PCM) versions of the MP3 coded input trans- Usually, DSP-based systems enhance the per-
single Xilinx® Virtex™-4 XC4VSX55 port stream. The PCM data is delivered formance of an analog prototype system.

April 2007 DSP magazine 17


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Left 75-μsec LPF


L+R
Pre-Emph 14 kHz

3.2 MHz : 100

Right dbx LPF VCO BFP


50-μsec
L-R 15-50 kHz
Encode Pre-Emph 14 kHz 32 kHz
IF
Output
3.2 MHz : 40

SCA dbx 50-μsec LPF VCO BFP


Encode Pre-Emph 7.5 kHz 80 kHz 60-90 kHz

Left 75-μsec LPF


Pre-Emph 7.5 kHz

3 MHz : 100

Right BFP
dbx 50-μsec LPF VCO
Encode Pre-Emph 7.5 kHz 30 kHz 15-50 kHz
IF
Output
3 MHz : 40

SCA dbx 50-μsec LPF VCO BFP


Encode Pre-Emph 7.5 kHz 75 kHz 60-90 kHz

Figure 3 – Signal processing chain for each channel of the FM modulator: stereo and non-stereo options

Here, the DSP-based system is required to and spectrally offset the baseband L-R signal A DSP Perspective
emulate the analog system. This is particular- component as well as the baseband SCA sig- As explained in the previous section, the
ly important because the acceptance test pro- nal component. The composite signal is then digital implementation of the modulator
cedure for the signals formed by the digital frequency modulated and up-converted to segment must mimic the performance
modulator chain is the procedure written for its appropriate RF center frequency. parameters of the legacy analog implemen-
the analog modulator chain. This modulation format is markedly dif- tation. This does not mean that the digital
Figure 3 shows a simplified block diagram ferent from the modulation format used in implementation must emulate the analog
of the analog processing chain for each FM the commercial FM band. There, the com- implementation. The DSP systems rule is
signal set. There are three input signals in patible stereo uses double side-band sup- not to emulate the analog process but rather
each set: L (left), R (right), and SCA. Also pressed carrier (DSB-SC) modulation for to return to first principles and avoid inher-
note that the modulator can operate in two the L-R and SCA signals and further con- iting legacy compromises. Although there
modes, stereo and non-stereo. The two tains a pilot signal to enable demodulation of are some processing blocks common to both
modes differ in filter bandwidths (14 kHz or the suppressed carrier signals. realizations, others are purely DSP related.
7.5 kHz) and center frequency of the two The composite signal is then FM mod- For example, the analog system uses a
VCOs (32 kHz and 80 kHz or 30 kHz and ulated to the RF band center. Remember conventional VCO (voltage controlled oscil-
75 kHz, respectively). not to confuse the FM modulation lator) to implement the two FM modulators
Of course, the digital modulator must described in this transceiver with the com- required for each signal set. The digital sys-
mimic both modulation modes. In this mod- mercial FM modulation scheme with tem uses complex baseband phase modula-
ulator, narrowband FM is used to modulate which you are familiar. tion of the up-sampled and digitally

18 DSP magazine April 2007


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integrated input signal to form the digital Note that interpolators are used through- three signals are subjected to three different
FM sequence. The block diagram of the out the modulation process. We do this to processing paths that have limited common-
DSP-based FM modulator is illustrated in permit signal processing at the lowest sample ality. Interestingly, only a single-channel
Figure 4. rate consistent with the signal bandwidth. processor was programmed into the system;
This process forms a complex baseband The interpolators are applied to the sampled this single processor is sequenced through
sequence whose phase derivative is propor- data signal at appropriate points in the pro- the 384 signals to be channelized.
tional to the input signal. The sample rate cessing flow to enable bandwidth expansion The stereo components are initially
of this sequence is raised by a second digi- in successive processing stages. processed by a butterfly to form the standard
tal interpolator and digitally heterodyned L+R and L-R components. The L-R and
to shift the baseband spectrum to the Single-Channel Processing Block SCA signals are encoded in dbx dynamic
desired center frequency. The complex Figure 5 is a block diagram of a single-chan- range enhancement filters. All three channels
exponentiation and the DDS are imple- nel processing block that handles a stereo sig- are then pre-emphasized by first-order
mented by two versions of the well-known nal set and an SCA signal. Each of the three lead/lag filters, with the L+R pre-emphasis
CORDIC (Coordinate Rotation Digital input signals is delivered to this block as 16- zero at 2.1 kHz and the L-R and SCA pre-
Computer) algorithm. bit-wide data at a 48-kHz sample rate. The emphasis zeros at 3.2 kHz. All three paths are

Q
v(n) = w( n)
d(n) s(n) p(n) w(n) P
P/Q y(n)
1-to-4
Accumulator exp(j 2π --) Arbitrary
Up-Sample
Re-Sample f
exp(j 2π c n)
fs
KOSC
fc
DDS
fs

Figure 4 – Signal flow diagram: DSP-based complex baseband FM modulator

IIR
Left (L+R) 48-to-293
75-μsec LFP
Arbitrary
Pre-Emph 14-kHz
Re-Sample
IIR IIR CORDIC IIR
48-to-293 Gain
dbx 50-μsec LFP DDSFM-MOD BPF
Arbitrary &
Encoder Pre-Emph 14-kHz 35-kHz
Re-Sample Up-Converter
Right (L-R)
Gain Gain
KACC 32 kHz KACC
IIR IIR CORDIC IIR
SCA 48-to-293 DDSFM-MOD
dbx 50-μsec LFP BPF
Arbitrary &
Encoder Pre-Emph 14-kHz 35-kHz
Re-Sample Up-Converter

Gain
KACC 32 kHz
Satellite Clock Domain Transceiver Clock Domain

Figure 5 – Block diagram of single-channel processing block: stereo and SCA signal

April 2007 DSP magazine 19


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128-Path Polyphase Filter


75.008 MHz

11 Taps per Path


128-Point FFT
Odd
256 Channels 1:2 Up-Sampler

Samples

256-Channel Adder
225.024 MHz

1-to-3
Quantize DAC
Up-Sample
Half Band Frequency Shift
128-Path Polyphase Filter

225.024 MHz
11 Taps per Path

DDS
128-Point FFT

50 MHz
Even
Samples

Figure 6 – Polyphase channelizer and final post-processing tasks to operate output DAC

filtered to limit their 3-dB bandwidth with output of the two paths performing the 200 of these channels are formed with
the L+R and L-R band edges at 14 kHz FM modulation and spectral translation. data streams obtained from the MP3
and with the SCA band edge at 7.5 kHz. An important design consideration was decoders. These baseband channels are
The L+R signal and the SCA signal are embedded in the 192:293 and 48:293 merged in a polyphase up-sampling
up-sampled 1-to-4 to 192 kHz by up-samplers. These re-samplers are arbi- channelizer. The channelizer raises the
polyphase FIR filters in preparation for trary interpolators that transfer data sam- sample rate by a factor of 1:256 from
the complex baseband FM modulators ples from the input satellite clock domain 293 kHz to 75.008 MHz. The two-sided
described in the previous section. The to the local transceiver clock domain. bandwidth of each composite baseband
outputs of the two baseband FM modula- The three signal paths are separately channel is approximately 180 kHz. The
tors are again filtered to control their 3-dB amplitude scaled to control their relative spacing between centers of the channel-
bandwidths, which have experienced spectral densities and are merged by addi- ized signal is 293 kHz.
bandwidth expansion caused by the non- tion. The summed signal is scaled once From the channel width and the
linear FM modulation. The L-R FM- again and delivered as one of 200 inputs channel spacing, we find that the transi-
modulated low-pass filter bandwidth is 35 to a 256-path polyphase channelizer that tion bandwidth of the prototype low-
kHz, while the SCA FM modulated low- performs the complex baseband channel- pass filter used in the channelizer is 113
pass filter bandwidth is 30 kHz. Both ization and raises the sample rate to kHz. To achieve 96-dB isolation between
FM-filtered signal components are up- 75.008 MHz. This final scaling is used to channels, the stop-band attenuation of
sampled 192:293 by polyphase FIR filters control the spectral densities of the sepa- the prototype filter has 96-dB out-of-
to an output sample rate of 293 kHz. In rate channels across the composite modu- band attenuation levels. Using standard
turn, the outputs of the interpolators are lated bandwidth. equations found in filter design texts, we
spectrally translated by an IQ heterodyne can estimate the length of the prototype
to form real signals at their design center Output Interpolator, low-pass filter that meets the specified
frequencies. The L-R is translated to 32 Channelizer, and Up-Converter sample rate, pass-band bandwidth, tran-
kHz and the SCA is translated to 80 kHz. We have examined the signal processing sition bandwidth, and out-of-band
The filtered L+R signal is up-sampled blocks required to implement a single attenuation levels. This length is approx-
48:293 in a polyphase FIR filter to 293 channel of composite baseband signal imately 2,896 taps. To better fit into the
kHz – the same sample rate formed at the with offset FM sub-carriers. A total of 256 paths of the polyphase partition, the

20 DSP magazine April 2007


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filter length is reduced slightly to 2,816 FFT and polyphase channelizer at a 75- processor. The processor could be the
taps. The polyphase partition forms 256 MHz output rate, and the final interpolator embedded PowerPC™ 405 hard IP
paths of 11 taps each. at a 225-MHz output rate. This impressive block, the MicroBlaze™ soft-processor
Figure 6 is a block diagram of the 256- body of processing employed less than 60% core, or a processor external to the FPGA.
path polyphase channelizer implemented of the FPGA resources. In the past, the Signum engineering
as a cascade of a 256-point fast Fourier team developed high-performance FPGA-
transform (FFT) and the polyphase parti- FPGA Design Flow based DSP systems using conventional
tion of the prototype low-pass filter. The We used the Xilinx System Generator for HDL-based design flows for synthesis and
output data rate of the polyphase filter is DSP model-based design flow to realize the simulation. In comparison, we estimate
75.008 MHz. This time series is resampled transceiver. This is a tool chain that extends that our System Generator-based design
in the final interpolator to 225 MHz. The The MathWorks’s Simulink framework flow compressed the development time to
up-sampled series is heterodyned to move with FPGA hardware-generation capabili- the final transceiver by a factor of roughly
the spectral center of complex baseband ties. Although Simulink has not tradition- 10x compared to HDL-based flows.

Figure 7 – Re-modulator board showing Xilinx Virtex-4 FPGA that implements 384 FM modulators
implemented on 192 modulator boards in the equipment bay shown in Figure 1.

channelized time series to approximately ally been associated with hardware design, Conclusion
50 MHz. The real valued offset series is we found that System Generator was an The transceiver hardware described here
finally re-quantized to 14 bits and delivered excellent vehicle for developing FPGAs. is already replacing the fielded legacy ana-
to the 225-MHz DAC. The output of this System Generator is a visual design envi- log system hardware. Because this hard-
DAC is passed through an analog smooth- ronment that allows you to work at a suit- ware is DSP-based, we can easily
ing filter to suppress the spectral remnants able level of abstraction from the target incorporate additional capabilities and
following the DAC’s sin(x)/x filtering. hardware and to use the same computation enhancements in the near future. Our
graph not only for simulation and verifica- next goal is to replace the analog legacy
FPGA Resources tion but for FPGA hardware implementa- FM receivers (that demodulate our
The Xilinx Virtex-4 XC4VSX55 FPGA con- tion. System Generator blocks are bit- and remodulated signal) with DSP-based sys-
tains a DSP cornucopia of 512 multiplier cycle-true behavioral models of FPGA tems with matching enhanced capabili-
accumulator slices (18 x 18) and 320 blocks intellectual property (IP) components, or ties. With inserted enhancements at both
of 18-Kb RAM operating at 500 MHz. The library elements. The library-based ends of the communication link, the
modulator board is shown in Figure 7. approach results in design cycle compres- service provider will be able to offer addi-
Remember, this board implements the func- sion, in addition to generating area-effi- tional revenue-generating communica-
tion and tasks of the 192 analog FM modu- cient high-performance circuits. tion services.
lators mounted in the bay shown in Figure 1. In addition to providing a natural For more information, contact Fred
The modulator implemented 200 sets of dbx development environment for develop- Harris at fred.harris@sdsu.edu. For Signum
encoders, pre-emphasis filters, multiple low- ing FPGA signal processing implementa- Concepts FPGA-based activity, contact
pass filters, FM modulators, multiple inter- tions, System Generator has a rich set of Wade Lowdermilk at wade.lowdermilk@
polators at 48-kHz input and 192-kHz features that support the development of signumconcepts.com. For X-Digital Systems
output rates, clock domain interpolators and heterogeneous applications comprising activity, contact Ian Lerner at ilerner@
re-samplers to 293 kHz, the final 256-point not only the FPGA element but a xdigital.com.

April 2007 DSP magazine 21