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International Conference on Innovative Mechanisms for Industry Applications

(ICIMIA 2017)

Design of 2T XOR Gate Based Full Adder


Using GDI Technique
1
KORRA RAVI KUMAR, 2 P.MAHIPAL REDDY, 3 M.SADANANDAM, 4 SANTHOSH KUMAR.A, 5 M.RAJU
Sree Chaitanya College of Engineering, Karimnagar, Telangana, India.
1 3
ravikumar.korra@gmail.co m ,2 mahipalred@gmail.co m, mittapallysadanandam@gmail.co m,
4 5
santhosh.allenki@gmail.com, m.raju2002@g mail.co m

Abstract: Full Adder is one of the fastest adder used in the Pass transistor logic (PTL) has few advantages over CMOS
complex data processing to perform fast arithmetic operations. technology. The lower interconnecting effect is just because of
The main aim of this paper is a design of 2T XOR gate based full a small area [2,3], high speed due to small node capacitances,
adder using GDI technique.2T XOR gate is an absolutely
low power consumption because of less number of transistors
necessary primitive in the design of full adder. Intension behind a
novel method of 2T XOR gate based Full adder design is to [4].But logic design in PTL also has threshold drop across
reduce power improve the speed with an optimized area by pass transistor results in reduced sink and source current
means of transistor count. GDI approach tend to provide the (drive current) leads to reduce the operating speed at low
optimized conditions, the novel method is then applied to Full supply voltages and high input voltage at the regenerative
adder design. The entire work is carried out in the 180nm inverters is not VDD [5]-[7]. Double threshold loss problem
technology of LTspice tool is used for time delay, Xilinx 14.7 IS E, encountered by the 10 transistors full adder[8], The design of
Basys3 Artix7 device is used for power analysis. The resulting low-power high-speed adder has become one of the most
analysis shows that the proposed method is better than
important and essential researches [9].because of PMOS
conventional CMOS .
transistor in the inverter is not fully off and hence static power
Keywords—GDI, CMOS, XOR, XILINX, ARTIX7, BASYS3 dissipation occurs. A Morgenshtein, A.Fish, and Israel
A.Wagner introduced a new method to get small area low
I. INTRODUCTION power consumption and high-speed for low power digital
Now a day’s electronics is characterized by so many combinational circuit design known as Gate Diffusion Input
factors, one of the main issues in very large scale integration [10].
in power consumption because of the complexity of the circuit
The aim of this work is to build a Full Adder circuit
increase transistor count on a chip. Concentration towards
with 2T XOR gates using GDI technique. This designing is
research in low power VLSI (Very large scale integration)has
carried out in 180nm technology. Section II presents an
increased with increase in transistor count on a chip. High
overview of basic GDI technology in Section III describes
power consumption leads to increase the temperature of the IC
about basic CMOS full adder. Section IV deals with proposed
and directly shows the effect on battery durability in portable
6T full adder design with 2T XOR gate using GDI technique.
devices. Three different types of power consumption are there
Section V shows the results and Discussion. Section VI is all
in COMS VLSI circuits of which the primary one is static
about conclusion.
power consumption is due to unwanted leakage current when
transistor is used in Off state, the second one is dynamic II. GATE DIFFUSION INPUT
power consumption is because of switching action of parasitic
components and the third one is short-circuited power Gate Diffusion Input – a new approach for low power
consumption due to current vary from VDD to VSS. digital combinational circuits this approach allows reducing
power consumptions, delay and area of the digital circuits to
Classical design of full adders normally used only maintain the low complexity of the logic design.
one logic style for the whole full adder design, standard static
CMOS, pass transistor logic and transmission gates are the GDI method employs a simple cell as shown in
most important logic styles in the conventional full adders [1]. Figure.1.[11] GDI cell has three input–G (Common gate input

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International Conference on Innovative Mechanisms for Industry Applications
(ICIMIA 2017)

of small nMOS and pMOS), P(input to the source/drain of builds with 2 Exclusive –OR gate and a 2 by 1 multiplexer. In
pMOS ) and N(input to the source/drain of nMOS).bulk this the sum is generated at the output of second XOR gate
terminal of both nMOS & pMOS is connected to N or P and the output carry is generated at multiplexer output as
respectively. Various inputs can be connected to P, G and N
shown in Figure.2.
terminals
IV. PROPOSED 6T FULL ADDER DESIGN

The performance of the full adder circuit can be


explained here as follows: The addition of two single bit
inputs A and B with input carry Cin gives the two single bit
outputs Sum and carry out Cout .

Where
Fig.1. Basic GDI cell
SUM A † B † Cin (1)
GDI technique consumes less silicon area compare to
other methods as it consists of less number of transistor count,
as the area is less the value of node capacitance is less [12]. COut A x B  Cin A † B (2)
For this reason the operating speed of GDI gate is high which
shows that GDI logic style is an efficient method of design. SUM X † Cin (3)
The threshold voltage depends on a source to bulk
voltage[13], the bulk terminal of nMOS and pMOS should be COut A† X (4)
connected to their diffusion to minimize the bulk effect,
variation in threshold due to change in VSB is called body Cin
SUM
effect. Body effect directly shows the impact of the threshold XOR

voltage when not connected to a source.


B
XOR
III. BASIC CMOS FULL ADDER A

Cout
MUX

Fig.3. Block diagram of full adder

T able.1. T ruth table for full adder


A B Cin SUM Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

Fig.2. CMOS full adder design 1 1 0 0 1


It is a combinational circuit with A, B and Cin as
1 1 1 1 1
inputs and SUM and Cout as output [14]. The full adder circuit

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International Conference on Innovative Mechanisms for Industry Applications
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Table.1. deals with the functional approach of full second XOR gate, input C in is connected to drain of M4,
adder. The standard way to build a full adder using XOR gates Cin _bar is connected to source of M3 and output of first XOR
and the multiplexer is as shown in Figure.3.The XOR gate and gate applied as input to the gate terminals of M3 and M4, the
multiplexer are two basic components in the design of full second XOR gate produces SUM as output.
adder circuit. Arithmetic and logical operations of the full
adder are completely based on XOR gate and multiplexer
blocks. The XOR gate design should have less number of
transistors for low power dissipation. The reason behind
adopting the multiplexer circuit in our proposed design is to
generate Cout . A transmission gate is used as multiplexer
because it speeds up the carry propagation and improves the
output voltage swing as level restoring circuit. The proposed
full adder circuit needs two XOR gates and one multiplexer,
requires only six transistors.

Fig.5. Proposed full adder design

Two AND gates and one OR gate of existing full


adder replaced with the multiplexer in proposed circuit. Here
output of first XOR gate is applied to the gate terminal of M5
and M6, input B is connected to drain of M6, input Cin is
Fig.4. 2T XOR gate connected to source of M5, multiplexer produces Cout.

Figure.4. is the design of XOR gate using GDI V. RESULT AND DISCUSSION
technique has two transistors pMOS and nMOS with A and B
inputs, when A, B both are at logic low pMOS is in ON state Table.2. shows that our proposed circuit gives
and nMOS is in OFF state so that the output is low. When improvement in area, power and delay analysis in contrast to
input A is low and B is high then pMOS off state and nMOS in other conventional technique. The area consideration shows
on state, so output is at high state, if A is high and B is low that the transistor count of proposed work greatly reduced
then pMOS on and nMOS off state so that the output is at compare to conventional CMOS technique [15], as transistor
high, when both inputs are high then output is at low, hence count reduces hardware complexity of the circuit decreases,
the above circuit acts as XOR gate. delay deceases leads to decrease in power consumption. Fig.6
shows the timing delay and power analysis which is tabulated
Figure.5. represents proposed full adder circuit with in table 2. In our proposed work power reduced by 44%, area
six transistors such as M1, M2, M3, M4, M5 and M6. M1 and reduced by 25%, time delay decreased by 53% compare to
M2 transistors act as first XOR gate, input A is connected to conventional CMOS technique. Time delay is calculated by
drain of M2, A_bar is connected to source of M1and B is using LTspice, area and power calculated by using Xilinx 14.7
connected at gate terminal of M1 and M2. M3and M4 acts as ISE tool by implementing on Basys-3 Artix7 devices.

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International Conference on Innovative Mechanisms for Industry Applications
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VI. CONCLUSION
From the above analysis it can be concluded that our
proposed full adder circuit has got better performance in case
of area, delay and power comparatively with conventional
CMOS full adder. It shows that GDI approach of full adder
design is better for complex data processing application.

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Fig.6. T ime delay for Full adder.
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