IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 22, NO.
4, APRIL 2012
A D-Band Cascode Amplifier With 24.3 dB Gain and
7.7 dBm Output Power in 0.13 m SiGe
BiCMOS Technology
Debin Hou, Student Member, IEEE, Yong-Zhong Xiong, Senior Member, IEEE,
Wang-Ling Goh, Senior Member, IEEE, Wei Hong, Fellow, IEEE, and Mohammad Madihian, Fellow, IEEE
Abstract—This letter describes a D-band 3-stage cascode ampli-
fier developed using the IHP 0.13 m SiGe BiCMOS technology.
The amplifier is implemented with low-loss transformer for
inter-stage matching and single-to-differential transformation.
The large-signal characteristics of the cascode HBT configuration
are used to optimize the bias condition for highest output power
and gain performance. A measured amplifier achieves a peak
power gain of 24.3 dB, with a 3 dB bandwidth of 20 GHz centered
at 130 GHz. The amplifier exhibits a saturated output power of
7.7 dBm and an output 1 dB gain compression point of 6 dBm
with a power consumption of 84 mW. The measured noise figure is
6.8 dB at 130 GHz and stays under 8 dB over the 3 dB bandwidth.
To the best of our knowledge, the proposed amplifier exhibits the
highest gain and output power among the silicon-based D-band
amplifiers reported so far.
Index Terms—Cascode, D-band amplifier, large-signal, mil-
limetre-wave, SiGe BiCMOS, transformer.
I. INTRODUCTION
M ILLIMETER-WAVE amplifiers operating above
100 GHz with high gain and output power are nec-
essary to ensure sufficient transmission range and sensitivity
in transceivers for high-data rate communication and imaging
applications [1]. In the D-band frequency range, previously re-
ported silicon-based amplifier had demonstrated output power
up to 6.3 dBm but relatively low gain of less than 10 dB using
single transistor topology [2]. A multi-stage cascode topology
was utilized in [3]–[5] to improve the gain performance to
21 dB but at the expense of a lower output power of around
Manuscript received November 15, 2011; revised January 24, 2012; accepted
February 02, 2012. Date of publication March 22, 2012; date of current
version April 11, 2012. This work was supported by A*STAR under Grant 102
129 0051 and National Basic Research Program of China (“973” Program,
2010CB327400).
D. Hou is with the State Key Lab. of Millimeter Waves, Southeast University,
Nanjing 210096, China and also with the Institute of Microelectronics, A*STAR
(Agency for Science, Technology and Research), Singapore 117685 (e-mail:
dbhou@emfield.org, weihong@seu.edu.cn).
Y.-Z. Xiong was with the Institute of Microelectronics, A*STAR, Singapore
117685. He is now with MicroArray Technologies Co., Ltd, Chengdu 610041,
China (e-mail: eyzxiong@ieee.org).
W.-L. Goh is with Nanyang Technological University, Singapore 639798
(e-mail: EWLGOH@ntu.edu.sg).
W. Hong is with the State Key Lab. of Millimeter Waves, Southeast Univer-
sity, Nanjing 210096, China
M. Madihian is with the Institute of Microelectronics, A*STAR, Singapore
117685. (e-mail: madihianm@ime.a-star.edu.sg).
Color versions of one or more of the figures in this letter are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LMWC.2012.2188624
1531-1309/$31.00 © 2012 IEEE
191
0 dBm caused by the inherent higher knee voltage
characteristics of the cascode structure that result in a smaller
output voltage swing compared to a single transistor amplifier
at the same supply voltage. In this letter, we have improved the
cascode circuit topology by separating the bias of the transistor
to address the existing drawback and optimize operating dc
points to ensure a high output power and high gain performance
through large-signal analysis. The corresponding three-stage
cascode amplifier implemented using a 0.13- m SiGe BiCMOS
technology exhibits a gain of 24.3 dB and an output power
of 7.7 dBm at 130 GHz, which are among the highest values
achieved from silicon-based D-band amplifiers reported to date.
II. CIRCUIT DESIGN
A. Amplifier Structure
Fig. 1 presents the schematic of our proposed three-stage
cascode amplifier, consisting of a single stage and two differ-
ential stages. The circuit is realized in an IHP 0.13 m SiGe
BiCMOS technology, featuring a of 240 GHz and an
of 290 GHz. SiGe HBTs of different sizes are deployed in each
stage to ensure low power consumption, without degrading the
output power and gain performance. The matching networks
are constructed using microstrip lines. The microstrip line is
implemented with top metal (TM2) as signal line and bottom
metal (M1) as ground with a separation of 9.83 m, as shown
in Fig. 2(a). The measured transmission loss is 1.6 dB/mm at
130 GHz. The amplifier input is matched for minimum noise
figure (NF) using an L-matching network. Also, a transmission
line inductor, (30 pH/60 m), between the emitter and ground
improves the input impedance matching and low frequency sta-
bility. To further increase the output power, a differential struc-
ture with stacked transformer is engaged in both the 2nd and
3rd stages, i.e., T1 for inter-stage matching and on-chip baluns
(B1 and B2) for signal division and combining. The proposed
stacked transformer and baluns are realized using the top two
metal layers (TM2 and TM1), and with floating lattice shields at
the bottom metal (M1), as illustrated in Fig. 2(b). This approach
ensures low loss (1 dB loss), wide-band frequency response,
compact size, and innate dc blocking. The cascode structure at
the 3rd stage facilitates an independent biasing for 6, to
assist in the optimization of the output power and gain.
B. Large-Signal Analysis of Cascode Structure
For optimum high power and high gain design, we inves-
tigated the large-signal properties of the cascode SiGe HBTs
192 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 22, NO. 4, APRIL 2012

Fig. 1. Schematic representation of the proposed three-stage cascode amplifier, where V = 0:9 V, V = 2 V, and V = 1:5 V.

Fig. 2. (a) Cross-sectional view of the metal layers in a 0.13 m SiGe BiCMOS
technology, and (b) the transformer with floating lattice shield used in the pro-
posed amplifier design.

Fig. 5. Output properties of the amplifier at 130 GHz, with V = 09 : V,

V =2 V and various V , from 1.2 to 2 V. The gain and the saturated output
power are obtained on the condition P = 028 dBm and P = 05 dBm,
respectively.

be seen, increases dramatically when shifts from 1.2 V

to 1.5 V, and stays at around 300 for higher than 1.5 V, and
this is where both and operate in the active region. Ac-
cordingly, to operate the amplifier to attain both the high output
power and high gain, an optimal bias of the cascode struc-
Fig. 3. DC I -V characteristics of the proposed cascode topology with bias ture will be 1.5 V.
V =15
: V and load line matching.
C. Implementation of Cascode Amplifier
Based on the large-signal analysis for the cascode structure,
the cascode amplifier’s power gain and saturated output power
at 130 GHz with different were simulated and are shown
in Fig. 5. The power gain response, which is in accordance with
the current gain seen in Fig. 4, reaches the peak value when
is around 1.5 V and remains unchanged at above 1.5 V.
Similarly, the output power attains a peak value of 8.5 dBm at
1.4 V and decreases gradually with . Consequently, the op-
timal bias region for high power gain and output power op-
Fig. 4. Cascode current gain  and V variation with V . eration is between 1.4 V to 1.6 V. Hence, we set V
with V and V to simulate for the small signal
under nominal supply voltage, , and different bias condition S-parameters of the amplifier shown in Fig. 6. The results indi-
. First, to operate the device under maximum frequency of cate a maximum power gain of 27 dB, with a 3 dB bandwidth
oscillation, , we set to 2 V, and , the base voltage of of 21.5 GHz centered at 130 GHz.
transistor , to 0.9 V as the quiescent point, which yields an
of 12 mA as the optimum collector current density (1.8 mA/ III. FABRICATION AND EXPERIMENTAL RESULTS
m) for maximum operating condition, as demonstrated in The proposed amplifier depicted in Fig. 7 is fabricated using
Fig. 3. Second, to avoid large signal distortion, the minimum the IHP 0.13 m SiGe BiCMOS process. The setup for the
collector voltage, , should be equal to and is called S-parameters measurement involves a vector network analyzer
the -point on the optimal matching load line, where the (VNA) and a D-band (110–170 GHz) VNA extender calibrated
peak is mA, and with a base current, , of with the on-wafer LRRM standards. As for the power charac-
80 A, as shown in Fig. 3. Fig. 4 illustrates both the current teristics test, the setup involves an R&S SMF 100-A signal gen-
gain, , and variation versus the . As can erator connected to a D-band quad-mixer extender as a signal
HOU et al.: D-BAND CASCODE AMPLIFIER WITH 24.3 DB GAIN AND 7.7 DBM OUTPUT POWER
Fig. 6. Simulated and measured S-parameters and NF of the amplifier, under
the bias conditions of: V =09
: V, V =2V, and V =15
: V.
Fig. 7. Microphotograph of proposed 3-stage cascode amplifier. The chip size
2
is 700 430 m including test pads.
Fig. 8. Measured P , gain and PAE at 130 GHz, under the bias conditions
of: V =09: V, V =2 V, and V =15 : V.
source, and a D-band power meter for collecting the output
signal. The noise figure was also measured with a D-band CW
noise source and a high sensitivity D-band spectrum analyzer
receiver. The measured noise figure error after calibration is
within 1 dB in the D-band frequency range. All results were
based on on-wafer measurement.
Measured output power and gain at 130 GHz as well as the
small signal S-parameters are, respectively, shown in Figs. 5 and
6. The measurement results exhibit the same trend as the simu-
lation but with some performance deteriorations due to the un-
derestimation of the resistive parasitic elements of the device
model at the millimeter-wave frequency range. The amplifier
exhibits a measured peak gain of 24.3 dB at 132.5 GHz, and
with a 3 dB bandwidth of 20 GHz from 123 to 143 GHz. In
the 3 dB bandwidth range, the input and output return losses
are better than 17 dB and 5 dB, respectively. The measured NF
is 6.8 dB at 130 GHz and less than 8 dB over the 3 dB band-
width. Fig. 8 presents the power sweep results at 130 GHz. The
power compression starts at output of 6 dBm, with sat-
urated output power of 7.7 dBm. The circuit draws a total
current of 42 mA at 2 V supply. The measured peak power added
193
TABLE I
COMPARISON OF D-BAND ON-CHIP AMPLIFIERS
efficiency (PAE) is noted to be 6.8% when the input power
is of dBm.
Table I summarizes the performance of the recently published
D-band on-chip amplifiers with different device technologies.
Using silicon-based technologies, the cascode topology demon-
strates a higher power gain but a lower output power perfor-
mance when compared to the common emitter or common col-
lector topology. However, by optimizing the bias conditions and
employing low-loss transformer and also balun matching, the
current work has achieved a power gain of 24.3 dB and an output
power of 7.7 dBm, with comparable NF and bandwidth at a rela-
tively low supply voltage of 2 V. Compared to compound semi-
conductor amplifier [6], the silicon-based amplifier has better
gain performance, necessitates lesser power consumption, but
has slightly lower output power.
IV. CONCLUSION
This letter describes a 3-stage D-band cascode amplifier using
the 0.13 m SiGe BiCMOS process. Through large signal anal-
ysis of the core cascade topology, the bias conditions were opti-
mized to realize an amplifier that provides high power gain and
high output power. The developed amplifier can be used in high
data rate wireless communication and imaging applications that
are over 100 GHz.
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