How I Learned to Stop Worrying and Love Flash Endurance
Vidyabhushan Mohan, Taniya Siddiqua, Sudhanva Gurumurthi, Mircea R. Stan†
Dept. of Computer Science, † Dept. of Electrical and Computer Engg., University of Virginia
{vm9u,taniya,gurumurthi,mircea}@virginia.edu
Abstract
Flash memory in Solid-State Disks (SSDs) has gained
tremendous popularity in recent years. The performance
and power benefits of SSDs are especially attractive for
use in data centers, whose workloads are I/O intensive.
However, the apparent limited write-endurance of flash
memory has posed an impediment to the wide deploy-
ment of SSDs in data centers. Prior architecture and sys-
tem level studies of flash memory have used simplistic
endurance estimates derived from datasheets to highlight
these concerns. In this paper, we model the physical pro-
cesses that affect endurance, which include both stresses
to the memory cells as well as a recovery process. Using
this model, we show that the recovery process, which
the prior studies did not consider, significantly boosts
flash endurance. Using a set of real enterprise workloads,
we show that this recovery process allows for orders of
magnitude higher number of writes and erases than those
given in datasheets. Our results indicate that SSDs that
use standard wear-leveling techniques are much more
resilient under realistic operating conditions than previ-
ously assumed and serve to explain some trends observed
in recent flash measurement studies.
1 Introduction
Flash memory has gained tremendous popularity in re-
cent years. Although initially used only in mobile de-
vices, the drop in the price of NAND flash memory has
paved the way for its use in mass storage devices as well,
in the form of Solid State Disks (SSDs). SSDs offer sev-
eral advantages over Hard Disk Drives (HDDs) such as
lower power, higher I/O performance (especially for ran-
dom I/O), and greater ruggedness.
Despite these benefits, one of the main impediments to
the wide adoption of SSDs in servers has been its appar-
ent limited write endurance. Flash memory blocks can
wear out after a certain number of write (program) and
erase operations. Manufacturer datasheets quote values
that range from 10,000-100,000 program/erase (P/E) cy-
cles for NAND flash endurance. Architecture and sys-
tems papers that explore the use of flash memory use
these values to estimate endurance [1]. However, at the
physical level, endurance is a more complex process, in-
volving stresses due to charge trapping in the tunnel ox-
ide of the floating gate transistors induced by P/E opera-
tions, but also a recovery process that detraps the charge
and partially heals the devices [18, 11]. By modeling
both stress and recovery, we can get deeper insights into
the endurance characteristics of flash and make a more
accurate assessment of SSD endurance in enterprise stor-
age systems. Recent papers on NAND flash chip mea-
surements provide evidence that endurance is higher than
the values reported in datasheets [6, 2], which further
motivates studying this phenomenon in more detail.
In this paper, we make the following contributions:
• We develop an analytical endurance model for
NAND flash memory suitable for use in architec-
ture and system design research.
• We use this model to quantify the impact of charge
trapping and detrapping for both single-level cell
(SLC) and multi-level cell (MLC) NAND flash.
• We study the endurance of an enterprise-class SSD
when exercised by real enterprise workloads. We
show that, due to charge detrapping, NAND flash
that uses standard wear-leveling techniques can sup-
port two orders of magnitude higher number of P/E
cycles than those given in datasheets. These results
indicate that SSDs can be safely deployed in data
centers without endurance concerns and explains
the reason behind some surprising observations in
recent flash measurement studies [6, 2].
The organization of the rest of the paper is as follows.
The next section explains flash memory operation and
how these operations affect endurance. We then present
our analytical endurance model in Section 3 and the im-
pact of charge detrapping is quantified in Section 4. Sec-
tion 5 describes the experimental methodology for the
SSD-level endurance experiments and the results from
these experiments are given in Section 6. Finally, Sec-
tion 7 explains the future work and concludes the paper.
2 Flash Memory Operation and Flash Re-
liability
This section provides an overview of how NAND flash
memory operates and explains how these operations af-
fect flash endurance. A detailed discussion on flash
memory at the circuit level is given in [3] and [1] de-
scribes the architecture of flash based SSDs. Flash is a
type of EEPROM (Electrically Erasable Programmable
Read-Only Memory) which supports three basic opera-
tions: read, program (write), and erase. A flash mem-
ory chip consists of the flash memory array and addi-
tional peripheral circuitry to perform operations. The
flash memory array consists of Floating Gate Transis-
tors (FGTs), which act as memory cells (in this paper,
the terms “memory cell” and “FGT” refer to the same
physical entity and are used interchangeably). The FGT
is similar to a regular MOS transistor except for an addi-
tional floating gate between the channel and the control
gate. This floating gate is isolated from the rest of the
device by dielectric (oxide). This helps retain charges on
the floating gate for an extended period of time (on the
order of years), hence providing non-volatility. Adding
or removing charges to/from the floating gate causes a
shift in the threshold voltage of the FGT and this shift is
sensed during read. The memory array is partitioned into
blocks that are, in turn, subdivided into pages. A page is
the smallest granularity at which the read and program
operations are performed. NAND flash does not support
in-place writes and hence an erase operation is neces-
sary before reprogramming the page. Such space man-
agement tasks within a SSD are performed by a Flash
Translation Layer(FTL).
These program and erase operations are stress events
that have a detrimental impact on the reliability of flash
memory as they affect both retention and endurance. The
typical data retention time for flash memory is 10-20
years [9]. However, as a flash memory cell is repeatedly
programmed and erased, the oxide layer becomes weak
which leads to an increase in the Stress Induced Leakage
Current (SILC) of the memory cell, thus affecting data
retention. On the other hand, endurance is a measure of
the number of P/E cycles that a flash memory cell can
tolerate while preserving the integrity of the stored data,
and is a function of the charge trapping characteristics of
the oxide [18, 11]. Every stress event increases the like-
lihood of charges getting trapped in the oxide, which can
lead to an undesirable increase in the threshold voltage of
the memory cell. If a sufficiently high number of charges
get trapped in the oxide, it will no longer be possible to
reliably read the cell.
Although a memory cell that undergoes a large num-
ber of stress events will have more charges trapped in
its oxide, several transistor-level studies of NAND-flash
memory have shown that it is possible to detrap (i.e., re-
move) some of the charges from the tunnel oxide under
certain conditions [18, 11, 17]. Beneficial conditions for
detrapping include higher external temperatures and qui-
escent periods between successive stress events. Further-
more, the measurement studies indicate that introducing
a quiescent period to allow detrapping can be applied at
temperatures as low as 25◦ C, which is the typical exter-
nal ambient temperature of a disk [7]. Since the quies-
cent periods help improve endurance, we refer to them as
recovery periods.
3 Flash Endurance Model
In order to analyze how stress events and recovery peri-
ods impact the endurance of NAND flash memory under
various usage scenarios, we have developed an analytical
model that captures how these two parameters affect the
threshold voltage of memory cells. This model is con-
structed by synthesizing the results from device physics
papers on NAND flash memory cells [18, 11, 19]. These
papers provide information about how the parameters are
related and also provide memory cell level measurements
of stresses and recovery for a range of values.
The model consists of two parts - one for stresses and
the other for recovery. The first part of the model gives
the relationship between the increase in threshold voltage
due to charge trapping (δVth,s ) and the number of stress
events on the oxide. The second part gives the relation-
ship between the threshold voltage shift due to recovery
(δVth,r ), the amount of trapped charges in the oxide due
to stress calculated in the first part (δVth,s ), and the re-
covery period (t). Using these two parts, we calculate the
effective increase in threshold voltage of a memory cell
due to trapped charges (δVth ) after a stress event and a
subsequent recovery period. We now explain these two
components of the model in more detail.
3.1 The Stress Model
The threshold voltage of a memory cell increases due to
charge trapping with the number of stress events (pro-
gram or erase cycles) [19]. There are two types of traps
that form in the oxide - interface traps and bulk traps -
which contribute to the increase in the threshold voltage.
It has been shown that both types of traps have a power-
law relation to the number of P/E cycles on the memory
cell as [19]:
δNit = A ∗ cycle0.62
δNot = B ∗ cycle0.30
where A and B are constants, cycle is the number of
program or erase cycles on the cell, and the terms δNit
and δNot are the interface and bulk trap densities respec-
tively. In addition to providing this power-law relation-
ship, [19] also provides empirical data on how δNit and
δNot vary with cycle. We calculated the values of con-
stants A and B to be 0.08 and 5 respectively for the sub-
90nm process technology from this empirical data. Simi-
lar device characterization data can be used for other pro-
cess technologies in our model to estimate endurance.
The total threshold voltage increase due to trapping is
divided into interface trap voltage shift (δVit ) and bulk
trap voltage shift (δVot ). Park et al. [14] give the rela-
tionship between δVit and δNit and between δVot and
δNot to be:
δNit ∗ q
δVit = (1)
Cox
δNot ∗ q
δVot = (2)
Cox
where q is electron charge (1.6 × 10−19 Coulombs) and
Cox is the capacitance of the oxide. The value of Cox
depends on the feature size of the NAND flash cell.
Hence the increase in threshold voltage of the memory
cell due to trapped charges, δVth,s , is given by:
δVth,s = δVit + δVot (3)
3.2 The Recovery Model
According to Yamada et al. [18], the threshold voltage
shift due to detrapping depends on the recovery period
and the amount of charge trapped in the oxide. This re-
lationship is given by:
t
δVth,r = cvt ∗ ln( ) (4)
t0
where t is the recovery period between successive stress
events to the same cell (in seconds), t0 is 1sec and cvt de-
pends on the amount of trapped charge (Q) present in the
oxide. The value of the recovery period, t, is assumed to
be finite and greater than one second. We conservatively
assume that no charge detrapping occurs for recovery pe-
riods less than one second. Yamada et al. also show that
cvt has a logarithmic dependence on Q [18]. Since Q
is directly proportional to the stress voltage, δVth,s , cvt
also has a logarithmic dependence on δVth,s . Yamada et
al. provides empirical plots of how cvt varies with δVth,s
[18] . Using these plots, we get:
δVth,s
cvt = ln( ) (5)
V0
The unit of cvt is in mV and V0 is 1mV .
Combining equations (4) and (5), the change in the
threshold voltage shift due to recovery, δVth,pr is given
by:
δVth,s t related failure and understand how the duration of the
δVth,pr = ln( ) ∗ ln( ) (6)
V0 t0
where δVth,s is given by equation (3). Since the physical
process of recovery is not perfect, we introduce a term K
which denotes the efficiency of recovery process. Dis-
cussions with the industry [12] indicate that K does not
exceed 60%.Hence, equation (6) is modified as:
δVth,pr if δVth,pr < K * δVth,s
δVth,r =
K ∗ δVth,s otherwise
(7)
The effective increase in the threshold voltage due to
trapped charges after stress and recovery, δVth , is given
by:
δVth = δVth,s − δVth,r (8)
Equations (3) and (7) can be used to estimate the en-
durance of a NAND flash memory cell based on the num-
ber of stress events (P/E cycles) and the recovery periods
that the cell experiences. The stress events and recovery
periods for a workload can be tracked using an storage
system simulator such as Disksim [5]. While the model
captures the impact of stress and recovery on a single
memory cell, we track stress events due to program and
erase operations at the granularity of a page and block
respectively. Also one can use the methodology given
above for both SLC and MLC by varying the maximum
allowed threshold voltage shift.
3.3 Limitations of the Model
Currently, the model has two limitations:
• The model does not capture the impact of temper-
ature on stress and recovery. The constants in our
model are estimated from published datapoints for
25◦ C, which is approximately the external ambient
temperature of a disk drive in a server with a well-
designed cooling system [7].
• If the memory cell is used in MLC mode, program-
ming each n-bit value requires a different amount of
time [3] and hence the duration of the stress events
would be different for different bit values. More-
over, the amount of charge that is trapped in the ox-
ide also depends on the bits to be stored in the cell.
Currently, the model does not account for these vari-
ations and estimates the impact of stress and recov-
ery in a way that is agnostic to the actual bits stored
in the cells.
Despite these limitations, the model captures the pri-
mary effects of charge trapping and detrapping on the en-
durance of NAND flash and is suitable for use in storage
system simulations. This model can be used by system
architects to estimate how a particular workload would
affect the endurance characteristics of an SSD prior to
deployment and configure their storage system accord-
ingly.
4 Impact of Charge Detrapping on SSD
Endurance and Model Validation
Having derived a model for the threshold voltage shift
due to stress and recovery, we now analyze the impact
of charge detrapping on flash memory cells over differ-
ent timescales. The goal of this analysis is to ascertain
the extent to which charge detrapping can improve the
reliability of flash memory cells by delaying endurance
quiescent period affects the extent of the recovery.
Before we begin the analysis, we first need to precisely
define what “failure” means with respect to endurance.
The data stored in a flash memory cell is identified by a
specific voltage level. An n-bit MLC has 2n distinct volt-
age levels, each of which corresponds to an n-bit value
(an SLC flash cell is merely the case where n=1, which
corresponds to two voltage levels - one for a digital “0”
and the other for a “1”). Let ∆Vth,spread be the thresh-
old voltage range for a single voltage level in a memory
cell and ∆Vth be the difference in voltage between ad-
jacent levels. This is illustrated in Figure 1 for n = 2
(2-bit MLC). When the charges trapped in the oxide re-
sult in a threshold voltage increase of ∆Vth or higher, it
will no longer be possible to clearly distinguish between
different voltage levels. As a consequence, it will not
be possible to reliably read from or write to the mem-
ory cell. We define this situation as a failure. We define
the endurance limit as the total number of P/E cycles be-
fore this condition occurs. Once the endurance limit is
reached, a page is considered to have failed and is no
longer usable. Manufacturer datasheets specify an en-
durance limit of 10K and 100K P/E cycles for MLC and
SLC chips respectively. However, these values specify
the minimum number of P/E cycles that the chip is ex-
pected to tolerate before failure, tested under high stress
conditions where the flash cells are continuously erased
and rewritten with little or no recovery time between suc-
cessive stress events [17]. There is anecdotal evidence
in recently published papers on measurements of NAND
flash chips [6, 2], that, in the common case, when there
are recovery periods between the stress events, the en-
durance of flash is higher than the values specified in
datasheets.
Figure 1: Threshold voltage distribution for a 2-bit MLC
In Figure 2, we plot the change in δVth with the num-
ber of P/E cycles, over a number of timescales for the
recovery period, for the sub-90nm process technology.
We consider the case where there is no recovery between
successive stress events, which is how the datasheet val-
ues are computed, and also cases where the recovery
time is varied from 10 seconds to over 2 days. To il-
lustrate how these curves translate to endurance, we plot
the ∆Vth for SLC and 2-bit MLC flash. These values
are shown as horizontal lines in the graph and are ob-
tained from threshold voltage distributions of prototype
NAND flash memory chips published in the literature.
2-bit MLC devices have ∆Vth values that are approxi-
mately equal to ∆Vth,spread and have been shown to vary
from 0.6V to 0.7V [4]. We assume ∆Vth to be equal to
∆Vth,spread for SLC devices as well. The ∆Vth,spread
of SLC has been reported to vary from 1.4V to 2.0V
[13, 10]. Based on this data, we assume the ∆Vth of
SLC to be 1.7V and 2-bit MLC to be 0.65V. The por-
tions of the curves below the horizontal lines correspond MSNTM (MSNFS). Each workload consists of several
to failure-free operation of the cell. The number of P/E sub-traces, each of which correspond to the I/O activ-
cycles attainable for each recovery period and the im- ity during a specific interval of time (e.g., an hour) on a
provement in endurance over the case where there is no typical day, and the collection of these sub-traces span
detrapping between successive stresses is given in Table at least one full day. We use all the sub-traces of each
1 (for clarity, in the figure we omit a few of the datapoints workload in the simulation to characterize the variations
given in the table). in the I/O behavior and their impact on the SSD over a
δVth vs Recovery Period between P/E cycles one-day period.
3.5
No Recovery
Endurance Metric: We report endurance in terms of
Recovery Period = 10s
Recovery Period = 50s
Recovery Period = 100s
the number of P/E cycles. Since different blocks may
3
Recovery Period = 1000s
Recovery Period = 5000s
undergo a different number of P/E cycles based on the
2.5
Recovery Period = 10000s
Recovery Period = 15000s workload and FTL behavior, we report the average num-
Recovery Period = 1 day
Recovery Period = 2 days ber of P/E cycles and the minimum and maximum val-
ues observed across all the blocks. We report endurance
δVth (V)

2
SLC, ∆Vth = 1.7V at the end of 5 years of activity. This 5-year service life
1.5 allows us to examine the impact of P/E cycles on en-
durance well before retention related reliability problems
1 arise (the retention period of flash is 10-20 years [9]).
2-MLC, ∆Vth = 0.65V
Estimating Endurance Over the Service Life: Since
0.5
the service life spans multiple years whereas the traces
0
record only a single day of activity, we need a way of
10 100 1000 10000 100000 1e+06 1e+07 1e+08 estimating the activity on the SSD over this long time
P/E Cycles
period. Since each trace represents the I/O activity over
Figure 2: Increase in δVth with P/E cycles for different the course of a typical day, one approach could be to re-
recovery periods. peatedly replay the trace in Disksim and simulate 5 years
Recovery SLC, ∆Vth = 1.7V 2-bit MLC, ∆Vth = 0.65V
worth of activity. However, this approach would require
Period P/E Cycles Endurance P/E Cycles Endurance excessively long simulation times. We instead use a sta-
Increase Increase tistical approach to estimate the I/O activity on the SSD.
No recovery 107535 1x 10652 1x In order to estimate endurance, we need to capture two
10 seconds 153186 1.4x 13749 1.3x aspects of stress behavior: (1) the distribution of stress
50 seconds 1028724 9.6x 52444 4.9x
100 seconds 1837530 17.7x 99913 9.3x events across various pages and blocks in the SSD (spa-
1000 seconds 6214983 57.8x 403082 37.8x tial behavior), and (2) the distribution of the recovery
5000 seconds 11093823 103x 780723 73.3x periods to individual pages and blocks (temporal behav-
10000 seconds 13753999 127x 990014 92.9x ior). To determine these distributions, we collect an out-
15000 seconds 15497892 144x 1129379 106x put trace over the course of a Disksim simulation that
1 day 24274492 225x 1879352 176x
2 days 28487539 264x 2247910 211x
records when a particular page or block within a certain
flash chip is programmed or erased. We collect one such
Table 1: Endurance limits with charge detrapping. output trace for each sub-trace,which allows us to cap-
We can see that, when there are no recovery periods, ture any phase behavior within a workload. From this
the P/E cycles for the SLC and MLC datapoints approx- output trace, we characterize the spatial behavior of the
imately match the values given in datasheets (100K and workload by creating a histogram of the stresses to the
10K P/E cycles respectively), which concurs with the ex- different flash chips in the SSD to determine the fre-
pected behavior. We can also see that a recovery period quency at which pages/blocks within a particular chip are
between successive P/E cycles can significantly boost en- stressed. Since wear-leveling operations are performed
durance, which concurs with recent flash chip measure- within each flash chip in an SSD [1] we use a uniform
ment studies [6, 2]. A recovery period of a few hours distribution to model the pattern of stresses within a chip.
provides two orders of magnitude improvement. How- We characterize the temporal behavior of the workload
ever, as the recovery periods increase beyond a day, we by creating a histogram of the recovery periods of all
start getting diminishing endurance benefits. the pages within the SSD. Using these statistical distri-
The Role of ECC: It is important to note that charge de- butions of the spatial and temporal characteristics of a
trapping does not preclude the use of ECC. ECC is still workload’s stress behavior on the SSD, we extrapolate
required to handle bit errors that happen due to disturb the stress behavior over the service life of 5 years.
events and hence complements detrapping to boost relia- 6 Results
bility. The number of P/E cycles over the 5-year service life of
5 Experimental Methodology the SSD for each workload is given in Figure 3(a). Each
bar gives the average number of P/E cycles across all the
Simulator and Workloads: We use the Disksim SSD SSD blocks while the error-bar shows the smallest and
extension [1] that facilitates studying a variety of SSD largest number of P/E cycles observed across the blocks.
designs. We simulate a 32GB SSD composed of 8 4GB We can see that there is significant variation in terms of
SLC NAND flash chips, similar to enterprise-class SSDs the number of P/E cycles that blocks experience across
currently available [8]. the different workloads over the SSD service life. The
Our workloads consist of block-level I/O traces col- RAD and EXCH workloads impose fewer stresses on
lected from various production systems within Microsoft the blocks whereas LM and MSNFS impose far greater
[16, 15]. We evaluate four workloads: Live MapsTM number of stresses. The change in δVth for the block
(LM), ExchangeTM(EXCH), RADIUSTM (RAD), and that experienced the largest number of P/E cycles for

each workload is given in Figure 3(b). We observe that
across all the workloads, the increase in δVth over the
5-year period is well below the SLC ∆Vth of 1.7V. This
is true even for LM and MSNFS whose P/E cycles are
close to or greater than the datasheet specified endurance
limit of 100K P/E cycles. This is due to detrapping dur-
ing the recovery periods between stress events. We can
also observe that, although the number of P/E cycles for
the most heavily stressed block in EXCH is significantly
lower than that in MSNFS, the δVth of MSNFS is only
slightly higher than that of EXCH. This is because the
relationship between δVth and the number of P/E cycles
is not linear, as discussed in Section 3.
P/E cycles over a 5 year period (in thousands)
Number of P/E cycles per workload for a 5 year period
160
140
120
100
80
60
40
20
0
LM RAD EXCH
Workloads
(a) P/E cycles experienced over the service life.
The error-bars correspond to the smallest and largest
number of cycles for a block in the SSD.
Change in δVth over a 5 year period for different workloads
0.07
0.06
0.05
δVth (V)
0.04
0.03
0.02
0.01
0
LM RAD
Workloads
(b) Change in δVth for the block with the
highest P/E cycles. ∆Vth =1.7V for SLC Flash.
Figure 3: Endurance results for enterprise workloads.
The distribution of the recovery periods of the SSD
blocks for the workloads over the service life is given in
Table 2. We can see that most, if not all, SSD blocks
in all four workloads experience recovery periods in the
order of thousands of seconds. As Table 1 indicates, re-
covery periods of such durations can significantly boost
endurance, allowing the blocks to undergo several mil-
lions of P/E cycles before reaching the endurance limit.
The amount of time required for reaching the endurance
limit is much longer than the NAND flash retention pe-
riod. Therefore, endurance is not a major flash reliability
concern under realistic data center usage scenarios and a
much wider array of I/O intensive applications can lever-
age the performance and power benefits of flash-based
SSDs than previously assumed.
Benchmarks Recovery Period (seconds)
[1k-5k) [5k-10k) [10k-15k) [15k-20k)
LM 100 0 0 0
RAD 0.001 0.0023 99.9957 0.001
EXCH 0.002 99.857 0.141 0
MSNFS 100 0 0 0
Table 2: Recovery time distributions. [X, y) indicates
recovery periods of duration t where X ≤ t < y.
7 Future Work
While this work has focused on one aspect of flash mem-
ory reliability, namely endurance, we are also trying to
answer other questions related to flash memory reliabil-
ity. Our immediate focus is to validate our model with
real chip measurements. We are in the process of build-
ing a test board for this validation. As mentioned in Sec-
tion 3.3, our model does not capture the impact of tem-
perature on stress and recovery. We plan to model the
impact of this parameter in the future. Another aspect
of reliability we plan to model is Bit Error Rate (BER).
Prior studies have shown that BERs depend on the age
of a flash chip [6]. Modeling the relation between the
age of a flash chip and BERs will provide insights into
the strength of ECC required for correcting such errors.
MSNFS We also plan to model SILC to factor-in retention. Over-
all, modeling these phenomena provides a comprehen-
sive analysis of NAND flash reliability.
8 Acknowledgments
We thank Neal R. Mielke (Intel), Sriram Sankar (Mi-
crosoft), Steve Schlosser (our shepherd), and the anony-
mous reviewers for their valuable inputs. This research
has been supported in part by NSF CAREER Award
CCF-0643925, NSF grant CNS-0551630, and gifts from
Google and HP.
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