Diodes

Lesson #6
Chapter 3

BME 372 Electronics I – 180

J.Schesser
 Diodes
• Typical Diode VI Characteristics
– Forward Bias Region
id
– Reverse Bias Region
– Reverse Breakdown Region + vd -
– Forward bias Threshold 5
id
4

1
vd
0
-7 -5 -3 -1 1 3 5 7
-1
Reverse -2
breakdown Reverse bias Forward bias region
-3
region region
-4

-5

VI stands for Voltage Current

BME 372 Electronics I – 181
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 Zener Diodes

• Operated in the breakdown region.

• Used for maintain a constant output voltage

BME 372 Electronics I – 182

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 Load Line Analysis

• Let’s see how to use a diode in a circuit.

R Load Line
39
i D  amps
35
+ + 31

VSS iD vD 27
23

-- -- 19

15

11

• Use KVL for this circuit 3

-1
-0. -0. -0. 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8

Vss = RiD + vD
3 2 1
v D volts

• This equation is plotted on the same graph as

the diode VI characteristics.
BME 372 Electronics I – 183
J.Schesser
 Load Line Analysis
i D  amps Vss = RiD + vD
39 Operating Point Vss =1.6V, R=50kΩ
35
Q-point
vD=0; 31
Load Line
iD= Vss / R 27 Highest Voltage
23
=32amps 19 vD=Vss
Highest Current 15 =1.6V;
11
7
iD=0
3

-1
-0. -0. -0. 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
3 2 1
BME 372 Electronics I – 184
v D volts
J.Schesser
 Ideal Diode

• Basically, a switch
– Forward Bias: any current allowed, diode on
– Reverse Bias: zero current, diode off
– No reverse breakdown region i
5

4
d

2 Diode on
Diode off 1
vd
0
-7 -5 -3 -1 1 3 5 7
-1

-2

-3

-4

-5

BME 372 Electronics I – 185

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 How do we Analysis a Circuit with an Ideal
Diode
• For a real diode we use load line (graphical analysis)
• For an ideal diode, we use a deductive method:
1. Assume a set of states for the diodes
2. Solve the circuit to find the currents, iD, of diodes
assumed to ON and the voltages, vD, of the diodes
assume to be OFF
3. Check to see if iD is positive for all diodes assumed to
be ON and vD is negative for all diodes assumed to be
OFF
4. If this is true, then the solution is complete; otherwise
return to step 1 by assuming a different set of states
for the diodes.
BME 372 Electronics I – 186
J.Schesser
 Example
4k D1 D2

+ +
6k 3V
10V
-- --

1. Assume D1 OFF and D2 ON

D2 2. Solve the circuit to find the currents, iD, of
D1
4k iD2 diodes assumed to ON and the voltages, vD,
+ vD1 -- of the diodes assume to be OFF
+ 6k
+ iD2 = 3/6k = 0.5mA OK POSITIVE
3V
10V vD1 = 10 - 3 = 7 V NOT OK SHOULD BE
-- --
NEGATIVE
3. NEED TO START OVER WITH
ANOTHER ASSUMPTION

BME 372 Electronics I – 187

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 Example
4k D1 D2

+ +
6k 3V
10V
-- --

1. Assume D1 ON and D2 OFF

D2 2. Solve the circuit to find the currents, iD, of
D1
4k
iD1 diodes assumed to ON and the voltages, vD,
-- vD2 + of the diodes assume to be OFF
+ 6k
+ iD1 = 10/10k = 1mA OK POSITIVE
3V
10V vD2 = 3 - 6 = -3 V OK NEGATIVE
-- --
3. SOLUTION FOUND!!!!

BME 372 Electronics I – 188

J.Schesser
 How Do We Use Diodes
• Rectifier circuits
– Half-wave: only one (positive or negative) side of a
waveform is passed
– Full-wave: waveform is made single sided
• Wave Shaping
– Clipping Circuits: waveforms are limited in amplitude
– Clamping Circuits: the extreme values of a waveform is
clamped to a set value
• Logic Circuits
– AND and OR gates
• Voltage Regulators

BME 372 Electronics I – 189

J.Schesser
 Rectifier Circuits

• Half Wave Rectifier 1.5

Vin(t) = Vm sin(ωt) 0.5

0
0 5 10 15 20 25 30
-0.5

-1

-1.5

1.5
+ +
Vin(t) -- RL vo
1

0.5
-- 0
0 5 10 15 20 25 30
-0.5

-1

-1.5

BME 372 Electronics I – 190

J.Schesser
 Rectifier Circuits

• Half Wave Rectifier 1.5

with a smoothing 0.5

Capacitor
0
0 5 10 15 20 25 30
-0.5

• Peak Detector
-1

-1.5

• Envelop Detector 1.5

0.5

0
+ + 0 5 10 15 20 25 30
Vin(t) -- vo
-0.5

-1
--
-1.5

BME 372 Electronics I – 191

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 Rectifier Circuits

• Full Wave Rectifier 1.5

Vin(t) = Vm sin(ωt) 0.5

0
0 5 10 15 20 25 30
-0.5

-1

-1.5

1.5
+ +
Vin(t) -- vo
1

0.5
--
0
0 5 10 15 20 25 30
-0.5

-1

-1.5

BME 372 Electronics I – RL

192
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 Wave Shaping Circuits

• Clipper Circuits 20

10

Vin(t) = Vm sin(ωt) 0
0 5 10 15 20
R
-10
-
V2
+
-20
D1
Vin(t)
+
+ vo
-- +
20
V1 D2
- -- 10

vo 0
0 5 10 15 20
V1 D1 is ON -10

vin -20
D1 & D2 are OFF

BME 372 Electronics I – 193

D2 is ON V2
J.Schesser
 Clamping Circuit
Clamping Circuit Vin
15 Capacitor
10 Vout

• Clamping Circuits 5

Vin(t) = Vm sin(ωt) ‐5
0 5 10 15 20 25

‐10

C ‐15

‐20

‐25
D1 + Vo Time (seconds)
+
Vin(t) --
- • Note at t = 0, the voltage across the
capacitor is zero and when the diode is
forward biased, the capacitor charges
up to Vm during the time the diode
conducts which is when Vin(t) > 0
Vo(t) = vd = Vin(t) – VC
• Thereafter the diode remains reverse
Note VC charges to VM biased since vd = Vm sin(ωt) – Vm will
never be positive and the capacitor
Vo(t) = vd = Vm sin(ωt) – Vm can’t discharge and Vo is always < 0
BME 372 Electronics I – 194
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 Wave Shaping Circuits
Clamping Circuit Vin+VI

• Clamping Circuits
20 Capacitor
15 Vdiode

Vin(t) = Vm sin(ωt)
10 Vout
5
0
0 5 10 15 20 25
‐5
‐10
‐15
+
+
D1 ‐20

Vin(t) - Vo
--
V1
-
+ •
Vo(t) = Vin(t) – VC
vd = Vin(t) – VC+V1
Note VC charges to VM +V1
Vo(t) = Vm sin(ωt) – (Vm+ V1)
vd = Vmsin(ωt) – (Vm+ V1)+V1
= Vm sin(ωt) – Vm
‐25
‐30 Time (seconds)
The capacitor charges up to Vm + V1
during the time the diode conducts which
is when Vin(t) +V1 > 0
• Thereafter the diode remains reverse
biased since vd = Vm sin(ωt) – Vm will
never be positive the capacitor can’t
discharge and Vo is always < -V1
BME 372 Electronics I – 195
J.Schesser
 Wave Shaping Circuits
Clamping Circuit Vdiode
20 Capacitor
15
• Clamping Circuits
Vin+VI
10 Vout
5
Vin(t) = Vm sin(ωt) 0
0 2 4 6 8 10 12
‐5
C ‐10
‐15
‐20
+
+
D1 ‐25
‐30
Vin(t) -- - Vo Time (seconds)

V1
+ - • A resistor is added to the
circuit to allow for changes in
Vo(t) = Vin(t) – VC input voltage so that the
capacitor can discharge if Vin
Vo(t) = Vm sin(ωt) – (Vm+ V1) drops below Vm

BME 372 Electronics I – 196

J.Schesser
 Wave Shaping Circuits

• Logic Circuits • AND gate

• OR gate + 5V

va va

vb vb
+ +
vc vc
Vo Vo

-
-

• Output is high when • Output high only when

any input is high all inputs are high
BME 372 Electronics I – 197
J.Schesser
 Voltage Regulation
• We want to design a circuit such that its output
voltage does not fluctuate due to changes in the
load or source.
• Source Regulation: Change in Output voltage
due changes in Source Voltage
Vload
Source Regulation   100%
VSS
• Load: Change in Output voltage due changes in
Load
Vnoload  V full load
Load Regulation   100%
V full load
BME 372 Electronics I – 198
J.Schesser
 Zener Diode Regulator
Id 5

• Load Line: Vss = -RiD - vD

0
R -20 -15 -10 -5 0 5

+ - -5
Vd

VSS iD vD
-10
-- +

-15

• R=1k, VSS=15 -20

– vD = -10.5
• VSS=20
Vload .5
– vD = -11 Source Regulation   100%   100%  10%
VSS 5

BME 372 Electronics I – 199

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 Zener Diode Regulator
• Load Line Using a Thevenin’s Equivalent: Id 5

VT = -RTiD – vD -20 -15 -10 -5

0
0 5

• Vss = 24, R = 1.2 k, RL = 6 k -5

Vd

R -10

+ - -15

VSS iD vD RL
Full Load: Load = RL  6k -20
-- + RL 6
Thevenin's Equivalent: VT  VSS  24  20
RL  R 6  1.2
RT RL R 6  1.2k
RT    1k
RL  R 6  1.2
VT 20
- Load Line Intercepts vD  VT  20; iD     20m
+ RT 1k
VT iD vD vD  11V
No Load: Load = RL  
-- + VSS 24
Load Line Intercepts vD  VSS  24; iD     20m
R 1.2k
Load: vD  11.5V

.5
Load Regulation: 100%  4.5%
11

BME 372 Electronics I – 200

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 PN Junctions - Shockley Equation
Shockley Equation
15
14 i D  amps
13
12

id 11
10
9
8
7
6

+ vd - 5
4
3
2
1
0
-0.3 -0.2 -0.1 -1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
v D volts
vD

iD  I S (e nVT
 1) where iD and vD are the diode current and voltage,
I S is called the reverse bias saturation current,
and VT is the called the thermal voltage and is
kT
VT  where k is the boltzman constant, 1.38  10 -23 Joule/  Kelvin,
q
T is the temperature of the junction in degrees Kelvin,
and q is the magnitude of electric charge of an electron, 1.60  10 -19 coulombs
n is called the emission coeficient as takes values between 1 and 2
BME 372 Electronics I – 201
J.Schesser
 Small Signal Equivalent Circuit for a Diode
Using the Shockley Equation
• We can represent a diode by a resistor if the current and
voltage are small signals Shockley Equation
15
14 i D  amps

Define a resistance near the Q - point : 13

12
11
10

 di  9

ΔiD   D  Δv D
8
7

 dvD  Q
6
5
4
Q point
3
2
1
 di  
1
0

rd   D  
-0.3 -0.2 -0.1 -1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
v D volts

 dvD  Q 
vd  id rd
1 1 Note that I DQ is the value of iD
 d v D
   1 nV
v
DQ
 
rd   [ I S (e  1)]     I S
nV T
e T
  VDQ
dv nV
 D  Q   T  Q  at the Q - point  I S e nV T

1
 1 VnV  DQ
1
 I S e  T
 I DQ  nVT
 nVT  rd    
where VDQ is the value of vD at the Q - point  nVT  I DQ
BME 372 Electronics I – 202
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 Basic Semiconductor Electronics
• Atomic Structure of Valence-4 elements like Carbon, Silicon,
Germanium, etc.
– have 4 valence electrons in its outer atomic shell
– these atoms form covalent bonds with 4 other atoms in a lattice
• When the energy levels of these electrons are raised several of these
bonds may become randomly broken and a free electron is created
– as a result these electrons are free to move about in the material similar to
electron conduction occurs in a metal
– in addition to the free electron, a negative particle, a “hole” which is a
positive “particle” is created which also moves freely within the material.
• As electrons and holes move through the material, they may encounter
each other and recombine and, thereby, become electrically neutral
• This type of material is called an intrinsic semiconductor

BME 372 Electronics I – 203

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Intrinsic Silicon Crystal
Complete Lattice

+4 +4 +4

+4 +4 +4

+4 +4 +4

BME 372 Electronics I – 204

J.Schesser
 Intrinsic Silicon Crystal
Thermal Energy causes a bond to be broken and a free
electron and hole are created

+4 +4 +4

+4 +4 +4

+4 +4 +4

BME 372 Electronics I – 205

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 Doped Semiconductor Material
• If we incorporate a small impurity of five or three valence band materials into
a 4 valence band lattice, we have created an extrinsic semiconductor which is
doped with an impurity
• n-type semiconductor
– Doping with five valence material (e.g. Arsenic) to create additional free (donor)
electrons and a static positive charged ion in the core lattice
– Majority carriers are electrons; minority carriers are holes
– The concentration of electrons in a n-type semiconductor = concentration of the
donor electrons + the concentration of free holes (which is the same as the number
of electrons which have randomly broken their valence bonds)
• p-type semiconductor
– Doping with three valence material (e.g., Gallium) to create additional free (donor)
holes and a static negative charged ion in the core lattice
– Majority carriers are holes; minority carriers are electrons
– The concentration of holes in a p-type semiconductor = concentration of the donor
holes + the concentration of free electrons (which is the same as the number of
holes which have randomly broken their valence bonds)

BME 372 Electronics I – 206

J.Schesser
 Doped silicon material

+4 +4 +4 +4 +4 +4

+4 +5 +4 +4 +3 +4

+4 +4 +4 +4 +4 +4

n-type free electrons p-type free holes

BME 372 Electronics I – 207

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 Carrier Concentrations and Recombination

• There are two types of carrier concentrations

– Majority carriers due to the doping
• Electrons in n-type
• Holes in p-type
– Minor carriers to due thermal excitation
• Holes in n-type
• Electrons in p-type
• Recombination: when an electron meets a hole, they combine
to complete the bond
• Generation: thermal excitation creates new carriers
• Equilibrium exists when the rate of recombination equals the
rate of generation

BME 372 Electronics I – 208

J.Schesser
 PN Junction
• When a p-type semiconductor is fused with a n-type, the following
occurs at the junction.
– Because the concentration of electrons is greater on n-type side, holes
from the p-type diffuse across the junction to the n-type side
– Likewise electrons diffuse across the junction from the n-type to the p-
type material
– These carriers recombine and what remains are the negatively charged
ions on the p-type side and positively charged ion on the n-type side.
• The ions which are tied to the lattice form an electric field which
prohibits the flow of carriers across the junction.
– The area where these ions and their associated electric field are situated is
called the depletion region since it is depleted of holes and electrons
– The electric field which prohibits the flow of carriers is called the barrier
potential

BME 372 Electronics I – 209

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PN Junctions Prior to being Fused

p n

Unbiased PN Junction

BME 372 Electronics I – 210

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PN Junctions Unbiased

Depletion
Region
- - + +
- - + +
p n
- - + +
- - + +
Unbiased PN Junction

BME 372 Electronics I – 211

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 Reverse Bias PN Junction
• When an external voltage is a applied to a PN junction such that the n-
type is more positive than the p-type, then we say that the PN junction
is reverse-biased and the following happens:
– The external voltage creates an electric field which enhances the barrier
potential and the depletion region becomes wider since the majority
carriers are pulled away from the junction (e.g., the electrons in the n-type
material are attracted away from the junction by the positive voltage).
– However, this applied field supports the flow of minority carriers across
the junction (e.g., the holes in the n-type material are attracted across the
junction by the enhanced electric field of the widened depletion region)
and when they cross the junction they become majority carriers (e.g., the
minority carrier n-type holes now become majority carriers once they
cross the junction to the p-type) and are attracted away from the junction
as described above.
– Since the flow across the junction is due to minority carriers the current
flow is small (this is sometimes called the reverse-based leakage current).

BME 372 Electronics I – 212

J.Schesser
PN Junctions Reverse Biased
Depletion
Region
- - - + + +
p -- -
-
-
-
+
+
+
+
+n
+
- - - + + +
Electrons Holes

- +
Reverse-biased PN
Junction

BME 372 Electronics I – 213

J.Schesser
 Forward Bias PN Junction
• When an external voltage is a applied to a PN junction such that the n-
type is more negative than the p-type, then we say that the PN junction
is forward-biased and the following happens:
– The external voltage creates an electric field which opposes the barrier
potential and the depletion region becomes smaller provided it is larger
than the voltage barrier of the depletion region (typically, a few tenths of a
volt)
– This allows for the further flow of majority carriers across the junction
– As the majority carriers cross the junction, the become minority carriers
and then recombine the majority carriers on the other side
– Since the flow across the junction is due to majority carriers the current
flow is large.

BME 372 Electronics I – 214

J.Schesser
PN Junctions Forward Biased
Depletion
Region

- +
- +
p n
- +
- +
Holes Electrons

+ -
Forward-biased PN Junction

BME 372 Electronics I – 215

J.Schesser
 PN Junctions Junction Capacitance
Depletion
Region
- - + +
- - + +
p n
- - + +
- - + +
Unbiased PN Junction

• The ions at the junction look like charges on a two

plates of a capacitor and, thereby, create a
capacitance effect
• We call this the junction capacitance
BME 372 Electronics I – 216
J.Schesser
 PN Junctions Diffusion Capacitance
Depletion
Region

- +
- +
p - + n
- +
Holes Electrons

+ -
Forward-biased PN Junction

• The charges which cross the junction holes on the n-side

and electrons on the p-side also looks like charges on a two
plates of a capacitor and, thereby, adds to the capacitance
effect
• We call this the diffusion capacitance
BME 372 Electronics I – 217
J.Schesser
 Small Signal Equivalent Circuit Updated

• In addition to the resistance of the junction rd, we need to

add the junction capacitance and the diffusion capacitance
• In addition, there is a resistive voltage drop due to bulk of
the material on both sides of the junction, Rs
• Now the small signal equivalent circuit becomes:
Cj

Rs Cj
rd Rs

Reverse Biased
Forward Cd
Biased BME 372 Electronics I – 218
J.Schesser
 Homework

• Probs. 3.2, 3.3, 3.5, 3.15, 3.16, 3.17, 3.20,

3.22, 3.24, 3.54, 3.61, 3.62, 3.63, 3.65, 3.73,
3.74
• For problem 3.16a repeat with D2 reversed
• For problem 3.16c repeat with the +15V
source replaced by -15V

BME 372 Electronics I – 219

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