Dv48sbt1e PDF

Reference No.
83130 55025
48 SB antennas
DVOR 432
VHF Omnidirectional Radio Range
Doppler
Technical Manual
Part 1
Equipment Description
As for details, the electrical and mechanical information given in the

documentation supplied with each equipment prevails
All rights reserved

E 2004
Thales ATM GmbH
Stuttgart
Printed in Germany
NAVAIDS
Conventional Navaids Documentation Structure
DVOR 432
The equipment documentation comprises:
Part Technical Manuals Code No.

1 Equipment Description (incl. Annex NF) 83130 55025
2 Operation and Maintenance (incl. Annex NF) 83130 55026
Volume Drawing Set Code No.

Standard
A Delivery List, Parts List, 83051 48660
Schematic diagrams and Layout Drawings
B Delivery List, Parts List, 83051 48660
C Delivery List, Parts List, 83051 48660
Nextfield (option)
A Delivery List, Parts List, 83051 48660
B Delivery List, Parts List, 83051 48660
C Delivery List, Parts List, 83051 48660
Ed. 07.04 48 SB
DVOR 432
Equipment Description Preliminary Remarks
PRELIMINARY REMARKS
The equipment manuals for DVOR 432 (50 W and 100 W, single or dual) comprise:
PART CONTENTS CODE NO.

1 Equipment Description 83130 55025
2 Operation and Maintenance 83130 55026
This Technical Manual Part 1 includes the Equipment Description with the chapters below:
1 General Information
2 Technical Description Transmitter and Antenna Switching Unit
3 Technical Description Antenna System
4 Emergency Power Supply
5 Remote Maintenance and Monitoring Configuration (RMMC)
Annex DVOR Nextfield (optional)
Chapter 1 contains general system descriptions. The equipment−specific descriptions are contained
in Chapter 2, and the antenna−specific descriptions in Chapter 3. There are only slight differences
between the 50 W and 100 W versions (single or dual) as far as components and functions are con-
cerned. These versions are not therefore described separately; instead the relevant special feature
are made clear by means of notes. The nextfield monitoring option is described in the Annex to this
manual.
Since it is not possible to include modifications, such as those which may be made to circuitry details
or dimensioning in the interests of technical progress, in the Technical Manual, we should point out
that questions of detail should always be answered using the technical documentation supplied with
the system. It is possible that reference numbers of drawings or subassemblies used in this descrip-
tion are no longer contained in the set of drawings supplied (Volume A to C), but rather than (to con-
form with the system) they have been replaced by new drawings with another number. Please carry
out a once−only check on the basis of delivery list supplied and exchange where appropriate.
Description and use of the PC User Program will be found in the Technical Manual ADRACS, Code
No. 83140 55324.
MARK SYMBOLS
To get the best out of the navigation systems Navaids 400 you should study the contents of this manu-
al carefully. In particular you should familiarize yourself with the marks given in this manual which are
highlighted for easy recognition:
CAUTION WARNING
Cautions call attention to methods Warnings call attention to methods,

and procedures which must be procedures or limits which must be
followed to avoid damage to followed precisely to avoid injury to
equipment. persons.
NOTE or REMARK : For more information about operations.
Ed. 07.04 48 SB A
DVOR 432
Preliminary Remarks Equipment Description
Table of effective pages

Basic edition: 07.04
Pages Ed.−No. Remarks
Title 07.04
A 07.04
B 09.05
I to X 07.04
AV−1 to 16 07.04
1−1 to 60 07.04
2−1 to 4 07.04
2−5 to 6 09.05
2−7 to 9 07.04
2−10 09.05
2−11 to 72 07.04
3−1 to 10 07.04
4−1 to 2 09.05
5−1 to 6 07.04
Annex 07.04 DVOR Nextfield (optional)
Trademarks: Microsoft and MS−DOS are registered trademarks, WINDOWS is a trademark of the Microsoft Corporation. IBM is a registered trademark of the International
Business Machines Corporation. Pentium is a registered trademark of the Intel Corporation. All other mentioned product names may be trademarks of the
respective manufacturers and must be observed.
Note Despite of careful editing work technical inaccuracies and printing faults cannot be excluded in this publication. Change of text remains reserved without notification.
B 48 SB Ed. 09.05
DVOR 432
Equipment Description Table of Contents
TABLE OF CONTENTS
Section Title Page
CHAPTER 1 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1
1.2 DVOR/VOR PRINCIPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−3
1.2.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−3
1.2.2 Navigation Signal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−3
1.2.2.1 VOR Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−3
1.2.2.2 DVOR Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−4
1.2.2.2.1 Doppler Effect and Direction−Dependent FM . . . . . . . . . . . . . . . . . . . . . . . . . . 1−5
1.2.2.2.2 Electronic Simulation of the Antenna Movement . . . . . . . . . . . . . . . . . . . . . . . . 1−6
1.2.3 Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−8
1.3 TECHNICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−9
1.3.1 Dimensions and Weight of the Transmitter Rack . . . . . . . . . . . . . . . . . . . . . 1−9
1.3.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−9
1.3.3 Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−9
1.3.4 System Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−9
1.3.5 Equipment Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−10
1.3.5.1 Carrier Transmitter (CSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−10
1.3.5.2 Carrier Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−10
1.3.5.3 Sideband Transmitters (SB1/SB2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−10
1.3.5.4 Sideband Modulation (Blending) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−11
1.3.5.5 Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−11
1.3.5.6 BIT and Measuring Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−11
1.3.5.7 PIN−Diode Switching Unit (PDSU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−11
1.3.6 Antenna System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−12
1.3.6.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−12
1.3.6.2 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−12
1.3.6.3 Monitor Dipole . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−12
1.3.7 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−13
1.3.8 Notes on "Standby" operational Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−13
1.3.9 Conformity and Licensing Approval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−14
1.4 SAFETY PRECAUTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−15
1.4.1 Operating at the Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−15
Ed. 07.04 48 SB I
DVOR 432
Table of Contents Equipment Description
Section Title Page
1.4.2 Handling Subassemblies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−15

1.4.3 Handling Lead Batteries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−16
1.4.4 Components with Beryllium Oxide Ceramic . . . . . . . . . . . . . . . . . . . . . . . . . 1−16
1.4.5 Using Lithium Batteries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−17
1.4.6 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−17
1.4.7 Observation of Safety Regulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−17
1.5 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−19
1.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−19
1.5.2 Brief Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−19
1.5.3 Peripheral Subassemblies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−20
1.5.4 General Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−20
1.6 FUNCTIONAL DESCRIPTION OF THE TRANSMITTER . . . . . . . . . . . . . . . . . . 1−23
1.6.1 DVOR−Transmitter Signals for the DVOR Antenna . . . . . . . . . . . . . . . . . . . 1−23
1.6.2 Signal Generation in the Transmitter of the DVOR 432 . . . . . . . . . . . . . . . . 1−24
1.6.3 Digital controlled Transmitter RF−Signal Generation . . . . . . . . . . . . . . . . . 1−27
1.6.3.1 Basic Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−27
1.6.3.2 Sideband Signal Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−27
1.6.3.3 Carrier Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−28
1.6.4 Modulation Control Realization with Microprocessor Techniques . . . . . . 1−29
1.6.5 RF Signal Processing of the Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−31
1.6.5.1 Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−31
1.6.5.2 Modulator 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−32
1.6.5.3 Control Coupler Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−33
1.7 FUNCTIONAL DESCRIPTION OF THE MONITOR . . . . . . . . . . . . . . . . . . . . . . 1−34
1.7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−34
1.7.2 Monitor Sensors for the DVOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−35
1.7.3 Processing of the monitor signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−35
1.7.4 Monitor Actions at Alarm Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−41
1.8 FUNCTIONAL DESCRIPTION LRCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−43
1.8.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−43
1.8.2 Introduction to the Local Control Panel (LCP) . . . . . . . . . . . . . . . . . . . . . . . 1−43
1.8.3 Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−43
1.9 FUNCTIONAL DESCRIPTION POWER SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . 1−45
1.9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−45
II 48 SB Ed. 07.04
DVOR 432
Section Title Page
1.9.2 Startup Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−45

1.10 NAVAIDS SOFTWARE (DVOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−49
1.10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−49
1.10.2 Description of the DVOR Transmitter Software . . . . . . . . . . . . . . . . . . . . . . 1−49
1.10.3 Description of Monitor Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−51
1.10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−51
1.10.3.2 System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−51
1.10.3.3 Main Program Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−51
1.10.3.4 Basic Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−52
1.10.3.5 Monitor Software Tasks and Activities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−52
1.10.3.6 Monitor SW Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−52
1.10.3.7 Main Program Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−54
1.10.3.7.1 Short Description of the MAIN PROGRAM Modules . . . . . . . . . . . . . . . . . . . . . 1−56
1.10.3.8 Interrupt Program Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−57
1.10.4 Description of LRCI Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−59
1.10.4.1 Short description of the Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−59
CHAPTER 2 TECHNICAL DESCRIPTION DVOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1

TRANSMITTER AND ANTENNA SWITCHING UNIT (ASU)
2.1 GENERAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1
2.1.1 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1
2.1.2 Basic Components of a Transmitter Rack . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2
2.1.2.1 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2
2.1.2.2 Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2
2.1.2.3 Local/Remote Communication Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2
2.1.2.4 Generation of the Operating Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2
2.1.2.5 Antenna Switching Control and RF feeding (ASU) and PDSU . . . . . . . . . . . . 2−4
2.2 MECHANICAL DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−5
2.2.1 DVOR Transmitter Rack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−5
2.2.2 PIN−Diode Switching Unit (PDSU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−5
2.2.3 Shelter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−11
2.3 DESCRIPTION OF SUBASSEMBLIES OF THE TRANSMITTER RACK . . . . . 2−13
2.3.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−13
2.3.2 Overview Subassemblies DVOR Transmitter Rack . . . . . . . . . . . . . . . . . . . 2−13
2.3.3 Transmitter Subassemblies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−15
Ed. 07.04 48 SB III

DVOR 432
Section Title Page
2.3.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−15

2.3.3.2 Synthesizer (SYN−D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−15
2.3.3.3 Modulators (MOD−110, MOD−110P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−17
2.3.3.4 Carrier Amplifier (CA−100C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−19
2.3.3.5 Control Coupler (CCP−D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−20
2.3.3.6 RF−Duplexer and ASU RF−Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−22
2.3.3.7 Modulation Signal Generator Control (MSG−C) . . . . . . . . . . . . . . . . . . . . . . . . 2−23
2.3.3.8 Modulation Signal Generator Signal (MSG−S) . . . . . . . . . . . . . . . . . . . . . . . . . 2−27
2.3.4 Monitor Subassemblies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−31
2.3.4.1 Monitor Signal Processor (MSP−CD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−31
2.3.4.2 Control and Selector Logic (CSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−35
2.3.5 LRCI Subassemblies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−39
2.3.5.1 Local Control Panel (LCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−39
2.3.5.1.1 Local Control CPU (LC−CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−40
2.3.5.1.2 DIMM−CPU board (PC/386−I or PC/520−I) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−42
2.3.5.1.3 Local Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−43
2.3.5.2 Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−45
2.3.5.2.1 Dedicated Line Modem LGM1200MD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−45
2.3.5.2.2 Switched Line Modem LGM 28.8D1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−46
2.3.5.3 Voice Amplifier (VAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−48
2.3.6 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−49
2.3.6.1 Overview DC/DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−49
2.3.6.2 DC Converter Modules 5 V (DCC−3−05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−50
2.3.6.3 DC Converter MV (DCC−MV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−51
2.3.6.4 DC Converter 28 V (DCC−28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−54
2.3.6.5 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−56
2.3.6.6 Power Management Module (PMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−56
2.3.6.7 Power Management of Navaids Installations . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−57
2.3.6.8 AC/DC Converter (ACC−54) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−58
2.4 DESCRIPTION OF ASU SUBASSEMBLIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−61
2.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−61
2.4.2 Overview ASU−Subassemblies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−61
2.4.3 Phase Monitoring and Control (PMC−D) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−62
2.4.3.1 Phase Monitoring and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−62
IV 48 SB Ed. 07.04
DVOR 432
Section Title Page
2.4.3.2 Sideband Antenna Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−64

2.4.3.3 ASU−Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−64
2.4.4 Modulator Sideband Blending (MOD−SBB) . . . . . . . . . . . . . . . . . . . . . . . . 2−65
2.4.5 Blending Signal Generator (BSG−D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−67
2.4.6 PIN−Diode Switching Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−70
2.4.6.1 ASU−Commutator Interface (ASU−CIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−70
2.4.6.2 Antenna Switching Unit Commutator (ASU−C) . . . . . . . . . . . . . . . . . . . . . . . . . 2−70
CHAPTER 3 TECHNICAL DESCRIPTION ANTENNA SYSTEM . . . . . . . . . . . . . . . . . . . . . . . 3−1

3.1 GENERAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
3.2 SYSTEM CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
3.3 SIDEBAND AND CARRIER ANTENNAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2
3.3.1 Sideband Antenna . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2
3.3.1.1 Balance−to−Unbalance and Matching Transformer . . . . . . . . . . . . . . . . . . . . 3−5
3.3.1.2 Options: Matcher and Decoupling Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7
3.3.2 Carrier Antenna . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−8
3.4 ANTENNA COUNTERPOISE (SUPPORT AND SCAFFOLDING) . . . . . . . . . . . 3−9
3.5 MONITOR DIPOLE (NEARFIELD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−10
CHAPTER 4 EMERGENCY POWER SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−1
CHAPTER 5 REMOTE MAINTENANCE AND MONITORING CONFIGURATION (RMMC) . 5−1

5.1 APPLICATION AND DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−1
5.1.1 Hierarchy of RMMC Remote Control System Components . . . . . . . . . . . . 5−2
5.1.2 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−3
5.1.2.1 Local Remote Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−3
5.1.2.2 Remote Control and Status Equipment RCSE 443 . . . . . . . . . . . . . . . . . . . . . . 5−3
5.1.2.3 Remote Control and Monitoring System RCMS 443 . . . . . . . . . . . . . . . . . . . . . 5−4
5.1.2.4 Local Communication Unit LCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−4
5.1.2.5 Remote Maintenance Center RMC 443 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−4
Ed. 07.04 48 SB V
DVOR 432
VI 48 SB Ed. 07.04
DVOR 432
LIST OF FIGURES
Fig.−No. Title Page
Fig. 1−1 Enroute navigation with DVOR, principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1
Fig. 1−2 Diagrammatic view of a DVOR installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−3
Fig. 1−3 Azimuth as a function of the phase angle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−4
Fig. 1−4 Generation of the direction−dependent FM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−5
Fig. 1−5 Frequency spectrum of the DVOR (VOR) omnidirectional radio beacon . . . . 1−6
Fig. 1−6 (D)VOR signal amplitude modulated with 30 Hz and 9960 Hz . . . . . . . . . . . . 1−6
Fig. 1−7 Switching of the sideband antennas in the DVOR . . . . . . . . . . . . . . . . . . . . . . . 1−7
Fig. 1−8 Components with beryllium oxide ceramic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−16
Fig. 1−9 Basic structure of a DVOR system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−21
Fig. 1−10 Azimuth angle between aircraft and ground station . . . . . . . . . . . . . . . . . . . . . 1−23
Fig. 1−11 Arrangement of the electronically rotated DVOR antenna . . . . . . . . . . . . . . . . 1−24
Fig. 1−12 Generation of the modulated RF CSB, unmodulated USB (SB1) and . . . . . . 1−25
LSB (SB2) signals; feeding of the antenna via PDSU
Fig. 1−13 Concept of sideband signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−25
Fig. 1−14 Antenna Switching Unit subassemblies (ASU), block diagram . . . . . . . . . . . . 1−26
Fig. 1−15 Generation of sideband signals (example USB) . . . . . . . . . . . . . . . . . . . . . . . . 1−27
Fig. 1−16 Generation of the DVOR carrier signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−29
Fig. 1−17 Address Counter and RAM data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−30
Fig. 1−18 DVOR transmitter modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−31
Fig. 1−19 Concept of the DVOR VHF Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−32
Fig. 1−20 Concept of the Modulator 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−32
Fig. 1−21 Concept of Control Coupler CCP−D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−33
Fig. 1−22 Monitoring Concept, general view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−34
Fig. 1−23 Position of the monitor dipole in the radiated field . . . . . . . . . . . . . . . . . . . . . . 1−35
Fig. 1−24 Concept of Monitor Signal Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−36
Fig. 1−25 Spectrum of the VOR multiplex signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−36
Fig. 1−26 Discrete Fourier Transformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−37
Fig. 1−27 DVOR antenna monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−41
Fig. 1−28 Dual AN 400 Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−42
Fig. 1−29 Power supply, block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−46
Fig. 1−30 DVOR 432, 50/100 W, dual version; simplified block diagram . . . . . . . . . . . . . 1−47
Fig. 1−31 System software, overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−49
Fig. 1−32 Transmitter SW flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−50
Ed. 07.04 48 SB VII

DVOR 432
Fig. 1−33 Monitor SW flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−53
Fig. 1−34 Monitor SW main program modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−54
Fig. 1−35 Basic structure of COMMUNICATION INTERRUPT . . . . . . . . . . . . . . . . . . . . . 1−58
(valid for transmitter and monitor)
Fig. 1−36 Basic flow diagram of the 960 Hz INTERRUPT service routine . . . . . . . . . . . . 1−58
Fig. 1−37 Overview LCP SW structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−59
Fig. 2−1 DVOR 432 system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−3
Fig. 2−2 Main components of a DVOR transmitter cabinet . . . . . . . . . . . . . . . . . . . . . . . 2−3
Fig. 2−3 Power distribution (standard), block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−4
Fig. 2−4 Transmitter rack DVOR and outdoor PDSU housing . . . . . . . . . . . . . . . . . . . . 2−6
Fig. 2−5 Transmitter rack DVOR, front door open . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−7
Fig. 2−6 Locations in the DVOR transmitter rack in the 50 W and . . . . . . . . . . . . . . . . 2−8
up to 100 W versions
Fig. 2−7 Assignment and scheme of subassemblies for DVOR . . . . . . . . . . . . . . . . . . . 2−9
Fig. 2−8 PIN−Diode Switching Unit (PDSU), housing and subassemblies . . . . . . . . . 2−10
Fig. 2−9 Navaids shelter, dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−11
Fig. 2−10 Standard shelter, ground plan and electrical installation DVOR (example) . . 2−12
Fig. 2−11 Circuit diagrams of subassemblies (Transmitter rack) . . . . . . . . . . . . . . . . . . . 2−13
Fig. 2−12 Synthesizer (SYN−D), block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−16
Fig. 2−13 Modulator 110 and 110P (MOD−110, MOD−110P), block diagram . . . . . . . 2−18
Fig. 2−14 Carrier amplifier (CA−100C), block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−19
Fig. 2−15 Control Coupler (CCP−D), block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−21
Fig. 2−16 RF−Duplexer (RFD1−C RFD2−SB) and ASU RF−components, . . . . . . . . . 2−22
block diagram
Fig. 2−17 MSG−C, simplified overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−23
Fig. 2−18 Modulation Signal Generator (MSG−C), block diagram . . . . . . . . . . . . . . . . . 2−25
Fig. 2−19 MSG−S, simplified overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−27
Fig. 2−20 Modulation Signal Generator (MSG−S), block diagram (1 of 2) . . . . . . . . . . . 2−28
Fig. 2−21 Modulation Signal Generator (MSG−S), block diagram (2 of 2) . . . . . . . . . . . 2−29
Fig. 2−22 Monitor Signal Processor (MSP−CD), simplified overview . . . . . . . . . . . . . . . 2−31
Fig. 2−23 Monitor Signal Processor (MSP−CD), block diagram . . . . . . . . . . . . . . . . . . . 2−33
Fig. 2−24 Control and Selector Logic (CSL), overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−35
Fig. 2−25 Control and Selector Logic (CSL), Switch on logic . . . . . . . . . . . . . . . . . . . . . . 2−36
Fig. 2−26 Control and Selector Logic (CSL), coaxial relays control . . . . . . . . . . . . . . . . . 2−36
Fig. 2−27 Control and Selector Logic (CSL), battery monitoring, over−discharge . . . 2−37
protection
VIII 48 SB Ed. 07.04

DVOR 432
Fig. 2−28 Control and Selector Logic (CSL), DME interface . . . . . . . . . . . . . . . . . . . . . . . 2−37
Fig. 2−29 Control and Selector Logic (CSL), test generator . . . . . . . . . . . . . . . . . . . . . . . 2−38
Fig. 2−30 LCP, overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−39
Fig. 2−31 Local Control CPU (LC−CPU), block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 2−41
Fig. 2−32 DIMM−CPU board, block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−42
Fig. 2−33 Local Control Interface (LCI), block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−43
Fig. 2−34 Control Interface (LCI), visible front view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−43
(text example: system status screen)
Fig. 2−35 LGM1200MD, block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−45
Fig. 2−36 LGM 28.8, block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−47
Fig. 2−37 Voice Amplifier (VAM), block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−48
Fig. 2−38 DC converter DCC−3−05, block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−50
Fig. 2−39 DC converter DCC−MV, block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−52
Fig. 2−40 DC converter DCC−28, block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−55
Fig. 2−41 Power Management Module (PMM), block diagram . . . . . . . . . . . . . . . . . . . . . 2−56
Fig. 2−42 Power management Navaids with PMM, overview . . . . . . . . . . . . . . . . . . . . . . 2−57
Fig. 2−43 AC/DC converter (ACC−54), block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−59
Fig. 2−44 ASU subassemblies, functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−61
Fig. 2−45 Circuit diagrams of subassemblies of the Antenna Switching Unit . . . . . . . 2−61
(ASU) function
Fig. 2−46 Phase Monitor and Control (PMC−D) including ASU interface, block diagram . . . . .
2−63
Fig. 2−47 Modulator Sideband Blending (MOD−SBB), block diagram . . . . . . . . . . . . . . 2−66
Fig. 2−48 Blending Signal Generator (BSG−D), block diagram . . . . . . . . . . . . . . . . . . . . 2−69
Fig. 2−49 Antenna Commutator Interface (ASU−CIF), block diagram . . . . . . . . . . . . . . 2−70
Fig. 2−50 Antenna commutator (ASU−C), block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 2−71
Fig. 3−1 DVOR antenna installation (example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
Fig. 3−2 Current distribution and setting of the capacitors . . . . . . . . . . . . . . . . . . . . . . . 3−3
Fig. 3−3 Spacing of the capacitor plates as a function of the operating frequency . . 3−4
Fig. 3−4 Connection diagram of individual radiators of the sideband antenna . . . . . . 3−4
Fig. 3−5 Resistance behaviour of the balance−to−unbalance and . . . . . . . . . . . . . . . 3−5
matching transformer
Fig. 3−6 Setting trimming capacitor CTr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6
Fig. 3−7 Vertical pattern of a DVOR loop antenna . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6
Fig. 3−8 Optional Matcher and Decoupling Module, circuit diagram . . . . . . . . . . . . . . . 3−7
Ed. 07.04 48 SB IX
DVOR 432
Fig. 3−9 Setting trimming capacitor C5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7
Fig. 3−10 Single radiator on sideband antenna . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−8
Fig. 3−11 Single antenna, cover removed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−8
Fig. 3−12 Supports and framework, example installation . . . . . . . . . . . . . . . . . . . . . . . . . 3−9
Fig. 3−13 Framework decking and antenna circle with carrier antenna and . . . . . . . . . 3−10
sideband antennas
Fig. 3−14 Mast with monitor dipole (example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−10
Fig. 4−1 Discharge times (guiding values) by use of the VARTA battery set . . . . . . . . 4−3
Fig. 5−1 RMMC, overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−1
Fig. 5−2 Hierarchy of the RMMC system components . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−2
Fig. 5−3 Example Configuration: RCMS 443 for two ILS and VOR/DME/TACAN . . . . 5−5
X 48 SB Ed. 07.04
NAVAIDS 400
Conventional Navaids List of Abbreviations
ABKÜRZUNGSVERZEICHNIS
LIST OF ABBREVIATIONS
LISTE D’ABRÉVIATIONS
LISTA DE ABREVIATURAS
A Antenne
Antenna
Antena
AC Alternating Current
Courant alternatif
Corriente alterna
ACA Analogical Carrier Amplifier (BITE signal)
Amplificateur pour porteurs analogiques (signal BITE)
Amplificdor portador analogico (señal BITE)
ACC Alternating Current Converter
ADC Analog−Digital Converter
Convertisseur analogique/numérique
Convertidor analógico/digital
ADCS Analog−to−digital Converter Subsystem
Sous−système convertisseur analogique/numérique
Subsistema convertidor analógico/digital
ADR Analog Display Routine
Routine affichage analogique
Rutina de indicator analógico
ADRACS Automatic Data Recording And Control System
ADSB Alternating Double Sideband
Bande latérale double alternante
Banda lateral doble alternante
ADU Antenna Distribution Unit
Antennen−Verteileinheit
Ensemble de distribution d’antenne
Unidad de distribución de antena
AF Audio Frequency
Basse fréquence
Audiofrequencia
AFC Automatic Frequency Control
Commande automatique par fréquence
Control automático de frecuencia
AGC Automatic Gain Control
Commande automatique de gain
Control automático de ganancia
AM Amplitude Modulation
Modulation d’amplitude
Modulación de amplitud
Ed. 07.04 AV−1

NAVAIDS 400
List of Abbreviations Conventional Navaids
AMP AMPlifier
Amplificateur
Amplificador
ANSI American National Standards Institute
ASB Alternating SideBand
Bandes latérales alternantes
Banda lateral alternante
ASC Antenna Switch Control
Commutateur d’antennes de commande
Control de conmutador de antena
ASCII American Standard Code for Information Interchange
Code standard américain pour l’échange d’informations
Código stándard americano para el intercambio de informaciones
ASM Antenna Switch Module
Module de commutateur d’antennes
Módulo de conmutador de antena
ASU Antenna Switching Unit
Ensemble de commutation d’antennes
Unidad de conmutación de antena
ATC Air Traffic Control
Contrôle du trafic aérien
Control del tráfico aéreo
ATIS Air Traffic Information System
Système d’informations du trafic aérien
Sistema de informaciones del tráfico aéreo
ATM Air Traffic Management
AWD Automatische Wähleinrichtung für Datenverbindungen
Automatic dialling equipment for data connections
Dispositif automatique de sélection pour liaisons d’acheminement de données
Dispositivo automático de selección para comunicaciones de datos
BAZ Back−Azimuth
BCD Binär Codiert Dezimal
Binary Coded decimal
BCPS Battery Charging Power Supply
Chargeur de batterie et bloc d’alimentation
Chargador de bateria y equipo de alimentación
BD Baud
Baud
Baudio
BF Basse Fréquency
Audio Frequency
Baja frecuencia (audiofrecuencia)
BIT(E) Built−in Test (Equipment)
Dispositif de test intégré
Dispositivo de test integrado
AV−2 Ed. 07.04

NAVAIDS 400
BKZ BefehlsKennZahl
Command code number
Numéro indicatif de commande
Número indicador de orden
BNC Bayonet Navy Connector
Koaxialverbinder mit Bayonetkupplung
BP Backplane
Rückwandverdrahtung
bro. broches
polig
pin
BSE Betriebs− und Schutzerde
System and protective ground
Prise de terre de système et terre de protection
Puesta a tierra del sistema y de protección
BSG−D Blending Signal Generator
Générateur de signaux de transition
Generador de señal de transición
BST Baustahl
Structure steel
Acier de construction
Acero de construcción
BUSGNT Bus Grant
Autorisation de bus
Autorización de bus
BUSRQ Bus Request
Demande de bus
Solicitud de bus
CA Carrier Amplifier
CAB Cabinet
Armoire
Armario
CAT Category
Kategorie
Category
Categoría
CCA Circuit Card Assembly
Baugruppe
Assemblage de la carte de circuit
CCITT Commitée Consultatif International Téléphonique et Télégraphique
International Telegraph and Telephone Consultative Committee
CCP Control Coupler
Coupleur de commande
Acoplador de control
Ed. 07.04 AV−3

NAVAIDS 400
CDI Course Deviation Indicator
Indicateur de déviation (cap)
Indicador de desviaciòn de rumbo
CD−ROM Compact Disc − Read Only Memory
Disque compact −Mémoire à lecture
Disco compacto − Memoria permanente
CE Conformité Européen oder/or/ou Communautés Européennes
CEE International Commmision on Rules for the Approval of Electrical Equipment
CLR; CL Clearance signal
Signal de Clearance
Señal de Clearance
CMOS Complementary Metaloxide Semiconductor
Semi−conducteur oxyde métallique complémentaire
Semiconductor complementario de óxido metálico
CONC Phone Concentrator
Telefon−Umschalteinrichtung
Installation de commutation téléphonique
Centralilla teléfonica
CPU Central Processing Unit
Zentrale Prozessoreinheit
CR Carriage Return
Retour du chariot
Retorno de carro
CRC Cyclic Redundancy Check
CRT Cathode Ray Tube
Tube cathodique
Tubo catódico
CRS; CS Course signal
Kurssignal
Signal de directif
Señal de rumbo
CSB (1) Carrier signal with SideBands (HF)
Signal de porteuse avec bandes latérales
Señal de portadora con bandas laterales
CSB (2) Control&Status Board (part of the LCSU)
CSL Control and Selector Logic
Logique de commande et de sélection
Lógica de control y de selección
CTOL Conventional Take−off and Landing
Décollage et atterrissage classiques
Despegue y aterrizaje convencionales
CTS Clear to Send
Prêt à émettre
Listo para transmitir
AV−4 Ed. 07.04

NAVAIDS 400
CW Continuous Wave
Fortlaufende Welle
Ondes continues
Ondas continuos
DAC Digital/Analog Converter
Convertisseur numérique/analogique
Convertidor digital/analógico
DAS DME−based Azimuth System
Système d’azimut basé DME
Sistema de acimut basado en DME
DC Direct Current
Courant continu
Corriente continua
DCC DC−Converter
Convertisseur de courant continu (Convertisseur CC)
Convertidor de corriente continua (convertidor CC)
DCC−MV DC−Converter Multivolt
Convertisseur CC−Multivolt
Convertidor CC−Multivolt
DCC−MVD DC−Converter Multivolt Doppler
Convertisseur CC−Multivolt Doppler
Convertidor CC−Multivolt Doppler
DDM Difference in Depth of Modulation
Differenz der Modulationsgrade
Différence de taux de modulation
Diferencia de grados de modulación
DDS Direct Digital Synthesis
DFS Deutsche Flugsicherung
Administration of air navigation services
Bureau de la sécurité aérienne
Instituto de protección de vuelo
DFT Diskrete Fourier Transformation
Discrete Fourier Transformation
DIF Differenzsignal
Difference signal
Signal différentiel
Señal diferencial
DIN Deutsche Industrie Norm
German industrial standard
Norme industrielle allemande
Norma industrial alemana
DIP Dual−In−Line Package
DME Distance Measuring Equipment
Equipement de mesure de la distance
Equipo de medición de la distancia
Ed. 07.04 AV−5

NAVAIDS 400
DSB Double Sideband
Bandes latérales doubles
Banda lateral doble
DSP Digital Signal Processing
Digitaler Signal Prozessor
DSR Data Set Ready
Enregistrement des données prêt
Registro de datos listo
DTR Data Terminal Ready
Terminal de données prêt
Terminal de datos listo
DU Distribution Unit
Verteilereinheit
Ensemble de distribution
Unidad de distribución
DVOR Doppler Very High Frequency Omnidirectional Radio Range
Radiophare omnidirectionnel VHF Doppler
Radiofaro omnidireccional VHF Doppler
EC European Community
ECU Executive Control Unit
Ausführende Steuereinheit
Ensemble de contrôl exécutif
Unidad de control ejecución
EEPROM Electrically Erasable Programmable Read Only Memory
Mémoire à lecture seule, programmable et erasable électrique
Memoria permanente borrable eléctricamente y programada
EMC Electromagnetic Compatibility
Elektromagnetische Verträglichkeit
ENBT Enable Bus Transfer
Validation transfert de bus
Conexión transferencia de bus
EPLD Electrically Programmable Logic Device
Elektrisch programmierbare Schaltungseinheit
Montage programmable électrique
Circuito programado eléctricamente
EPROM Erasable Programmable Read Only Memory
Mémoire à lecture seule, programmable et erasable
Memoria permanente borrable y programada
EUROCAE European Organization for Civil Aviation Electronics
Organisation européenne pour l’électronique de l’aviation civile
Organización europea para la electrónica de la aviacion civil
FAA Federal Aviation Administration

Administration fédérale de l’aviation
Administración federal de aviación
AV−6 Ed. 07.04

NAVAIDS 400
FET Feldeffekttransistor
Field−effect transistor
FFM Farfield Monitor
(FF) Moniteur de champ lointain (zone Fraunhofer)
Monitor campo lejano
FIFO First In/First Out
Premier entré/premier sortie
Primera entrada/primera salida
FM Frequency Modulation
Modulation de fréquence
Modulación de frecuencia
FPE Functional Protection Earth
Betriebsschutzerde
FSK Frequency−Shift Keying
Frequenzumtastverfahren
Manipulation par déplacement de fréquence
Método de manipulación de frecuencia
GP, GS Glide Slope, Glide Path
Gleitweg
Radiophare d’alignement de descente
Transmisor de trayectoria de descenso
HF Hochfrequenz
Radio frequency
Haute fréquence
Alta frecuencia
IC Integrated Circuit
Integrierter Schaltkreis
Circuit intégré
Circuito integrado
ICAO International Civil Aviation Organization
Organisation de l’aviation civile internationale (OACI)
Organización de aviación civil international (OACI)
ILS Instrument Landing System
Système d’atterrissage aux instruments
Sistema de aterrizaje por instrumentos
IM Inner Marker
Radiobalise intérieure
Radiobaliza interior
INC Indication and Control
Anzeige und Steuerung
Indicateur et contrôle
Panel de indicaciones y control
INT Interface Unit
Schnittstelleneinheit
Unité d’interface
Unidad de interfase
Ed. 07.04 AV−7

NAVAIDS 400
INTFC Interface Board for monitor
Schnittstellenkarte für Monitor
Platine d’interface du moniteur
Placa enchufable de la interfase de monitor
I/O−Port Input/Output−Port
Ein−/Ausgabeport
Porte d’entrée/sortie
Puerto de entrada/salida
ISO International Organization for Standardization
Internationale Organisation für Normung
Organisation Internationale de Normalisation
I/Q In Phase/Quadraturphase
In−phase/Quadratur−phase
KADP Kabeladapter
Cable adapter
Adaptateur de cable
Adaptador de cable
LCC Local Communication Control
LCD Liquid Crystal Display
Ecran à cristaux liquides
Indicador de cristal liquido
LCI Local Control Interface
Interface de commande locale
LCP Local Control Panel
Panneau de commande locale
LCSU Local Control and Status Unit
LCU Local Communication Unit
LED Light Emitting Diode
Diode électroluminiscente
Diodo electroluminiscente
LF Line Feed
Avancement de ligne
Avance de línea
LG−A Localizer/Glide Path − Audio Generator
LLZ/GP − Générateur Audio
LG−M Localizer/Glide Path − Monitor Processor
LLZ/GP − Processeur du Moniteur
LGM Modembezeichnung (LOGEM)
Modem assignation
LLZ/LOC Localizer
Radiophare d’alignement de piste
Localizador
AV−8 Ed. 07.04

NAVAIDS 400
LP Leiterplatte
Printed circuit board
Plaquette à circuits imprimé
Placa de circuito impreso
LPF Low Pass Filter
Filtre passe−bas
Filtro de paso bajo
LRCI Local/Remote Communication Interface
LRU Line Replaceable Unit
LSB (1) Lower Sideband (HF DVOR)
Bandes latérales inférieures
Banda lateral inferior
LSB (2) Least Significant Bit (digital)
m Modulationsgrad
Mod−Depth
Taux de modulation
Profundidad (grado) de modulación
MEU Marker Extension Unit
Unité de radiobalise d’extension
Fuente de alimentación suplementaria de la radiobaliza
MIA Monitor Interface Adapter
Adapteur d’interface du moniteur
Adaptador de la interfase de monitor
MIB Monitor Interface Board
Platine d’interface du moniteur
Placa enchufable de la interfase de monitor
MLS Microwave Landing System
Système d’atterrissage aux micro−ondes
Sistema de aterrizaje por microondas
MM Middle Marker
Radiobalise médiane
Radiobaliza intermedia
MOD Modulation
Modulation
Modulación
MODPA Modulator/Power Amplifier
Modulateur/Amplificadeur de puissance
Modulador/AmplificadorAlimentación
MOD−SBB Modulator Sideband Blending (DVOR)
Modulateur de transition des bandes latérales
Modulador de transición de banda lateral
MON Monitor
Moniteur
Monitor
Ed. 07.04 AV−9

NAVAIDS 400
MOS Metallic Oxide Semiconductor
Semi−conducteur métal oxyde
Semiconductor de óxido metálico
MPS Minimum Performance Specification
Spécification de rendement minimum
Especificación de rendimiento mínimo
MPU Marker Processing Unit
Unité de marqueur de traitement
Procesador de radiobaliza
MSB Most Significant Bit
MSG Modulation Signal Generator
Générateur de signaux de modulation
Generador de señal de modulación
MSP Monitor Signal Processor
Processeur de signaux de moniteur
Procesador de señal de monitor
MSR Monitor Service Routine
Routine de service de moniteur
Rutina de servicio de monitor
MTBF Meantime between Failures
Temps moyen entre défauts
Tiempo medio entre fallos
MTTR Meantime to Repair
Temps moyen de réparation
Tiempo medio de reparacion
MUX Multiplexer
Multiplexeur
Multiplexor
MV Multivolt
NAV Navigation
Navigation
Navigation
Navegación
NAVAIDS Navigational Aids
Navigationsanlagen
Aide de navigation
Radioayudas a la navegación
NC Normally closed
Normalement fermé
Normalmente cerrado
NDB Non−Directional radio Beacon
Radiophare omnidirectional
Radiofaro omnidireccional
AV−10 Ed. 07.04

NAVAIDS 400
NF Niederfrequenz
Audio frequency
Basse fréquence
Baja frecuencia
NFK Niederfrequenzknoten (Sternverteiler)
Star distributor (for audio frequency)
NFM Nearfield Monitor
Moniteur de champ proche
Monitor campo cercano
NM Nautical Mile
Mile nautique
Milla náutica
NO Normally open
Normalement ouvert
Normalmente abierto
OAB Optocoupler Adapter Board
Platine d’adaptateur d’optcoupleur
Placa enchufable del adaptador optoacoplador
OACI Organisation de l’aviation civile internationale (= ICAO)
International Civil Aviation Organization
Organización de aviación civil international
OIO Opto Coupler Isolated Input/Output
OM Outer Marker
Radiobalise extérieure
Radiobaliza exterior
PC Personal Computer
PCB Printed Circuit Board
Carte à circuit imprimé
Tarjeta de circuito impreso
PDME Precision DME
DME de précision
DME de precición
PE Protection Earth
PEP Peak Envelope Power
Spitzenleistung
Puissance de pointe
Potencia punta
PLL Phase Locked Loop
Boucle à verrouillage de phase
Bucle de bloqueo de fase
PM Phase Modulation
Pasenmodulation
Modulation de phase
Modulación de fase
Ed. 07.04 AV−11

NAVAIDS 400
PMC Phase Monitor and Control
Moniteur de phase et commande
Monitor de fase y control
PMM Power Management Module
POP Power on Parallel
POSN./Pos. Position
Axe
Posición
PROM Programmable Read Only Memory
Mémoire à lecture seule et programmable
Memoria permanente programada
PRUM Protector Unit Marker
Radiobalise d’unité de protection
Unidad de protección de la radiobaliza
PRUT Protector Unit Tower
Unité de protection
Unidad de protección
PS Power Supply
Bloc d’alimentation
Equipo de alimentación
PSI Power Supply Interface
Interface du bloc d’alimentation
Interfase equipo de alimentación
PSS Power Supply Switch
PSW Interrupteur de puissance
Interruptor de alimentación
PSN Position
Position
Axe
Posición
PSTN Public Switched Telephone Network
PTT Post Telephone and Telecommunications (Authority)
PVC Polyvinylchlorid
Polyvinyl chloride
Chlorure de polyvinyl (C.P.V.)
Chloruro de polivinilo
PWR Password Routine
Routimne de mot de passe
Rutina de contrasena
RAM Random Access Memory
Mémoire à accés aléatoire
Memoria de acceso aleatorio
RC Remote Control
Télécommande
Control remoto
AV−12 Ed. 07.04

NAVAIDS 400
RCMS Remote Control Monitoring System
Système de télécommande et de surveillance
Sistema de control y monitoreo remotos
RCSE Remote Control and Status Equipment
RCSR Remote Control Service Routine
Routine de service de télécommande
Rutina de servicio de control remoto
RCSU Remote Control Status Unit
REU Remote Electronic Unit
RF Radio Frequency
Haute fréquence (HF)
Radiofrecuencia
RIA Remote Interface Adapter
Adaptateur d’interface de télécommande
Adaptador de interfase telemando
RIAX Remote Interface Adapter extended
Adaptateur d’interface de télécommande étendé
Adaptador suplementario de interfase telemando
RISC Reduced Instruction Set Computing
Rechner mit reduziertem Befehlssatz
RL Radio link
Richtfunkverbindung
Liaison hetzienne
Radioenlace dirigido
RMMC Remote Monitoring and Maintenance Configuration
ROM Read Only Memory
Mémoire à lecture seule
Memoria permanente
RST Restart
Remettre en marche
Nueva puesta en marche
RTC Real Time Clock
Echtzeituhr
Rythme en temps réel
Reloj en tiempo real
RTCR Real Time Clock Routine
Routine de rythme en temps réel
Rutina de reloj en tiempo real
RTS Request to send
Marche l’émetteur
Activación del transmisor
RWY Runway
Landebahn
Piste d’aviation
Pista de aterrizaje
Ed. 07.04 AV−13

NAVAIDS 400
RX Receiver
Récepteur
Receptor
RXC Receiver Clock
Rythme du récepteur
Reloj de receptor
RXD Receiver Data
Données de récepteur
Datos de receptor
RXRDY Receiver Ready
Récepteur prêt
Receptor listo
S Switch
Commutateur
Conmutador
SB Sideband
Bandes latérales
Banda lateral
SB1, SB2 Sideband 1, Sideband 2
Bandes latérales 1, 2
Banda lateral 1, 2
SBA Sideband A (used in VOR)
Bandes latérales A (utilizé en VOR)
Banda lateral A (utilizado para VOR)
SBB Sideband B (used in VOR)
Bandes latérales B (utilizé en VOR)
Banda lateral B (utilizado para VOR)
SBO Sideband Only
Bandes latérales seulement
Banda lateral solamente
SBR Subrack
Sous−bâti
Subrack (con junto)
SCC Serial Communication Controller
SDM Sum of Depths of Modulation
Somme des taux de modulation
Suma de grado de modulación
SMA Subminiature connector type A
Miniatur HF−Steckverbinder für Mikrowellenanwendungen
SPDT Single Pole Double Throw
Commutateur unipolaire
Conmutador unipolar doble
SP3T Single Pole 3 Throw
Commutateur unipolaire triple
Conmutador unipolar triple
AV−14 Ed. 07.04

NAVAIDS 400
STOL Short Take−Off and Landing
Système de décollage et d’atterissage court
Despegue y aterrizaje corto
SUM Summensignal
Summation Signal
Signal de la somme
Señal de suma
SW Software
SYN (1) Synchronisation
Synchronisation
Sincronización
SYN (2) Synthesizer
TACAN Tactical Air Navigation
Navigation aérienne tactique
Navigación aérea táctica
TCXO Temperature Compensated Crystal Oscillator
Temperatur kompensierter Quarzoszillator
Oscillateur à quartz compensé par témperature
Oscilador de cuarzo termo compensado
TEG Test Generator
Générateur de test
Generador de test
THR Threshold
Schwellwert
Valeur de seuil
Nivel determinado
TNC Threaded Navy Connector
Koaxialverbinder mit Gewindekupplung
TNV Telephone Network Voltage
TOR Time Out Routine
Routine de temps de suspension
Rutina de tiempo de suspensión
TTL Transistor−Transistor Logic
Logique transistor−transistor
Lógica transistor − transistor
TX Transmitter
Emetteur
Transmisor
TXC Transmitter Clock
Rythme d’émetteur
Reloj de transmisor
TXD Transmitter Data
Données d’émetteur
Datos de transmisor
Ed. 07.04 AV−15

NAVAIDS 400
TXRDY Transmitter Ready
Emetteur prêt
Transmisor listo
USART Universal Synchronous/Asynchronous Receiver/Transmitter
Récepteur/émetteur universel synchrone/asynchrone
Receptor/transmisor universal síncrono/asíncrono
USB Upper Sideband (HF DVOR)
Bandes latérales supérieures
Banda lateral superior
UV Ultraviolet
Ultraviolet
Ultravioleta
VAM Voice Amplifier
Amplificateur vocal
Amplificador vocal
VCO Voltage Controlled Oscillator
VGA Video Graphic Adapter
VHF Very High Frequency
Hyperfréquence
Hiperfrecuencia
VOR Very High Frequency Omnidirectional Radio Range
Radiophare omnidirectionnel VHF
Radiofaro omnidireccional VHF
VSWR Voltage Standing Wave Ratio
Taux d’ondulation
Grado de ondulación
VTOL Vertical Take−off and Landing
Décollage et atterrissage verticaux
Despegue y aterrizaje vertical
WI Width signal
Breite−Signal
Signal faisceau
WT Wechselstrom−Telegrafie
Voice−frequency carrier telegraphy
Télégraphie harmonique à ondes porteuses
Telegrafía armónica
ZU Zeichenumsetzer
Modem for data transfer
Convertisseur de signaux
Convertidor de señal
AV−16 Ed. 07.04

DVOR 432
Equipment Description General Information
CHAPTER 1
GENERAL INFORMATION
1.1 INTRODUCTION
The VOR (Very high frequency Omnidirectional Radio range) is a radio navigation aid recommended
by the ICAO and introduced internationally for short and medium range aircraft guidance. It can be
remote controlled and remote monitored.
The DVOR radio navigation equipment is a further development of the conventional VOR. Through
its utilisation of the Doppler effect and a wide−based antenna system it is able to produce a consider-
ably more precise azimuth signal. DVOR radio navigation installations are used mainly where the geo-
graphical conditions are difficult.
The principle on which the (D)VOR operates is based on the measurement of the phase angle of two
30 Hz signals radiated by the station. One signal (reference signal) is radiated with the same phase
in all directions. For the second 30 Hz signal (variable signal), the phase relationship relative to the
first signal changes as a function of the azimuth. The electric phase angle measured in the airborne
receiver corresponds to the azimuth angle.
Using the VOR receiver installed in his aircraft the pilot is able to obtain the following information from
a DVOR or VOR radio navigation installation:
1. The azimuth indication of the aircraft’s position relative to the ground beacon, i.e. the angle be-
tween magnetic North and the direction ground beacon to aircraft.
2. The bearing which indicates whether the aircraft is flying to the left or right of the preselected course
(position line) or whether it is exactly on it.
3. The "from/to" indication which shows whether the aircraft is flying toward the (D)VOR beacon or
away from it.
The aircraft position is marked by the intersection of two position lines, which can be obtained by
switching the VOR airborne receiver consecutively to the frequencies of two CVOR or DVOR beacons
(C=Conventional, D=Doppler). To evaluate the indications only a map is required, and the knowl-
edge of the CVOR or DVOR positions and a CVOR/DVOR frequency chart. In addition, a VOR beacon
can be approached on a homing flight using the CDI instrument (Course Deviation Indicator) or with
help of an automatic flight management system.
ÂÂÂÂ
ÂÂÂÂ ÂÂÂÂÂ
2
DVOR B
ÂÂÂÂÂ DVOR c
ÂÂÂÂÂ
ÂÂÂÂÂ
DVOR A
Fig. 1−1 Enroute navigation with DVOR, principle
Ed. 07.04 48 SB 1−1

DVOR 432
General Information Equipment Description
The main features of the Navaids family in general and the DVOR 432 in particular are as follows:
− Available as single or dual equipment with power up to 50 W or 100 W

− advanced technology "state of the art", in conformance with ICAO standards
− Antenna configuration: 48 sideband antennas with DSB radiation, having a minimum of distortion
on the 9960 Hz subcarrier
− High signal quality and long time stability of transmitted signals, real time monitoring
− Microprocessor controlled transmitter: Generation of sinusoidal modulation signals and control
of amplitude and phase of the RF signals, therefore no readjustment necessary
− Microprocessor controlled monitoring system: internal and field sensing points providing the input
to the monitoring process. Monitoring signals are sampled and computed by means of Discrete
Fourier Transforms (DFT) and evaluated by the processor of the MSP.
− For the DVOR monitoring system, an optional nextfield monitor provision is implemented which
allows the evaluation of the DVOR−signal received at the counterpoise edge by up to 4 nextfield
dipoles.
− BITE routine permits continuous, automatic testing of the installation with measurement of trends.
Automatic fault diagnostic to LRU level (LRU=Line Replaceable Unit).
− Modular design, extensive common use of subassemblies within the Navaids 400 family. All trans-
mitter and monitor subassemblies including power supply (BCPS) and, with DVOR, the control
parts of the Antenna Switching Unit (ASU) are housed in the same cabinet. The distribution assem-
bly, the PIN−Diode Switching Unit (PDSU), to the individual antennas of the DVOR system is pre-
ferably located in a box below the counterpoise on an appropriate mounting.
− Local LCD display and control panel for system status indication, basic controls and measurement
data indication of transmitter and monitor. Manual key lock and enable/disable function for opera-
tion modes.
− Standard PC used as local or remote interface (via RMMC) between the system and the operator
for first setup, operation and maintenance: All signal parameter settings and monitor alarm limits
can be entered by a menu driven supervisory program (e.g. ADRACS). The status (overall and de-
tailed) as well as all measured data can be displayed or printed.
− Central remote control and monitoring possibility using the RMMC system (Remote Monitoring
and Maintenance Configuration) at any distance (e.g. dial−up line and auto−dialling). Hence
drastic reduction in maintenance effort. The remote equipment is self testing and signalizes failure
or line interruption.
The DVOR system can be combined with a DME (Distance Measuring Equipment) to form a DVOR/
DME station. Then an aircraft can determine its position by referring to the location of a single DVOR/
DME station.
The DVOR equipment can be supplied already installed in a 10 ft container shelter. The DVOR−anten-
na system is mounted on a counterpoise optionally available in different heights as made necessary
depending on local conditions.
1−2 48 SB Ed. 07.04

DVOR 432
1.2 DVOR/VOR PRINCIPLE
1.2.1 General
Todays airway network is marked by a number of CVOR and DVOR ground beacons operating in the
108...118 MHz frequency range and having a transmission range of up to 300 km (optical propagation
characteristics of VHF). CVOR/DVOR produces an azimuth information which enables the pilot of an
aircraft to fly from one (D)VOR station to another on a preselected course. Deviations from this course
are indicated by an instrument giving the information "fly to the right" or "fly to the left" and also a
"to/from" indication showing whether the aircraft is flying toward the beacon or away from it. The basic
arrangement of a DVOR installation is shown in Fig. 1−2.
Distribution assembly (example)
Antennas
Shelter
Cabinet DVOR incl. ASU
THALES ATM
Counterpoise
DVOR 432
Fig. 1−2 Diagrammatic view of a DVOR installation
1.2.2 Navigation Signal Parameters
As the basis for the explanation of the DVOR method, first the principle of the VOR method is de-
scribed.
1.2.2.1 VOR Method
The RF signal radiated by a VOR is modulated by two 30 Hz sinewaves. Both 30 Hz signals have a
certain phase relationship, which is dependent on the direction from which the signal is received. The
phase relationship is identical to the geographical angle between North and the direction of the air-
craft relative to the ground beacon (azimuth). One of the two 30 Hz modulations is irrespective of the
azimuth (reference signal), whilst the phase relationship of the second 30 Hz modulation to the refer-
ence signal varies with the azimuth (variable signal). The reference signal and the variable signal are
modulated in different ways.
The direction−independent (reference) signal frequency modulates a subcarrier of f0 ±9960 Hz with
a frequency shift of ±480 Hz. The subcarrier is then radiated as amplitude modulation of the carrier
f0 with 30 % modulation depth by a horizontally polarised antenna with omni−directional characteris-
tics. In addition, the carrier f0 is modulated with an identity code (1020 Hz) as well as with voice
(300...3000 Hz).
The direction−dependent (variable) signal is radiated by 2 crossed dipoles. The crossed dipoles re-
ceive sideband signals from the two sideband transmitters with a 90° phase difference in the enve-
lope. The carrier of the sideband signals is suppressed. This results in a signal−in−space with a "fig-
ure−eight pattern" rotating 30 times per second.
Since the carrier f0 is radiated by an antenna with omnidirectional characteristics, the superposition
of the carrier and the 30 Hz sidebands in the field − if the phase is correctly set − produces a pure
amplitude modulation, with the phase of the resulting 30 Hz signal being dependent on the azimuth,
related to the 30 Hz reference signal.
Ed. 07.04 48 SB 1−3

DVOR 432
1.2.2.2 DVOR Method

See Fig. 1−3 to 1−7.
In the DVOR the functions of the two 30 Hz modulations have been interchanged as compared with
the conventional VOR. This means that the 30 Hz modulation which amplitude−modulates the VHF
carrier now acts as the reference signal, whilst the directional, frequency−modulated 30 Hz modula-
tion (variable signal) is contained in the 9960 Hz subcarrier. The modulated carrier signal is trans-
mitted omnidirectionally by a stationary center antenna. It is amplitude−modulated with the voice
(300...3000 Hz) and the identity code in addition to the 30 Hz reference signal. The 9960 Hz subcarrier
signal is transmitted by a sideband radiator, which can be considered to be rotating along a circular
path. The radiated sideband frequency is offset by +9960 Hz or −9960 Hz with respect to the carrier
frequency. If the sideband radiator rotates with a frequency of 30 Hz, the Doppler effect will cause the
subcarrier to be frequency−modulated as a function of the azimuth.
A circle with radius "R" of 7.5...6.5 m is required in the frequency range from 108 to 118 MHz, in order
to obtain the frequency deviation of ±480 Hz stipulated by the ICAO. The equation for determining
"R" is derived from the formula for the Doppler effect.
The different methods used to generate the two 30 Hz signals in the VOR and DVOR is of equipment−
internal significance only. The VOR receiver installed in the aircraft has no means of determining exter-
nally whether the received signal originates from a VOR or DVOR ground station. However the DVOR
permits a considerably more precise azimuth specification thanks to the wide−base antenna system
which can be realized only by utilisation of the Doppler effect. The two 30 Hz signals have a particular
phase relationship with respect to one another and with respect to magnetic north in accordance with
the azimuth. With an azimuth angle of 0° (North) the phase angle between the two signals is 0°. With
an azimuth angle of 180° (South) the phase angle is 180°, with an azimuth angle of 90° (East) it is
90° and with an azimuth angle of 270° (West) it is 270°. The radio reference lines, along which the
azimuth angle remains constant, are radial with respect to the DVOR installation. Fig. 1−3 shows the
phase relationship which is obtained between the reference signal and the direction−dependent sig-
nal in various directions.
N Reference Signal
0°
Variable Signal
270° 90°
DVOR
t t
180°
Fig. 1−3 Azimuth as a function of the phase angle
1−4 48 SB Ed. 07.04

DVOR 432
1.2.2.2.1 Doppler Effect and Direction−Dependent FM
Fig. 1−4 shows generation of direction−dependent frequency modulation with the aid of the Doppler
effect. If omnidirectional antenna A is orbiting mechanically in an anticlockwise direction, the frequen-
cy measured by the two observers B1 and B2 will be increased or reduced due to the Doppler effect
(providing the diameter "D" is negligible as compared with the distance of the observers from the sys-
tem), depending on whether the antenna is moving towards the observers or away from them. The
frequency change f is a function of the orbiting speed or the orbiting frequency fn, the diameter "D"
of the orbit and the mean radiated wavelength 0. The relationship is expressed as follows:
f+p D fn
l0
If antenna A begins its orbit at point 1 and continues via 2 and 3 to 4, the frequencies received by the
two observers B1 and B2 will change as a function of time. If a reference signal with the same frequen-
cy is transmitted at the same time by an omnidirectional, central antenna M, the phase angle between
the reference signal (of antenna M) and the changing frequency (of antenna A) will be in proportion
to the azimuth (observer’s position), i.e. the phase relationship of signal M and A with respect to one
another is a function of the azimuth. The reference point is magnetic north (point 1), where both sig-
nals are in−phase.
1
Movement of radiator A
on a circular path A 1 2 3 4 1
f
t
B1
B1
2
M 4 f
t
B2
D
3 Reference Signal
t
B1 and B2 are reception

points at a great distance B2
from the DVOR installation.
Fig. 1−4 Generation of the direction−dependent FM
It can be seen from the frequency spectrum (Fig. 1−5) that the azimuth−dependent frequency modu-
lation of the DVOR is located on the subcarrier f1= 9960 Hz. The two sidebands (f0+f1) and (f0 − f1)
are generated separately in the DVOR transmitter for this purpose, and radiated via "rotating" outer
antennas. The powers and phase relationships of the sidebands with respect to the carrier are set
such that when added in the farfield an amplitude−modulated composite signal re−emerges.
Ed. 07.04 48 SB 1−5

DVOR 432
If the outer antennas for the two sidebands are then allowed to orbit in an anticlockwise direction, but
with their phases reversed, the requirement for frequency modulation of the sidebands in the double
sideband mode is fulfilled automatically, namely that an increase in the frequency in the upper side-
band must be coupled with a lowering of the frequency in the lower sideband and vice versa.
The depth of modulation of the individual frequencies can be adjusted within certain limits.The values
which apply for the normal cases are:
− 30 Hz navigation signal 30 %
− 9960 Hz auxiliary carrier 30 %
− Voice 30 %
− Identity code 10 %
Reference Signal
(VOR: Variable signal)
(VOR: Reference signal) Carrier (VOR: Reference signal)
Variable signal Variable signal
30 Hz FM 30 Hz FM
ËËËËËË ËËËËËËË
Deviation ±480 Hz Deviation ±480 Hz
ËËËËËË ËËËËËËË
Voice, Identity −30 Hz AM +30 Hz AM Voice, Identity
f0 − 9960 Hz
ËËËËËË f0
ËËËËËËË f0 + 9960 Hz
Subcarrier Subcarrier
Lower sideband Upper sideband
Fig. 1−5 Frequency spectrum of the DVOR (VOR) omnidirectional radio beacon
Composite RF signal
Fig. 1−6 (D)VOR signal amplitude modulated with 30 Hz and 9960 Hz
1.2.2.2.2 Electronic Simulation of the Antenna Movement

See Fig. 1−7.
The subcarrier frequency deviation of ±480 Hz and the carrier frequency range of 108...118 MHz are
the same as with the conventional VOR. Taking a mean carrier frequency of 113 MHz (= 2.65 m) the
equation below reveals that the orbit must have a diameter of 13.5 m:
Df l
D+ ,
p fn
1−6 48 SB Ed. 07.04

DVOR 432
The orbital movement of the sideband signals at an orbiting frequency of 30 Hz is best implemented
by electronic means. 48 fixed, equidistant single antennas are installed on the orbit for this purpose.
They are fed in sequence via an antenna switching unit such that the focal point of radiation orbits
at the desired velocity.
If the double sideband method is used (f0+f1 and f0−f1), the two sidebands whose focal points of
radiation are orbiting in the same direction are transmitted by antennas opposite one another on the
orbital path. To achieve this effect the antenna switching unit activates sideband antenna 1 with the
upper sideband (f0+9960 Hz) and sideband antenna 25 with the lower sideband (f0−9960 Hz) simul-
taneously (Fig. 1−7a). When antennas 1 and 25 reach their radiation peak, the adjacent antennas
2 and 26 are activated. As soon as these reach their radiation peak, the upper sideband of antenna
1 is switched to 3 and simultaneously the lower sideband of antenna 25 is switched to 27 (Fig. 1−7b).
This method of activation of the sideband antennas and the modulation of the sideband signals result
in a continuous, almost smooth orbiting of the focal points of radiation of the upper and lower side-
bands.
1 3 5 7
3 2 1 48 47 t
f0 + 9960 Hz
Upper sideband
2 4 6
M
25 27 29 31
f0 − 9960 Hz
26 28 30
Lower sideband
23 24 25 26 27
t
a) b)
Fig. 1−7 Switching of the sideband antennas in the DVOR
Ed. 07.04 48 SB 1−7

DVOR 432
1.2.3 Monitoring
According to ICAO, Annex 10 all navigation systems must be permanently monitored for correct radi-
ation by an independently operating monitoring system.
In the case of the DVOR this signal monitoring is performed by one or two monitors, whereby signal
components are obtained via equipment−internal coupling circuits and one (or two) monitor dipoles,
and supplied to the monitor.
In case of dual monitoring these are split by the monitor divider switch and transferred to the two moni-
tors, whereby the monitor 1 signal processing is driven by monitor signal processor 1 and the monitor
2 by monitor signal processor 2 in order to select the various signals in accordance with a specified
control sequence. The actual values of the signals are compared with nominal values by the proces-
sor. Any deviation from the nominal values exceeding specified tolerance thresholds always leads to
an alarm and to an automatic switchover to the standby transmitter or shut down of the system.
A special option is the nextfield monitoring facility. Nextfield monitoring is achieved by one or two next-
field dipoles located on the counterpoise edge. The DVOR installation including nextfield monitoring
comprises additional components and supplies for the antenna system.
The nextfield monitoring can be used with or without the standard nearfield monitor dipoles.
1−8 48 SB Ed. 07.04

DVOR 432
1.3 TECHNICAL DATA
The system is compliant with ICAO Aeronautical Telecommunications, Annex 10, Volume 1, Part 1,
5th Ed. July 96 with amendments. It meets the requirements for double sideband systems with 48
sideband antennas and 1 carrier antenna. The DVOR is available in 2 versions: 50 W or 100 W.
The device fulfills the EMC requirements of EC Guideline 89/336/EEC. It bears the CE Designation
and is licensed according to REG TP SSB FL 008 Licensing Test Regulations (see section 1.3.9).
1.3.1 Dimensions and Weight of the Transmitter Rack
Height 1736 mm
Width 611 mm
Depth 661 mm
Weight (100/50 W) approx. 220/200 kg
1.3.2 Power Supply

AC voltage input (with BCPS) 115 VAC to 230 VAC, min 98/max. 264 VAC
48...64 Hz
DC−voltage output BCPS modules (ACC) nom. 48 VDC, max. 12 A each;
fine adjustment for optimal trickle charging,
setting range ±1 V (adaptation to temperature
dependent battery charging voltage)
DC voltage input (system) 43...62 V, e.g. from BCPS
Emergency power supply 48 V battery, standby parallel operation
Power consumption approx. 841 W (DVOR 100 W, excl. battery
recharging, cold standby)
1.3.3 Environmental Conditions

Ambient temperature
Operation indoor ( 1000 m above sea level) −10 to +50 °C (temporary peaks up to 55 °C)
( 3000 m above sea level) −10 to +30 °C
Operation outdoor equipment −40 to+70 °C
Transport −30 to +70 °C
Relative humidity ( 1000 m above sea level) max. 95 % (−10 to+35 °C); max. 60 % (> 35 °C)
( 3000 m above sea level) max. 90 %
Non operation and transport up to 100 % with condensation
Atmospheric pressure
Operation up to 10,000 ft (approx. 3000 m)
Transport up to 50,000 ft (approx. 15000 m)
1.3.4 System Data

Azimuth accuracy Better than ±1° measured over flat ground at
3° elevation and 300 m distance
Azimuth stability Better than ±0.5° measured at the monitor
Coverage Slant distance range in accordance with "23 dBW"
of Fig. C−13, Attachment C to Part I, Vol. I, ICAO
Annex 10, depending on the transmitter power and
the height of the antenna counterpoise above the
ground (3.0 to 10.0 m)
Ed. 07.04 48 SB 1−9

DVOR 432
1.3.5 Equipment Data

1.3.5.1 Carrier Transmitter (CSB)
Radio frequency range 108 ... 117.95 MHz
Channel pattern 50 kHz, defined by synthesizer
Carrier frequency tolerance ±0.001 %
Output impedance 50
Nominal output power 50 W or 100 W

Output power setting of carrier Programmable in steps of 0.1 W
Harmonic of carrier 2.5 x 10−7 W
Spurious 2 x 10−7 W
1.3.5.2 Carrier Modulation
Reference signal
Modulation frequency 30 Hz ±0.01 %
Depth of amplitude modulation 30 % ±1 %, programmable 0 ... 39.9 %
in steps of 0.1 %
Course setting range 0 ... 359.9°, programmable in steps of 0.1°
Identity
Tone frequency 1020 Hz ±0.01 %
Keying (Morse code) Sequence of max. 4 letters, programmable
set time duration (quartz stabilized) Dot/Pause: 125 ms; Dash: 375 ms
Repetition time 7.5 s
Depth of amplitude modulation 0 ... 20 %, programmable in steps of 0.1 %
Voice
Range 300 ... 3000 Hz, flat within ±3 dB
Depth of amplitude modulation 0 ... 40 %, programmable in steps of 0.1 %
Stabilization and linearisation of carrier modulat. With feedback loops for envelope and RF phase
Distortions 3 % for the sum of all harmonic components
Carrier phase stability <±5°, referred to synthesizer reference phase
1.3.5.3 Sideband Transmitters (SB1/SB2)

Sideband offset of carrier
Upper sideband +9960 Hz ±1 Hz
Lower sideband −9960 Hz ±1 Hz
Output impedance 50
Output power 0 ... 15 W or 30 W depending on the carrier power,
programmable in steps of 0.5 %
RF phase setting range SB1 0 ... 359°, programmable in steps of 1°
9960 Hz harmonics 2nd harmonic −40 dB
3rd harmonic −50 dB or less
4th harmonic −60 dB
and above
Phase stability of sideband <±5° (difference USB−LSB)
1−10 48 SB Ed. 07.04

DVOR 432
1.3.5.4 Sideband Modulation (Blending)
Modulation frequency 720 Hz for upper and lower sideband,
sine and cosine half−wave
Blending function Sine/cosine half−wave; other functions
programmable as option
Level programmable in steps of 1 %
Depth of amplitude modulation > 99 %
1.3.5.5 Monitoring
Azimuth measurement range 0 ... 359.9°
Azimuth measurement accuracy ±0.15°
Available monitor channels Maximum 2 RF−channels
Alarm conditions In accordance with recommend of ICAO Annex10
Monitor signal processing: S Time multiplex
S Fourier analysis of sideband signals
S Numerical comparison of significant DVOR
parameters and programmable alarm limits
S Precautionary alarm for azimuth
S Programmable alarm delay
S Monitor self test
Alarm and Warning limits:
Carrier RF−level Programmable upper and lower limits in
steps of 1 %; measurem. range 0...199.9 %
Azimuth Programmable upper and lower limits in
steps of 0.1°; measurem. range 0 ... 359.9°
30 Hz FM deviation (Var.) Programmable upper and lower limits in
steps of 0.1; measurem. range 0 ... 25
30 Hz AM depth (Ref.) Programmable upper and lower limits in
steps of 0.1 %; measurem. range 0...39.9%
9960 Hz AM depth (Var.) Programmable upper and lower limits in
steps of 0.1 %; measurem. range 0...39.9%
Identity Programmable upper and lower limits for
Mod.aDepth; Alarm if coded identity is not present
Alignment and performance measurement Various measurement data can be displayed
via PC and ADRACS−software
1.3.5.6 BIT and Measuring Functions
Digital subfunctions GO/NO GO bits displayed in BIT words
Analog subfunctions Analog test signals sampled periodically, then
digitized and evaluated via BIT subroutines
Fault location Via PC and ADRACS−software by interrogation
down to LRU−level (Line Replaceable Units)
1.3.5.7 PIN−Diode Switching Unit (PDSU)
Housing, to be mounted below counterpoise 721 x 491 x 210 [mm] (WxDxH), approx 45 kg
Number of RF switches 48 for supplying the antennas with upper and
lower sidebands; impedance 50
Switching frequency 720 Hz ±0.01 %, phase−locked with 30 Hz
reference signal
FM synchronization 25 steps, selectable and programmable
Ed. 07.04 48 SB 1−11

DVOR 432
1.3.6 Antenna System

1.3.6.1 General Characteristics
Dimensions of the individual antenna
Diameter 0.8 m
Height 1.4 m
Temperature range −40 ... +70 °C
Relative humidity 0 ... 100 %
Weather protection Glass−fiber−reinforced polyester cover

Wind load (operational) Up to 160 km/h
Hailstones Up to 1 cm diameter without damage to radome
Collocation of DME antenna Mast, secured to the edge of the counterpoise

Collocation with TACAN antenna Secured to a non−metallic base above the carrier
antenna (center of antenna circle)
Antenna counterpoise
Diameter of counterpoise 26 m (optional: 30 m), 12−sided
Height above ground 3 m, 5 m, 7 m, or 10 m
Diameter of sideband antenna circle 13.5 m, for generation of a modulation index of
16 ±1
Materials
Supports Galvanized iron construction
Decking Galvanized welded wire mesh, mesh size
100 x 100 mm
1.3.6.2 Electrical Data

Antenna elements
Type Alford loop antenna
Frequency range 108 ... 118 MHz
Impedance 50
Polarization omnidirectional horizontal
Suppression of vertical polarization >40 dB
Decoupling >20 dB
Active return suppression Via optional decoupling module in each antenna
supply line
Cone of silence ±30° off vertical
Deviation from horiz. omnidirectional pattern <±0.5 dB in magnitude
<±5° in phase
1.3.6.3 Monitor Dipole

Type (Nearfield Monitor) Yagi antenna
Location At least 200 m (650 ft) from the carrier antenna;
shorter distances permissible for special applica−
tions on request
Number 1 or 2 (different azimuth angles)
Optional: Nextfield Monitor up to 3 monitor dipoles mounted at the edge of
the counterpoise
1−12 48 SB Ed. 07.04

DVOR 432
1.3.7 Interfaces
− PC connector*/** Serial, SubD, 9 pin, male on top of the cabinet
− MODEM connectors*/*** 2−wire, via SubD, 9 pin, male, on top of the cabinet
LGM1 (opt.) 2−wire dedicated line or 2−wire switched line
LGM2/DME (opt.) 2−wire switched line or configured as
RS232 interface
LGM3/NDB (opt.) 2−wire switched line or configured as
RS232 interface
− Input voice or ATIS for VAM (opt.)*/*** 2−wire, acc. CCIT M1040, via SubD, 9pin, male,
on top of the cabinet, to input transformer
at BP−C on the rear side of the cabinet
Input level (incl. transformer) min. 80 mV (−20 dBm), threshold noise
suppression
max. 5 V (+16 dBm)
Input impedance 600 Ohms
− DME−Interface: SubD, 37 pin, male, at top of cabinet
input optocoupler log 0= max. 1 mA
log 1= max. 10 mA
output optocoupler max. 35 V/150 mA
− LCP (spare in/out) OIO IN/OIO OUT SubD, 25 pin each, male/female, on top of cabinet
input optocoupler (16x) log 0= max. 1 mA
log 1= max. 10 mA
output optocoupler (16x) max. 35 V/150 mA
* according EN60950 (IEC950) ** SELV−circuit (Safety Extra Low Voltage) *** TNV−circuit ( Telephone Network Voltage)
1.3.8 Notes on "Standby" operational Mode

The NAVAIDS Technical Manuals distinguish between the hot standby and cold standby operating
states as follows:
" Hot Standby
− Both transmitters are in operation − i.e. one transmitter is connected by means of a command to
the antenna (aerial), the second is connected to a dummy load (standby).
In NORMAL operation mode the Monitor Bypass is off. If the radiating transmitter fails, the system
automatically switches the antenna to the standby transmitter. The switch over time is 20 ms.
ILS installations are generally operated in the hot standby mode.
" Cold Standby
− One transmitter (TX1 or TX2) is in operation (i.e. connected to antenna or to dummy load), the sec-
ond is switched off by means of a command.
If the radiating transmitter fails, the monitor and controller ensure connection and initialisation of
the standby transmitter and antenna switch−over. This process takes about 6 seconds.
VOR and DVOR installations are generally operated in the cold standby mode.
REMARK: The desired standby mode can be selected by means of a SW command. A modification
can be easily performed. For VOR/DVOR the "Hot Standby" is only available in Mainte-
nance mode. It is not available for operational mode.
Ed. 07.04 48 SB 1−13

DVOR 432
1.3.9 Conformity and Licensing Approval
The DVOR 432 device of the Navaids air navigation system complies with the requirements of EC
Guideline 89/336/EEC in its implementation.
Individually, the device fulfills the requirements of the following EMC Guidelines:
− EN 55022 Ed. 1998 Interference Transmittal, Class B
− EN 50082−1 Ed. 1997 Interference Resistance
− ETS 300 339 Ed. 1998 EMC for Radio Transmission Devices
− EN60950 (IEC950) Device Safety
Furthermore, the device fulfills the requirements of the REG TP SSB FL 008 Licensing Test Regula-
tions for the radio transmission interface.
1−14 48 SB Ed. 07.04

DVOR 432
1.4 SAFETY PRECAUTIONS
1.4.1 Operating at the Device
The supply voltage should always be disconnected by actuating switch TX1 or TX2 on the PMM sub-
assembly before removing a subassembly or a plug−in connection in order to avoid injury to persons
or subsequent damage to subassemblies (for exceptions see Part 2, Operation and Maintenance,
Chapter 6).
WARNING
Mains subunit ACC (BCPS): The device should be disconnected from the mains before
commencing maintenance or installation operations.
The heat sinks of the modulators (MOD−110P) and of the carrier amplifier (CA−100C)
may warm up during operation. This is normal and does not have any affect on the func-
tioning of the devices. Avoid touching the heat−sinks when the cabinet door has been
opened for any reason. When replacing this subassemblies it is recommended to let
them cool down for a while or take suitable measures (e.g. gloves). When replacing the
subassemblies SYN and CCP avoid touching the heat sinks of the MOD−110P.
1.4.2 Handling Subassemblies
When replacing subassemblies and plug−in cards containing electrostatically sensitive compo-
nents, special precautionary measures should be taken during removal, transport and installation in
order to prevent damage to the components.
PCB’s containing electrostatically sensitive components are marked with this symbol:
This type of damage may be caused when the person performing the subassembly replacement
bears a static charge due to friction with an insulated floor covering or with synthetic articles of cloth-
ing (eg. soles) and the charge is transferred to the terminals of the MOS components.
In order to avoid this, positive contact should be made between tsystem ground and the hand before
and during removal or insertion of the subassembly. Any body charge is then discharged to the sys-
tem ground. When the subassembly has been removed, the short−circuit bar provided should be
connected to the connector strip, and the subassembly placed in a special container or envelope.
When the subassembly is inserted the appropriate procedure should be followed. The sequence is
described below:
− Discharge the body by touching the system ground with both hands,
− Remove the subassembly from the special container,
− Remove the short−circuit bar from the subassembly,
− Touch the device ground,
− Insert the subassembly, if possible whilst retaining contact with the device ground.
Further instructions on this type of safety measure can be found in the Technical Manual, Part 2.
Ed. 07.04 48 SB 1−15

DVOR 432
1.4.3 Handling Lead Batteries
WARNING
Before starting up a battery, i.e. before filling an empty battery with acid, the relevant in-
structions in Part 2 should always be observed.
Protective goggles should be worn for all maintenance operations which involve opening the acid
screw caps. Any acid which spatters should be removed immediately from the clothing by washing
with water or any soda solution (100 g soda to 1 l water) on account of its highly caustic effect. Penetra-
tion of soda or soda solution into the cells should be avoided at all costs.
When the emergency battery is charged up during mains operation oxyhydrogen gas can result from
the decomposition of the water. For this reason the ventilation holes on the outside of the battery box
should not be sealed.
1.4.4 Components with Beryllium Oxide Ceramic
Some subassemblies in NAVAIDS installations are equipped with transistors containing beryllium
oxide. These transistors are in accordance with the latest state of the art and are used all over the
world.
The ceramic components with beryllium oxide incorporated in the transistors are completely harm-
less in a solid, compact state. The transistors mentioned in the table should never be dismantled or
shattered. Please take notice that if any of these transistors are opened, care should be taken to avoid
any beryllium oxide dust being produced as this is harmful to health.
This notice should also be observed when the components are scrapped or disposed of.
Beryllium oxide is contained in the high−power transistors listed below:
Transistor Type Code Number Used in Unit Code Number
BLF242 MOD−110 83134 26100

BLF245 MOD−110 83134 26100
BLF244 MOD−110P 83134 26200
BLF246 MOD−110P 83134 26200
BLF248 CA−100C 83134 30100
Fig. 1−8 Components with beryllium oxide ceramic
1−16 48 SB Ed. 07.04

DVOR 432
1.4.5 Using Lithium Batteries
Always read the label on the battery. Thales ATM recommends only those with lithium copper oxide.
Other types of lithium battery, e.g. those with lithium sulphur dioxide, are not approved by Thales ATM
for use in navigation systems (see also instructions in Part 2, Operating and Maintenance, Chapter
6).
WARNING
Do not recharge, disassemble, heat above 100 °C or incinerate any lithium cell. Do not
short−circuit the cell or solder directly on it. Disregard of the norms regarding the use of
lithium batteries may cause the risk of fire, explosion and the leakage of toxic liquid and
gas. Run−down batteries are objects that can pollute the environment and must be dis-
posed of taking the proper precautions.
1.4.6 Miscellaneous
During thunderstorms work outside the shelter or on the antenna system is not allowed due to the
risk of lightning.
1.4.7 Observation of Safety Regulations
In addition to the above−mentioned instructions for avoiding damage and injury, locally valid safety
regulations should always be observed.
Ed. 07.04 48 SB 1−17

DVOR 432
1−18 48 SB Ed. 07.04

DVOR 432
Equipment Description Functional Description
1.5 FUNCTIONAL DESCRIPTION
1.5.1 General
The Navaids system consists of hardware based on RF and AF subassemblies and of software which
controls the hardware to a large extent. The system is subdivided into the following units:
− Transmitter in dual or single version (TX1, TX2)
− Monitor in dual or single version (MSP1, MSP2)
− Local/Remote Communication Interface (LRCI)
− Power supply
− Antenna switching control and RF distribution
− Antenna system
Transmitter and monitor are controlled by own individual microprocessors. Both communicate via the
LRCI. The transmitter processor performs the following tasks:
− Digital signal generation
− Control/adjustment of amplitude (envelope), RF phase and phase polarity
− Calculation of the settings for the transmitter subassemblies
− Communication
The monitor processor performs the following tasks:
− Processing and evaluation of the signals of the field dipole(s)
− Execution of suitable actions in case of fault detection (station changeover or shut down)
− Ensuring its own performance independent of environmental conditions and component aging
The antenna switching control performs the following tasks:
− Generating and processing the RF and switching signals for the PIN−Diode Switching Unit
(PDSU), which is located externally and distributes the sideband signals to the SB−antennas.
The Navaids software packages (i.e. transmitter SW, monitor SW, LRCI SW and ADRACS) looks after
and supports the most important tasks as follows:
− Startup (alignment and calibration of the antenna system and the navigation system)
− Modulation and transmitter control
− Signal generation
− Monitoring the navigation signal
− Support in system repair and maintenance
− Operation of the system (local/remote)
1.5.2 Brief Description

See Fig. 1−9.
Fig. 1−9 shows the basic structure of a DVOR system. Transmitter and monitor are dualized, whereby
each monitor monitors the aerial transmitter. The remaining subassemblies in the signal path of the
transmitter are not dualized. These are mostly components which cannot be practically dualized,
such as RF duplexer, antenna switching control and RF distribution, the antennas and cables and the
main passive components which are inherently reliable.
Each transmitter comprises an RF section, in which the carrier frequency is generated, modulated
and amplified to the output power level, and the Modulation Signal Generator, which generates the
modulation signals controlled by its microprocessor, carries out the evaluation for control of the signal
shape (amplitude/phase) and supplies control signals to the RF section. Each transmitter has a sepa-
rate power supply. If one transmitter fails, the other remains operational.
Ed. 07.04 48 SB 1−19

DVOR 432
Functional Description Equipment Description
The RF Duplexer supplies the signal of one transmitter to the antennas via the PIN−Diode Switching
Unit (PDSU), while the output power of the standby transmitter is switched to a dummy load. Ampli-
tude and phase are controlled such that the specified signal−in−space pattern is obtained. The two
monitors monitor the generated and radiated DVOR signal directly by one (or two) nearfield dipole(s).
As an option up to three nextfield dipoles located at the counterpoise edge can be used instead of
the nearfield dipole.
The monitor consists of the Monitor Signal Processor, which ensures of correct radiation of the signal.
It evaluates the signals of the internal sensors and the field dipole(s). The selected RF signals are am-
plified, normalized to a certain level, demodulated, filtered and converted to individual, digital values.
The Monitor Signal Processor evaluates the measured values by means of a Fourier analysis and
compares them with the reference values. The monitor changes over or shuts down the transmitter,
if a limit is exceeded. The results can be read out and interpreted locally or remotely via a connected
PC equipped with the suitable software (e.g. ADRACS). A system status indication is also displayed
on the local indication panel. The monitors exchange status signals. If one monitor fails, the intact
monitor decides immediately without waiting for a response from the other. This ensures that the mon-
itors react fast and correctly in all situations, even if one of them fails. The transmitters and the moni-
tors are independent of one another. Depending on the stipulated safety class, either one or two moni-
tors are provided.
The LRCI makes available the following interfaces:
− Communications of the individual functional groups
− Controls for the equipment
− local display and local control of the equipment for the operator
− Remote control functions
All relevant data or parameters can be set locally or remotely via an intelligent terminal (PC/Laptop).
A change−over or shut down is also possible. For integrity reasons data entry (input/change) is only
possible in the maintenance mode (monitors bypassed). Access to the system is barred by a pass-
word procedure with different security levels. The software to be used is referred to as ADRACS.
The battery−charging power supply (BCPS) supplies the entire system with the DC supply voltage
(nom. 48 V). The BCPS can be connected to a mains input voltage in the range from nominal 115 VAC
to 230 VAC. A floating battery connected in parallel ensures that the power supply is uninterruptible.
The BCPS applies the correct voltage required to keep the batteries fully charged. The construction
of the BCPS is modular, with a building−block concept allowing up to four 12 A modules.
Up to three modules (usually provided) are allowed to be used for a mains voltage of 115 VAC with
the normal wiring concept. For a 115 Vac supply with four modules provided, standard mains wiring
has to be adapted concerning diameter of supply cables, size of mains terminals and mains filter.
1.5.3 Peripheral Subassemblies
The main switch on the PMM (Power Management Module) switches on directly the power supply for
both monitors and the LRCI.
1.5.4 General Block Diagram
Fig. 1−30 provide an overview of the subassemblies and signal flow in the DVOR system.
1−20 48 SB Ed. 07.04

DVOR 432
ANTENNAS (DVOR)
CENTRE ANTENNA SIDEBAND ANTENNAS FIELD DIPOLE 1 FIELD DIPOLE 2
CARRIER 1...48 (optional)
ASU
PIN−Diode Switching Unit (PDSU)
control CSB SB1 SB2
PDSU−Control and RF−supply

Signal divider*
RF−DUPLEXER
CSB
CSB
SB1
SB2
SB1
SB2
TRANSMITTER 1 TRANSMITTER 2 MONITOR 1 MONITOR 2
RF RF
Signal Generation Signal Generation
and and
Amplification Amplification
Modulation Signal Modulation Signal Monitor Signal Monitor Signal

Generator Generator Processor Processor
DC/DC−Converter DC/DC−Converter DC/DC−Converter DC/DC−Converter
48 VDC nom.
(53,5 VDC) Local/Remote Communication Interface
DC/DC−Converter
Battery Charging Power Supply

Cabinet
Emergency Battery 48 V
Mains Telephone line RS 232
115/230 VAC Remote Control Local PC
* Signal divider to both monitors, if only one field dipole is used (standard).
Fig. 1−9 Basic structure of a DVOR system
Ed. 07.04 48 SB 1−21

DVOR 432
1−22 48 SB Ed. 07.04

DVOR 432
1.6 FUNCTIONAL DESCRIPTION OF THE TRANSMITTER
This functional description of the transmitter provides an introduction to the signal generation and
conditioning. It will be of use in understanding the subsequent chapters, since certain relationships
are discussed in advance. Remark: In DVOR, the sidebands SB1, SB2 are assigned to ’USB’, ’LSB’.
1.6.1 DVOR−Transmitter Signals for the DVOR Antenna
See Figs. 1−10, 1−11.
The DVOR radiates a radio frequency carrier with which are associated two separate 30 Hz modula-
tions. One of these modulations is such that its phase is independent of the azimuth of the point of
observation (reference phase). The other modulation (variable phase) is such that its phase at the
point of observation differs from that of the reference phase by an angle equal to the bearing of the
point of observation with respect to the DVOR. Compared to a CVOR station for the DVOR system
both 30 Hz modulations are reversed. The conventional VOR is more sensitive for multipath reflec-
tions from fixed object, near and distant, such as trees, power lines, buildings and mountains which
rise the bearing errors. The improved radio navigation beacon DVOR relies on the Doppler change
in frequency which would result if a radiation antenna is moved around a large diameter circle. If the
antenna is rotated 30 times a second, the signal at a distant observation point will be frequency modu-
lated at a 30 Hz rate. The modulation index is determined by the diameter of the circle.
N
Reference signal
Variable signal
0 0°
N t

270° (D)VOR
W O 90°
t t
S
180°
t
Fig. 1−10 Azimuth angle between aircraft and ground station

The effect of a rotating antenna is simulated by using a ring of antennas and switching the RF signal
to each in turn. Provided sufficient antennas are used and the pulse RF energy is suitable shaped,
the simulation is good. The shape of the modulation envelope is called the ’blending function’. The
azimuth−dependent information is contained in the phase of the frequency modulation.
The reference phase of the 30 Hz amplitude modulated carrier signal is radiated from a single antenna
at the center of the ring. The aperture of the Doppler VOR antenna is much more greater than in con-
ventional equipments. By virtue of the resulting ’space diversity’, effects due to reflections are greatly
reduced. The bearing information is inherently determined by the geometry of the antenna array and
since the Doppler VOR array is large it can be made very stable and accurate.
The DVOR 432 is a Double Sideband DVOR system (DSB DVOR) and is full compatible with all exist-
ing airborne VOR receivers. In a DSB DVOR system signals 9960 Hz above and below carrier fre-
quency (Upper Sideband → USB / Lower Sideband → LSB) are radiated simultaneously from 48 side-
band antennas diametrically opposed to the ring. Both sidebands are commutated at 30 Hz in the
same direction.
Ed. 07.04 48 SB 1−23

DVOR 432
At the receiver, the 9960 Hz signals resulting from the combination of the carrier with each sideband
add in phase.
Monitor dipole (distance typically 200 m)

DME antenna (optional)
Ring of 48 sideband antennas Centre antenna (carrier)

PDSU (example location)
Counterpoise
Fig. 1−11 Arrangement of the electronically rotated DVOR antenna
1.6.2 Signal Generation in the Transmitter of the DVOR 432

See Fig. 1−12, 1−13, 1−14.
The audio modulation signals for the carrier signal are generated digitally in the block Modulation Sig-
nal Control and Measurement. The signal generation control is done by microprocessor techniques.
Control loops including measurement circuits are used to generate the RF−signals for carrier (CSB),
upper sideband (USB) and lower sideband (LSB) feeding the DVOR antenna system via the PIN−
Diode Switching Unit (PDSU). The carrier and sideband frequencies are generated by a synthesizer,
which delivers its output signals to three modulator modules. One modulator together with the carrier
amplifier (CA−100C) is used to generate the carrier signal with 30 Hz sidebands (CSB). The remaining
two modulators generate USB and LSB. Both sideband output signals of the sideband modulators
are continuous wave (cw = not modulated).
The modulators amplify the RF−frequency signal from the synthesizer and the RF−amplitudes and
envelopes are controlled by the modulation signal generator and control circuits. Bidirectional cou-
plers are used to get probes of the actual signal amplitude. By comparing the actual signal values
with programmed values within the memory of the microprocessor, the control voltages are derived
by the microprocessor and fed back to the modulator modules. To get the required output power a
carrier amplifier (CA−100) is used to amplify the CSB up to 100 W. The Modulation Signal Control
and Measurement is realized within the DVOR 432 equipment with the modules Modulation Signal
Generator (MSG) and Control Coupler (CCP). The kind of realization is described below.
1−24 48 SB Ed. 07.04

DVOR 432
DVOR Antenna System

...
PIN−Diode Switching Unit (PDSU)
RF processsing
Carrier Amplifier Carrier

Modulator CA−100 CSB
Upper sideband
Modulator RF
USB (SB1) Duplexer
Synthesizer D
REF
Lower sideband
Modulator
LSB (SB2)
Modulation Signal Control and Measurement Antenna switching control
Fig. 1−12 Generation of the modulated RF CSB, unmodulated USB (SB1) and LSB (SB2)
signals; feeding of the antenna via PDSU
The sideband signal blending modulation and antenna switching control is implemented in the trans-
mitter cabinet. The signal processing of the antenna switching control has the task to process the USB
and LSB cw signals in a form to get the required feeding signal for the even and odd sideband anten-
nas. The basic signal processing concept for one sideband (USB) is shown in Fig. 1−13. The signal
processing for the second sideband is identical. In addition the phase relation USB to LSB with re-
spect to the carrier is measured for phase control purposes. The PIN−Diode Switching Unit assem-
blies are used to commutate the blended sideband signal to the sideband antennas. The blending
function itself is optimized to get a smooth transition and a minimum of spurious modulation on the
9960 Hz amplitude modulation.
Carrier antenna A49
(+47 dBm) A10
CSBin A09
A08 Sideband antennas
CSB
PIN−Diode Switching Unit A07
Z2 A06
26 dB Blending A05
Modulator
CSB cos A04
Z1 USBout ASM A03

USBin
3 dB
A02
Blending
Z3 Modulator A01
20 dB sin
USB incident CSB (15 dBm) + USB reflected ASM
3 dB SIN blending COS blending
Detected Coupler odd antennas even antennas
USB
LO
10 kHz Bandpass
USB 10 kHz TP2 IF RF −5 dBm
A01 A03 A05 A07

A02 A04 A06 A08
Fig. 1−13 Concept of sideband signal processing
Ed. 07.04 48 SB 1−25

DVOR 432
For simplification, the selected complex blending functions are defined here as a cosine and a sinu-
soidal waveform (cos and sin). With respect to one sideband (e.g. LSB), cos−blending is used for
the odd and sin−blending for the even antennas. The commutation to the second antenna is acti-
vated at the minimum of the blending function. The realization in form of a block diagram is shown
in Fig. 1−14. Modular designed Antenna Switching Modules (ASM) in form of 2P12T−switches are
used to commutate the RF signals to the 48 sideband antennas. Two ASM for the even and another
two ASM for the odd sideband aerials are connected to the aerial via the feeding cables. Two ASM
circuitries are built each by the Commutator board ASU−C a and b. The sin−blended USB−signals
and sin−blended LSB−signals are radiated from the even sideband antennas. The cos−blended
USB−signals and cos−blended LSB−signals are radiated from the odd antennas. The carrier an-
tenna in the center of the ring has the number 49 (A49). The Blending Modulators (MOD−SBB) are
based on an absorptive modulation concept. PIN−diodes are used to modulate the sideband signals
in a way to keep the VSWR at the input and output constant at an impedance of 50 Ω. The Phase−
and Monitoring Control module (PMC−D) is used to extract the differential RF phase. Due to the num-
ber of 2 times 24 sideband aerials, the commutation clock must be 720 Hz and is generated on the
Blending Signal Generator board (BSG−D).
Each ASM−module gets its switch commands from the BSG−D. The switch commands generated
by frequency counters on the BSG−D are synchronized by a 30 Hz signal coming from the MSG of
the active transmitter and are synchronized with the 30 Hz AM on the carrier signal.
The digital generated blending waveforms (sin/cos) for the MOD−SBB are produced on the Blending
Signal Generator board (BSG). The blending function is stored in an EPROM which is addressed for
readout by a frequency counter. With control data coming from the µP of the Modulation Signal Gener-
ator via the ASU−Interface (on PMC−D) the amplitudes of the four different blending signals are ad-
justed during installation to get the correct 9960 Hz amplitude modulation in the radiated farfield of
the DVOR station.
A49
A02
ASU−C a
MOD−SBB
Carrier (CSB) CSB ASM
SIN SP12T
USB (SB1) DPDT

USB switch A24
Circ. A26
COS
LSB (SB2)
LSB
Circ. ASM
SP12T
MOD−SBB A48
A01
SIN ASU−C b
DPDT
switch ASM
COS SP12T
A23
A25
8+4 bit ASM

Control Data SP12T
TX1 30HZE
PMC−D BSG−D
TX2 (incl. ASU interface) to/from ASU−INT (incl. switch control) 30HZO
48V A47
30 Hz Sync.
+5 V
ASU−CIF −15 V
Transmitter cabinet Antenna Switch Control PDSU
Fig. 1−14 Antenna Switching Unit subassemblies (ASU), block diagram
1−26 48 SB Ed. 07.04

DVOR 432
1.6.3 Digital controlled Transmitter RF−Signal Generation
1.6.3.1 Basic Concept
See Fig. 1−15.
A frequency synthesizer module for the frequency range from 108 MHz to 118 MHz generates the RF−
frequencies of the specified frequency channel in conformance with the international standards of
ICAO Annex 10 Volume I. For the DSB DVOR, the carrier frequency as well as upper and lower side-
band frequencies have to be generated. An RF−Modulator modulates and amplifies the synthesizer
output signal according to the system power requirements. The modulator has control inputs for
− the amplitude (envelope),
− the RF−phase and
− the polarity of the RF−phase.
The control signals of the modulator are generated under the supervision of a microprocessor (µP
Intel 80186) which has the ideal 30 Hz reference signal stored in its program memory. For the DVOR
sideband signals the dc control voltage for the cw RF output power is loaded into a data register. Also
the sideband RF phase control voltage is set via a data register. At the output of the RF−Modulator
a directional coupler couples out at the incident port a probe (−20 dB) of the output signal which is
fed to the ASU. The incident signal gets amplitude demodulated and A/D−converted with a defined
fixed sampling rate for further processing by the microprocessor. The actual measured signal param-
eter under control (amplitude) is compared against the operator programmed reference data.
Data In/Out DVOR Antenna
ASU Control
ASU
D/A Converter
P 80186 Data Register Modulator USB
1 SBA
Phase reversal
D/A Converter Phase Control

Sinus table Data Register 2
(ROM) Carrier LSB RF (USB)
Synthesizer
108 − 118 MHz
RF Reference LSB
D/A Converter
1 Control Coupler
P−Bus
Fig. 1−15 Generation of sideband signals (example USB)
1.6.3.2 Sideband Signal Control

For the DVOR system three different RF signals have to be generated and controlled (see table 1).
With the aid of an RF−multiplexer at the input of the circuits for the precision amplitude detection the
same circuits are used for all three transmitter signals. While the reference value for the amplitude
control is a defined selectable voltage, the reference value of the phase is a selected − system defined
− phase difference between the vector sum of the carrier signal to the upper sideband (USB) and the
vector sum carrier signal to lower sideband (LSB).
Ed. 07.04 48 SB 1−27

DVOR 432
The differential phase measurement is executed in the DVOR ASU by a time interval counter, which
counts the 9960 Hz phase difference between the down−converted USB− and LSB−9960 Hz sig-
nals. During installation of the DVOR the RF−phase gets aligned and is than controlled to this aligned
phase value by the µP of the MSG. The control procedure is such, that only the RF−phase of the USB
is controlled while the phase of the LSB−signal is set to the midpoint of the control voltage of the
analog phase shifter of the MOD−110. The DVOR−signals with the quantizing used for the digital
signal generation are shown in the table below.
DVOR−Signals Modulation Number of Samples Amplitude− Phase−

per 360° of 30 Hz Quantization Quantization
Carrier Signal 2 024 (11 Bit) 2 048 (11 Bit) analog controlled
USB−Signal (SB1) DC 1 4 096 (12 Bit) 4 096 (12 Bit)
LSB−Signal (SB2) DC 1 4 096 (12 Bit) 4 096 (12 Bit)
Table 1 DVOR−signals to the ASU
The DVOR sideband signals USB and LSB generated by the transmitter are single sideband signals
(SSB−signals). The RF frequencies are 9960 Hz offset from the carrier frequency. Adding finally the
signal processed USB− and LSB−signals to the carrier in the radiated field, the double sideband
DVOR signal is generated.
1.6.3.3 Carrier Signal Generation

See Fig. 1−16.
In addition to the circuit shown in Fig. 1−15 used for the amplitude and phase control of USB and
LSB the feedback loop for the Carrier Signal is realized as an analog control circuit. A control amplifier
(part of the Modulator 110) receives the detected output signal and delivers the control voltage ac-
cording to the digital controlled reference input to the modulator. This analog control is necessary
due to the characteristic of the voice signal which is not periodic.
The Random Access Memory has stored the 30 Hz−periodic DVOR reference signal with the defined
30 Hz AM, the data for the identity signal (ID) are also loaded into a RAM and gets amplitude controlled
by the multiplying D/A−Converter, and both signals are added together by the summing amplifier.
In configurations where a voice signal is specified, also the level−controlled voice signal is added.
While the sideband signals USB and LSB have only the cw−modulation the carrier signal has besides
the 30 Hz AM reference signal in addition an amplitude modulation for the coded station identity signal
and optional with a voice signal (ground to air communication).The various modulation signals being
individual controlled in its amplitude (multiplying D/A−converter) are added together and build the
reference for the analog control loop for the carrier envelope.
The synchronism of the carrier AM signal to the sideband commutation of the ASU is achieved by a
30 Hz trigger signal to the ASU. The control procedure for the carrier RF−phase is not shown in Fig.
1−16. The carrier RF−phase is also controlled like the amplitude by an analog feedback loop. The
RF−reference signal (shown in Fig. 1−15) is used within the control coupler module to get the zero
IF−signal of the output of the carrier amplifier. The amplitude of this zero IF−signal will only be zero
volt, if the carrier signal is in phase quadrature to the RF−reference signal. This criteria is used to con-
trol the carrier RF−phase.
1−28 48 SB Ed. 07.04

DVOR 432
Carrier Antenna (A49)
Frequency
RF Modulator
Synthesizer
Control Amplifier Demodulator
Summing Amplifier
D/A Converter D/A Converter D/A Converter A/D Converter
ID tone RAM Voice Amplifier Navigat. Reference Signal

RAM
Microprocessor System
PTT−Line 80186
Modulation Address Counter
Modulation Signal Generator
Fig. 1−16 Generation of the DVOR carrier signal

With the kind of digital signal processing described before with high resolution A/D−converters and
D/A−converters (12 bits) the RF transmitter signals have optimal performance data with respect to:
− the audio phase and audio frequency accuracy and stability,
− the stability of the amplitudes for carrier and sideband signals,
− the RF−phase and frequency accuracy and stability and
− the distortion factor.
1.6.4 Modulation Control Realization with Microprocessor Techniques

See Fig. 1−17.
The control procedure is implemented by the use of a microprocessor, type Intel 80186. As described
before the way to achieve the real time control is the application of an addressing counter which con-
trols the readout of all the Random Access Memories (RAM) for the carrier modulation signal genera-
tion. The data content of the RAM defines the actual amplitude for the cell being addressed by the
address counter and the clock for the address counter is a binary multiple of 30 Hz (218 S 30 Hz). For
the DVOR, the waveform is a 30 Hz sinewave the signal is according to Fig. 1−17. The data content
of the RAMs for the modulation signals are fixed for the analog controlled carrier signals. The purpose
of the continuous modulation control updating is to compensate nonlinearities of the semiconductors
used to generate the transmitter signals. The nonlinearities would result in distortions and the genera-
tion of undesired harmonics of the audio signals. As described before, the DVOR transmitter gener-
ates signals as shown in the table 2 below.
DVOR−Signals Modulation Number of Samples Amplitude− Phase−

per 360° of 30 Hz Quantization Quantization
Carrier Signal 30 Hz AM, 16 348 (15 bit+Sign) 2 048 (11 bit) analog controlled
1020 Hz ID, composite signal
300 Hz to 3 kHz Voice analog controlled
Upper Sideband DC 1 4 096 (12 Bit) 4 096 (12 Bit)
Lower Sideband DC 1 4 096 (12 Bit) 4 096 (12 Bit)
Table 2 DVOR transmitter signals
Ed. 07.04 48 SB 1−29

DVOR 432
1
0.5
S12 (t) 0
−0.5
−1 t
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035
1/30 s
2048
1536
1024
512
t
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035
Fig. 1−17 Address Counter and RAM data
The control process is implemented in time multiplex mode for the individual signals, with measure-
ments and data register updates of control data in a sequence of:
− Carrier RF−phase (measurement only)

− USB−amplitude
− LSB−amplitude
− USB−phase (differential phase correction)
Besides the sideband modulation control function the microprocessor of the Modulation Signal Gen-
erator controls also the measurements of various internal signals of the transmitter as a Built−In Test−
function (BIT−function). The signal measurements are accomplished by the same A/D−Converters
as used for the modulation control signals. To achieve this, in front of the A/D−Converter an analog
multiplexer is used to select the desired signal. The BIT check against BIT warning limits gives an indi-
cation of non normal functional performance and allows to optimize maintenance and eases fault
location of defective modules. The processor internal BIT−check is executed interrupt controlled 5
times per second. In addition with 1 ms intervals the ID coding is controlled.
Since amplitude measurements of the sideband signals close to the zero crossings are inaccurate,
the control voltage is linearized by a special sw−routine in these zones. Starting at fixed interpolation
point addresses to the left and right of a zero crossing, it draws a straight line through the crossing
(i.e. it replaces the sine with its argument).
The procedure for phase control is similar, since the actual values available in the zero crossing region
are likewise inaccurate. Here, the control voltage is formed with the aid of interpolated values to the
left and right of the crossing. Since the amplitude−dependent phase shift in the modulator is small,
the phase control voltage only needs to be pre−distorted slightly.
1−30 48 SB Ed. 07.04

DVOR 432
1.6.5 RF Signal Processing of the Transmitter
See Figs. 1−12, 1−18.
RF−Modules with RF signal processing of the DVOR transmitter are:
− Synthesizer−D (SYN−D)
− Modulator−110 (MOD−110)
− Carrier Amplifier 100 W (CA−100C)
− Control Coupler−DVOR (CCP−D)
The RF−Duplexer (RFD) is used in case of an alarm to switch over to the standby transmitter. The
modules MSG−S and MSG−C are without any RF signal processing.
To DVOR antenna system
PDSU
antenna switch control

ASU interface
MOD−110 CA−100C
Carrier
actual value
RFD
MOD−110 USB (SB1)
SYN−D actual alue

REF
MOD−110
LSB (SB2)
Amplitude Control/ actual

Phase Control value
MSG−S CCP−D
Frequency select
BITE
MSG−C
Transmitter 1 Transmitter 2
Communication Interface RS 232C
Fig. 1−18 DVOR transmitter modules
1.6.5.1 Synthesizer
See Fig. 1−19.
The carrier frequency of the DVOR transmitter is generated by a synthesizer. A Voltage Controlled
Oscillator (VCO) generates the DVOR frequency channels with a frequency spacing of 50 kHz. The
reference frequency is 20 MHz, which is divided by 400 to get the desired value for the frequency de-
tector, which is operated also at 50 kHz. Two further VCOs are phase locked to the carrier to generate
the USB and LSB frequencies. The data for the requested frequency channel is delivered via a serial
data command from the MSG−C module.
Ed. 07.04 48 SB 1−31

DVOR 432
The RF−output is divided additionally to supply the carrier frequency for:
− the Carrier Modulator,
− the Upper Sideband Modulator,
− the Lower Sideband Modulator,
− the Control Coupler (reference signal).
Data In RF Out
CSB
VCO REF
Frequency
and
Phase/Frequency 50 kHz Coupler 3 dB
20 MHz Detector Master (f)
Reference Oscillator PLL0 Integrator/filter 108 − 118 MHz Amplifier
Frequency channels VHF: 50 kHz
Feedback Loop R= 400
N = 2160 for 108.00 MHz
N = 2161 for 108.05
VCO USB
Clock reference PLL1
RF Out USB
f+9960 Hz
VCO LSB
Clock reference PLL2
RF Out LSB
f−9960 Hz
Fig. 1−19 Concept of the DVOR VHF Synthesizer
1.6.5.2 Modulator 110

See Fig. 1−20.
The RF signal processing of the Modulator 110 fulfills the requirements described in the section ’mod-
ulation control’. The RF−Signal passes the following subfunctions:
− Attenuator to improve the VSWR
− Mixer to allow the controlled phase reversal
− Phase shifter (2 stages) to get a controlled analog phase shift of > 400°
− Preamplifier stages 25 dB
− Modulation stage for envelope control
− Final amplifier to get the specified 30 W output power and
− Bidirectional coupler to get the incident and reflected signal component.
Amplitude Feedback
Amplitude control
Phase Control to CCP

Control amplifier Detector
Phase
Phase Feedback Vreflected
Control amplifier
Amplitude
Phase Reversal
In −6 dB Out
20 dB 15 dB 10 dB 10 dB 13 dB
Phase switch Phase shifter Preamplifier 13 dBm Controlled RF amplifier RF 30 W
Fig. 1−20 Concept of the Modulator 110
1−32 48 SB Ed. 07.04

DVOR 432
In the case of application as sideband modulator the output signal is fed directly to the RF−Duplexer
(RFD). Within the module RFD the aerial port has a low path filter to suppress the carrier harmonics.
In the case of application as a carrier modulator the output feeds the carrier amplifier (CA−100C),
where the signal processing consists in amplification only (gain ≈ 14 dB).
1.6.5.3 Control Coupler Signal Processing

See Fig. 1−21.
The control coupler for the DVOR has the function to demodulate the envelopes of the RF−carrier
and RF sideband signals and to detect the RF−phase of the carrier signal.
For the analog control loops, the carrier signal is divided for the precision amplitude demodulation
and for the phase detector. The carrier phase control loop uses the fact, that only signals being in
quadrate at mixer inputs (LO, RF) delivers zero volt at its IF−output.
The actual cw RF sideband signals get amplitude demodulated and are used to control the sideband
output power.
RF input signals:
REF signal LO IF Carrier Phase
RF
attenuator
3 dB
Carrier Amplitude
dB
Carrier SPxT select
CSB 3 dB
dB
USB dB
Amplitude
LSB dB
Fig. 1−21 Concept of Control Coupler CCP−D
Ed. 07.04 48 SB 1−33

DVOR 432
1.7 FUNCTIONAL DESCRIPTION OF THE MONITOR

This functional description of the monitor provides a introduction to the monitoring concept. It will be
of use in understanding the subsequent chapters, since certain relationships are discussed in ad-
vance.
1.7.1 Overview
See Fig. 1−22.
The monitor has two functions. The first is to detect impermissible signal changes in the field by moni-
toring actual field signals. If an incorrect navigational signal is detected, the monitor switches over
to the standby transmitter or shuts the system down if no standby system is available. The second
is to ensure that varying environmental conditions and component aging do not influence the per-
formance of the monitor itself (fail−safe behavior). The monitoring process is implemented by hard−
and software−modules. The RF−signal (from field sensor) is amplified, normalized to a defined level
and demodulated by a precision detector. Before sampling (the sampling rate is 960 Hz) and D/A−
conversion the composite video signal is filtered to avoid aliasing in the Discrete Fourier Filter algo-
rithm (DFT) of the monitor processor which follows. By the filter−algorithm the dc−component and
the modulation components of the navigational frequencies are extracted. By comparison with pro-
grammed and stored alarm limits the components are checked for in tolerance or out−of−tolerance.
If the parameter is out−of−tolerance an alarm condition is detected and the executive action
(switch−over or shut−down) is initiated
Automatic Monitoring of the radiated signal is provided to continuously monitor and initiate executive
action to change over to standby or to close down as appropriate when certain tolerances are ex-
ceeded. The parameter to be monitored are as follows:
− azimuth
− amplitude modulation depth of 30 Hz AM
− amplitude modulation depth of 9960 Hz AM
− frequency deviation of 30 Hz FM
− carrier level and
− availability and correctness of identity Morse coded tone
− carrier frequency
− radiation of all sideband aerials
from field monitor
Pin Diode Switch
RF Bandpass
Filter
AGC
Amplifier
Sampling Precision
Oscillator Detector
Anti Aliasing
Divider Filter
Sample&Hold
Circuit
A/D uP80186 Switch over/Shut down to CSL

Converter Data to LRCI
Fig. 1−22 Monitoring Concept, general view
1−34 48 SB Ed. 07.04

DVOR 432
1.7.2 Monitor Sensors for the DVOR
See Fig. 1−23.
A suitable sensor position for the DVOR system is a nearfield Yagi antenna located >100m offset from
the DVOR counterpoise (typically 200 m). Usually one monitor sensor in a dualized monitor system
is used only; its signal is distributed between the two monitors in equal parts by means of an RF power
divider. As an option a nextfield monitoring capability is available.
typically 200 m
* Monitor antenna
Counterpoise
DVOR
* * nextfield monitor dipoles (optional)
Fig. 1−23 Position of the monitor dipole in the radiated field
1.7.3 Processing of the monitor signal

See Figs. 1−24, 1−25, 1−26, 1−27.
The monitor antenna signal is supplied via a RF−band−pass filter (108 to 118 MHz) with steep edges
to an amplifier with a processor−controlled attenuator. This controlled amplifier amplifies the RF level
up to 6 dBm. The composite DVOR signal is demodulated by the precision demodulator, whereby
the DC and AC signal components map ideally the level and modulation depth of the received monitor
antenna signal. The bias voltages of the detector−diodes are compensated and do not falsify the
measurement of the modulation depth of the signal parameters. The straight forward amplifier design
provides the maximum possible gain stability.
The different modulation signal components have to be extracted out of the composite video signal.
The extraction is accomplished by hard− and software modules. The hardware modules to extract
the signal components are:
− 150 Hz Low pass filter (LLZ) for DC− and 30 Hz components

− 10 kHz High pass filter with peak rider for 9960 Hz modulation depth
− 10 kHz Filter with 30 FM−demodulator for 30 Hz FM (reference signal)
− 1020 Hz Filter with peak rider for Identity Tone (ID)
Due to the design specification the Monitor Signal Processor for the VOR and the Doppler VOR is
identical and provisions are provided for the DVOR antenna monitoring. First the processor−con-
trolled analog switch (Multiplexer1) selects one of the two signal sources (measurement signal or test
generator signal) for the following hardware processing.
Ed. 07.04 48 SB 1−35

DVOR 432
Monitor dipole
12 bit D/A
converter
AGC
RF band−pass
filter Precision ID Discriminator
Controlled amplifier demodulator
1020 Hz filter Peak Rider Processor 80C186

4 BIT signals
III incl.
Measurement Memory/Peripherals/
Signal 0 Control Circuits
150 Hz low pass
Test generator Sample
filter 0 &
signal Hold
1 60 Hz
ASU DIF low pass 12 bit A/D
to measure USB/LSB 2 10 kHz high pass Peak rider I converter
level filter
filter 2
ASU SSB
to measure LSB level 3 II
10 kHz filter FM dmodulator
1
ATE5
3
Multiplexer 1 Multiplexer 2 Multiplexer 3
Monitor data to Status to/from

LRCI Co−Monitor
Fig. 1−24 Concept of Monitor Signal Processor
The following signal components (Fig. 1−25) after the hardware processing are fed to the Multiplexer
2 and selected for further processing by the microprocessor:
− DC− and 30 Hz AM component,
− Envelope of 9960 Hz subcarrier,
− 30 Hz FM (reference signal) and
− Identity tone (ID)
A single−pole 60 Hz low pass filter allows the non attenuated signal flow only of signal components
having a frequency of 60 Hz or lower. In addition to the signals to be monitored, the Multiplexer 3 is
also used to select and to measure test signals for equipment BIT. Mainly the supply voltages of the
transmitter 1 and 2 are a/d−converted and evaluated.
U(f)
A0
30 Hz AM 1020 Hz 9960 Hz with 30 Hz FM

A1
Fig. 1−25 Spectrum of the VOR multiplex signal
The further processing to extract signal components is accomplished by software. The next filter to
extract the signal components to be monitored is implemented by a Discrete Fourier Transformation
algorithm by the microprocessor. This requires the sampling and digitizing of the analog signals.
1−36 48 SB Ed. 07.04

DVOR 432
A 960 Hz sample command controls the Sample & Hold Circuit including a 12−bit A/D−Converter.
Each of the signal components to be evaluated by the DFT gets selected for the duration of 64 sam-
pling intervals. The last 32 sampled measurements are stored in the memory of the µP and evaluated
according the schematic of Fig. 1−26.
a) Demodulated 30 Hz component in the time function b) Spectrum of the demodulated 30 Hz component
U(t) Ax [%]
100 A0
A1
t f [Hz]
0 30 60 90 120
c) Spectrum analysis of the demodulated signal in the monitor processor
SAMPLE BUFFER DIGITAL FILTER BANK SPECTRAL AMPLITUDE EVALUATION Data

and
Status
Individual values in Computing the amount Evaluation of signal com- flag
a 30 Hz period, Computing the discrete of the individual ponents
storage of 32 samples complex frequencies spectral lines
Microprocessor
ȍx
31
A0 + n + A DC |A 1| + ǸR20(1) ) I2m(1) A DC + RF * Level
n+0
|A 30Hz|
ȍx |A 2| + ǸR20(2) ) I2m(2)
31
2p Modulation depth +
A1 + n e*j32 n + A 30Hz A DC
n+0
|A 3| + ǸR20(3) ) I2m(3)
ȍx
31
A2 +
2p
e*j32 2n + A 60Hz |A 2| ) AAA.|A 5|
n Distortion +
A DC
|A 4| + ǸR20(4) ) I2m(4)
n+0
ȍx
31
2p
A3 + e *j 3n
+ A 90Hz Imaginary part
n 32 f 30Hz + arctan
n+0 |A 5| + ǸR (5) ) I (5)
2
0
2
m
Real component
ȍx
31
2p
A4 + n e*j32 4n + A 120Hz q + f Var * f Ref
n+0
ȍx
31
2p
A5 + n e*j32 5n + A 150Hz
n+0
Fig. 1−26 Discrete Fourier Transformation
The time interval for each DFT cycle of 64 interrupts is part of an overall time frame, which is periodic.
The overall time frame is three seconds and is shown in table 2 and the monitor frame in table 3.
Ed. 07.04 48 SB 1−37

DVOR 432
DFT Measurement Interval for the Function Path in Fig. 1−24 / Remarks
Cycle #
0 − Evaluation of the DC−Component, MUX 1: 0
− Evaluation of 30 Hz AM MUX 2: 0
− Evaluation of the 60 Hz Component MUX 3: I
− Calculation of the 30 Hz AM Vector angle
1 − Evaluation of the 30 Hz FM Index MUX 1: 0
− Calculation of the 30 Hz FM Vector angle MUX 2: 1
− Calculation of the Azimuth (Angle AM − FM) MUX 3: I
2 − Evaluation of the 9960 Hz Envelope MUX 1: 0
− Calculation of the 9960 Hz Distortion MUX 2: 2
MUX 3: I
3 − Evaluation of the 9960 Hz Envelope MUX 1: 0
− Calculation of the 9960 Hz Distortion MUX 3: II /(provisionally only)
( 60/90/120/150 Hz)
4 − Calculation of the 1020 Hz AM MUX 2: 4
MUX 3: I
5 Testgenerator−Signal MUX 1: 1
− Evaluation of the DC−Component, MUX 2: 0
− Evaluation of 30 Hz AM MUX 3: I
− Calculation of the 30 Hz AM Vector angle.
− Evaluation of the 30 Hz FM Index MUX 2: 1
− Calculation of the 30 Hz FM Vector angle MUX 3: I
− Calculation of the Azimuth (Angle AM − FM)
− Evaluation of the 9960Hz Envelope MUX 2: 2
− Calculation of the 9960 Hz Distortion MUX 3: I
8 − Measurement of Temperature Sensor
9 DVOR only: Lower Sideband (LSB) MUX 1: 2
− Evaluation of the 60/90/120/150 Hz Components MUX 2: 0
− Calculation of the Distortion MUX 3: I
10 DVOR only: Upper (USB) minus Lower Sideband MUX 1: 3
− Evaluation of the 60/90/120/150 Hz Components MUX 2: 0
− Calculation of the Distortion MUX 3: I
Table 2 DFT cycle, Overall time frame and path
1−38 48 SB Ed. 07.04

DVOR 432
Frame Counter # DFT Cycle time in s Remarks
0 8 0,0000 Temperature
1 0 0,0667 RF−Level, 30 Hz AM, 60 Hz
2 1 0,1333 30 Hz FM, Azimuth
3 2 0,2000 9960 Hz AM
4 4 0,2666 1020 Hz AM
5 9 0,3333 LSB
6 10 0,4000 USB − LSB
7 3 0,4666
8 4 0,5333 1020 Hz AM
9 0 0,6000 RF−Level, 30 Hz AM, 60 Hz
10 1 0,6666 30 Hz FM, Azimuth
11 2 0,7333 9960 Hz AM
12 4 0,8000 1020 Hz AM
13 5 0,8666 TSG, RF−Level, 30 Hz AM, 60 Hz
14 6 0,9333 TSG, 30 Hz FM, Azimuth
15 7 1,0000 TSG, 9960 Hz AM
16 4 1,0666 1020 Hz AM
17 0 1,1333 RF−Level, 30 Hz AM, 60 Hz
18 1 1,2000 30 Hz FM, Azimuth
19 2 1,2666 9960 Hz AM
20 4 1,3333 1020 Hz AM
21 9 1,4000 LSB
22 10 1,4666 USB − LSB
23 3 1,5333
24 4 1,6000 1020 Hz AM
25 0 1,6666 RF−Level, 30 Hz AM, 60 Hz
26 1 1,7333 30 Hz FM, Azimuth
27 2 1,8000 9960 Hz AM
28 4 1,8666 1020 Hz AM
29 5 1,9333 TSG, RF−Level, 30 Hz AM, 60 Hz
30 6 2,0000 TSG, 30 Hz FM, Azimuth
31 7 2,0666 TSG, 9960 Hz AM
32 4 2,1333 1020 Hz AM
33 0 2,2000 RF−Level, 30 Hz AM, 60 Hz
34 1 2,2666 30 Hz FM, Azimuth
35 2 2,3333 9960 Hz AM
36 4 2,4000 1020 Hz AM
37 9 2,4666 LSB
38 10 2,5333 USB − LSB
39 3 2,6000
40 4 2,6666 1020 Hz AM
41 0 2,7333 RF−Level, 30 Hz AM, 60 Hz
42 1 2,8000 30 Hz FM, Azimuth
43 2 2,8666 9960 Hz AM
44 4 2,9333 1020 Hz AM
Table 3 Monitor frame
Ed. 07.04 48 SB 1−39

DVOR 432
Each evaluation of a DFT cycle is identical and analyses the 30 Hz (A1) and harmonics (A2 to A5). The
microprocessor system of the MSP stores 32 discrete amplitude values xn for each DFT cycle period
which shall be analyzed. They are used to calculate the complex amplitudes of all the 30 Hz harmonic
frequencies which builds the periodic waveform. The complex e−function shown in Fig. 1−26 is not
used for the calculation, but is instead converted to cos(ωt) and i . sin(ωt), with which the data in the
microprocessor unit is simpler to process. A Fourier analysis is performed with the 32 measured val-
ues.
The relationship sin wt + Ǹ1 * cos 2 wt means that the Am calculation (m = 0...5) can be restricted to the
cos values. In order to reduce the number of multiplication operations to a minimum, the symmetrical
properties of the cos function are exploited, leaving only 7 operations:
cos 11.25° ; cos 22.5° ; cos 33.75° ; cos 45° ; cos 56.25° ; cos 67.5° ; cos 78.75°.
These multipliers are stored in the memory as constants. The following calculations are performed:
− RF component, by summing all the measured values (DC component A0 )

− Real and imaginary components from A1 to A5
− A1 , A2 , A3 , A4 and A5
− Azimuth angle from the meas and ref (30 Hz AM vector angle to 30 Hz FM vector angle)
Each DFT cycle has a duration of 64 interrupts (exact two complete 30 Hz periods). The first 32 mea-
sured data after the new DFT cycle has been selected are not used for DFT−signal processing, the
time is used to settle. The measurement data defined by interrupts #33 to #64 of a DFT cycle are used
for the signal analysis with a discrete Fourier transformation. Since 32 interrupts correspond to exactly
one 30 Hz period (and 64 interrupts to two 30 Hz periods), the measurements for each channel always
start at the same time with respect to the 30 Hz audio phase. This is important for the azimuth calcula-
tion, which takes direct account of the phase of the 30 Hz AM and 30 Hz FM signals. The measurement
and evaluation cycle is designed so that the values measured for the previous channel are evaluated
during the measurement period of the new selected channel. After the Fourier analysis and the evalua-
tion of the measured values of the different channels have been completed, the monitor checks the
results and assesses the radiated parameter. The monitor alarm check is a comparison of calculated
values of the monitor signal parameter against user programmed alarm and warning limits.
The identity signal is verified by measuring the 1020 Hz depth of modulation. Due to the signal struc-
ture (Morse code keying) the microprocessor checks dots, dashes and space for correctness.
The carrier frequency is monitored by internal signals in counting the frequency of a prescaler output
signal of the synthesizers in operation.
The complete design of the DVOR ASU is based on a concept in having a 50 Ω−matching with a good
VSWR during all switching conditions of the 30 Hz period. Due to this design the sideband antennas
can be used as receiving aerial for the carrier signal transmitted by the center antenna (A49). With
the arrangement shown in Fig. 1−27 at the mixer output a 9960 Hz signal of the considered sideband
is available. In cases the connection to one sideband aerial is missing the 9960 Hz signal gets a gap
in the signal. The 9960 Hz signals derived from the USB and LSB get analyzed and a missing sideband
antenna gets detected by the monitor signal processor.
To optimize the detection, the signal ’detected USB’ minus ’detected LSB’ is generated, in which the
30 Hz AM component of both signals is compensated. Thus the DFT of the USB − LSB gives 30 Hz
and harmonic components which are compared against alarm limits.
1−40 48 SB Ed. 07.04

DVOR 432
Carrier antenna A49
(+47 dBm)
A10 CSB out CSBin

A09
Sideband antennas A08
A07 PIN−Diode Switching Unit
Z2
A06 ASM 26 dB
A05 CSB reflected
cosine CSB incident
A04
A03 USBout Z1
Blending USBin
3 dB
A02 Modulator
ASM
A01 Z3
sine
20 dB
USB reflected + USB incident
CSB (15 dBm) received
3 dB
COS blending Coupler Detected
SIN blending
even antennas odd antennas USB (SB1)
10 kHz 10 kHz
−5 dBm IF TP2 Band−pass USB (SB1)
A01 Mixer
A07 A05 A03
A08 A06 A04 A02
Fig. 1−27 DVOR antenna monitoring

Since the measurement is derived from the carrier signal received at the sideband aerial, the observed
signal has the 30 Hz AM component (Fig. 1−27). To remove (or to reduce) the 30 Hz component of
the two signals derived in the path for the upper – and lower sideband processing, these are added
with one signal inverted to get USB/LSB. The derived signal USB/LSB is influenced by the DVOR sig-
nal frequencies like 30 Hz and harmonics, the 9960 Hz subcarrier frequency and the blending modula-
tion frequency (1500 Hz / 2= 750 Hz), which are not synchronized together. Thus the value for distor-
tion versus measurement condition will change its value depending on the actual signal amplitudes
versus time axis. The alarm limits have to be set to have a sufficient margin to the measured value.
But as minimum, if one sideband element is removed, the alarm limit must be exceeded.
Besides the USB/LSB signal a Single Sideband Signal (the LSB) is used for the antenna fail detection
since in case two opposite elements on the DVOR antenna ring would fail, the USB/LSB processing
will get a reduction of the distortion value but the measured Single SB−signal distortion will grow up
and will indicate alarm.
1.7.4 Monitor Actions at Alarm Conditions

See Fig. 1−28.
In general the monitor actions and functions are divided into
− executive monitoring
− warning monitoring.
To avoid the radiation of false guidance signals the executive monitor initiates in case of an alarm a
switch−over or a shut down of the DVOR system. The monitor shall be fail safe, i.e. a monitor circuit
failure results in an alarm condition.
The warning monitor gives an indication only. The warning indicates that important parameters are
within pre−alarm condition or that less important parameters (parameters considered to be not es-
sential for the radiated guidance) have reached their limit. Besides to the monitor warning also mainte-
nance warnings are indicated which are derived by the BIT of the transmitter control or the checks
of the LRCI−processor.
Ed. 07.04 48 SB 1−41

DVOR 432
With a dualized monitor system as in Fig. 1−28, both monitors evaluate the sensor signals. For an
executive monitor action according to the EUROCAE ED 57A the dualized monitor configuration may
be selectable as an OR−function or as an AND−function. The switch over or shut down is initiated
for the monitor OR−function in case one monitor detects an alarm independent of the monitoring re-
sult of the second monitor system. For the monitor AND−function both monitor systems must have
an alarm condition. According to EUROCAE ED 57A for the OR−function, a monitor system being
faulty the DVOR ceases operation, which decreases the system availability; for the AND−function,
a faulty monitor system may cause the radiation of an erroneous navigation signal, which decreases
the safety and integrity. To avoid this situation, the ’Extended AND function’ was created (see below).
The monitor performance is checked continuously by evaluating the defined signal of a Test Signal
Generator. The monitor evaluation process is executed in time multiplex mode. For the radiated signal
to be monitored and for the test signal, identical signal processing hard− and software modules are
used. If the monitor processing has a failure, the defective monitor is declared as faulty and the se-
cond monitor is active only. Thus in case of a dualized monitor system and the OR−function selected
the shut down of the DVOR can be avoided and only a degradation is indicated and transmitted to
the maintenance center via the remote control system. Having selected the monitor AND−function
and both monitor systems fed with the identical sensor signal, the monitor results should be similar.
However, monitor measurement accuracy tolerances exist. Therefore additional extended alarm
check tolerances have been introduced for the AN 400 DVOR monitoring. The procedure is such, that
in case one monitor detects parameters above the standard alarm limits but not exceeding the ex-
tended alarm limits, the DVOR stays operational, indicating the alarm only. If the specific parameter
becomes worse the second monitor may also detect the alarm condition which then activates the
switch over/shut down procedure. In case the second monitor detects no alarm and the parameter
value of the first monitor exceeds the extended alarm limit, the DVOR is shut down.
To be compliant with the specification EUROCAE ED 57A, the standard AND−function can be config-
ured. However for DVOR systems, the ’Extended−And−function’ is recommended because it in-
creases the system integrity. The monitor configuration OR/AND/Extended−AND can be selected
(refer to PC User Program).
Monitor
Antenna System Sensor
19" cabinet
RF−Duplexer
Transmitter 1 Transmitter 2 Monitor 1 Monitor 2

RF−Signal RF−Signal
Generation and Generation and
Amplification Amplification
Monitor Signal Monitor Signal

Modulation Signal Modulation Signal Processor * Processor
Generator Generator
DC/DC Converter DC/DC Converter DC/DC Converter DC/DC Converter
Battery Charging
Power Supply Local&Remote Communication Interface
Cabinet Fuse
Battery Fuse
Emergency PTT line Local PC
Mains 230 VAC
Battery (Pb)
48 V (53.5 V) * Status Exchange
Fig. 1−28 Dual AN 400 Equipment
1−42 48 SB Ed. 07.04

DVOR 432
1.8 FUNCTIONAL DESCRIPTION LRCI
1.8.1 Overview
The interfaces requested for the equipment are realized in the Local/Remote Communication Inter-
face (LRCI). The task of the LRCI is communication with the different functions, controls for the equip-
ment, local display and local control of the equipment for the operator, and remote control functions.
The LRCI includes the Local Control Panel (LCP), individual Modem units and a VAM unit (opt.). These
units are supplied by the DC/DC Converter DCC−3−05/3. The Modem units enable communication
to the remote site. Modems used for dedicated line or switched line applications are available.
1.8.2 Introduction to the Local Control Panel (LCP)
Each equipment (ILS−LLZ, ILS−GP, CVOR, DVOR) includes the LCP which enables the control of
the LRCI functions and the local control by means of a microprocessor 80386 SX (or TI486), as well
as the status display of the station. It consists of a Local Control CPU board (LC−CPU) and a Local
Control Interface (LCI) for main status indication, equipment status and measurement data and
manual controls (switch commands) for basic control functions. Besides serial data interfaces to the
monitor and transmitter processors an RS 232C interface is also implemented for the local PC−con-
trol with ADRACS (Automatic Data Recording And Control System) and to the remote site via the Mo-
dem. Summary of the features:
− Communication to subsystems
− Interface to collocated stations (DME, NDB)
− Built−in−Test−Equipment
− BCPS Control
− Programming station parameters
The LCP represents the interface of the NAV−Station and the outside world e.g. Remote−Control.
The LCP controls ten serial control channels. A NAV−Station normally consists of two transmitters,
two monitors (which are called subsystems) and the LCP. There exists also the option of collocated
stations like NDB or DME which data are also available through the LCP. The Local Control Interface
(LCI) has indication lamps for the main status and a menu driven liquid crystal display (LCD) for indica-
tion of status and measurement data and manual controls to perform simple activities like ON/OFF
or CHANGE−TX. It is controlled by the LC−CPU.
1.8.3 Data Transmission
Switching on the Station the LCP reads the configuration−files in the RAM−Floppy, initializes the Sta-
tion and brings it into a normal operational state. The communication between LCP and the subsys-
tems works after the master−slave principle. The LCP sends automatically telegrams (which are
called INTERNAL) with an configured frequency between 0.04 Hz and 10 Hz (in steps of 100 ms) to
the subsystems (monitors transmitters). From the answers of the subsystems the LCP gets the neces-
sary information to compose the Main Status of the station and to check if all subsystems are correctly
working and available.
If the remote control is connected, it is possible to get directly data from transmitters, monitors or the
LCP itself to have detailed status information or to program station parameters. Every time data are
requested from a PC the LCP sends also the INTERNAL telegrams to compose the Main−Status. For
reliability the telegrams are checked with a cyclic redundancy check (CRC) after ANSI X3.99−1979
with the CCIT V.41 generator polynomial.
Ed. 07.04 48 SB 1−43

DVOR 432
1−44 48 SB Ed. 07.04

DVOR 432
1.9 FUNCTIONAL DESCRIPTION POWER SUPPLY
1.9.1 Overview
See Fig. 1−29.
The power supply used for the DVOR system is normally the 230 VAC mains. An emergency power
supply must be provided by a battery to ensure that operation is not interrupted if the mains power
fails. The 230 V mains supplies the Battery Charging Power Supply (BCPS), which in turn supplies
a DC voltage to the navigation system and keeps the parallel floating battery charged. An uninterrupt-
ible power supply is thus available for a transitional period if the mains power fails. One (or two) of
the power modules (ACC), of which there can be up to four, acts as a standby in case of failures, mak-
ing the system extremely reliable. The output voltage is normally 54 V DC (max. 12 A per module),
corresponding to the maximum charge of a lead battery with 24 cells. The number of modules which
are connected in parallel is sufficient not only to operate the navigation system, but also to permit the
floating battery to be recharged within a reasonable time. If one of the modules fails, the others con-
tinue working normally.
The BCPS provides the supply voltage to the PMM (Power Management Module), which is used to
switch both the NAV equipment complete and following the two transmitters (TX1 and TX2) on and
off either individually or together. The switches in the PMM also provide overcurrent protection. In ad-
dition, a voltage monitor is implemented on the CSL which cuts off the load completely via the PMM
if the operating voltage drops below 43 V in order to prevent the battery from being exhausted and
damaged. A measurement facility of battery current and installation current is also implemented on
the CSL. Downstream of the PMM are the DC converters DCC−3−05, DCC−MV and DCC 28 (used
for 100 W only), which supply the voltages for the transmitters, monitors, the LRCI and the CSL. They
generate the component voltages 5 V, ±15 V, 28 V exactly from the nominal 54 V (43...62 V). The DC
converters take the form of switching regulators. They incorporate circuits for current limiting, overvol-
tage cutoff and internal monitoring. The CSL which has a DC−converter (±15 V) on board is supplied
directly downstream of the PMM with the nominal 54 V. A measurement facility of battery current and
installation current is implemented on the CSL.
The ASU subassemblies are supplied by individual DC converters on the BSG−D (+5/±15 V) and
the PDSU by DC converters on the ASU−CIF (+5/−15 V). The transmitters, monitors, and LRCI as-
semblies are supplied by separate power supply modules. The LRCI, the two monitors and the CSL
are operational as soon as at least one switch on the PMM is switched on. The power supply to the
transmitters is switched on and off either from/via the LRCI or by the monitors via the CSL with control
lines. It supplies the signal generation and the RF stages with the power amplifiers.
1.9.2 Startup Procedure

When the system is switched on with the NAV and the TX1 (TX2) switch on the PMM subassembly,
all the power supply modules will be connected to the 54 V voltage, but only the modules for supplying
the LRCI, CSL and the monitors will actually be switched on. The request ENTER PASSWORD ap-
pears on the PC. If an input is not made, or if an incorrect password is entered, further action will not
be possible. If the password is entered correctly, the system is ready to accept commands. Transmit-
ter TX1 or TX2 can then be switched on via the LRCI or the connected PC with the appropriate com-
mand. The DC converters used to supply the active transmitter are activated via control lines. The
converters for supplying the transmitter which is not yet active remain switched off. Each of the two
transmitters can be switched on and off separately with the switches on the PMM. If one transmitter
is switched off for maintenance purposes, it is not necessary to enter the password again when it is
switched back on. All command inputs however require a password to be entered if the system was
previously switched to remote (i.e. if it was operated via the remote control system) and has now been
reset to local the key switch to allow it to be operated locally.
Ed. 07.04 48 SB 1−45

DVOR 432
PDSU/ASU−CIF
DCC +5/−15
ASU/BSG−D
DCC +15, −15, +5
Transmitter 1 Monitor 1 Monitor 2 Transmitter 2
5V 5V
5V 28 V 5V 28 V
+15 V +15 V
−15 V −15 V
28 V 28 V
CSL
LRCI
5V
DCC−3−05 DCC−3−05 DCC−3−05

DCC−MV DCC28 /1 /3 /2 DCC−MV DCC28
100 W only 100 W only
F1 F2
Transmitter 1 Transmitter 2
TX1 TX2
NAV
PMM
ACC (BCPS−Module) Emergency Battery
54 VDC
Mains 230 VAC
Control line
Fig. 1−29 Power supply, block diagram
1−46 48 SB Ed. 07.04

DVOR 432
from Transmitter 2 Field monitor***
1 2 ASU subassemblies PDSU
CSB
SB2
SB1
A49
1) Installations 100 W: MOD−110P is replaced by a MOD−110 and a CA−100. The actual RF value output Carrier antenna 49
TRANSMITTER 1 and MONITOR 1 of the Mod−110 is terminated by a load, the actual RF value is now derived from the CA−100. ASU−C
A02
a
RF duplexer CSB
to sideband antennas A1 to 48; centre antenna 49

components ASM
30 Hz AM inside cabinet rear SP12T
Phase control analog
Carrier amplifier CSB
Carrier modulator CSB 50 W or 100 W 1) CSB SB1S
1) RFD1−C A24
CA−100 USB sin A26
MOD−110* MOD−SBB DPDT
1) SB1 cos
SB1
Amplitude control SB2S ASM
analog Load (used with 100 W)
SP12T
Synthesizer 1)
RFD2−SB Circ. SB1C
LSB sin
f0 Sideband modulator SB1
Actual RF value
SB1
SB2 SB2
MOD−SBB A48
DPDT
f0 + 9960 Hz cos A01
MOD110 Circ. ASU−C
Ref f0 Actual RF value SB2C b
f0 − 9960 Hz Amplitude/ ASM
Phase values
Phase control SP12T
Control
SYN−D 30HZO 30HZE
SB2 A23
Sideband modulator SB2 A25
MOD110 Actual RF value ASM

Control/BIT
TX1 PMC−D BSG−D SP12T
Amplitude/ ASU interface t/f ASU int.
Reference carrier Phase control
TX2 30HZ sync.
A47
+5V
Control Coupler
Monitor 1
Monitor 2
+15V +5 V
DCC05/15 Antenna switch ASU−CIF
−15 V
CCP−D control and 30HZ sync. −15V control
48V
On/Off from CSL
RF changeover control
mod. signal
30 Hz AM/identity/voice/DC DC 48 V
Channel select/control
BIT−Signals Actual amplitude value SB
Control line BIT signals TRANSMITTER 2 and MONITOR 2
BIT signals
DCC 28 28 VDC for transmitter
28 VDC MSG−S MSG−C MSP−CD MSP−CD MSG−C/MSG−S

DCC−MV ±15 VDC Modulation Signal Generator Modulation Signal Generator Monitor Signal Processor Monitor Signal Processor Modulation Signal Generator
Signal generation transmitter control
5 VDC
CSL
V.24 / RS232 V.24 / RS232
DCC−3−05/1 (TEG)
V.24 / RS232 V.24 / RS232
5 VDC for monitor
DCC−3−05/2 DC−Converter on/off TX2
to/from ASU/ PMC−D
DCC−3−05/3 5 VDC for LRCI

to/from
Status
to transmitter 2 ASU / PMC−D
MSG−S
DC 48 V DC 48 V
On/Off control from CSL

Over discharge protection/ Battery monitoring
5V LRCI
DC 48 V TX1
PMM to transmitter 2 DC48 V TX2
V.24 / RS232 Local Control CPU Local Control Interface
On/Off TX1/TX2
VAM MODEM* LCP
ACC Modem* RS232/TTL LC−CPU LCI
(optional)* LGM1200MD o. LGM 28.8 Modem*
53,5 VDC ACC 2 16 16

V.24 / RS232 V.24 / RS232
(48 VDC nom.)
ACC Tower Remote site/LGM1** DME/LGM2** NDB/LGM3** Inputs Outputs Diagnosis Analog DME−Interface
48 V nom. (voice etc.) (spare) (spare) ID−Interface
Local PC (optional
Battery ACC (ADRACS)
100 W only Mains 115 to 230 VAC
* optional ** optional for modem *** Standard is 1 monitor dipole, the signal of which is divided to both MSP−VD
Fig. 1−30 DVOR 432, 50/100 W, dual version; simplified block diagram
Ed. 07.04 48 SB 1−47

DVOR 432
Equipment Description Software Description
1.10 NAVAIDS SOFTWARE (DVOR)
1.10.1 Overview
The software of the Navaids system has a modular structure. It is subdivided into the TRANSMITTER
SW, MONITOR SW, LRCI SW and the user software for PC. Description and use of the PC User Pro-
gram will be found in the Technical Manual ADRACS, Code No. 83140 55324. The equipment SW
is stored in the EPROM of the microprocessor for transmitter (MSG−C), monitor (MSP−CD, −L, −G)
and LCP. It cannot be modified by the user. The valid system version can be checked via the PC.
NAVAIDS
Software packages
Transmitter software Monitor software LRCI software

Transmitter processor Monitor processor LCP Processor
Signal generation Transmitter/signal monitoring Communication
RF amplification, RF radiation Local Control
User Software
ADRACS
Operation, maintenance
Fig. 1−31 System software, overview
1.10.2 Description of the DVOR Transmitter Software

See Fig. 1−32.
The transmitter software controls the transmitter functions. It is build up with the following software
modules.
− TRANSMITTER_INITIALIZATION
When a transmitter is switched on, this module initializes the transmitter HW for generating the
carrier and sideband modulation signals and resets all power output controlling devices. After the
synthesizer initialization, the antenna switching unit (ASU) is initialized and the adjusted power and
phase control values are set. Then the transmitter starts its operation.
− TRANSMITTER_MAIN_LOOP
After the transmitter initialization, the transmitter software enables the 1000 Hz and communication
interrupts and enters an endless loop. In the endless loop, the following actions take place:
S execution of LCP input commands, if the PROGRAM flag is set
S modulation control
S BITE measurement and evaluation
− COMPLETE_PROGRAMMING
If the PROGRAM flag has been set by the COMMUNICATION_INTERRUPT, this module interprets
and executes LCP input commands based on the specified transmitter command set (alarm limit,
calibration factors etc.)
Ed. 07.04 48 SB 1−49

DVOR 432
Software Description Equipment Description
− TRANSMITTER_CONTROL
The main task of TRANSMITTER_CONTROL is to ensure the stability of the generated sideband
amplitude and phase modulation signals using digital signal processing. Thus, non−linear effects
caused by amplitude and phase modulation are corrected. Furthermore, slow signal changes due
to temperature effects and component ageing are also corrected. This module mainly handles the
tasks modulation control and BITE measurement and evaluation. The actions are divided into the
following processing steps:
S measurement of AC−BITE signals according to a AC−BITE channel selection scheme
S measurement of DC−BITE signals according to a DC−BITE channel selection scheme
S measurement of ASU−BITE signals according to a ASU−BITE channel selection
scheme, if the transmitter is the aerial transmitter
S measurement of the carrier RF phase
S measurement of the 9960 Hz sideband RF phase, if the transmitter is the aerial transmitter
S control of the amplitude control voltage (DC) of sideband 1 (USB)
S control of the amplitude control voltage (DC) of sideband 2 (LSB)
S control of the RF phase control voltage of sideband 1 (DC) if the transmitter is the aerial
transmitter
S BITE evaluation
S internal house−keeping (up−date of status flags and so on)
− 1000_HZ_INTERRUPT
The 1000 Hz hardware interrupt routine of the transmitter performs the following tasks:
S controlling of the Morse code switching signal
S measurement of the 30 Hz signal
S keeping track of the power on/off indication
(which is set/reset by the monitors when the aerial transmitter is changed)
S management of the elapsed time counter
S transmitter timing management
− COMMUNICATION_INTERRUPT
(same structure as monitor COMMUNICATION_INTERRUPT)
TRANSMITTER MAIN LOOP 1000 Hz INTERRUPT COMMUNICATION INTERRUPT

INIT Start Start
Carrier RF Phase ID Code Communication Interrupt

Routine
See Fig. 1−35
9960 Hz SB RF Phase BITE Measurement every 200 ms:
− DC−values: measuring directly
− AC−values: Measuring specified
SB1 (USB) Amplitude (DC) sampling points
SB2 (LSB) Amplitude (DC) Check Power On/Off
SB1 (USB) RF Phase (DC) Return Return
BITE Check (AC/DC/ASU)
Fig. 1−32 Transmitter SW flow chart
1−50 48 SB Ed. 07.04

DVOR 432
1.10.3 Description of Monitor Software
1.10.3.1 Introduction
The DVOR monitor SW is written in the high level language PL/M86 (Programming Language for Mi-
crocomputers for 80x86 processors) from INTEL. Some subroutines are realized in assembler
(ASM86) in order to optimize processing speed. The DVOR monitor SW performs the monitor control
functions. It can be roughly subdivided into the parts "system initialization" and the "system monito-
ring". The most important functions are as follows:
− Monitoring of the active (aerial) transmitter

− Control of transmitter change−over and switch−off procedures
− Communication with the LCP
− Measurement and evaluation of the BITE signals
The SW has a relatively simple structure. It consists of main program, which implements the control
flow of the software as a "finite state machine". This method is also used in other modules to establish
their control flow. The tasks of each phase are assigned to main modules, which in turn can call other
submodules, in order to perform further tasks.
1.10.3.2 System Initialization
After power on the program clears the main memory (RAM) and initializes the interrupt controller, the
timers, the serial interface to the LCP and the various parallel interfaces required by the processor
for monitoring the transmitter. The operating data for the monitor are stored in the non−volatile main
memory (battery back−up). These data are secured by a CRC check word and checked during the
initialization. If the CRC check fails (for example due to low voltage of the back−up battery), the data
are cleared and set to default values stored in a table in the EPROM memory area. In this case, BITE
warning is displayed. After the system initialization, the program enters the main program endless
loop starting the monitoring process.
1.10.3.3 Main Program Loop
The main program loop performs the following activities:
− monitor channel selection

− discrete fourier transform (DFT) processing
− alarm check
− alarm evaluation
− BITE evaluation
− monitor house−keeping and in case of switch−over/switch−off alarm condition
− executive measures like switch−over or switch−off of the transmitters.
The data measurement for the monitoring process is controlled by a 960 Hz hardware interrupt, thus
providing equidistant data sampling. Besides the data input from the A/D converter, the 960 Hz inter-
rupt routine performs some further actions, like the management of the time and date counters.
The communication process for the data exchange with the LCP via a serial data link is also interrupt−
driven. However, the 960 Hz interrupt has the highest priority, i.e. if both interrupts occur simulta-
neously, the 960 Hz interrupt routine is carried out first.
Ed. 07.04 48 SB 1−51

DVOR 432
1.10.3.4 Basic Procedure
After the initialization phase, the program activates the tasks defined for the remaining phases in an
endless loop. At the beginning of the loop, the monitor status variable determines, whether the normal
operation (monitoring process) is performed or an executive monitor action takes places (switch−
over or switch−off). The normal operation first selects the monitor channel for data sampling and then
carries out the data processing of the channel data previously measured. The channel selecting pro-
cess is based on a fixed channel selection scheme (channel selection table) and controlled by a frame
counter. The data processing for the previous channel is interrupted by the 960 Hz interrupt to get
and store the data of actual selected channel.
1.10.3.5 Monitor Software Tasks and Activities
The main task of the DVOR monitor software is to ensure the integrity of the navigation signals ra-
diated by the active transmitter. If the monitor detects a faulty signal and its alarm delay counter has
expired, it switches the active transmitter off and puts the stand−by transmitter into operation. If this
transmitter also fails, the station is switched off. The main activities consists of
− sampling of data for monitoring controlled by the 960 Hz interrupt

− discrete fourier transform of sampled data
− calculation of the RF level, calculation of modulation depths of the 30 Hz and 9960 Hz AM signals,
calculation of the modulation index of the 30 Hz FM signal and calculation of the azimuth
− alarm check and alarm evaluation
− display of monitor status and measurements results
− executive actions in the case of faulty signals.
The monitor has two operating modes:
− MONITORING mode
− BYPASS mode.
The behavior in both modes is slightly different. In the BYPASS mode, the monitor accepts input com-
mands. It is used to adjust the monitor settings and during transmitter adjustment or maintenance.
The monitoring process is also performed, except that in the case of an alarm situation, executive
actions are blocked. In the monitoring mode, no input commands are accepted. The transmitter
states (on, off, aerial, stand−by) are full under monitor control.
However, the data output (monitor status, measurement results) is performed in both modes. When
the monitor is switched on, it always enters the bypass mode. There are two LCP commands for
changing manually from one mode to the other. The selected mode is indicated visually on the LCP
display by the lamp hBYPASSED".
1.10.3.6 Monitor SW Sequence

See Fig. 1−33.
Figure 1−33 shows the typical control flow for the monitoring process. While the data for the selected
channel are sampled (controlled by the 960 Hz interrupt, every 1.04 ms), the data of the previous
channel (DFT, alarm check and so on) are processed. The length of a channel (channel time) is 64
interrupts (66.67 ms) i.e. two 30 Hz periods. The data sampled during the first 32 interrupts are not
used, only the data of the second half (interrupts 32 to 63, one 30 Hz period) are stored for further
processing.
1−52 48 SB Ed. 07.04

DVOR 432
The overall processing time (monitoring process, BITE evaluation, house−keeping, time for interrupt
handling) may not exceeds the channel time. In the worst case, all these activities consume about
15 ms processing time, thus the processor spends most of the channel time to wait for the end of the
channel.
POWER
ON MAIN PROGRAM 960 Hz INTERRUPT PROGRAM
SYSTEM
INITIALIZATION
Set Monitor State = 0
START
Switch over action ok
Monitor State=0
Evaluation of Case
Monitor State
MONITOR N
Case 0 or Case 1,2,5
STATUS
"NORMAL"?
Alarm Case
Processing Y
.
. Check of
Channel Select INTERRUPT COUNTER
(x)
. >31 <=31
64 Interrupts x 1,04 ms = 66,7 ms
A
DFT Filtering
(x−1) Input from MSP
64 INTERRUPTS
CHAN. MEASUREM. DATA

Monitor Alarm Check
(x−1)
Evaluation of Action Table
Monitor Alarm Evaluat. using Interrupt Counter
(x−1)
Check of Monitor State

0 or <>0 Increment
. INTERRUPT COUNTER
BITE Evaluation
.
. End of
Monitor Management INTERRUPT
Check Program Flag

Bypass On Bypass Off
RETURN
Complete Programming
Do A
while Interrupt Counter
<64
Change over/Switch off Routine
Fig. 1−33 Monitor SW flow chart
Ed. 07.04 48 SB 1−53

DVOR 432
1.10.3.7 Main Program Modules

See Fig. 1−34.
The activities controlled by the main program can by characterized as follows:
− initialization
− monitoring process (monitor status = NORMAL)
− executive actions
For modularity reasons, the tasks of these activities are assigned to so called modules (an entity,
which can be compiled and tested separately). The hierarchical structure of these modules is shown
below:
MAIN$PROGRAM
INIT
CMOSRAM$CHECK
Initialization
EPROM$CHECK
CHANNEL$SELECTION
DFT$FILTER
ALARM$CHECK
ALARM$EVALUATION
BITE$EVALUATION Monitor "NORMAL" status
COMPLETE$PROGRAMMING
MONITOR$MANAGEMENT
ALARM$EVALUATION Alarm handling
Fig. 1−34 Monitor SW main program modules
- Main Program
This is the control program. After the initialization, it enables the interrupts and enters an endless loop.
The 960 Hz hardware interrupt is the base for the time management. The control flow is implemented
by a finite state machine. At the beginning of the loop, the monitor state variable is evaluated. It con-
trols the transition between the defined monitor states. The states are defined as follows:
1−54 48 SB Ed. 07.04

DVOR 432
− State 0 (normal state)
This state is the initial state. In this state, the normal monitor processing is performed:
S channel selection
S discrete fourier transform
S alarm check
S alarm evaluation
S BITE evaluation
S monitor house−keeping
If the monitor is in the BYPASS mode, input commands in this state are also accepted (for example
the change of a monitor alarm limit). A transition to another state can occur, if the monitor is in the
MONITORING mode end encounters an alarm situation or if the co−monitor indicates a switch−
over or switch−off action by setting the flag hMAINAL" in the monitor status exchange interface.
− State 1 (alarm state transmitter 1 failed)
This state is entered from state 0, if transmitter 1 is the aerial transmitter and fails. Depending on
the transmitter states, the monitor performs the following actions.
Case hstand−by transmitter 2 available":
S up−dating of the alarm history
S switching on of the stand−by transmitter (transmitter 2)
S setting of the stand−by transmitter aerial (RF relays)
S switching off of the faulty transmitter
S initializing of the monitor processing (reset alarm counter and status)
S transition to state 0 (normal state)
Case hstand−by transmitter 2 not available" (a switch−over action was already performed):
S setting of the power off signal (transmitter 1 stops radiation) and setting of the transmitter 1
stand−by (RF relays)
S enter state 5 (switch off state)
− State 2 (alarm state transmitter 2 failed)
This state is entered from state 0, if transmitter 2 is the aerial transmitter and fails. Depending on
the transmitter states, the monitor performs the following actions.
Case hstand−by transmitter 1 available":
S switching on of the stand−by transmitter (transmitter 2)
S setting of the stand−by transmitter aerial (RF relays)
S switching off of the faulty transmitter
S initializing of the monitor processing (reset alarm counter and status)
S transition to state 0 (normal state)
Case hstand−by transmitter 1 not available" (a switch−over action was already performed):
S setting of the power off signal (transmitter 2 stops radiation) and setting of the transmitter 2
stand−by (RF relays)
S enter state 5 (switch off state)
− State 3 and State 4 are not used.
− State 5 (alarm state switch off)
This is the switch−off state. It can be entered either from state 1 or 2 depending on the transmitter
configuration, if the stand−by transmitter is not available. In this case, the equipment has to be
switched off. In order to guarantee a time−out of 20 s between subsequent attempts of switching
on the equipment after a switch−off, the monitor waits 20 s in an idle loop and then switches off.
Ed. 07.04 48 SB 1−55

DVOR 432
1.10.3.7.1 Short Description of the MAIN PROGRAM Modules
INIT
This module initializes the monitor hardware (interrupt controller, timers, serial controllers, output reg-
isters).
CMOSRAM_CHECK
This module checks the integrity of the monitor data in the non−volatile memory area (CRC check).
Based on the result of this check, the stored data are used (check ok) or set to default values (check
not ok, BITE indication).After that, all variables required for the monitor operation are initialized.
EPROM_CHECK
This module computes the BYTE−sum of the installed EPROM’s and compares this sum with the
checksums stored in the serial EEPROM. If an error is detected MONITOR FAULT is set.
CHANNEL_SELECTION
The channel selection routine updates the frame counter which checks the monitor channel timing,
and determines the next channel to be activated on the basis of a channel sequence table. It uses
the channel number to establish the channel selection code and outputs these to registers on the
MSP. It also updates the AGC settings. The routine also manages the channel setup in single−chan-
nel mode, if the monitor is in BYPASS mode. If the single channel mode is selected, the desired chan-
nel number is derived from the programmed channel number
DFT_FILTER
While the measured values of the new channel (x) are being sampled, this module performs a har-
monic analysis (DFT) for the 32 measured values of the previous channel (x−1), in order to compute
the RF level (mean of the 32 measured values) as well as the real and imaginary components of the
30 Hz signal and its first four harmonics (60 Hz, 90 Hz, 120 Hz, 150 Hz).
It determines the individual signal amplitude from the real and imaginary components. Finally, it saves
the computed values for future evaluation.
ALARM_CHECK
This routine uses the results of the DFT FILTER for a further signal evaluation and an alarm check.
Depending on the channel which needs to be processed (x−1), it checks the measured channel pa-
rameters against the set alarm limits, updates the associated alarm flags in the status field of the indi-
cation lamps.
ALARM_EVALUATION
This module starts by checking the MAINAL bit from the status exchange interface (messages from
the co−monitor). If the co−monitor has set the MAINAL bit, it has initiated a changeover or switch−off
procedure. In this case the routine determines the necessary transition to one of the defined alarm
states.
If MAINAL is not set, the routine checks the alarm status output of the ALARMCHECK module (alarm
flags in the status field of the indication lamps) and updates the alarm counter. The further proceeding
depends on the value of the alarm counter and on the monitor bypass, monitor fault and monitor con-
figuration conditions (AND, OR). Based on these conditions, it decides to stay in the current state or
to enter one of the alarm state.
1−56 48 SB Ed. 07.04

DVOR 432
BITE_EVALUATION
The BITE routine compares the measured values (equipment parameters, e.g. operating voltages)
which are measured in the 960 Hz interrupt routine fixed, predefined limit values contained in a table
of constants in the EPROM. It updates the internal BITE result list on the basis of the test results. The
routine also check the digital BITE signals and updates the result list.
COMPLETE_PROGRAMMING
If the monitor is in the BYPASS mode and the PROGRAM Flag has been set by the COMMUNICA-
TION_INTERRUPT, this module interprets and executes LCP input commands based on the specified
monitor command set (alarm limit, calibration factors etc.).
MONITOR_MANAGEMENT
This module is responsible for internal monitor house−keeping. It manages updates of status infor-
mation (aerial/standby flag, transmitter status, etc.). It continuously compares the set alarm limits with
the maximum permissible limit and sets MONITOR FAULT, if an alarm limit is set outside meaningful
values.
ALARM_EVALUATION
See above, alarm states 1, 2 and 5.
1.10.3.8 Interrupt Program Modules

See Fig. 1−36.
960_HZ_INTERRUPT
The 960 Hz hardware interrupt informs the processor that new, digitized measured values are avail-
able for input. The main task of the 960 Hz interrupt service routine is to accept the sampled data from
the MSP−CD A/D converter. The value of the interrupt counter is increment, and checked after each
interrupt to ensure that it is between 0 and 63. If the value reaches 64, the cycle for the current channel
evaluation is terminated by setting the counter to 0. Based on the interrupt counter, the program per-
forms some further tasks:
− generation of the 120 Hz dynamic monitor life signal
− up−dating of the elapsed time counter
− managing of the frequency measurement
− managing of the analogue BITE measurements
− managing of the identity code measurement
COMMUNICATION_INTERRUPT
This module controls the serial controller on the MSP−CD, which handles the data exchange with
the LCP via a serial interface (RS232C, V.24 level) according to the defined Navaids 400 communica-
tion protocol for the communication process hLCP to Sub−Units" (Sub−Units are the monitors and
transmitters). The LCP is the communication master. The synchronization to the start of telegram is
realized in software, the hardware handshake lines of the serial communication interface are not used.
Ed. 07.04 48 SB 1−57

DVOR 432
Start
Telegram answer or input no

no action
complete
yes
Input telegram valid no

no action
yes
Input or output output
input
Bypass On
Load requested data to
yes no output buffer
Set program flag Set message

’Not in Bypass’
Start sending first byte of answer of telegram
Return
Fig. 1−35 Basic structure of COMMUNICATION INTERRUPT (valid for transmitter and monitor)
960 Hz INTERRUPT
Evaluation of monitor state
monitor state "NORMAL" monitor alarm case
Evaluation of Interrupt Counter
No Action
Check of interrupt counter
> 31 <= 31
Input of Channel−Measurement
Data from MSP
Evaluation of Action Table Using Interrupt Counter
Elapsed time Frequency,

No Action BITE,
meter
Identity code
measurement
Increment Interrupt Counter
End of Interrupt
Fig. 1−36 Basic flow diagram of the 960 Hz INTERRUPT service routine
1−58 48 SB Ed. 07.04

DVOR 432
1.10.4 Description of LRCI Software
1.10.4.1 Short description of the Modules
See Fig. 1−37.
The LCP−Software is a customer of the RMMC−Software−package, e.g. the LCP−Software get the
orders from the RMMC−part with the DEPOSIT−ORDER−command and returns the result with the
DEPOSIT_RESULT−command. The RMMC−part controls the communication to the remote control
and the LCP−part the communication to the subsystems inside the station. The Modules of the LCP−
Software are:
− REU−CUSTOMER−MANAGEMENT
Receives Order and perform queueing with DEPOSIT−ORDER command. After queueing the
PERFORM entry of the task is called and performs a rendezvous with the four subsystem tasks
by calling REQUEST−STATI. After completion of data acquisition the SUBSYSTEM−MANAGER
reports ALL−READY and terminate the rendezvous. The command SPLIT−RESULT splits the tele-
gram information into data−records. The command PUZZLE−Result prepares of these records
the RESULT−telegrams. The DEPOSIT−Result command finally returns the RESULT−telegrams
to the RMMC−part of the SW−Package.
− SUBSYSTEM−MANAGER
The SUBSYSTEM−MANAGER contains the four tasks depending to each Subsystem(TX1, TX2,
MON1, MON2). It performs the communication between the subsystems and the LCP.
− CSL_MANAGER
The CSL−MANAGER consists of two tasks. The T_ADW_CTR task controls the multiplexer and
ADC and is responsible for data−acquisition of BITE. The T_BCPS task is responsible for the cal-
culation of the Battery−Capacity.
− INC_MANAGER of the Station.
Consists also of two tasks. The T_BUTTON_OBSERVER task controls the pushbuttons of the
LCP−panel and the T_AUTO task controls the automatic activities.
Ê
ÊÊ
PC Terminal
External Communication (e.g. RMMC)

RS232/RS422/T TL RS232/RS422/T TL RS232/RS422 TTL RS232 RS232
1. Dial DME 2. DIAL NDB AUX 1 other LGM1 RC Unit LOCAL PC Diagnosis
COM3 COM4 COM5 COM6 COM8 COM7
Communication to external units
DEPOSIT RESULT DEPOSIT ORDER
CSL_MANAGER T_CONTROL INC_MANAGER
T_ADW_CTRL
LCP T.BUTTON:OBSERVER
SUBSYSTEM_MANAGER
Internal Communication
T_BCPS T_AUTO
T_SUB T_SUB T_SUB T_SUB
I_AM PERFORM_EXTERNAL_ACTION
RS232 READY PERFORM_INTERNAL_ACTION
COM9 COM10 COM1 COM2

Mon1 Mon2 TX1 TX2
Fig. 1−37 Overview LCP SW structure
Ed. 07.04 48 SB 1−59

DVOR 432
1−60 48 SB Ed. 07.04

DVOR 432
Equipment Description Description Transmitter and ASU
CHAPTER 2
TECHNICAL DESCRIPTION DVOR
TRANSMITTER AND ANTENNA SWITCHING UNIT (ASU)
2.1 GENERAL
2.1.1 System Overview
The DVOR installation comprises the following main components and accessories:
− Transmitter rack housing the transmitter and monitor, single or dual, the antenna switching control
and RF feeding (ASU subassemblies) and a power supply/battery charging (BCPS)
− Emergency power supply (48 V lead battery)
These components are housed in a building or shelter. Since there is possibility of generated oxyhy-
drogen, the battery is separately housed.
− Antenna system
The DVOR antenna system comprises 49 individual antennas mounted on a counterpoise with a
diameter of approx. 26 m (optional: 30 m) and supported at a height of 3, 5, 7 or 10 m above the
ground by an appropriate number of struts.
− PIN−Diode Switching Unit (PDSU)
The PDSU is seen as part of the ASU subassemblies. As standard, it is located outside the shelter
and mounted with an appropriate support below the DVOR counterpoise. Optionally it can also
be mounted within the shelter.
− Monitor dipole
The nearfield monitor dipole is mounted on a mast in a distance of approx. 200 m from the center
of the counterpoise at a height of approx. 1.3 m above the counterpoise.
As an option, a nextfield dipole configuration can be used instead of or in addition to. For informa-
tion about nextfield monitoring refer to Annex Nextfield in this manual.
− Cable set
− Grounding
The cabinet and the PIN−diode switching unit below the counterpoise are connected via 5 coaxial
RF−cables and a control cable. The switching unit feeds the antenna system via 48+1 coaxial cables.
External signals obtained via the 1 (or optional 2) nearfield monitor dipole(s) are supplied to the moni-
toring system (consisting of 1 or 2 monitors). If only 1 nearfield monitor dipole is used (standard instal-
lation) the coaxial connecting cable between the monitor dipole and the monitor is led in the building
or shelter to a divider, which distributes equivalent signals to the dual monitors.
A grounding network must be laid around the shelter; but there are no special requirements made
with respect to its symmetry.
The DVOR transmitter can be controlled, monitored and maintained from the tower via a respective
remote control and monitoring system (e.g. RMMC).
Ed. 07.04 48 SB 2−1

DVOR 432
Description Transmitter and ASU Equipment Description
2.1.2 Basic Components of a Transmitter Rack

The main components of a DVOR transmitter rack are as follows (see Fig. 2−2):
− Transmitter
− Monitoring system (monitor)
− Local/remote communication interface (LRCI)
− Operating voltage supply
− Antenna switching control and RF feeding (ASU subassemblies) and PDSU
The PDSU should also be included in this list as far as its function is concerned, though not from the
point of view to the assignment of subassemblies of the transmitter rack.
2.1.2.1 Transmitter
The dualized transmitter generates the RF signals required for this type of installation. These signals
are fed to the ASU subassemblies and the PDSU and radiated via the antenna system. Signal genera-
tion and transmitter control are microprocessor controlled. A single transmitter configuration is also
applicable.
2.1.2.2 Monitor
The dualized monitor is supplied with signals from internal sensors and informations obtained from
the radiated RF field via a monitor dipole. The RF signals obtained are digitized and fed to the monitor
signal processor for processing. A single monitor configuration is also applicable.
2.1.2.3 Local/Remote Communication Interface
The LRCI is the focal point for internal/external communication between the transmitter and the moni-
tor, the local or remote operator and the system, including any connected subsystems. All commu-
nication with the system takes place via a local or remote intelligent terminal (PC or laptop), which
is used for all settings, commissioning and maintenance. Both MAIN STATUS indication, basic set-
tings (on/off, change over, Mon. Bypass) and call up of certain transmitter or monitor measurement
data is performed with the Local Control Interface (LCI) of the Local Control Panel (LCP).
2.1.2.4 Generation of the Operating Voltages
See Fig. 2−3.
The transmitter rack requires a nominal supply voltage of 48 V. The mains module (ACC) of the BCPS
supplies an output DC voltage of 54 V and max. 12 A. Two or three of the modules are connected in
parallel depending on the power requirement of the navigation system. The value of 54 V is derived
from the trickle charge voltage for a 48 V lead battery.
The DC/DC converters housed in the transmitter rack and the PDSU act as switched−mode regula-
tors, which supply the necessary supply voltages +28 V, ±15 V and +5 V and −24 V (PDSU) with
a high efficiency. The voltages are generated by the following types of converter, namely:
− DC/DC−Converter DCC−MV : +28 V/11 A; +15 V/2.5 A; −15 V/1 A; +5.2 V/3 A
− DC/DC−Converter DCC−28 : +28 V/14 A
− DC/DC−Converter DCC−3−05 module 1 : +5.1 V/1.2 A
− module 2 : +5.1 V/1.2 A
− module 3 : +5.1 V/5 A
− DC/DC−Converters on BSG−D (ASU) : ±15 V/1.6 A; +5.1 V/5 A
DC/DC−Converter of ASU−CIF (PDSU) : +5.1 V/5 A; −15 V/1.6 A
The DCC−3−05 contains three individual modules on a single board, which supply the monitors and
the LRCI−subassemblies. The DCC−28 is used only in the 100 W versions.
2−2 48 SB Ed. 07.04

DVOR 432
approx. 200 m (typical)
DVOR antenna system (1)
A24
A46 2
A16
A48 A49 Carrier antenna A14
**
A1 A13
A47 **
A2 A12 A15
** A3 A4 A5 A6 A7 A8 A9 A10 A11
** ** **
** ** ** ** **
** ** ** ** ** **
1...48 A15...A47
49
4 Control
* optional
** Coupling cables between antennas 1...48 and the correspondent decoupling module
SB1/2
3 DVOR−Shelter
are optionally available; the standard version uses no coupling cables. A matcher module is
availiable as option.
Mon2*
Mon1
Tower Carrier
5
7 6
1 Antenna system: 48 sideband antennas, 1 carrier antenna 5 DVOR−transmitter rack

2 Monitor dipole (1 or 2) 6 Battery for emergency power supply
3 Divider (used with 1 monitor dipole) 7 Remote control
4 PIN−Diode Switching Unit (PDSU)
Fig. 2−1 DVOR 432 system overview
Antenna system
Monitor Dipole(s)
49 1...48
PIN−Diode Switching Unit
CSB SB1 SB2
antenna switching control and RF feeding
Transmitter Monitor
RS 232 RS 232
LRCI
Modem
Operating voltages RS 232
RMMC Terminal
(PC/Laptop)
DC−Converter
Supply voltage
Mains ACC (BCPS)
Transmitter rack
NOTE: Diagrammatic view, dual installation not shown for purpose of clarity.
Fig. 2−2 Main components of a DVOR transmitter cabinet
Ed. 07.04 48 SB 2−3

DVOR 432
PDSU
ASU−CIF
DC/DC Converter
XMTR 1 MON 1 LRCI/CSL MON 2** XMTR 2**
* *
DC/DC DC/DC DC/DC DC/DC** DC/DC**
Converter Converter Converter Converter Converter
MOD−SBB
F2
BSG−D **
DC/DC
Converter on/off control on/off control**
on CSL sense
PMC−D sense (Iload/Ibat)
ASU−Interface control
sense
ASU TX1 Control input F1

TX2**
Supply line NAV
48 VDC
Mains module Mains module not equipped Mains module

1 2* 4
TX cabinet
* 100 W only Mains

** dual Version (115 VAC to 230 VAC)
Fig. 2−3 Power distribution (standard), block diagram
2.1.2.5 Antenna Switching Control and RF feeding (ASU) and PDSU

See Fig. 2−1.
The ASU subassemblies in combination with the separate PIN−Diode Switching Unit (PDSU) are
used to simulate the movement of the sideband antennas around the carrier antenna. Sideband an-
tennas 1 to 48 are supplied such that, for example, the radiation peak of SB1 results at antenna 1,
and at the same time the radiation peak of SB2 results at antenna 25 opposite. Antennas 2 and 26
are then activated immediately after. The orbiting frequency of the sideband is 30 Hz, which means
that this method permits simulation of almost continuous orbiting.
The genuine double sideband method (DSB) introduced in the System 4000 and also used with the
navaids generation AN 400 ensures a high degree of reliability through the now 48 sideband anten-
nas. A failure in 1, 2 or 3 sideband antennas will not lead to the failure of the antenna system, but rather
will cause merely a minor fault in the 30 Hz FM, the effects of which on the azimuth error characteristic
are relatively insignificant.
2−4 48 SB Ed. 07.04

DVOR 432
2.2 MECHANICAL DESIGN
2.2.1 DVOR Transmitter Rack
The cabinet is made of sheet steel. It can accommodate five standard 19" subassembly carriers (sub-
rack). The subracks are assembled with plug−in units which are designed as double or single Euro-
form printed circuit boards (PCB) with dimensions of 233.4 x 200 [mm] or 100 x160 or 100 x 220 [mm].
The printed circuit boards are interconnected in each subrack on a motherboard back panel. The sub-
racks itself are connected together via flat ribbon cables with plug−in connectors or via plug−in or
screw−on coaxial cables (used for RF connections) at the rear. The front of the cabinet is hidden by
a front door which can be key locked and swung open by a door handle. The local control and indica-
tion panel (LCP) is flush−mounted in the front door. The cabinet rear is closed by a rear door which
can also be swung open by a door handle. When installing the equipment sufficient access space
should be left between the rear of the transmitter rack and the shelter wall to allow to open the door
and the use of measuring equipment if necessary.
The RF outputs to the PDSU which supplies the antennas and the monitor inputs are located on top
of the cabinet. The AF or interface connections (e.g. PDSU−control, modem, voice amplifier, DME−
Interface etc.) are located on top of the cabinet and those for the power supply are located on the
back panel of the BCPS subrack or on a terminal bar in the lower part on the rear side of the cabinet.
The cabinet, which has a perforated metal plate at the top and bottom, is self−ventilated (no forced
ventilation necessary). The components of the RF Duplexer including the filter, the couplers and circu-
lators are mounted inside on the side walls of the cabinet and are accessible from the rear.
CAUTION
Do not block or seal the holes for the cooling air supply at the bottom of the rack or the
cooling air outlet at the top of the rack (transmitter)!
WARNING
The heat sinks of the modulators (MOD−110P) and of the carrier amplifier (CA−100C)
may warm up during operation. This is normal and does not have any affect on the func-
tioning of the devices. Avoid touching the heat−sinks when the cabinet door has been
opened for any reason. When replacing this subassemblies it is recommended to let
them cool down for a while or take suitable measures (e.g. gloves). When replacing the
subassemblies SYN and CCP avoid touching the heat sinks of the MOD−110P.
2.2.2 PIN−Diode Switching Unit (PDSU)

See Fig. 2−4, 2−8.
The PIN−Diode Switching Unit (PDSU) as external part of the antenna switching unit subassemblies
is accommodated in a special housing suitable for outdoor mounting. It is normally located below
the counterpoise. Optionally an indoor mounting is also possible. The input/output connectors are
located on one side of the PDSU. From the transmitter cabinet, 4+1 coaxial RF−cables and an AF
control and power supply cable are fed to the inputs of the PDSU. The AF control and power supply
input can be a CA20 35pin MIL connector (outdoor mounting) or a SubD37pin connector (indoor
mounting). From the PDSU 4x12 coaxial RF−cables are fed to the individual sideband antennas. The
carrier (CSB) RF−cable is fed directly to the center antenna. The PDSU contains two commutator
boards (ASU−C) and a ASU−control interface (ASU−CIF). The ASU−CIF board within the PDSU
is accessible from an opening on one side.
Ed. 09.05
07.04 48 SB 2−5
DVOR 432
PDSU
Housing, not assembled
1 2 3
4 5 6
rear view
front view
1 LCP front panel with key switch
2 front door locking
3 rear door locking
4 Input SB−RF (2x 2); Output SB−antennas (2x 24)
5 Access opening and location of AF control and power supply input if PDSU is mounted indoor
6 Location of AF control and power supply input if PDSU is mounted outdoor
Fig. 2−4 Transmitter rack DVOR and outdoor PDSU housing
2−6 48 SB 09.05
Ed. 07.04
DVOR 432
1 2 3 4
rear view
front view
1 Local Control Panel (LCP)

2 ASU subassemblies
3 RF−Duplexer RFD1−C
4 RF−Duplexer RFD2−SB
5 100 W Power Amplifier CA100C
Fig. 2−5 Transmitter rack DVOR, front door open
Ed. 07.04 48 SB 2−7

DVOR 432
Connector panel
Ê ËË Ê Ê Ê
Ê ËË Ê Ê Ê
Ê ËË Ê Ê Ê
Monitor & Control
USB
LSB
Circulators
Modem*
Modem*
Modem*
BP−C
ASU control
Ê ËË Ê Ê Ê
VAM*
LCP USB
MDS−D*
RFD Components:
Ê Ê Ê Ê
PMC−D
CSB
MSP−1
MSP−2
RF−coupler Dummy loads

−−
RF−coupler
DCC−3−05
CSL
RF−filter/Relays
Ê Ê Ê Ê
LSB
LSB
USB
Ê
Ê Ê
Ê Ê
Ê Ê
Ê
Ê Ê Ê Ê
cooling baffle
Ê Ê Ê Ê
Ê Ê Ê Ê
MOD−110P***
Ê Ê Transmitter 1 Ê Ê
MOD−110 or
BP−T /TX1
MOD−110
MOD−110
DCC−MV
MSG−C
MSG−S
Ê Ê Ê Ê
SYN
CCP
Ê Ê Ê Ê
Ê Ê Ê Ê
Ê Ê Ê Ê
CA−100/1
Transmitter 2**
Ê Ê Ê Ê
MOD−110** or
MOD−110P***
MOD−110**
MOD−110**
DCC−MV**
Ê Ê Ê Ê
MSG−C**
MSG−S**
SYN**
CCP**
Ê Ê Ê Ê
BP−T /TX2**
Ê Ê Ê Ê
Ê
Ê
PMM
Ê
Ê Ê
Ê
PMM
Ê
Ê
Ê Ê Ê Ê
DC/DC conv. 100 W
BP−DC BP−ASU
Ê Ê Ê Ê
MOD−SBB
MOD−SBB
Ê Ê Ê Ê
DCC−28**
BSG−D
ASU control
DCC−28
Ê Ê Ê CA−100/2**
Ê
Ê
Ê Ê
Ê Ê
Ê Ê
Ê
Ê Ê Ê Ê
AC/DC converter
Ê Ê Ê Battery and power supply connection
Ê
ACC**
Ê Ê Ê Ê
ACC
ACC
−−
Ê
Ê Ê
Ê Ê
Ê
BP−BCPS
Ê
Ê
Subracks:
Mains connection and mains filter
Front Rear
Version 100 W * optional ** not used in single version

NOTE: The diagram shows the locations of the plug−in and screw−on subassemblies (printed circuit boards). The mo-
dule assignment for DVOR is shown in greater detail in Fig. 2−7.
Fig. 2−6 Locations in the DVOR transmitter rack in the 50 W and up to 100 W versions
2−8 48 SB Ed. 07.04

DVOR 432
TYPE OF INSTALLATION: DVOR 50W, 100 W; Dual version TYPE OF INSTALLATION: DVOR 50W, 100 W; Single version
SUBRACK Subassemblies used SUBRACK Subassemblies used
View from left to right Cabinet, preassembled assign. to Cabinet, preassembled
Front door LCP LCP
Cabinet on top Connector panel Connector panel
Cabinet, rear, left, top 1x coupler; CSB 1x coupler; 1x RF−Filter CSB
RFD1−D: load, 1x relay, −
1x RF−Filter
Cabinet, rear, right, top 2x coupler, 2x circulator; SB1/SB2 2x coupler; 2x circulator; SB1/SB2
RFD2−D: 2x relay; load, 2x RF−Filter
2x RF−Filter
Monitor&Control, left CSL CSL
MSP−CD Mon1 MSP−CD Mon1
MSP−CD Mon2 − −
− − − −
PMC−D ASU PMC−D ASU
− − −
Monitor&Control, upper VAM*/** (100 W) VAM*/** (100 W)
right − −
Modem* LGM1 Modem* LGM1
Monitor&Control, lower DCC−3−05 LCP DCC−3−05 LCP
right Mon1 Mon1
Mon2 −
Transmitter 1 MOD−110 SB1 MOD−110 SB1
MOD−110 SB2 MOD−110 SB2
SYN−D SYN−V
MSG−S MSG−S
MSG−C MSG−C
CCP−D CCP−V
MOD−110**/110P*** CSB MOD−110**/110P*** CSB
DCC−MV TX1 DCC−MV TX1
Cabinet, rear side CA−100** TX1 CA−100** TX1
Transmitter 2 MOD−110 SB1 not assembled
MOD−110 SB2
SYN−D
MSG−S
MSG−C
CCP−D
MOD−110**/110P*** CSB
DCC−MV TX2
Power Management PMM PMM
Cabinet, rear side CA−100** TX2 not assembled −
ASU−Control MOD−SBB ASU MOD−SBB ASU
MOD−SBB ASU MOD−SBB ASU
BSG−D ASU BSG−D ASU
DC/DC−Converter** DCC−28** TX2 − −

DCC−28** TX1 DCC−28** TX1
AC/DC−Converter − −
ACC −
ACC ACC
ACC ACC
Cabinet rear, bottom Battery and power supply Battery and power supply
connection, mains filter connection, mains filter
* optional ** 100 W version only *** 50 W version only 1) Nextfield option
Fig. 2−7 Assignment and scheme of subassemblies for DVOR
Ed. 07.04 48 SB 2−9

DVOR 432
1 2 3
7 6
1 Mounting cover for PDSU subassembly 5

2 24 SB antenna BNC connectors (odd), RF−feeding to antennas*
3 24 SB antenna BNC connectors (even), RF−feeding to antennas*
4 PDSU housing
5 Control and DC supply connector (CA20 35pin MIL connector)
6 Handle, optional
7 Control and DC supply connector (Sub−D, 37pin), used with indoor mounting option
* screwed or Quick Lock (QN) version

1 2 3 4
9
10 5
11
1 ASU−C (commutator for 24 SB antenna, even)

2 Support with ASU−CIF board
3 ASU−C (commutator for 24 SB antenna,odd)
4 Mounting cover for PDSU subassembly, dismounted 8 7 6
5 RF−inputs (ODHI/ODLO) from transmitter
6 Control and DC supply connector (CA20 35pin MIL), used with outdoor mounting
7 Access opening
8 PDSU housing
9 RF−inputs (EVHI/EVLO) from transmitter
10 Cover, used with indoor mounting option
11 Control and DC supply connector (Sub−D, 37pin), used with indoor mounting option
Fig. 2−8 PIN−Diode Switching Unit (PDSU), housing and subassemblies
2−10 48 SB 09.05
Ed. 07.04
DVOR 432
2.2.3 Shelter
See Fig. 2−9, 2−10.
The Navaids shelter is used as permanent housing for electronic navaids equipment. The Standard
Shelter is a self−supporting transport unit which is especially suited for the whole range of transporta-
tion means. It stands all climatic conditions worldwide and is designed for a minimum life−cycle of
10 years with the exception of mechanical damages. To cover the requirements the Standard Shelter
bases on the definition on transport containers ISO/DIN standards. It consists of a self−supporting,
distortion resistant aluminium frame construction with eight ISO corners and standardized container
dimensions.
The walls are made of sandwich panels and give options for the fixing of various installation items.
The polyurethane layer ensures best thermal isolation. The floor is covered with an antistatic material
which is connected to the system ground to protect maintenance personnel and to avoid damage
of electronic equipment. The personnel door is located at the front side of the container. It is fitted with
a key lock and can be locked outside and from inside. The inner and outer sides of the shelter are
painted white (RAL 9002), and optionally with an additional outside finish in warning colours as per
ICAO Annex 10. The navaids shelter is anchored using the ISO corners and twist locks to four founda-
tion blocks. The shelter itself is splash−proof, resistant against sea climate and insensitive to salt wa-
ter, fungus and termites.
A complete electrical installation is already provided which can easily be adapted to specific project
requirements. The battery box, which is hermetically sealed from the interior in its operating state, is
accessible from the inside of the shelter and ventilated from the outside. Its shelf−type construction
provides space for a block of batteries (48 V, 256 Ah max.) for the Navaids equipment as well as for
collocated equipment. Ventilation is provided by one or two through−the−wall air conditioning units
and thermostat. The air conditioning equipment is designed to fulfil the environmental conditions for
all products installed in the container. One fire extinguisher is provided. Other options comprise ob-
struction lighting, heater, table and chair, book−shelves, or an additional sun roof.
2438
Support for A/C
2991 2438
(Dimensions in mm; Tare weight approx. 900 kg)
Fig. 2−9 Navaids shelter, dimensions
Ed. 07.04 48 SB 2−11

DVOR 432
10 ft Container Shelter
Air Conditioner (option)
Â
Â
Concrete foundation
Lead through used

for DVOR antenna Location of AN 400 cabinets
connections
Ventilation of battery box (DVOR, DME)
Battery Box
Wiring Diagram of electrical Installation
option box Main Distribution Panel

Main Fuse
switch
L1 *
L2
L3
Residual
Current Breaker
N 40
I>
0.03
FI1
B2A
B10A B18A C20A C20A C20A C20A

B10A
B10A
PE F4 F3 F1 F2 F5 F6 F7 F8 F9
change o.
Overvoltage
Protection
4 3 1
Spare 2 5 6 7 8 9 10
optional
..
optional
BCPS θ junction box

DME
.... + 48 V
− set to heater
.... TX DME A/C1 A/C2 36 °C
....
Earth Collector Bar
BCPS if available Temp.

TX Rack Sensor
DME Inside Light Socket outlets Air−Conditioner
etc. Single Phase "Option"
F21 (G0.2A)
F20 (K50A)
Station Ground
20 protected wires
− −
+
twilight obstruction light
Signal lines 90 V/Type F
Emergency battery switch antenna
NF 600 OHM 48 V
Line Terminal Box
* Example diagram for Mains Supply with 3 Phases, , N and PE
Fig. 2−10 Standard shelter, ground plan and electrical installation DVOR (example)
2−12 48 SB Ed. 07.04

DVOR 432
Equipment Description Transmitter Subassemblies
2.3 DESCRIPTION OF SUBASSEMBLIES OF THE TRANSMITTER RACK
2.3.1 General
All plug−in or screw−on subassemblies (printed circuit boards) in the transmitter rack are described
in Section 2.3, the subassemblies of the antenna switching control and RF−supply which are located
in the transmitter rack and the outdoor PIN−Diode Switching Unit (PDSU) are described in Section
2.4. Their tasks are described and illustrated with the aid of simplified block diagrams. The integration
within the complete system is shown in block diagram Fig. 1−30. More details about the subassem-
blies (printed circuit boards), which may exceed the information given in the following description part
and figures, may be taken from the circuit diagrams listed in Fig. 2−11.
2.3.2 Overview Subassemblies DVOR Transmitter Rack
SUBASSEMBLY ASSIGNMENT CODE NUMBER*) REFERENCE

Transmitter: 2.3.3
Synthesizer DVOR (SYN−D) 83135 28300 2.3.3.2

Modulator (MOD−110) 83135 26101 2.3.3.3
(MOD−110P) 83135 26200
Carrier Amplifier (CA−100C) 58351 01000 2.3.3.4
Control Coupler DVOR (CCP−D) 83135 29301 2.3.3.5
RF−Duplexer 1 (RFD1−C) 58351 00840 2.3.3.6
RF−Duplexer 2 (RFD2−SB) 58351 00830
Modulation Signal Generator Control (MSG−C) 83135 27200 2.3.3.7
Modulation Signal Generator Signal (MSG−S) 83135 27100 2.3.3.8
Monitor: 2.3.4
Monitor Signal Processor (MSP−CD)** 83135 22301 2.3.4.1

Control and Selector Logic (CSL) 83135 23100 2.3.4.2
Lokal/Remote Control Interface: 2.3.5
Local Control Panel (LCP) 83135 21001 2.3.5.1

Modem, dedicated line (LGM 1200MD) 84045 83233 2.3.5.2.1
Modem, switched line (LGM 28.8D1) 84045 83245 2.3.5.2.2
Voice Amplifier (VAM) 83131 71701 2.3.5.3
Power Supply: 2.3.6
DC−Converter 5 V (DCC−3−05) 83135 12100 2.3.6.2

DC−Converter Multivolt (DCC−MV) 83134 12300 2.3.6.3
DC−Converter 28 V (DCC−28) 83134 12200 2.3.6.4
Power Management Module (PMM) 83135 30500 2.3.6.6
AC/DC−Converter (ACC−54) 58341 20101 2.3.6.8
Antenna Switching Unit subassemblies (ASU) 2.4
*) The code numbers given may differ to those of the delivered installation in individual cases. In such case the actual code
number can be taken from the delivery list of the installation or the drawing set.
** The MSP−CD, Ref. No. 83135 22301 replaces the MSP−VD, Ref. No. 83135 22300 and the MSP−D, 83135 22400 (nextfield only).
Fig. 2−11 Circuit diagrams of subassemblies (Transmitter rack)
Ed. 07.04 48 SB 2−13

DVOR 432
Transmitter Subassemblies Equipment Description
2−14 48 SB Ed. 07.04

DVOR 432
2.3.3 Transmitter Subassemblies
2.3.3.1 Overview
The DVOR transmitter section, the function of which is to generate the RF signals and amplify the RF,
consists of the following subassemblies (single):
− Synthesizer SYN−D
− Modulator for carrier (1x) MOD−110P (50 W) or MOD−110 (100 W version only)
− Carrier amplifier CA−100C (100 W version only)
− Modulator for sideband (2x) MOD−110
− Control coupler CCP−D
− RF duplexer RFD1−C and RFD2−SB (relays used in dual version)
− Modulation signal generator (signal) MSG−S
− Modulation signal generator (control) MSG−C
The synthesizer supplies the RF input signals to the modulators (CSB, SB1, SB2) and a reference
signal (REF) to the control coupler. The modulators MOD−110P/MOD−110 supply the power which
is needed to drive the antenna in a system up to 50 W. In a 100 W system the modulator MOD−110
(instead of MOD−110P) and the carrier amplifier CA−100C are used in the CSB branch. The micro-
processor−controlled modulation signal generator generates and controls the signals of the trans-
mitter section.
2.3.3.2 Synthesizer (SYN−D)

See Fig. 2−12.
The SYN−D generates the RF fundamental frequency signals f0, f1 and f2, which are needed to supply
the modulators for the carrier (CSB) and the two sidebands (SB1, SB2). The frequency can be set
between 108 and 118 MHz. The frequency of the oscillators (VCOs) is determined by the channel pat-
tern of the synthesizer (50 kHz). The desired frequency channel can thus be set easily with the com-
puter if the frequency changes. The VCOs for the CSB and for SB1 and SB2 are synchronized with
a frequency difference of 9960 Hz by means of phase−locked loops (PLL). The synthesizer also sup-
plies a reference signal for transmitter monitoring, which is fed to the Control Coupler (CCP). The fol-
lowing functional units are provided for each frequency:
− Reference oscillator
− Control circuit and VCO for f0
− Control circuit and VCO for f1 (f0 + 9960 Hz)
− Control circuit and VCO for f2 (f0 − 9960 Hz)
− Phase coupler between the VCOs
− Phase−locked loop, Output stages and monitoring
The 20 MHz frequency generated by the reference oscillator is used in the PLL0 circuit (D3) to set the
voltage control value for the CSB−VCO to the required frequency value with the control signal ob-
tained from the frequency select circuit (D7). The PLL ensures that this frequency is maintained. This
RF−output signal is distributed in different pathes as reference signal, carrier signal CSB and for con-
trolling the sideband VCOs for SB1 and SB2. One path of the RF−signal is fed to Mixer U1 of the SB1
VCO. It generates the difference (IF) between the carrier frequency f0 and the sideband frequency f1,
which then is compared with the frequency difference preset by D15 via D10 in the phase control
circuit (D17). This signal is used to form the control voltage for the VCO. The RF−output signal is led
out as signal SB1. The RF signal of SB2 is generated similarly. The frequency difference signal for D18
is derived from D17. Signals BFM0, BFM1, BFM2 are used for frequency measurement on the
MSP−VD. Each RF output is assigned a BIT detector (BFR1, BFC1, BFSBA0, BFC2), which informs
Ed. 07.04 48 SB 2−15

DVOR 432
the MSG−C via MSG−S that the RF signal is present and correct. The locking of the SB1/SB2 PLL
is indicated via a LED each, located at the front of the SYN−D.
The location of the two SYN−D (transmitter 1 and 2) is shown in Fig. 2−6.
BFR1
V20 REF1
N39 to CCP
N24,59
N40 BFC1
to MSG−S
PLL0 VCO CSB 3 dB
G1 Divider Detector f=50 kHz f =108...118 MHz N4 V19 CSB1
20 MHz D3 N7,6 N11,59 to MOD−110
N
1
Phase/
frequency 3 dB
N9,8 N5,6,7 G2 N3
Reference Loop Filter
Oscillator Select 6 dB
D7 D1,2
V1 V2 V24 V23
6 dB
CSSYN1 BLPLL0
to MSP−VD/MSG−C
Frequency select
6 dB 6 dB
from MSG−C to MOD−110
N D6
40 BFM0
N2 D4 BFSBA0
G3 BFM0
V28 SB1/SBA
7868,400
kHz N17,60 to MOD−110P
Uref N43
N28
VCO SB1
f0−f f=9,96 kHz f0−9960 Hz
N47,49 V25 N16
D10 Detector N22
1
N Phase/
Frequency V39...43 2 dB V26 V27
D17 Select N51,50 N48 G4
Loop Filter
Select
D14,15 Comparator lo
V38 U1
IF HF
f0
N57
CSSYN2 setting
Frequency offset
f=9960 hz BFM0 BFM1
from MSG−C D23
Detector
Phase/ N BLPLL1
D21 to MSP−VD/MSG−C
Frequency BFM1 40
D16,11,12 D8 N15 V53
BFC2
V32 SB2/CSB2
N18 N21,64 to MOD−110P
Uref N45
N29
VCO SB2
F f0+9960 Hz
f0+f f=9,96 kHz
N53,52 V30 N20
Detector N23
Phase/
Frequency V44...48 2 dB V29 V31
D18 Select
N56,55 N54 G5
Loop Filter
Comparator lo
V49 U2
IF HF
f0
N58
BFM0 BFM2
D23
Detector
Phase/ N BLPLL2
D20 to MSP−VD/MSG−C
Frequency BFM2 40
D19,13,22 D9 N19 V54
Fig. 2−12 Synthesizer (SYN−D), block diagram
2−16 48 SB Ed. 07.04

DVOR 432
2.3.3.3 Modulators (MOD−110, MOD−110P)
See Fig. 2−13.
The modulators are modulatable RF amplifiers for the 108...118 MHz frequency band. They are used
as either carrier modulator/transmitter or sideband transmitter. Both the RF phase and the amplitude
of the RF signal can be modulated. The MOD−110P and MOD−110 differ in their maximum power
output. The MOD−110 is used for the sidebands (SB1, SB2) and the MOD−110P for the carrier (CSB)
up to 50 W. In the 100 W version the MOD−110 instead of MOD−110P acts as a driver for the power
amplifier CA−100C in the CSB branch.
The carrier frequency is amplitude−modulated in the carrier modulator (CSB) with a 30 Hz signal and
the identification (1020 Hz) and voice signals. The phase and amplitude of the carrier modulator are
analog−controlled. Since no SBO signal is generated in the DVOR system, the phase control voltage
is determined by comparing the measured phase value of the antenna switching unit with the setpoint
selected for the MSG−C. The position of the phase switch is computed by the MSG−C. The ampli-
tude control value is derived from the setpoint selected for the MSG−C and the actual value specified
by the control coupler (CCP).
The RF signal received from the synthesizer is supplied to an attenuator (−9 dB) at the input with a
level of 10 dBm. It is reduced there to a suitable level for the phase switch Z2. This switch allows proc-
essor−controlled phase shift keying (0°/180°) via IC4. The keying ratio can be adjusted slightly with
potentiometer R151, in order to optimize the carrier suppression in the sideband branch (factory ad-
justment). The RF signal is supplied to the first phase shifter Z3 with varicap diodes V25 and V26 and
then the second phase shifter Z1 with varicap diodes V16 and V17. The capacitance of these diodes
can be varied with a control voltage (UPH) via phase control circuit IC2, IC300 and IC1, in order to
set the transit phase of Z3 and Z1. Phase shifter Z3 enables the optimum phase control voltages
(approx. 5 V) of the next phase shifter Z1 to be set (for both the CSB and SBO). IC2 is fed with different
signals enabled by switch IC300 for individual purposes: In the MOD for CSB, IC2 acts as amplifier
for phase control for proportional control of the CSB signal. The I−controller IC1 compensates the
static phase offset and feeds a dc voltage to IC2, whilst IC2 compensates the phase of the CSB signal
as a function of the actual value. The input signals for IC1 and IC2 are obtained from the phase detec-
tor of the CCP. When the MOD is used as sideband transmitter, IC2 acts as amplifier for the control
value for setting the sideband phase. The SBO phase is controlled by software. The control signal
is received from the MSG−C. The RF preamplifier IC9/Q10 follows the phase shifter Z1. This stage
amplifies the level at the output of the phase shifter section to +13 dBm.
The RF output stage consists of three series−connected amplifier stages (Q11, Q12 and Q13). Each
stage is connected to the next stage, both at the input and at the output, by means of a complex trans-
formation network. The input signal is amplified by 10 dB in the RF driver stage Q11, modulated by
the RF driver stage Q12 and amplified by a further 13 dB in the RF output stage Q13. Q12 is modulated
with amplifiers IC6...8. The modulation amplifier disables the control circuit by means of a protection
circuit if the modulation signal is missed, to prevent possible damage to the RF power section. The
output network of Q13 is designed so that no tuning is necessary over the entire frequency bandwidth
from 108 to 118 MHz.
The output line contains a coupler (Z4), which extracts part of the RF at −20 dB and supplies it to the
CCP. When used as driver for the CA−100C this output is terminated by a load. Part of the reverse
RF power is supplied to a demodulator and made available as a BIT signal. The demodulated output
signal is made available via an amplifier (IC10) after decoupling as a BIT signal. The temperature of
the heatsink of the modulators is measured via R325 and fed to MSG−S for evaluation.
The location of the MOD−110 or MOD−110P (transmitter 1 and 2) is shown Fig. 2−6.
Ed. 07.04 48 SB 2−17

DVOR 432
to MSG−S
RF section 1 RF section 2
R325 to CCP
Detector
Phase switch Phase shifter Preamplifier controlled RF amplifier
0/180°
Reverse RF
IC10 ACxR
Q11 Q12 Q13 Z4
RF in RF out
from SYN Z2 Z3 Z1 IC9/Q10
UPH
R151 ACxM
dynamic
Phase control Driver Q4 IC10
IC4 IC2 Detector
AMC
IC300 Over amplifying IC6,7,8 AF amplifier

protecting circuit for mod. signal
static Q2, Q3
phase
control
IC3
IC1
IC3
F1
AF section
MODU actual nominal 28 V

0/180°−switch control
processor controlled Ph Up/ FCxPC FCxP from MSG−C Feedback signal Modulation signal
from MSG−C Ph down CSB Feedback FCxA MODCx
wired up as from CCP Phase from CCP for CSB from MSG−S
carrier modulator detector
x=1 or 2
to MSG−S
RF section 1 RF section 2
R325 to CCP
Detector
Phase switch Phase shifter Preamplifier controlled RF amplifier
0/180°
Reverse RF
IC10
ASBxR
Q11 Q12 Q13
Z4
RF in RF out
from SYN Z2 Z3 Z1 IC9/Q10
UPH
R151 ASBxM
Phase control Driver Q4 IC10
amplifier
IC4 IC2 Detector AMC
IC300 Over amplifying IC6,7,8 AF amplifier

protecting circuit for mod. signal
Q2, Q3
IC3 IC1
IC3 F1
AF section
not used not used not used

MODU actual nominal 28 V
control
0/180°−switching from MSG−C
processor controlled SBO−Phase Feedback signal Amplitude control
from MSG−C from Q4 for SBO from MSG−C/MSG−S
from MSG−C
wired up as sideband transmitter
x=1 or 2
Fig. 2−13 Modulator 110 and 110P (MOD−110, MOD−110P), block diagram
2−18 48 SB Ed. 07.04

DVOR 432
2.3.3.4 Carrier Amplifier (CA−100C)
See Fig. 2−14.
The CA−100C is a single−stage RF power amplifier for the 108...118 MHz frequency band with an
output power of 100 W. It operates with a balanced amplifier. The MOD−110 carrier modulator works
as a driver and outputs the control voltage, which is balanced by means of a filter and supplied to the
power FET V1A/V1B. The amplified signal is matched to an unbalanced line via a filter and supplied
to the −30 dB coupler at the output. Part of the forward signal is supplied to the CCP via the coupler.
The reverse signal is rectified and made available as a BIT signal (ACA1R). The signal upstream of
the coupler is likewise brought out as a BIT signal (ACA1) via another detector circuit.
The FET transistors and the wiring board are mounted on a heat sink, whose temperature is moni-
tored with R24. The 28 V supply conductors to the FETs are each protected by a soldered−in fuse
(F1/F2).
The location of the CA−100C (transmitter 1 and 2) is shown in Fig. 2−6.
28 V
F1/10 A Temperature monitoring
CSB to CCP
Detector −30 dB
R24
Reverse / BIT siganl
V5 ACA1R to MSG−S
Balancing filter Balancing filter
V1A
CSB in CSB out

from MOD−110 V1B KO
BIT−Signal
V4 ACA1 to MSG−S
F2/10 A
28 V
Fig. 2−14 Carrier amplifier (CA−100C), block diagram
Ed. 07.04 48 SB 2−19

DVOR 432
2.3.3.5 Control Coupler (CCP−D)

See Fig. 2−15.
The CCP−D is used to condition the forward RF signal components obtained via bidirectional cou-
plers on the MOD−110P or CA−100C (version >30 W). It demodulates the envelope amplitudes and
the RF phase of the CSB and the amplitudes of SB1/SB2, and returns them to the modulator as actual
values. The exact envelope curve is demodulated from the carrier (CSB) for the amplitude control cir-
cuit. An actual voltage is derived for the phase control circuit by comparing the RF phase of the carrier
signal (CSB) with the reference signal (from the synthesizer). The desired signal is electronically
through−connected to the measuring device for digital control of the sidebands (SB1 and SB2); the
amplitude is measured directly, and the phase indirectly, by analyzing the Cartesian components (u
x sin and u x cos ).
The CSB forward signal is supplied to the coupler N54 via a 3 dB attenuator and split into two compo-
nents of equal magnitude. One of the signal components at N54 is used to obtain the actual values
for the analog carrier control loop. The signal required for analog control of the carrier is supplied via
an attenuator and the amplifier N30 to the coupler N49 and split. One signal component at N49 is
demodulated by the precision modulator (N8, N1), then amplified with N7 and made available as the
analog controlled variable FCIA for amplitude control in the CSB modulator. The signal picked off by
the amplifier N2 is supplied to the MSG with inverse polarity as the BITE ACIF signal.
The other signal component at N49 is supplied to the mixer U1 via a 12 dB attenuator. This mixer
compares the actual CSB phase of N49 with the phase of the reference frequency RFref, which is sup-
plied to it directly by the synthesizer via a 12 dB attenuator and the amplifier N31. If the useful signal
and the reference signal are in phase quadrature, U1 outputs a 0 V control voltage via a filter to the
amplifier N9. If the phase shift is increased or reduced however, U1 outputs a proportional voltage,
which is then amplified by N9 and supplied as the analog signal FCIP to the phase shifter in the
MOD−110P (CSB). The absolute value of the RF phase of the carrier is insignificant, though it must
remain constant as a function of time, temperature and modulation depth.
The second signal component of the CSB signal at N54 is supplied to the PIN diode switch N45. The
forward signal of SB1 is injected into this branch via N45 and that of SB2 via N47. The control signals
required for these switches are supplied by the MSG−C. They act on driver stages, which make the
necessary control currents available for the diode switches. The signal produced downstream of each
diode switch is used to obtain the actual values for the three digital loops that control the sidebands
and the carrier. It is supplied to the coupler N51 via a 7 dB attenuator and the amplifier N34, and from
there to a demodulator (N14, N5) that measures the amplitude. It is then made available via the ampli-
fier N15 as the VRFA signal. This signal used for digital sideband amplitude control is supplied to the
MSG−S, digitized and further processed in the MSG−C.
The location of the two CCP−D (transmitter 1 and 2) is shown in Fig. 2−6.
2−20 48 SB Ed. 07.04

DVOR 432
12 dB lo U1 IF P−CS
FCIP
N31 N9 Phase CSB
W1 RF
HFref
from SYN−D N53
12 dB
12 dB R1
N30 N49 A−CS

W3 3dB
FCIA
CSB N8,N1 N7 Amplitude CSB
from MOD−110P N54
Control signals
or CA−100C (>30 W) from MSG−C
ACF
3dB
N2
Control
R3
N45
9 dB A−S/C
W2
SB1 VRFA
from MOD−110P N14,N5 N15 Amplitude SB
7 dB
N47 N34 N51
W5 9 dB
SB2
from MOD−110P
Signal select
Pin−Diode switch
P−CS,A−CS,A−S/C = measurement signals
Fig. 2−15 Control Coupler (CCP−D), block diagram
Ed. 07.04 48 SB 2−21

DVOR 432
2.3.3.6 RF−Duplexer and ASU RF−Components

See Fig. 2−16.
The RF signals of TX1 or TX2 are distributed to the components of the antenna switching unit by
means of the discrete RF−Duplexers RFD1−C (CSB) and RFD2−SB (SB1/2), with following compo-
nents:
− 3 coaxial antenna switching relays
− 3 harmonic filters Z7, Z1, Z2 (low−pass)
− Dummy load resistors and attenuators (2x)
In addition, there are RF−components in the following RF−signal path located on the RF−Duplexer
mounting plate. Its operation belongs to the phase monitoring function of the antenna switching con-
trol. These components are:
− 3 couplers (Z8, Z3, Z4)
− 2 circulators (Z6, Z5)
The function of the various components of the RF−Duplexer is to switch the antenna system over to
transmitter 1 or 2. The signals of the transmitter which is currently switched to the antenna by the coax-
ial antenna switching relays K1 (CSB) and K1/K2 (SB1, SB2) each pass through a harmonic filter, be-
fore being fed to the RF−components, the antenna switching control and RF−supply (MOD−SBB)
of the ASU−function. Any harmonics in the signals are filtered out by filters for CSB and SB1, SB2.
The transmitter which is active, but not switched to the antenna, is connected to a dummy load. The
changeover signals received from the monitor signal processor (MSP−CD) control the relays K1
(CSB) and K1/K2 (SB1, SB2). The relay position is fed back to the MSP−CD via CSL.
The location of the RF−Duplexer and ASU RF−components is shown in Fig. 2−6.
to outdoor PIN−Diode Switching Unit (PDSU)
EVLO EVHI ODLO ODHI

TX−cabinet
MOD−SBB MOD−SBB
20 dB
20 dB Z4
26 dB
Z8 Z3
1 1
Circulator Circulator
PMC−D USB 2 LSB 2
Z6 3 Z5 3
TX1 Control TX2
CSB RFD1−C SB1 RFD2−SB SB2
Harmonic filter Harmonic filter Harmonic filter
CSB USB LSB
Z7 Z1 Z2
50 Ohm/100 W/30 dB
50 Ohm/100 W/30 dB
50 Ohm/100 W
Antenna Antenna Antenna

changeover from MSP−CD changeover changeover
relay via CSL relay relay
K1 K1 K2
CSB/TX1 CSB/TX2 relay position SB1/TX1 SB1/TX2 SB2/TX1 SB2/TX2
Side wall, left, rear view changeover signals Side wall, right, rear view
Fig. 2−16 RF−Duplexer (RFD1−C RFD2−SB) and ASU RF−components, block diagram
2−22 48 SB Ed. 07.04

DVOR 432
2.3.3.7 Modulation Signal Generator Control (MSG−C)
See Fig. 2−17, 2−18.
The Modulation Signal Generator is formed by the MSG−C and the MSG−S. It generates and con-
trols the transmitter signals. The function of the MSG−C is to control all the operational sequences
which take place in the transmitter, e.g. control of the sideband modulation envelopes and the side-
band RF phases, while the MSG−S conditions the modulation signals for modulating the carrier and
sideband transmitters and processes BIT signals from the transmitter section. In systems which radi-
ate an identification signal (CVOR, DVOR), the CPU also generates the signal for keying this 1020 Hz
signal.
The MSG−C contains an 80C186 microprocessor as an embedded controller, together with the pe-
ripherals needed for various purposes. It is connected to the Local Control Panel (LCP) via a serial
interface. This interface is used to set the transmitter parameters and to report measurement results
and status information. The functions of the processor are defined by the associated software. The
processor and its peripherals have the following structure:
− Processor clock 20 MHz
− External address bus, buffered
− External data bus, buffered
− External control bus, buffered
− Serial EEPROM
− 16−bit register OUT (local data/local address)
− 16−bit register IN (local data)
− 8−bit register IN (status data)
− RS232 interface, 2x
− 1 MB EPROM
− 256 KB RAM, non−volatile, battery−backed
− Supply failure monitor, Watchdog timer
The MSG−C also accommodates other control and status registers, A/D converters and interface
circuits, including the signal RAM for signal generation and IN/OUT registers for ASU control.
SYN
Clock generation Readout control Bus coupling Signal memory
Address
MOD−110
Bus coupling
Chip−Select signals
Decoder
DL0..15
Bus coupling
MSG−S
Processor with AT1..7
memory
peripherals DT0..15
control n
Port signals
CCP
Hardware control signals
Coincidence A/D converter
circuit control
PMC−D
ASU−interface
Par/Ser RS232
Interface to LCP
RS232 LCP
Reserve
MSG−C
Fig. 2−17 MSG−C, simplified overview
Ed. 07.04 48 SB 2−23

DVOR 432
The Navaids 400 transmitter software is universal. The system type is stored in the serial EEPROM
(D63) along with various other information (program version and date, EPROM checksums). When
the system is switched on, the control program must first of all evaluate the information about the sys-
tem type. If the codes are unknown, an "Unknown system type" message must be displayed, so that
the operator can enter the correct type. The system type determines which transmitter signals must
be generated and controlled. It can be configured in the serial EEPROM of the MSG−C by means
of a command on the operator’s PC (remote or local). When a transmitter is started up, the CPU inter-
rogates the system type and generates the appropriate signals. During an initial startup procedure,
all the signals for power control remain set to zero.
The CPU of the MSG−C controls the transmitter functions with the aid of parallel registers and D/A
converters on the MSG−S. Two A/D converters on the MSG−S (D8,12), each with 32 channels, are
used to measure the analog BITE signals and the actual values for amplitude and phase control. The
control tasks include the following:
− Initialization of a transmitter after start−up, e.g. loading the modulation memories, setting of carrier
power and modulation depths
− Carrying out so−called ’fast’ amplitude and phase control for the sideband signals
− Modification of the entered transmitter parameters in the event of settings, alignments or mainte-
nance being necessary during operation (and possibly carrying out amplitude and phase control)
− Measurement and evaluation of the analog and digital BIT signals
The time base of the transmitter CPU is a 1 ms interrupt, which is generated internally in the CPU. This
interrupt also serves as the base for recording the measured values of the actual value signals used
to control the amplitude and phase of the sideband signals and to measure the analog BIT signals.
It has the highest priority of any interrupt in the system. There is also a second external hardware inter-
rupt from the serial communication controller (SCC, D16), which controls data communication with
the LCP. The Morse code is output in real time on the basis of a 1 ms interrupt.
All the data necessary to ensure orderly operation of the transmitter system (operating parameters),
such as tolerance limits and calibration factors, is stored in a background table in the non−volatile
RAM (D9,10) and protected by a check code (CRC). The transmitter software makes itself a working
copy of this data, providing no discrepancies are revealed when the memory area is checked before-
hand. In the event of an error (data lost due to dry battery, etc.) or during an initial startup procedure,
the transmitter operating parameters are taken from a default table stored in the EPROM (D7,8)
constant area. The data stored in the non−volatile RAM area is only accessed if the operator modifies
operational data in bypass mode. This is the only situation in which the entered parameters and the
checksum are updated.
Besides the processor part the MSG−C contains the following main functional units used for signal
generation and BIT evaluation control on the MSG−S:
− signal generation interface with signal memory (D57,58), address and data in/out registers
(D23,24,26,27,29,30)
− internal control (D31,32) and status register (D25,28)
− local address generation (D42..47)
− transfer and signal generation control circuits (D40,41,48..56) for MSG−S
The signals to be generated and controlled result from the type of installation. The sinusoidal modula-
tion signals are generated on the basis of a sine table with 16384 interpolation points per complete
period. The amplitude resolution is 13 bits. All the sinusoidal signals which are necessary to generate
the Navaids 400 signals can be derived from this table by means of address computations (modulus
16384).
2−24 48 SB Ed. 07.04

DVOR 432
DT0..7, 8..15 ID_CODE
OUT ID_CODE_DME
AT1..7 8 Bit
Register
DL0..7, 8..15 Control 2
ALC0...16 TX_MAINT
C1 D62 SP_OUT2
WR_DAC Signal SP_OUT1
Signal generation interface

control signals RAM
to MSG−S
internal controls for signal geneartion

128K
n D57 Decoder
CS DA1..8
and data transfer to MSG−S

Control
Synthes.
Signal
Transfer and signal generation

S.EEPROM
SP2TSC SC_AD1 RAM
CS_AD2 S_H2
D61
128K
CS_AD1 S_H1 6 8 D58
control circuits
SC_AD2 T_CODE0
T_CODE1
7 OUT START_T
16 Bit EQ_CODE
Control Control Control Decoder Register STRT_STP_U
signals signals signals chip select Local Addr. START_AD
16 Bit ALC15
A/D signal gener. signal gener. D/A conv. Register
conversion D29,30 CS ALC16
D54,56 Control 1 SH_1_R
D53 D52 D55 SH_2_R
IN SPREF1
16 Bit SP4TC0
sample
to CCP
A/D Control Register SP4TC1
Conver. Interface signal point SP4TC2
control Register Local data
control generation input C1 SP4TC3
D51
CS D31,32 EN_SIN_COS
D49 D50 D59,60 D26,27
OUT IN 0 Interface control

16 Bit 8 Bit A/D conv. control
status (D28) Register Register STS AD1 (D8) MSG−S
control (D31) ALC0..14 Local data Status 1 STS AD2 (D12) "
DLC0...15 output Serial data EEPROM
Bit 0...7 BLPLL2
Local Address generation
Register D23,24 CS
BLPLL1 SYN
Register Register SH ADR D28
KONC0...10
EN2 BLPLL0
D48 D46 D47
KOINC
DAT_EEP
ASC0..13 A/D direct control
Dekoder Interface control
Serial
Compare EEPROM D22 Watch Dog Trigger
MUX MUX MUX MUX
D40,41 D63 CLK
D42 D43 D44 DME_SHUT_DOWN
EN EN EN EN D45 EN2 0
POWE_ON_OFF
IN
8 Bit AERIAL_STBY
Register M2_FAULT
Counter/divider Status 1 M1_FAULT
491520 Hz Bit 8...15 5VM2
61440Hz D34 D25 5VM1
7.86432 TX DEF (TX address)
30720Hz D35 TC0..17
1920Hz MHz
120Hz D36
30Hz D37
D38
OUT
T15Hz 16 Bit CSL−OUT0..15
Register to ASU interface on
20 MHz PMC−D (DVOR)
CSL−OUT
RD/WR 2
CS
D17,18
Address
Timer IN
0 8 Bit
Register
CSL−IN CSL−IN0..7; from
ALE ASU interface on
PMC−D (DVOR)
DT/R EN1 D20
Processor 80C186 Data DTC0..15
SCC
P
INT S V3 V2
DEN D16
Control ATC0..15
Rx Tx
INT0
D1 SCC_INT
X7 Reset uP RAM LCP (A)

Battery Super− EPROM RS232
SL−389 visory Decoder 256 K 512 K Rx/Tx
V1
3,6 V D14 D9,10 D7,8 Reserve (B)
Life LED D13 EN EN D19,21
WDI
Fig. 2−18 Modulation Signal Generator (MSG−C), block diagram
Ed. 07.04 48 SB 2−25

DVOR 432
A total of 2048 interpolation points per signal (one 30 Hz period) is required for the output to the MSG
signal memory (D57,58), in other words every 8th table value is used to calculate the output values.
The phase resolution is as follows: 360°/16384 = 0.022°. For example the 1020 Hz identification sig-
nal comprises 34 periods during one 30 Hz oscillation. The 2048 interpolation points are then deter-
mined from the table with an increment of 8 x 34, weighted with the modulation depth and output to
the MSG signal memory.
The transfer sequence of a value to the MSG−C signal memory is as follows. The registers involved
are D23,24 (output data), D26,27 (input data), D29,30 (signal memory addresses), D31,32 (control)
and D25,28 (status acknowledge). If the transfer control circuit does not react a BIT failure is set.
− output designation address of signal memory
− output designation data
− set transfer start with pulse output to transfer flip−flop
− interrogation of transfer flip−flop status
The transfer sequence of a value from the MSG−C signal memory is as follows:
− output source address of signal memory
− set transfer bit code
− set transfer start with pulse output to transfer flip−flop
− interrogation of transfer flip−flop status at input register
The transfer mode is set with Bit 0 and 1 of control register D31,32. The modes contain: write to signal
RAM, read from signal RAM, write to coincidence register, write to D/A converter (on MSG−S). The
transfer mode "10" sends a statement to the interface control (D49) to write data to the coincidence
register (D59,60). The processor sets the sample point in the coincidence register, at which the A/D
converter control shall execute the measurement synchronized to the timing of the signal generation.
The sideband RF amplitudes are controlled digitally in a "fast" and "slow" mode. Fast control is used
when the operator changes a value, slow control is used for the system in operation. The actual value
is measured as follows:
− set channel VRFA of MUX1 on the MSG−S via control 1 (D31,32)

− select actual value of sideband to be measured on the CCP via control 1 (D31,32)
− unlock control circuits on MSG−C
− start coincidence check
− poll flag ready
− transfer data of A/D converter 1 of MSG−S via In register (D26,27)
If a fault occurs a BIT failure is set.
The sideband RF phases are also controlled digitally in a "fast" and "slow" mode. Fast control is used
when the operator changes a value, slow control is used for the system in operation. The slow control
is called up associated to the 1 ms interrupt. The actual value is measured as described for amplitude
measurement but channel VRFP of MUX1 is selected. If a fault occurs a BIT failure is set.
Analog and digital BIT signals are made available by the MSG−S for checking the reliability of the
signal generation circuits and the controlled subassemblies. The BIT measured values are checked
with configurable limits, and the results are stored in a table which can be displayed on the operator’s
PC if desired. If one of the monitored values is outside the specified limits, the transmitter CPU issues
a BITE warning on the main status panel. This warning is also output on the LCP (Local Control Panel).
The location of the two MSG−C (transmitter 1 and 2) is shown in Fig. 2−6.
2−26 48 SB Ed. 07.04

DVOR 432
2.3.3.8 Modulation Signal Generator Signal (MSG−S)
See Fig. 2−19, 2−20, 2−21.

The function of the modulation signal generator signal is to generate modulation signals for the carrier
modulator and the sideband transmitters. It cooperates closely with the MSG−C for initializing the
system, periodically checking the modulation depth and the reference powers and controlling the
sideband modulation signals (amplitude and phase). Data is exchanged in both directions. Together
with the MSG−C it polls and conditions the signals required for the various systems with the aid of
the software. Its most important tasks are listed below:
− Conditioning the carrier modulation signal (amplitude, identification, voice)
− Identification keyer/controller: generating the 1020 Hz identification tone and modulating it with the
code of the identification keyer as well as with the voice signal of the voice amplifier
− Conditioning the sideband modulation signals (amplitude, sign, phase)
− Interface to the synchronization logic for sideband control
− Digital/analog input BIT signals and A/D or D/A conversion
The modulation signals which are preconditioned in the MSG−S are passed on to the appropriate
modulators. The MSG−S receives the signals for the amplitude and phase measurements via the
control coupler and forwards them to the MSG−C. The latter supplies the signals for controlling the
actual value measurements of the amplitude and phase. Fig. 2−20 shows the signal path for genera-
tion of the modulation signals for carrier and sidebands, fig. 2−21 the signal path of the transmitter
BIT signals to the MSG−C.
sign VZSB1
VZSB2
DA_LOCAL_CONTROL D/A converter MOD−110
carrier
DL_0..15 MODC1A
MODC2A MOD−110
DA−R−CONTROL D/A converter MODSB1A sidebands
MODSB1P
MODSB2A
DL_0..15 MODSB2P
MOD−110
input register Bit signals
n digital SYN
Driver BIT−Signals
A/D converter SAMPLE&HOLD ANALOG internal
1 MULTIPLEXER analog CCP
1,2
BIT−Signals
external
A/D converter Driver analog
2 SAMPLE&HOLD ANALOG
MULTIPLEXER
HW CONTROL SIGNALS 3,4
STATUS SIGNALS
PORT SIGNALS n
MSG−C MSG−S
Fig. 2−19 MSG−S, simplified overview
Ed. 07.04 48 SB 2−27

DVOR 432
9960 Hz Low pass filter
WR_DAC
D Filter 1 Filter 2
A CSB1_ST5
Bus from/to MSG−C
N1 N3 N5 N8 N10 N11
Setting
DL0..7, 8..15
Mod. depth for CSB1
UREF_10VN
UREF D
AT1..7
10V A CSB1_ST
N17 N13 N15 D
A CSB1_ST6
Summing N14 N16
MODC1
CSB1 signal
DT0..7, 8..15
CSB1 Setting
D Identity 1020 Hz Uref CSB1 power
signal ID
A generation VOICE
N2 N4 N7 N9 N12
ID_ST
UREF_10V
ID_CODE Morse code keying SEL_SB2P= 0 : Phase control signal generated via RAM (ILS/VOR)
SEL_SB2P= 1 : Phase control signal generated via UREF (DVOR)
UREF_10VN
Setting SEL_SB2P N6 Select phase control signal
Mod. depth for SB2 modulator
voice
D VOICE_CSB
A SB2P_ST1
Setting
N19 N21,22 CSB2 power
Summing
CSB2 signal
Voice D
A CSB2
N26 N25 MODC2
D
A Setting
N18 N20 Phase control signal
N24 CSB1 modulator
D
A CSB_1_P
N33 N32 CSB1P
D
A
N29 N31
Setting
Generation SB1 power
Phase control signal
CSB1 modulator D
A SB1A
N27 N25 MODSB1A
SEL_SB1A= 0 : Amplitude modulation signal generated via RAM (ILS/VOR)
D SEL_SB1A= 1 : Amplitude modulation signal generated via UREF (DVOR)
SEL_SB1P= 0 : Phase control signal generated via RAM (ILS/VOR)
A SEL_SB1P= 1 : Phase control signal generated via UREF (DVOR)
N23 N24 SEL_SB1A
Setting
Generation Phase control signal
Ampl. mod. signal SEL_SB1P SB1 modulator
for SB1 modulator N28
D
A SB1P
N34 N32 MODSB1_P
D
A
N30 N31 Setting
Generation SB2 power
Phase control signal
SB1 modulator D
A SB2A
N42 N40 MODSB2A
SB2P_ST
D SEL_SB2A_0= 0 : Amplitude modulation signal generated via RAM (ILS/VOR)
A SEL_SB2A_0= 1 : Amplitude modulation signal generated via UREF (DVOR)
SEL_SB2A_1= 0 : Amplitude modulation signal selected with SEL_SB2A_0
N35 N37,38 SEL_SB2A_0 SEL_SB2A_1= 1 : Amplitude modulation signal generated as CSB signal
Generation SB2A_ST
Ampl. mod. signal SEL_SB2A_1
for SB2 modulator N41
D
A SB2P
3 Select signal N39 N40 MODSB2_P
D Control SEL_SB1A
register 1 SEL_SB1P Setting
A Low Byte SEL_SB2A_0 Phase control signal
N36 N38 D1 SEL_SB2A_1
SEL_SB2P SB2 modulator
Generation Control
Phase control signal register 2 8 Sign select signal
SB2 modulator Hi Byte for CSB and SB1,2
D2 −−−− not used in CVOR/DVOR
Fig. 2−20 Modulation Signal Generator (MSG−S), block diagram (1 of 2)
2−28 48 SB Ed. 07.04

DVOR 432
WR_DAC
Bus from/to MSG−C
CS_DA_1_R to N13 EN (CSB1)

an
Decoder CS_DA_2_R an N14 EN (CSB1)
to
DL0..12..14
CS_DA_3_R an N26 EN (CSB2)

to
Chip Select CS_DA_4_R an N27 EN (SB1)
to
for D/A convert. CS_DA_5_R to
an N42 EN (SB2)
transmitter bus CS_DA_6_R an N33 EN (CSB1)
to
CS_DA_7_R an N34 EN (SB1)
to
AT1..7
D3 CS_DA_8_R an N39 EN (SB2)

to
CS_DA_9_R an N19 EN (voice)
to
bit 0 VRFP
VRFA
SEL_D_BITE BUMODC1
DT0..7, 8..15
Decoder SEL_CR2 BUPHC1

AC1M
Analog AC1R
Chip Select Multiplexer BUMODSB1
for control and 1 BUPHSB1
input functions ASB1
ASB1R
BUMODC2
BUPH2
Converter 1 EN AC2M
D4
D5 AC2R
SEL0..3 ADVOR
D Sample
&
A Hold UREF10VN
D8 N43 BUMODSB2
bit 0
BUPHSB2
Temp. measure. ASB2
Power−Amp. Analog ASB2R
from CA−100C Multiplexer ACA1
N45 control Status control 2 ACA1R
ACA2
UREF10V from/to MSG−C ACA2R
ASP1
ASP2
Temp. measure. U_BATT
EN
on board
R243
SEL0..3 D6
N45
Temp. measure. bit 0 BFR1
MOD/1 SYN/2 SYN/1

CSB1 modulator from MOD−110 BFC1
BFSB1
N46 BFR2
INPUT Register BFC2
BIT signals BFSB2
Temp. measure. Bit 0...7 BLMODC1
CSB2 modulator from MOD−110 D17 BLMODSB1
EN2
N46
MOD/2
bit 0 BLMODC2
BLMODSB2
BASU (DVOR)
BFR0
INPUT Register
BFC0
SYN
SEL1_4 BIT−signals BFSBA0
Control register Bit 8...15 BFSBB0
from
2 4
Spare
Low Byte EN2 D18
3
C1 D7 IGS_C1
IGS_SB1
IGS_C2
to modulators
Control register 8 IGS_SB2
2 P_MODE_C1
CTRL_15
C1
Hi Byte SEL2_4 VZC1
D9 VZSB1
VZID
VZC2
VZSB2
Generation VRFP
sign 3 bit 0 VCC
CSB1, SBO1 FF CSB1ST2
input signals identity D13 CSB1ST5
D15 CSB1ST6
from control WR_DAC CSB1S2
register D2 2 Analog IDST2
FF IDST1
(see 1 of 2) Generation Multiplexer VOICEST
sign SEL1_4I D14 3 CSB1PST1
CSB2, SBO2 CSB1PST2
SB1AST1
D16 Converter 2 EN SB1AST2
SEL2_4I SB1AST3
Sample SEL0..3 D10 SB1PST1
D SB1PST2
&
A Hold
D12 N44 SB1PST3
bit 0 CSB2ST2
CSB2S2
SB2AST1
SB2AST5
control Status control Analog SB2AST6
Multiplexer SB2AST7
from/to MSG−C SB2PST1
4 SB2PST2
SB2PST3
VN−15−M
VP+15_M
EN V+28−1−M
V+28−2−M
SEL0..3 D11 ASP3
−−−− not used in CVOR/DVOR ASP4
Fig. 2−21 Modulation Signal Generator (MSG−S), block diagram (2 of 2)
Ed. 07.04 48 SB 2−29

DVOR 432
The modulation signals generated in the MSG−C are preconditioned in the MSG−S. The individual
D/A converters used for setting the signals are controlled from the MSG−C transmitter bus via De-
coder D3. The carrier modulation signal (CSB1) is a summing signal consisting of a dc component,
the navigation signal, identity and (optional) voice. The individual signal components (excluding the
dc component) can be set or changed by commands via software. The navigation signal from the
signal RAM on the MSG−C is fed to D/A converter N1 and via buffer amplifiers (N5,11) and a low pass
filter (N8,10) to a multiplying D/A converter N13 for setting the modulation depth. The identity signal
frequency of 1020 Hz is supplied via D/A converter N2 to amplifier N4, keyed with the ID code via soft-
ware switch N6 and fed via amplifier and filter N7 to the summing stage. The modulation depth of the
identity is set with the amplitude of the synthetic 1020 Hz sine wave. This setting is also valid for the
carrier modulation signal (CSB2) of the clearance transmitter in 2F installations. The voice is fed from
the voice amplifier to a multiplying D/A converter (N19) for setting the modulation depth then to the
summing stage. To set the CSB power the composite signal of N12 is fed to a multiplying D/A conver-
ter (N14) and via amplifier N16 to the CSB modulator. The phase control signal for the CSB modulator
is generated with D/A converter N29, set via a multiplying D/A converter (N33) and fed via N32 to the
CSB modulator.
The calculated sum curve of SB1 (SBA) is called up from the signal RAM and fed to D/A converter
N23, the phase control signal of SB1 (SBA) to D/A converter N30. Both are conditioned via software
controlled switch N28 for the type of installation (CVOR or DVOR) and supplied to multiplying D/A
converters N27 (power setting) and N34 (phase control signal setting) before they are fed to the side-
band modulator SB1 (SBA).
The calculated sum curve of SB2 (SBB) is called up from the signal RAM and fed to D/A converter
N35, the phase control signal of SB2 (SBB) to D/A converter N36. The amplitude modulation signal
is conditioned via software controlled switch N41 for the type of installation (CVOR or DVOR) and led
to multiplying D/A converter N42 (power setting). The phase control signal is conditioned via software
controlled switch N6 for the type of installation (CVOR or DVOR) and supplied to multiplying D/A con-
verter N39 (phase control signal setting). The sideband modulation signals are fed to the sideband
modulator SB2 (SBB).
The generation of the signs is controlled with the signal WR_DAC in D13,15 (sign CSB1, SBO1, iden-
tity) and D14,16 (sign CSB2, SBO2) and fed to the modulators. Control register D9 supplies the inter-
nal gain switch (IGS) control on the individual modulators.
The MSG−S contains four 16 to 1 multiplexers (D5,6,10,11) for evaluation of the analog transmitter
BIT channels including temperature measurement circuits (N45,46) for CA−100C, MOD−110 and
MSG−S itself. In DVOR installations additional 16 inputs (located on BSG−D in ASU rack) are fed
to input 15* (signal ADVOR) of multiplexer 1 (D5).
The MSG−C calls the BIT signals via control register D7,9. The signals are fed to the sample and hold
circuit N43,44 and converted to digital signals with A/D converter 1 (D8) or 2 (D12) and read for further
processing in the MSG−C. The digital BIT signals from the synthesizer and modulators available at
input register D17,18 are selected via Decoder D4 and read via the data bus from the MSG−C.
* (counting 0 to 15 for a 16 input multiplexer it means IN14)
The location of the two MSG−S (transmitter 1 and 2) is shown in Fig. 2−6.
2−30 48 SB Ed. 07.04

DVOR 432
Equipment Description Monitor Subassemblies
2.3.4 Monitor Subassemblies
The monitor section, which has its own microprocessor, monitors the radiated signal and detects any
errors or faults that might be critical for aviation. In addition to executive tasks, the monitor data can
be used to identify any deviations or minor deficiencies in performance at an early stage, insofar as
they might have a detrimental effect on the future continuity of service or system availability (warning
monitor). The response to an alarm is a logic−controlled changeover or disconnection of the trans-
mitters. This logic is described here together with the monitor subassemblies. The monitor subas-
semblies thus comprise:
− Monitor signal processor (MSP−CD)

− Control and selector logic (CSL)
2.3.4.1 Monitor Signal Processor (MSP−CD)

See Fig. 2−22, 2−23.
The MSP−CD is used in both the CVOR and DVOR systems. In the case of DVOR, two additional 9960
Hz directional voltages of the antenna switching unit (ASU) are evaluated. The MSP−CD ensures that
only correct navigation signals are radiated. If the navigation signals are found to contain errors, the
monitor signal processor initiates a changeover to the standby transmitter and disconnects the cur-
rently active transmitter. If the standby transmitter also radiates incorrect navigation signals, it is dis-
connected as well. The measurement units of the MSP−CD contain the demodulation, sampling and
conversion of the RF signal of the monitor dipole, processing of the signals of the ASU−control
(DVOR) for sideband antenna monitoring, processing of test generator signals and measurement of
BIT signals. The voice/signal is taken directly from the output of MUX1 to amplifier (N7) which permits
spoken announcements to be heard, along with any other messages which are modulated onto the
CVOR or DVOR signal, such as meteorological data in the AF band. Headphones or a high−imped-
ance loudspeaker can be connected to jack X12. The main functional units of the MSP−CD are as
follows:
− RF section for processing the monitor dipole signal

− AF signal processing
− Digital section with I/O ports
− Monitor processor with peripherals
Processor with
Monitor dipole RF signal processing memory
Peripherals
control
voice, X12, front side Monitor Data
to/from LRCI
Test signal RS232
generator (CSL) Multiplexer AF signal processing Multiplexer Status to/from
Co−Monitor
PMC−D 1 2
(ASU interface)
IN/OUT
Register to/from CSL
Low pass Multiplexer Sample A/D convert.
Analog data 3 & 12 Bit IN/OUT Bit signals
Hold Register internal
DC voltages
Fig. 2−22 Monitor Signal Processor (MSP−CD), simplified overview
Ed. 07.04 48SB 2−31

DVOR 432
Monitor Subassemblies Equipment Description
The field signal received from the monitor dipole is filtered by a band−pass filter for the 108...118 MHz
frequency band; it then passes through a switchable attenuator (N2,8,9) and is supplied to the AGC
amplifier (N10..12). The setting of the AGC amplifier is carried out by the monitor processor via D/A
converters N1,4. The user adjusts the control level of the RF attenuator so that the monitor measures
100 % RF level (normalization at RF level=100 %). The value set is not changed by the monitor during
monitoring. The downstream RF demodulator (V26,27,N15,16) supplies an envelope of the CVOR/
DVOR signal to the analog 8:1 multiplexer MUX1 (N6) which is used as preselector of one of the signal
sources for further processing:
− demodulated RF signal composed of dc, 30 Hz AM reference signal, 9960 Hz subcarrier
modulated with 30 Hz FM, 1020 Hz identity, optional voice
− signal from test generator (ATE1) composed of dc, 30 Hz reference signal, 9960 Hz subcarrier
modulated with 30 Hz FM
− 9960 Hz modulated with 30 Hz AM (DVOR)
− dc + superimposed ac voltages (DVOR)
The 1020 Hz frequency with the identification is filtered out directly to an individual evaluation chain.
In order to allow the presence of coded identification signals to be monitored with the necessary mod-
ulation depth, the 1020 Hz identification signal is supplied via a band−pass filter (N18), then rectified
(N21) and fed via a 10 Hz low pass filter to an identification level discriminator (N22) to confirm that
the set threshold limits have not been exceeded. Each time a transition occurs from an identification
interval to an identification code (1020 Hz), a flip−flop output is set and interrogated by the micropro-
cessor. The microprocessor resets the flip−flop again after the interrogation. If a correct identification
signal is not detected, the flip−flop is not set and an identification alarm is indicated.
All the other signals which pass through the MUX1 are amplified and filtered out in the AF signal proc-
essing section for subsequent evaluation and processing. The results of these circuits and the result
of the demodulated identification are supplied to a further 8:1 multiplexer MUX2 (N24). The signals
fed to the MUX2 are:
− DC + 30 Hz AM (from RC low pass filter)

− dc offset + 30 Hz FM (from FM demodulator V17...21)
− dc + superimposed interference (from AM demodulator N17, V24,25))
− reserve (signal ATE5, used for test purposes)
− dc keyed with Morse code (from output 1020 Hz identity signal demodulator N21)
The output of MUX2 is fed to a 60 Hz low pass filter which amplifies and suppresses the high frequency
interference components of the FM demodulator signal and the 9960 Hz subcarrier rectifier signal
(9960 Hz and harmonics). This signal is fed to channel 0 of a 16:1 multiplexer MUX3 (N28). In addition
the 9960 Hz subcarrier rectified signal is directly fed to the channel 15 of the MUX3. The other channels
of MUX3 are assigned to BIT signals of the dc converter. The output of MUX3 supplies the signals
selected by the processor to a sample and hold circuit (N29) and the A/D converter (N30). The fre-
quency signals of the synthesizer are fed to a digital 8:1 multiplexer MUX (D31) and selected for fre-
quency measurement in circuit D32. The measurement is executed for carrier (CVOR,DVOR) and up-
per and lower sideband (DVOR only). Depending on the interrupt scheme, the processor requests
the respective instantaneous value for evaluation. The measurement and evaluation of the signals
(first order parameter) including the frequency measurement results of D32 are executed in a fixed
monitoring time frame based on the 960 Hz interrupt signal. Each 960 Hz interrupt marks a measuring
interval. That means the processor is informed that a new measuring value at the A/D converter (N30)
is ready for transfer. The measurement of the analog BIT signals at MUX3 and the evaluation of the
indication signal are integrated in the general channel timing.
2−32 48SB Ed. 07.04

DVOR 432
UREF_10V 0
AGC
0/16 dB N4 N1 Reserve
A A (used in ILS)
RF−MON V26,27 OUT
108...118
MHz 0...16 dB N13,14 N15,16 D D 16 Bit
Register SH P
N2,8,9 N10...12 CS−GA CLK EE
EN SER EE
DAT IN EE
Analog ID discrim. CS−ATT

0 identity CS
1 MUX 1 D24,25
TEG ATE1
2 OUT
ASU DVOR
ME10KHZ 1020 Hz 10 Hz N22

MO10KHZ 3
N21
to MSP−CD/x
FAUREC2
N18 N22 0 MAINAL1
4...7 N6 SEL Morse−Indicat. TEGAL1*
dc keyed acc. to OUT FIRAL1
16 Bit SECAL1*
ATIS Morse code Register NFIAL1*
dc+30 Hz AM TESTAL1*
voice output MON_EXIXST1
X12 TX1 ON
N7 150 Hz X30/a10 TX1 OFF
600 Ohm used for
to CSL
TX2 ON
3.5 mm jack bush 30 Hz FM TX2 OFF
dc offset +30 Hz FM measurement only TX1 AERIAL
TX2 AERIAL
CS POWER OFF
D17,18
POWER ON
from MSP−CD/x
2 MAINAL2
Limiter 9960 Hz 30 Hz FM X28 5 kHz 0 TEGAL2*
FIRAL2
V46 N19,20 V17..21,N23 N26 SECAL2*
reserve 3 NFIAL2*
TEG ATE5 TESTAL2*
IN !MOFAU2
0 SEL 16 Bit !MOFAU1
dc + interference 1 OUT Register RFR1/1
Analog RFR1/2
from CSL
2 MUX 2 16 Bit RFR2/1
9960 Hz AM−Dem. 3 Register RFR2/2
4 OUT RFR3/1
N25 not used 5..7
MUX/att RFR3/2
N17,V24,25 control CS
D20,21 RFR4/1
N24 RFR4/2
D28,29
AF signal CS 2
60 Hz D/A control
Decoder
5VT1 0 Watch dog trig.
15Vt1
SEL to D14
−1
4 D23 Interf. control
15VNT1
28VT11 6
BIT signals 28VT21
DC converter 5VM1 4 0 STS AD
from SYN1/2
5VT2 3 Morse Code
15VT2 OUT BLPLL0/1
15VNT2 −1
12 Bit BLPLL1/1
28VT12 BLPLL2/1
28VT22 Analog A BLPLL0/2
5VM2 MUX 3 S&H IN BLPLL1/2
ABAT BLPLL2/2
N29 D 16 Bit
UREF_10V N28 Register BTX1/T1
BTX2/T1
from CSL
N30 BTX3/T1
BTX1/T2
4
960 Hz
BTX2/T2
BTX3/T2
CS D26,27 CHOV1
UREF 7,86432 A/D conv. Power On Off
MHZ
UREF −9.1V Control
feedback for exec. monitoring

N31,32 Timer 0 MONFAUDET 0 MONITOR_ID
UREF 6.8V G3 D33,34 5VT1 (DCTX1)
960 Hz 5VT2 (DCTX2)
DATEEP IN DATEEP
from SYN VL1/1,2
Frequency measure. D32 8 Bit MON_EXIXST2

CLKEE
BFM0/1 0
SEL Register not used
BFM1/1 1 Digital
BFM2/1 MUX
2
BFM0/2 3 OUT Timer 1 Timer 2 CS
BFM1/2 4 16 bit 16 bit D30
BFM2/2 Serial
D31 DATEEP
not used 5..7 EEPROM
GATE
D35
SCC
Address P
INT S
Timer 0
D16
20 MHz
ALE Rx Tx
G2 DT/R RD/WR 2
RS232 LRCI
Data Rx/Tx
Processor 80C186 Reserve
D19,22
SCC INT
DEN Control
INT0
D1 INT1
ABAT WDI from D23
Reset uP RAM EPROM

Battery Super−
S1 visory Decoder 256 K 512 K
3,6 V X7 D14 D13 D9,10 CS D7,8
Life LED CS
Fig. 2−23 Monitor Signal Processor (MSP−CD), block diagram
Ed. 07.04 48SB 2−33

DVOR 432
The A/D conversion control (D33,34) is supplied with a 960 Hz timing signal from the frequency mea-
suring circuit D32. A trigger pulse, which is tripped by this signal and supplied to the sample and hold
circuit, enables the instantaneous values of the waiting signals to be sampled there. A second trigger
pulse starts the A/D conversion in the A/D converter (N30). The output signals (data values) are sup-
plied to the monitor processor via the data bus. The monitor processor determines the DC component
and the signal components of the 30 Hz fundamental from 32 samples and supplies measured values
for the RF level, the 30 Hz AM and the 30 Hz FM. It also calculates the azimuth from the vectors of
the 30 Hz AM and the 30 Hz FM. It also determines the modulation depth and the signal "keying pres-
ent" for the 1020 Hz identification signal. The calculated results are compared against stored nominal
values. If the programmed alarm limits are exceeded a reaction is initiated.
The results of the monitoring are supplied to the Local Control Panel (LCP) to inform the operator at
any time about the actual status of the installation. The data is exchanged with the LCP via a serial
RS 232 interface (D19,22). The communication is interrupt controlled via the serial communication
controller (SCC) D16. The baud rate is 19200 Hz. The LCP is master for starting a data exchange. It
permanently requests the indication information from the monitors. The communication flow is indi-
cated by LED at the front panel of the MSP−CD board.
The monitor processor comprises an 80C186 microprocessor (D1) and the peripherals needed for
various purposes. The processor functions are defined by the associated software. A live LED at the
front panel of the MSP−CD board indicates operation of the processor. The processor and its periph-
erals have the following structure:
− Processor clock 20 MHz

− External address bus, buffered
− External data bus, buffered
− External control bus, buffered
− 16−bit register OUT, 3x
− 16−bit register IN, 2x
− 8−bit register IN, 1x
− RS232 interface, 2x
− 1 MB EPROM
− 256 KB RAM, non−volatile, battery−backed
− Supply failure monitor
− Watchdog timer
The monitor checks the EPROM sets (D7,8) during the initialization phase. The checksum of each
EPROM is stored in the EEPROM (D35). The input/output registers are used for transmitter control
signals to the CSL (D18,21,27), status signals from the synthesizer (D26), internal control (D24,25,
D28,29), feedback (D30) and coordination signals (D17,20) for executive monitoring and status ex-
change with the co−monitor.
The location of the two MSP−CD (transmitter 1 and 2) is shown in Fig. 2−6.
2−34 48SB Ed. 07.04

DVOR 432
2.3.4.2 Control and Selector Logic (CSL)
See Fig. 2−24 to 2−29.
The CSL has five main functional units:
− ON/OFF logic for transmitters 1 and 2
− Coaxial relay control
− Battery monitoring and over−discharge protection, free available auxiliary measurement inputs
− DME interface for collocation with DME
− Test generator
The CSL is supplied both with 5 VDC from the DCC−3−05/03 (also used for LRCI) and with ±15 VDC
from an on−board DC converter derived from the 48 V nominal voltage for specific control functions.
The shutdown message used for power management from the LCP to the BCPS via its optocoupler
interface is interrupted by X26 on the CSL, if e.g. no battery is connected.
Remote ON/OFF logic
Local/PC−Control Transmitter Control TX1 On/Off
On/Off from Manually on CSL DC−Converter On/Off for DC converter transmitter/ASU
Monitor 1 TX1/TX2
Monitor 2 TX2 On/OFF
CSB Coaxial relay control

Transmitter control:
Monitor 1 Changeover coaxial relay drive SBA (SB1)
Monitor 2 Aerial/Stdby TX1/TX2 SBB (SB2)
F2/0,5T Battery monitoring and addition. measurement inputs
48 V Over−
Battery discharge System On/Off
Battery voltages monitoring solid state relays on PMM
protection
over current circuit breaker
Analog voltage measurement Voltage LCP BIT evaluation
Temperature sensor (PT1000) measurement
from LCP DME interface
BCPS_OFF CSB X26 Identity Interface
control Optocoupler DME
BCPS_OFF_R TX On/Off PAL Interface
F1/1,6T Test generator

DC−Converter =
48 V = ±15 V Test generator Mon 1/Mon 2
N18
Fig. 2−24 Control and Selector Logic (CSL), overview

ON/OFF logic (Fig. 2−25): After initial on with power switches TX1 or TX2 the transmitter 1 and/or
2 can be switched on and off by entering a command code either at the LCP or at the local PC, by
the remote control or by an internal switching command from the monitor processor. The Off−com-
mand from the LCP can be inhibited removing jumpers X13, X14. As soon as transmitter 1 or 2 is
switched on, the DCC converters on the BSG−D receives its ON signal for the ASU. The transmitter
is switched on and off as follows: an On/Off command is sent to the logic (D25,16,7) of the CSL. The
output signals of this logic are fed to two flip−flop circuits (D32) which are set or reset by this signal
or a manual key switch at the front of the CSL board. The output supplies the driver switches (V50,51)
for the individual electronic switch control of the dc converter of both transmitters and ORed via NAND
gate (D18), the electronic switch control (V86,87) for the dc converter of both monitors. The TXOn
state is indicated for each with LED’s at the front of the CSL board. The dc converters of the monitors
and the ASU (on BSG−D) are switched off only if both transmitters are switched off (output of
D18="1"). A power−on reset (D25) sets the Flip−Flop circuits and circuits for control of a collocated
DME (Fig. 2−28) to a defined state. Circuits D35,36 are programmed logic arrays used to select the
monitor mode (D36) and the monitor fault reaction. In the event of an alarm or fault, a transmitter is
disconnected as soon as the monitor processor concerned receives the error message and sends
an OFF command to the ON/OFF logic. The control command from this logic causes the output volt-
ages of the DC converters concerned to be switched off.
Ed. 07.04 48SB 2−35

DVOR 432
S4 V33
Gate TX1on
LCP
digital control DC−converter

TX1on & PSTX11
TX1on M1 Flip−Flop D18 PSTX12
M2 S3 PSTX13
transmitter and monitor

X13
D32 V50 V91...93
TX1off
PSMON1
TX1off LCP &
M1 off D18
M2 V52 V86,87 PSMON2
S2 V34
TX2on
LCP
TX2on
& PSTX21
TX2on M1 Flip−Flop
D18 PSTX22
M2 S1 PSTX23
D32 V88...90
X14 V51
TX2off
TX2off LCP
M1 DME−Interface
M2 2 ST_1
D25,16,7 PAL off SEL_OR_FAULT PAL
OR ST_2
MON_EXIST/M1 Mode Select:
Monitor Fault
MON_EXIST/M2 monitoring
Power 4 X24
+5V
On X23
Reset D35
D25,7 2
D36
Delay 2 DME−Interface
TDELAY 7.5 Hz counter M2_1
from TG/D2 M2_0
D1,19,34 M1_1
PAL=programmed array logic M1_0
Fig. 2−25 Control and Selector Logic (CSL), Switch on logic

Coaxial relay control (Fig. 2−26): The transmitters are switched to either the antenna or a dummy
load locally, by remote control or by MSP 1 or 2. The RF paths are changed over by means of up to
4 coaxial relays. The position of each relay is announced to the MSP’s as BIT signals RFR1..4 via logic
circuits D21..24. To avoid unnecessary strain on the relays a changeover should be carried out with-
out TX power. For this a status flag is set on the CSL (D16/D31/2) which causes blanking of TX power
during, and keying after a changeover. BIT signals are generated via D31/1 and fed to MSP or DME
interface.
BIT signals
from MSP relay position
TX1_AERIAL/
M1 & K1/CSB D21..24
2 2 from MSP to MSG−C
D15 RFR1..4/1
M2 PWR_ON/
K1/SB1 4 M1 & power on/off
from MSP 2 2
TX2_AERIAL/ M2 D16 TX1,TX2
M1 & K2/SB2 FlipFlop
2 2 4 from MSP
M2 D15 D21...22 RFR1..4/2 PWR_OFF/ D31/2
M1 & M1,M2
2 2
M2 D16 to MSP
V53...60 BIT signals
FlipFlop CHOVI/M1,M2,T1,T2 to MSP hardware flag generation during
coaxial relais drive D31/1 5 CHOVI to DME interface change over procedure
Fig. 2−26 Control and Selector Logic (CSL), coaxial relays control
Battery monitoring (Fig. 2−27): In case of mains failure the power supply is continued without inter-
ruption by the connected emergency batteries. This means that the battery parameters have to be
tested to ensure the availability. The battery monitoring circuit (N15) measures the battery parame-
ters. The results are evaluated and respective actions are executed by the processor of the LCP. The
signals 1/2 (UBAT1±) and full (UBAT2±) battery voltage, battery current (IBAT±) and installation current
(ILOAD±) are supplied via differential amplifiers (N12) to the input of 16:1 multiplexer MUX (D11). The
current is proportional to the voltage drop over a resistor (0.002 ) located on the BCPS connection
panel (cabinet) each in the negative supply lines to battery and installation. The signals selected are
measured with the digital voltmeter DVM (D14) and fed to the LCP. The battery current is used as an
indication of the available battery capacity. As a result the DC converters for TX1/2 first are deactivated
by software command if the capacity falls below a programmed minimum value.
2−36 48SB Ed. 07.04

DVOR 432
The processor of the LCP, the CSL and the modems remain operational until the battery voltage drops
to a selectable value again. To prevent over−discharge, a voltage comparing circuit (N15) additionally
enables the overcurrent circuit breaker (H1..3) on the PMM. The standard protection is activated if
the battery voltage drops to a selectable value (with X19,20,21) or a user defined value with resistor
"R". After a delay of (D13) about 45 seconds, if mains has not returned the over−current circuit break-
ers (H3 on PMM) are tripped electromagnetically by V36 in order to disconnect the batteries from the
transmitter cabinet. Since the batteries are completely discharged the mains power supply must be
restored as soon as possible, or they will have to be recharged elsewhere to avoid damage. The instal-
lation has to be activated manually by TX1 and TX2 on the PMM. An automatic restoration of the instal-
lation after mains failure is available as a PMM option. This restoration is effected by circuits N9,14
and V35. For additional information refer to section "PMM". To the MUX (D11) can be supplied up to
6 external measurement voltages (range ±20 Vdc) via X84 and 2 externally connected temperature
sensors PT1000 (monitoring limits −50 °C/+200 °C) via X81/1,2 and 3,4 on BP−C.
Comparators Jumper:
F2/0,5 A N15 X18 Emergency battery exist
Delay Comp.
+48 V counter
H1,2,3 to PMM
V62 D13 N15 V36 3 (H1,2 not controlled)
N17
user X22 UREF 2,5V Comp. PF54 to PMM* Low if
X19 X20 defined UBAT > 48V
X21 R jumper enabling optional
hold−in circuit N9,14 V35 UBATmin to CSB
Low if
UBAT1− N12 not used Bat. discharged
UBAT1+ 0
1
U1 or fuse F2 blown
2
UBAT2− N12 control (MUX0...3)
3 from LCP
UBAT2+ 4
5
IBAT− 6 DVM
N11 7 MUX A/D conv.
IBAT+ 8 to LCP
R6 9
R5 10 D14 measured votage value
11
ILOAD− 12
N11 13 X19: 1.7 V (=40.8 V)
ILOAD+ X20: 1.8 V (=43.2 V)
14 X21: 1.875 V (=45 V)
Analog in (from X84 BP−CD) 15 D11
Temp in (from X81 BP−CD) R5/R6 factory adjustment R = continuous setting (40.8...45 V)
Fig. 2−27 Control and Selector Logic (CSL), battery monitoring, over−discharge protection
DME interface (Fig. 2−28): The function of DME interface is to through−connect the identification
code or the identification sync. signal of the CVOR/DVOR if they are collocated with a DME, so that
the CVOR/DVOR and the DME identifications are synchronized according to a defined pattern. If one
of the systems fails, the system which is still operational is informed by means of a digital signal. A
DVOR failure causes the DME identification to fall out of sync with the DVOR. A DME failure is reported
to the MSP−CD of the DVOR. Jumper on the CSL allow to match the exchange signals to the collo-
cated DME. Electrical isolation is ensured by the optocouplers in the interface functional group.
X5...X8 1−2=Optocoupler interf. 1
X7
X5...X8 2−3=Optocoupler + Darlington interf. 2
PAL +15 3
ID_OUT+
5VT2 ST_1 (24ID)
CHOVI ST_2 1 X8
ID_CODE DME/T1 V28 U1 2 3
ID_CODE DME/T2 V27
X11 ID_OUT−
3 2
5VT1 V77,75
MON 1 FAULT (DMEID)
1
T30/T1 V97
T30/T2 MON 2 FAULT 1
M1_0 X5
DME_ID or SYNC
2 OP_OUT+
M1_1 +15 3 (DMSL)
M2_0
STATION Operational X6
M2_1 1
D33 2 3
X12
3 2 OP_OUT−
ASSOC=1−3, 4−6 V77,,78
DME_STATUS X25 IND=2−3, 5−6 1 (VOROP)
V96
1 2 3
P12 S5
1
DMSD1 U2 3 OP_IN+
2
Inverter (DMSR)
4 X15
P13 6
DMSD2 D20 1=DME off V98 5 OP_IN−
0=DME on
(DM0VS)
Fig. 2−28 Control and Selector Logic (CSL), DME interface
Ed. 07.04 48SB 2−37

DVOR 432
Test Generator (Fig. 2−29): The test generator is an independent functional unit which generates
ILS/CVOR/DVOR AF−test signals to check the monitor. The test signals are stored in the EPROM
D9,10 (12 bit data). The memory is divided into an ILS range (16 test signals) and a CVOR/DVOR
range (16 test signals). These ranges are selected with jumper X17:
− X17 closed: ILS
− X17 open: CVOR/DVOR
The individual test signals can be selected with the rotary switch (S6) on the front of the CSL. The
switch has 16 hexadecimal coded positions (0 to F). Position 0 selects test signal 0, position 1 test
signal 1, etc. The test signals for CVOR/DVOR are so−called composite signals made up of a DC
component (approx. 6.8 V), a 30 Hz oscillation and the frequency−modulated 9960 Hz subcarrier.
The identification component is not part of the composite signals. The 9960 Hz subcarrier is frequen-
cy−modulated with a 30 Hz sine signal. The frequency deviation is ±480 Hz, which corresponds to
a modulation index of 480/30 = 16 (wideband FM). The phase between the 30 Hz AM and the 30 Hz
FM is 0° in the "0" position of the rotary switch and 90° in the "2" position. Like in an ILS system, the
signal of the test generator is part of the monitoring concept of a CVOR/DVOR system. This signal
is ideal for calibrating the phase evaluation of the two monitors, since it is generated digitally and is
thus extremely accurate. The accuracy of the monitor phase evaluation can be established and cali-
brated in the 0° phase position, for example. If the switch is then set to the 90° phase position, this
value must be confirmed by the monitors. In addition, the test generator signal supplies the exact
modulation depths of the 30 Hz reference oscillation and the 9960 Hz subcarrier (30 % modulation
depth each). In other words, it enables all the important measurements performed by the monitors
to be verified.
The following signals are assigned to the switch positions in the CVOR/DVOR range:
− 0 30 Hz AM, 30 %; 9960 Hz AM, 30 %; 30 Hz FM Mod.−Index=16; Azimuth= 0 degrees
− 2 30 Hz AM, 30 %; 9960 Hz AM, 30 % 30 Hz FM Mod.−Index=16; Azimuth= 90 degrees
− 3 30 Hz AM, 30 %; 9960 Hz AM, 30 %; 30 Hz FM Mod.−Index=16; Azimuth=135 degrees
− 4 30 Hz AM, 30 %; 9960 Hz AM, 30 % 30 Hz FM Mod.−Index=16; Azimuth=180 degrees
− A 30 Hz AM, 30 %; 9960 Hz AM, 30 %; 30 Hz FM Mod.−Index=15; Azimut= 0 degrees
− B 30 Hz AM, 30 %; 9960 Hz AM, 30 %; 30 Hz FM Mod.−Index=17; Azimut= 0 degrees
− C 30 Hz AM, 30 %; 9960 Hz AM, 30 %; 30 Hz FM Mod.−Index=25; Azimut= 0 degrees
− D Spare
− E Spare
− F Spare
The location of the CSL is shown in Fig. 2−6.
7864.320 Address EPROM

kHz D
counter 2x 512 K Mon1
A 9960 Hz
G1 D2..6 D9,10 N10 N7,6 N3,4 N5 N2
Test signal
Closed: ILS X17 Signal
Open: (D)VOR select Uref
0...F Mon2
S6 N8 N1
Fig. 2−29 Control and Selector Logic (CSL), test generator
2−38 48SB Ed. 07.04

DVOR 432
Equipment Description LRCI Subassemblies
2.3.5 LRCI Subassemblies
The local remote communication interface functional unit (LRCI) is the focal point for communication
between the various functional groups, the local control panel (LCP) and the remote control, and is
also used for certain other services (input for voice, weather report from the tower, etc.). The LRCI
consists of the following subassemblies:
− Local control panel (LCP)

− Modem for dedicated line (LGM1200MD, Party Line)
− Modem for switched line (LGM 28.8)
− Voice amplifier (VAM)
Each installation contains an LCP, which controls the LRCI functions and is responsible for local con-
trol and the local main status of the station. In addition to the serial interfaces for communication with
the monitor and transmitter processors (MSP−CD and MSG−C), it has an RS232 interface for con-
necting the local control unit to a standard PC with the ADRACS software and controls communica-
tion with the remote site via the modems. The LCP is supplied by an individual DC−Converter module
/3 on the DCC−3−05 board with +5 V and with ±15 V from the DC converter on the CSL.
(ADRACS = Automatic Data Recording And Control System)
2.3.5.1 Local Control Panel (LCP)

The LCP consists of two separate boards:
− Local Control CPU board (LC−CPU)
− Local Control Interface (LCI)
The location of the LCSU is shown Fig. 2−6.
MSG−C MSP−CD CSL MSG−C MSP−CD PC local PC−Remote PMM BCPS

Modems DME opto in opto out
LCU function Interface spare spare
TX1 TX2
RS232 in/out RS232 RS232 RS232/485/TTL opto out opto in in/out in out
opto out
Local Control CPU (LC−CPU)
Microprocessor DIMM−PC/386−I or DIMM−PC/520−I
in/out
Local Control Interface (LCI)
Fig. 2−30 LCP, overview
Ed. 07.04 48SB 2−39

DVOR 432
LRCI Subassemblies Equipment Description
2.3.5.1.1 Local Control CPU (LC−CPU)

See Fig. 2−31.
The LC−CPU and its processor is the switching center between the operator side (local or remote)
and the four subsystems of a dual Navaids system (two transmitters and two monitors). Its most im-
portant tasks are as follows:
− Communication control and communication with the various functional units
(e.g. transmitter internal, other systems like DME etc.)
− Sequence control
− Executive commands (e.g. to CSL via CSL connector X6)
− Local display control and local operation
− Remote control
− Battery measurement and monitoring
The LC−CPU board is equipped for these tasks with the peripherals needed for various purposes.
The CPU function is built by an individual CPU board (PC104 compatible), which is inserted to a
DIMM−connector on the LC−CPU board. The processor functions are defined by the associated
software. The respective memory area (EEPROM, DRAM, Flash memory) is located on the CPU
board. R/W−operarion of the RAM−disk is indicated by a flashing HD−LED. The real−time clock is
battery backed enabled via X36. The supervisory controller (D83) manages the battery voltage super-
vision, watch dog enabling (X35) and reset switch (S2). A live LED (H1) connected to the supervisory
controller indicates the LC−CPU is operable.
The LC−CPU board provides 10 serial communication ports. The serial communication controllers
(SCC) used have two channels each. Each channel has its own interrupt connected to an interrupt
request line on the PC104 bus. The serial controller clock input for baud rate generation is 1.8432 MHz
(standard PC COM). Three serial ports are provided with a jumper selectable signal interface which
can be set to RS232, RS422, RS485 or TTL. Each selectable port has an associated jumper bank:
− port 3: X95, X24, X41, X25...32
− port 4: X99, X15, X40, X16...23
− port 5: X8, X9, X11...14, X37...39
The following equipment functions and components are controlled via the serial interfaces:
− Communication between the transmitter and monitor processors (channel 1, 2, 9, 10)
− Communication with the local PC control unit (ADRACS software) (channel 8)
− Communication with the remote PC control unit via modem (channel 6)
− Communication with other equipment via serial interface or modem (channel 5)
− Additional communication channels via serial interface or modem, spare (channel 3, 4, 7)
The LC−CPU board provides several I/O registers with specialized signal function. After reset all out-
put register are cleared to zero. The Input/Output register function is used mainly to control both trans-
mitters. Registers 4, 5 (IN) and 6 (OUT) are used for control of battery measurement on the CSL. The
Local Control Interface (LCI) is controlled via registers 4,5 (OUT) and 3 (IN). On/Off commands for
TX1,2 are supplied to CSL via register 3 (OUT). Feedback signals from CSL (TX1on/TX2on) and BCPS
unit 1,2,3,4 (’exist’) are fed to register 6 (IN). They are used for information in the BIT program of the
LC−CPU. The number of installed ACC converter is entered by the user. Signal BFUSE from the bat-
tery switch signals an interruption of battery supply and is led via optocoupler (Addin1) and register
7 (IN) to the LC−CPU. The other additional optocoupler inputs (Addin2..4) are spare. The command
BCPS OFF supplied via optocoupler (Addout 2) and register 7 (OUT) to the BCPS, is used only if a
battery is installed and the battery capacity set is not 0 Ah. Additional executive commands (Ad-
dout1,3,4) are supplied via register 7 (OUT) to optocouplers. They are used for management of the
battery over−discharge protection (Addout1, 3, 4). Outputs Addout 5,6 are spare.
2−40 48SB Ed. 07.04

DVOR 432
Optocoupler
SCC RS232
Input 16552 Channel 1
Register port 1 Rx/Tx TX1
parallel 8x in X2 P
1
spare 8 8 8 bit
D10 port2 RS232
Optocoupler Channel 2
S Rx/Tx TX2
2
8
8 bit D63
parallel 8x in level conf. D50 RS485/
level 8 422
X81...84
configurable Output SCC TTL Channel 3
spare X2 Optocoupler Register 16552 LGM 2/DME
1 P PC Com 3
8 bit RS232
X2 D23 port3 Rx/Tx
configuration
parallel 8 jumpers
16 x OUT 2
spare 16 S
port4 RS485/
8 8 bit to UARTS (SCC) 422
D29 D71 TTL
Channel 4
CSL Interface Register LGM 3/NDB
PAL PC Com 4
from CSL Input Decoder RS232
ADB1...8 Register D80 Rx/Tx
X6 8 4 configuration
D1 jumpers
SCC
from CSL 16552
Input I/O
ADB9...12 Register P port6 Channel 6
X6 4 Decoder TTL
5 LGM1
OR (D14)
D2 D65,68 A0...3 RC−Unit
POL (D14) 4
STAT (D14)
UBATmin Output S
Register RS232 Channel 9
to CSL 6 port9 Rx/Tx Mon 1
MUX0,1,2,3 (D11) X6 8 D7 D0...7 D72
CTL bit 3,5..7
RUN (D14)
Output SCC
Indication control Register 16552
4,5 P RS232 Channel 7
16 bit port7 Rx/Tx PC Com 2
D39,38
Input S
Local Control Interface commands Register port8 RS232 Channel 8
(LCI) 3 Rx/Tx PC Com 1
8 bit Local PC
Ubat Fault D13 D78 X4
Out5...7
Output RS485/
TTL TX1 on
Register 422
X7 3
TX1 off TTL Channel 5
to CSL TX2 on 8 bit SCC
16552 ILS MK20A
X2 TX2 off
AUX 1
Out4 D41
P RS232
port5 Rx/Tx configuration
jumpers
Control
33/100* MHz S
port10 RS232 Channel 10
Process. clock
Rx/Tx Mon 2
PC104 board D64
Address bus
DIMM−PC/386−I or
DIMM−PC/520−I
Data bus Optocoupler
Input via CSL
Register X6 Interface
7 Parallel
Reset 8 bit 4 Addin 1..4
4
S2 Ubat Fault D33 D36...39
SCC clock
PAL Battery microprocess.
Decoder SL−389 Supervisory to D13
D86 3,6 V D83 D74
X35 1.8432 MHz Optocoupler
battery on Output via CSL
X36 Interface
IRQ watch dog on
Input Register X6
BCPS1
3...6 TTL Register to PMM/
BCPS2 7
10 6 BCPS
BCPS3
14...15 HD−LED Life LED
from CSL 8 bit 6 6 Parallel
BCPS4 8 bit
X2 TX1 on D3..6, 16,17 Addout 1..6
D62 D17
TX2 on
from
power supply X5 DCC−3−05/3
S1/1...8* +5 V/+15 V/−15 V
* with DIMM−PC/520−I * for optional use and CSL
Fig. 2−31 Local Control CPU (LC−CPU), block diagram
Ed. 07.04 48SB 2−41

DVOR 432
Auxiliary optocoupler isolated inputs via register 1,2 (IN) and optocoupler isolated outputs via register
1,2 (OUT) may be used for additional features of the user. The parallel, isolated inputs and outputs
can be reserved for various analog signals to supply additional information (e.g. burglary alarm, fire
etc.). The auxiliary inputs (IAUX8..15) can be set to high or low level logic with jumper X81..84. The
auxiliary outputs and inputs are available on top of the cabinet via Sub−D connectors.
The battery backup function on the LC−CPU board is connected to the CPU board for real−time
clock supply. The battery is a 0.8 Ah non rechargeable Lithium cell with a voltage rating of 3.6 V. For
battery backup to work, jumper X36 must be closed. The battery function is enabled if jumper X36
is closed. The battery voltage is compared against a fixed reference voltage. If the voltage drops to
<2.9 V a BIT signal is generated by the supervisory circuit D83.
The LC−CPU has its own RESET signal controlled by the switch S2 at the supervisory circuit D83.
This signal is ORed with the reset on the CPU board. The watch−dog on the LC−CPU board is active
if jumper X35 is closed and if enabled by software.
Additional connectors are provided on the LC−CPU board but not used. They are designed for optio-
nal connections of a keyboard (X10), printer (X53), an ethernet line (X100) or DME/NDB (X50 to 52).
2.3.5.1.2 DIMM−CPU board (PC/386−I or PC/520−I)

See Fig. 2−32.
The DIMM−CPU board is a PC104 compatible PC and consists of the following main components:
− Processor 80386SX or 586DX* − EEPROM (setup data)
− Standard AMI BIOS − 4 MB or 32 MB* DRAM
− address, data, control bus − Flash hard disk (8 MB or 32 MB*)
− Real−time clock − supervisory circuit
The CPU board has its own RESET signal. This signal is ORed with the push button reset line coming
from switch S2 on the LC−CPU board. The watchdog of the CPU board is not activate and used.
The CPU board is located piggy back on the LC−CPU board. It connects to a DIMM−socket.
I/O
33/100* MHz controller
Process. clock
Address
Processor 80386SX or 586DX* to/from

Data LC−CPU board
Control
uP EEPROM DRAM Flash disk

Super− BIOS Real time
visory EEPROM clock Set Up data 4 MB 8 MB
(32 MB)* (32 MB)*
Battery supply
32.768 kHz
Watch Dog/Reset
HD−LED
* with DIMM−PC/520−I
Fig. 2−32 DIMM−CPU board, block diagram
2−42 48SB Ed. 07.04

DVOR 432
2.3.5.1.3 Local Control Interface
See Fig. 2−33, 2−34.
The Local Control Interface (LCI) forms the local interface to the operator. It contains indication fields
for showing the local main status as well as a liquid crystal display (LCD) screen section, which is used
for control and indication functions useful for the operator to perform the most important control func-
tions locally and to recall measurement data of the transmiter and monitor. Additionally a key locked
switch function is established to change from local to remote control or to maintenance local opera-
tion. The graphics LCD screen can display up to 16 lines with up to 40 characters. The LCI is flush
mounted to the front door.
LCI LC−CPU
Audible
Alarm device B1 device
driver
X9
control lines
in/out
H1 to 3 Indicators Indicator
driver
Data
display data
Liquid Crystal Display Screen (TFT) brightness
R1
DC supply
key button S1 to 4
Key control
X4
key lock Interface
Fig. 2−33 Local Control Interface (LCI), block diagram
status Indicators TFT display
ALARM
Monitor−1 NORMAL EXECUTIVE
Monitor−2 NORMAL EXECUTIVE
WARNING
AERIAL TX−1 ON
DUMMY TX−2 OFF
NORMAL
MAINTENANCE
OPER. MODE REMOTE
MENU TXMTR MON DATA
REMOTE
LOCAL
MAINTENANCE
key lock key buttons (menu select)
Fig. 2−34 Control Interface (LCI), visible front view (text example: system status screen)
Ed. 07.04 48SB 2−43

DVOR 432
2−44 48SB Ed. 07.04

DVOR 432
2.3.5.2 Modem
2.3.5.2.1 Dedicated Line Modem LGM1200MD
See Fig. 2−35.
The LGM 1200MD is a universally applicable half duplex permanent line modem. The data transfer
rate is 1200 or 600 bit/s. The LGM 1200MD (MD=multidrop) is optimised for operation on permanent
two−wire lines in the so called party line mode. In this case, several modems are served by a control
station via one line only (polling mode). On replacement, the LGM1200MD is used instead of the
ZUA29. It occupies one LGM slot.
The LGM 1200MD operates in the voice band with FSK modulation, i.e. frequency shift keying in con-
formity with V.23 at 1300 and 2100 Hz with up to 1200 bit/s and 1300 and 1700 Hz with up to 600
bit/s. The data transfer method is half duplex or simplex. Generation of interfering trailing bits (on
deactivation of the remote transmitter) is largely excluded by process−controlled ”fast clamping” of
the received data. In the asynchronous mode, data transfer from 0 to 1200 bit/s or 0 to 600 bit/s is
possible, independently of the code and speed. A microcomputer controls and monitors all functions
of the LGM. Parameters for the processor and processor−independent circuitry can be influenced
by means of 14 adjacent coding switches. A power−on self−test is run. LEDs indicate transmit and
receive data activity or line seizure. The connected trunk lines are accessible via an ISEP test socket
on the front panel. (for monitoring the analog line signal). When the ”TEST” key on the front panel
is pressed, the modem is switched to the ”close range analog loop” (without transmitter) while the key
is pressed. This is also active during the transmission phase (the connection is then aborted).
In half duplex mode on two−wire connections, the participating data transmission equipment each
seizes the telephone line in succession. The respective DTE responsible for transmission controls
operation with the 105/S2/RTS (ready to send) signal. This activates the modem’s carrier. The DTE
must only offer data to the modem via the 103/D1/TD line once a specific delay after ready to send
has elapsed and the modem has switched the 106/M2/CTS (clear to send). During the delay time
between the ”ready to send” 105/S2/RTS and ”clear to send” 106/M2/CTS signals, the signal detector
of the receiving modem will already react and will adapt the clock signals of the receiver to the clock
pulse of the incoming signals.
transmit path
Over−
voltage
protection Level
a2 adaptation TxA
La
Lb FSK signal
b2
E converter
Level
connection
Filter RxA
adaptation
2−wire line
receive path
TD
Microprocessor
RD
DIL switch TTL/V.24 interface
Set 1...14 Data in/out
Fig. 2−35 LGM1200MD, block diagram
Ed. 07.04 48SB 2−45

DVOR 432
With the 109/M5/DCD (receive signal level) signal, the receiving modem indicates that it is capable
of forwarding received data (104/D2/RD). If the 109/M5/DCD (receive signal level) signal is not in the
ON state, the receive interface line (104/D2/RD) is in the ”I” state. A so−called fast clamping circuit
is integrated in the LGM1200MD to avoid trailing bits during reception. It is processor−controlled, with
the result that no more than 1 byte can occur as a trailing byte.
NOTE: When using the LGM1200MD the permanent line must be equipped with a termination
(600 Ohm/47 nF parallel) at the point where it ends (station and remote ends). The R/C
combination can be soldered onto the 9pin SubD connector together with the two−wire
line.
The location of the LGM1200D is shown in Fig. 2−6.
2.3.5.2.2 Switched Line Modem LGM 28.8D1

See Fig. 2−36.
The LGM 28.8 are high speed modems for duplex operation which support all common duplex modu-
lation procedures. The modems are designed for synchronous as well as asynchronous data trans-
mission according to the following CCITT modulation modes: V.34, V.32bis, V.32, V.22bis, V.22, and
V.21, which have implemented the data securing procedures according to V.42 and MNP4. Data com-
pressing to increase the baud rate is implemented according to V.42bis and MNP5. These procedures
enable a practical fault free transmission between two data terminal equipment (DTE) units. Depend-
ing on the procedure the transmission rate can be increased up to 38400 Bd (autobaud) using V.42bis
and the AT −mode/reliable mode. The modems can also communicate with modems from other ven-
dors at the same transmission rates, providing these modems comply with CCITT Recommendations
V.22 and V.22bis.
Software configuration is possible using AT or DNL commands while hardware configuration is per-
formed employing the DIP switches located at the bottom and on one side of the module. It is de-
signed for operation in public switched networks and consequently equipped with an integrated auto-
matic dialing facility (IAWD). Data connections can however also be set up by the subscriber dialing
manually and pressing the data key. Point−to−point operation on dedicated lines (leased or tie lines)
is likewise possible. Almost all the modem functions can be set by the data terminal equipment (DTE)
using a command set in accordance with CCITT Recommendation V.25bis. Correct operation of the
microprocessor and the signal processors is monitored by an integrated circuit, which initiates a
"master reset" if one of these processors malfunctions (watchdog).
A data connection can be set up by means of either the integrated automatic dialing facility or the
automatic call acceptance feature. It is also possible to dial out or to accept incoming calls manually.
No dialing takes place on dedicated lines. All the V.25bis commands and messages are exchanged
via the interfaces which are also used to transfer the actual data. After a call request with identification,
the LGM checks whether the subscriber line is already busy, i.e. whether the subscriber is in the pro-
cess of making a call.
If not, the outside line is seized. The LGM then transmits the dialed digits which have previously been
transmitted by the DTE. After the dialing procedure, an intermittent 1300 Hz tone is transmitted and
the modem waits for a constant 2100 Hz answer tone. As soon as this answer tone − which is trans-
mitted by modems with an automatic call acceptance facility − is identified, the two modems start
the prolog (handshake).
A data connection can only be terminated by the DTE, unless there is no carrier for more than 250
ms/10 s. In this case, the line seizure is canceled by the LGM. Eighteen switches are provided on the
2−46 48SB Ed. 07.04

DVOR 432
pc board for presetting the seven different operating modes, the four communication protocols and
various other parameters. A self−test is performed each time the modem is switched on. The default
setup is as follows: 2400 bd, V.22bis, autodial.
If autodial is set, the connection is set up automatically by the modem. The telephone number is noti-
fied to the modem by means of a request (command). This call request with identification can be pre-
ceded by a command for setting the transmission parameters. The command and the desired data
(transmission parameters and telephone number) can be transmitted automatically using the com-
munication software, i.e. the user does not need to concern him or herself with this.
The location of the LGM 28.8 is shown in Fig. 2−6.
La Busy detection
a2
Lb
Modem controller
b2
Data key detection

Ringing tone
detection
G
E
Setting
Fig. 2−36 LGM 28.8, block diagram
Ed. 07.04 48SB 2−47

DVOR 432
2.3.5.3 Voice Amplifier (VAM)

See Fig. 2−37.
The voice amplifier is supplied optional on request. It can be used in 100 W versions only. The task
of this subassembly is to process the voice signals received from the tower via a separate two−wire
telecommunications line to enable them to be supplied to the carrier modulator of the transmitter via
the modulation signal generator (MSG−S).
One part of the input stage of the VAM is located on the motherboard of the transmitter rack. It includes
two surge arresters, a transformer for potential isolation of the VAM from the telecommunication line
and − in the secondary circuit − a voltage−dependent zinc oxide protective resistor (VDR). On the
printed circuit board itself are further protective diodes (CR1..4) to prevent the AGC amplifier (IC3)
against remaining over−voltage conditions. IC3 contains two amplifiers and an AGC detector. The
gain is internally controlled as a function of the amplitude of the output via the AGC detector. IC3 is
supplied by the precise voltage regulator IC1.
The output signal of the AGC amplifier is amplified by 24 dB in IC5/1. It then drives the compressor
IC7 and the threshold switch control via IC5/2. The compressor reduces short−term amplitude fluc-
tuations in the AF signal. The signal then passes via an attenuating amplifier (IC8) to a 300 Hz high−
pass filter (IC9, 10) and a 3000 Hz low−pass filter (IC12, 13) for protection of the navigation signals.
The notch filter (IC11) eliminates from the voice signal the frequency components which are either
at the code frequency (1020 Hz) or very close to it. The threshold switch (Q1, Q2, IC4) prevents modu-
lation of the transmitter by the VAM if the voice signal is too weak, or if there is no voice signal at all.
The switch control signal is generated in the comparator IC4/1. The comparator is supplied first with
the rectified output signal of IC5/2 via IC6 and second with a threshold value derived from the voltage
regulator IC1 via decoupling circuit IC2/1. If the conditioned audio signal is below the set threshold
FET Q2 becomes conductive driven by transistor Q1 and the output of the VAM will be disabled. The
modulation factor of the transmitter can be set by means of a soldered resistor (R33) in the feedback
branch of the output amplifier (IC2/2).
The location of the VAM is shown in Fig. 2−6.
R33
300 Hz 3000 Hz 1020 Hz Voice

Overvoltage AGC− Compressor Threshold
Voice protection amplifier attenuator switch
CR1...4 IC3 IC5/1 IC7,8 IC9,10 IC12,13 IC11 Q1,2,IC4/2 IC2/1
Comparator
Input circuit
line transformer IC5/2 IC6 IC4/1
T1
LV1
Reference
voltage
LV2 IC1 IC2
BP−CE
Fig. 2−37 Voice Amplifier (VAM), block diagram
2−48 48SB Ed. 07.04

DVOR 432
Equipment Description Power Supply Subassemblies
2.3.6 Power Supply
The power supply of the Navaids installation is taken from mains (nom. 115 to 230 VAC) or from an
existing DC power supply (nom. 48 V). The equipment contains therefore a mains module with battery
charger (BCPS). The BCPS is modular in a building−block concept with several AC/DC converters
ACC−54 connected in parallel, and several DC/DC converters to generate the necessary voltages.
The location of the AC/DC and DC/DC converters is shown in Fig. 2−6.
2.3.6.1 Overview DC/DC Converter

A total of 5 DC converters (used for DVOR 50 W), or 7 DC converters (used for DVOR 100 W) are re-
quired for the DC voltage supply in a dual equipment version; these are subdivided into four groups:
Group 1 supplies transmitter 1 and comprises the following units:
− DC converter +28 V/11 A nom., +15 V/2,5 A, −15 V/1 A, +5 V/3 A (DCC−MV)
− DC converter +28 V/14 A (DCC−28), used in a 100 W version only
Group 2 supplies transmitter 2 and comprises the following units:
− DC converter +28 V/11 A nom., +15 V/2,5 A, −15 V/1 A, +5 V/3 A (DCC−MV)
− DC converter +28 V/14 A (DCC−28), used in a 100 W version only
Group 1 is supplied with the supply voltage of +54 V by over−current circuit breaker TX1 (subassem-
bly PMM), and group 2 is supplied via TX2 (subassembly PMM). Group 1 (group 2) is switched on
and off via an on/off pulse from the LCP via the CSL. The output command for disconnection in case
of a fault is issued by the MSP. Normal ON/OFF commands are entered manually via the local control
interface (LCI), the local PC or the Remote Control. In single DVOR versions group 2 is not available.
Group 3 and 4 DC−converter modules are located on one printed circuit board DCC−3−05. Group
3 supplies the monitors and comprises the following units:
− DC converter +5.1 V/1.2 A (DCC−3−05/module 1), Monitor 1

− DC converter +5.1 V/1.2 A (DCC−3−05/module 2), Monitor 2
The two DC converters are linked on the input side by an OR circuit; they obtain their supply voltage
of 54 VDC via over−current circuit breakers TX1 and/or TX2. In single versions of the DVOR the
DCC−3−05/module 2 is not used.
Group 4 supplies the units belonging to the LRCI and the CSL and comprises the following unit:
− DC converter +5.1 V/5 A (DCC−3−05/module 3), LRCI, CSL
The DC−supply of the ASU−subassemblies is described in section 2.4.
NOTE: The supply voltage of the DC converter described here is a rated 54 V for mains operation
or 48 V for battery operation. In mains operation the operating voltage may rise to 65 V;
in battery operation it may fall to 43 V (monitoring limits). The permitted input voltage
range of the DC converter is therefore between 43 and 65 V. The term "variable input volt-
age" has therefore been used in a number of cases in the description which follows. The
various voltage specifications should therefore be interpreted within this context.
Ed. 07.04 48SB 2−49

DVOR 432
Power Supply Subassemblies Equipment Description
2.3.6.2 DC Converter Modules 5 V (DCC−3−05)

See Fig. 2−38.
The DCC−3−05 subassembly is a DC converter which generates a stabilized output voltage from
a nominal input voltage of 54VDC (operating range 40...65V). The DCC−3−05 consists of three indi-
vidual DC/DC converter modules 1 to 3 which supply 5.1 V/1.2 A each for the monitor subassemblies
and 5.1 V/5 A for the LRCI subassemblies. The converter modules are subdivided into a primary and
a secondary section. The two sections are electrically isolated from each other in the power stage
by a transformer. The DC supply voltage is converted into an AC voltage in a feedback controlled fly-
back converter using current mode pulse width modulation. The 5 A module 3 (5 A) uses a forward
converter with a clock frequency of 30 kHz. The output is directly monitored and feedback to the pri-
mary control circuit via a pulse transformer, resulting in tight regulation of the output voltage. Current
limitation is provided by the primary circuit. For the monitor supply modules the on/off signal for both
DC/DC modules for the monitors is coupled via optocouplers to the inhibit input. The DCC−3−05
are activated and deactivated by manually actuating the switches on the subassembly PMM or by
means of the Tx On and Tx Off commands via software.
1 GND
Module 3
3,4,5 5VK+/5 A
Vo+
Vi+
Input Forward
Filter Converter
Vi−
Vo−
7,8 GND
Control
Module 1
10,11 5VM1+/1.2 A
1 11
Pulse Width
Modulator
3
10
13,14 GND
12
2
13
4 14
15 PSMON1
On/Off
16 GNDCPS
Module 2
17,18 5VM2+/1.2 A
1 11
Pulse Width
Modulator
3
10
20,21 GND
12
2
13
4 14
22 PSMON2
On/Off
23 GNDCPS
26 48 v
31 48 V GND
32 GND
Fig. 2−38 DC converter DCC−3−05, block diagram
2−50 48SB Ed. 07.04

DVOR 432
2.3.6.3 DC Converter MV (DCC−MV)
See Fig. 2−39.
The DCC−MV subassembly is a DC converter, which generates four stabilized output voltages from
a nominal input voltage of 54 V DC (operating range 40...65 V). The DCC−MV supplies the voltages
below at the output:
+28 V, nominal 11 A, max. 14 A
+15 V, 2.5A
−15 V, 1 A
+5.2 V, 3 A.
These voltages are referenced to a common neutral. The DCC−MV comprises a primary and second-
ary section. The two sections of the device are electrically isolated from each other both in the power
section and in the control and monitoring circuit by means of transformers and optocouplers. In addi-
tion the primary on/off signal is coupled also via optocoupler. A LED located on the front signals the
presence of the output voltage. The main functional units of the DCC−MV are:
V Power section
− Primary safety and softstart circuit
− Input filter
− Power conversion stage 28 V
− Power conversion stage 5 V and ±15 V
− Rectifier and output filter
− Voltage regulators for ±15V
V Control and monitoring section
− Primary controller including
auxiliary voltage generator,
control input On/off,
oscillator, pulse width modulator, controller,
driver stage
− Secondary controller and monitor including
voltage and current monitor 28 V and 5 V,
over/under−voltage and temperature monitor,
BIT/Alarm signalling
The DC supply voltage is converted into an AC voltage in a forward converter (FWC) for 28 V and a
flyback−converter (FBC) for 5 V and ±15 V. Both converter work with a clock frequency of approxi-
mately 100 kHz. A transformers each, which also ensures electrical isolation of the secondary section,
transforms the input voltage to the required output voltage. The dc converter is primary protected
against overcurrent or short circuit by means of fuse NSI1 (30 A).
If the input voltage is connected incorrectly, diode D1 will be enabled and the fuse is blown to prevent
any damage. R1 prevents against overvoltage peaks up to 130 VAC. The power section is initially iso-
lated from the input by means of the FET transistors T1,T2, which are controlled by IC1 and act as
primary on/off switch. The ON or OFF command which enables the main and auxiliary voltage is sup-
plied via optocoupler IC2.
The incoming voltage is smoothed and noise is suppressed by L/C elements in the input filter. The
voltage is reduced in the power conversion stage by means of electronically controlled chopping. IC5
as primary control circuit generates the chopping frequency of 100 kHz and controls both the driver
stage T11...12,TR6 for the 28 V power section with OUT1 (FWC) and directly the 5 V/±15 V power
section with OUT2 (FBC).
Ed. 07.04 48SB 2−51

DVOR 432
Primary safety circuit Filter Primary power section Secondary power section
Uin+
IC1
U T1,2
48 Vdc TR1
D1 R1
D2 Rectifier Filter
T3
Uin− NSI1/30 A
6.3x32mm +
28 V/11 A
TR2
28 V current
−
T4
U0
D3
FWC current Rectifier Filter
+
5 V/3 A
5 V current
−
U0
TR4 Rectifier voltage
regulator
+15 V
IC101 +
+15 V/2.5 A
TR3
−
T5
U0
Rectifier voltage
FBC current regulator
−15 V U0
IC102 +
−15 V/1 A
−
test connector heat sink

primary
Primary controller θ
disable 5V TR6
R173
disable 28V IC5

current FBC T14
enable current FWC
5 & 28 V sync 2 T10
Controller 28V T12
ST1 Controller 5V OUT1

overvoltage T11
OUT2
OK LED
Front panel
IC9 temperature
TR5
Uaux. overvoltage
sync2 BIT
Uaux. second. undervoltage signal
IC3 switch
enable T102
5 & 28 V
Remote RT/CT OUT IC7
On/Off current monitor
IC2 T8 Uaux. primary test connector
ref. volt. 28 V, 5 V secondary
Uref
disable
IC6 keep alive
IC8 voltage monitor
reference 28 V, 5 V
voltages
Auxiliary voltage generator Secondary controller and monitor ST2
FWC = Forward Converter

FBC = Flyback Converter
Fig. 2−39 DC converter DCC−MV, block diagram
2−52 48SB Ed. 07.04

DVOR 432
The 28 V driver stage in turn controls the 28 V power section (FWC) consisting of FET transistors T3,4,
building a bridge with D2,3. The bridge circuit chops the DC voltage. The chopped DC voltage is trans-
formed by TR2 to the desired value, then rectified and smoothed via an output filter.
The 5 V/±15 V power section (FBC) consists of FET transistor T5 and transformator TR3. T5 chops
the DC voltage. The chopped DC voltage is transformed by TR3 to three desired values with three
secondary windings. For the 5 V path the output voltage is rectified and smoothed via an output filter.
The secondary output current is monitored via the voltage drop on a series resistor. For the ±15 V
path the output voltages are rectified, smoothed and regulated to +15 V or −15 V with integrated volt-
age regulators IC101, 102. The regulated voltages are led via an smoothing output filter to the output.
The input voltage for the auxiliary voltage generator is extracted after the smoothing stage. The auxil-
iary voltage for primary and secondary controller and monitoring circuits is generated by an individual
converter built by IC3, T8 and TR5. It works with a clock frequency of approx. 100 kHz.
The output voltage is regulated directly via the turn−on time of the power stage in order to obtain
stabilized voltages of 28 V and 5 V. This regulation is implemented via the primary controller (IC5),
which obtains its information from the various current and voltage sensor circuits. The regulation
takes the form of changes in the pulse width, suppression of single clock pulses and deactivation.
The operational reliability of the converter is ensured by a number of monitoring circuits. The power
stages are protected against overvoltage, undervoltage and overcurrent conditions. It is interlocked
in the event of an automatic deactivation resulting from an overvoltage condition. This interlock can
be cancelled by interrupting the power supply or by entering the Tx OFF and Tx ON commands at
the keyboard of the rack or software command (PC).
A primary or secondary overcurrent condition will lead to pulse width control, which causes the output
voltage to be reduced. The current transformers TR1,TR4 monitor the primary power sections for
overcurrent conditions, whilst the secondary output current is monitored via the voltage drop on a
series resistor for the 28 V and 5 V path. As BIT signal a switch function, which indicates operation
of the DC converter, is implemented. In the event of a malfunction FET transistor T102 becomes con-
ductive and the front LED does not light.
Ed. 07.04 48SB 2−53

DVOR 432
2.3.6.4 DC Converter 28 V (DCC−28)

See Fig. 2−40.
The DCC 28 subassembly is a DC converter, which generates a stabilized output voltage of 28 V from
a nominal input voltage of 54 V DC (operating range 40...65 V). The nominal value of the output cur-
rent is 14 A. The DCC−28 comprises a primary and secondary section. The two sections of the device
are electrically isolated from each other both in the power section and in the control and monitoring
circuit by means of transformers and optocouplers. In addition the primary on/off signal is coupled
also via optocoupler. A LED located on the front signals the presence of the output voltage.The main
functional units of the DCC−28 are:
V Power section
− Primary safety and softstart circuit
− Input filter
− Power conversion stage
− Rectifier and output filter
V Control and monitoring section
− Primary controller including
auxiliary voltage generator,
control input On/off,
oscillator, pulse width modulator, controller,
driver stage
− Secondary 28 V controller and monitor including
voltage and current monitor,
over/under−voltage and temperature monitor,
BIT/Alarm signalling
The DC supply voltage is converted into an AC voltage in a forward converter with a clock frequency
of approximately 100 kHz. A transformer, which also ensures electrical isolation of the secondary sec-
tion, transforms this voltage to the required output voltage. The dc converter is primary protected
against overcurrent or short circuit by means of fuse NSI1 (30 A). If the input voltage is connected
incorrectly, diode D1 will be enabled and the fuse is blown to prevent any damage. R1 prevents
against overvoltage peaks up to 130 VAC. The power section is initially isolated from the input by
means of the FET transistors T1,T2, which are controlled by IC1 and act as primary on/off switch. The
ON or OFF command which enables the main and auxiliary voltage is supplied via optocoupler IC2.
The incoming voltage is smoothed and noise is suppressed by L/C elements in the input filter. The
voltage is reduced in the power conversion stage by means of electronically controlled chopping. IC5
as primary control circuit generates the chopping frequency of 100 kHz and controls the driver stage,
which in turn controls the power section consisting of FET transistors T3,4, building a bridge with
D2,3. The bridge circuit chops the DC voltage. The chopped DC voltage is transformed by TR2 to the
desired value, then rectified and smoothed via an output filter.
The output voltage is regulated directly via the turn−on time of the power stage in order to obtain a
stabilized voltage of 28 V. This regulation is implemented via the primary controller (IC5), which ob-
tains its information from the various current and voltage sensor circuits. The regulation takes the form
of changes in the pulse width, suppression of single clock pulses and deactivation. The operational
reliability of the converter is ensured by a number of monitoring circuits. The power stage is protected
against overvoltage, undervoltage and overcurrent conditions. It is interlocked in the event of an auto-
matic deactivation resulting from an overvoltage condition. This interlock can be cancelled by inter-
rupting the power supply or by entering the Tx OFF and Tx ON commands at the keyboard of the
rack or software command (PC).
2−54 48SB Ed. 07.04

DVOR 432
The input voltage for the auxiliary voltage generator is extracted after the smoothing stage. The auxil-
iary voltage for primary and secondary controller and monitoring circuits is generated by an individual
converter built by IC3, T8 and TR5. It works with a clock frequency of approx. 100 kHz.
A primary or secondary overcurrent condition will lead to pulse width control, which causes the output
voltage to be reduced. The current transformer TR1 monitors the primary power section for overcur-
rent conditions, whilst the the secondary output current is monitored via the voltage drop on a series
resistor. As BIT signal a switch function, which indicates operation of the DC converter, is imple-
mented. In the event of a malfunction FET transistor T102 becomes conductive and the front LED
does not light.
Primary safety circuit Filter Primary power section Secondary power section
Uin+
IC1
T1,2
48 Vdc U
D1 R1
D2 Rectifier Filter
T3
Uin− NSI1/30 A
6.3x32mm +
T102
TR2 28 V/14 A
28 V current
−
T4
D3
FWC current
test connector
primary heat sink
Primary controller
TR6 θ
disable 5V
R173
disable 28V IC5

T14
Fw. current
enable
5 & 28 V sync 2 T10
Controller 28V T12
overvoltage
ST1 OUT1
T11
OK LED
Front panel
IC9
TR5
Uaux.
temperature
overvoltage
sync2 Uaux. second. undervoltage BIT
IC3 switch signal
enable T102
5 & 28 V
Remote RT/CT OUT
On/Off current monitor
IC2 T8 Uaux. primary test connector
ref. volt. 28 V secondary
Uref
disable
IC6 keep alive
IC8 voltage monitor
reference 28 V
voltages
Auxiliary voltage generator Secondary controller and monitor ST2
FWC = Forward Converter
Fig. 2−40 DC converter DCC−28, block diagram
Ed. 07.04 48SB 2−55

DVOR 432
2.3.6.5 Power Management

The power management module consists of current/capacity measurement by the LCP with a user
defined shut down value of the main load (transmitter) and allows continued operation of the LCP and
modem down to a cutoff threshold for over−discharge protection by the CSL if the mains is not re-
stored before the threshold voltage is reached. The PMM comprises an additional solid state relay
to enable the shut down of the system just before the cutoff threshold to minimize the power con-
sumption. If the mains is now restored before the cutoff threshold is reached the solid state relay is
switched on, the LCP and the modem becomes operational and the system can be maintained re-
motely. The automatic restore option is used in CVOR/DVOR installations.
2.3.6.6 Power Management Module (PMM)

See Fig. 2−41.
The PMM comprises:
− Connection terminals for the supply voltage,
− 3 Over−current circuit breakers and over−discharge relays
− 1 solid state relay
− Voltage distribution
The connection terminals take the form of solid studs to which the lines of the supply voltage (54 VDC)
from the BCPS/floating battery are connected. The 0 V connection is at the same time system and
protective ground (BSE), and thus the central grounding point. The supply voltage is manually con-
nected first to the NAV equipment via over−current circuit breaker S3 (NAV) with a response at >30
A and following to the DC converters of the cabinet by means of over−current circuit breakers S1
(TX1) and S2 (TX2). S1 connects the supply voltage to the DC converter of transmitter 1, and S2 to
the DC converter of transmitter 2. S1 and S2 have an over−current protection function in addition to
their manual switching function. They respond at >16 A for either switch. Following S1, S2 for the
station the voltage is distributed by an OR circuit via a solid state relay K1 to the DC converter of the
monitors, LRCI and CSL. The OR operation means that these units are operational even if only one
of circuit breakers S1 and S2 is closed. The actual voltage value for the over−discharge protection
functional group on the CSL is derived directly behind the NAV switch. The power lines to the CSL
and to K1 are protected each with a fuse: F1 (1.0 A), F2 (6.3 A).
The location of the PMM is shown in Fig. 2−6.
to DME 415/435
S1
to DC converter TX1
to ASU (DVOR only), BSG−D
S3
K1 to DC converter MON1
54 VDC + H1
to DC converter MON2
to DC converter LRCI/CSL
F2
6.3 A
S2
to DC converter TX2
H3
Control Addout1 (off)
from LCP
Control PF54 (On)
H2 from CSL
to CSL (48 V)
F1
1.0 A Control
Over−discharge protection
from CSL (V36)
− 0V
Fig. 2−41 Power Management Module (PMM), block diagram
2−56 48SB Ed. 07.04

DVOR 432
2.3.6.7 Power Management of Navaids Installations
See Fig. 2−42.
The PMM enables an automatic restore feature for CVOR/DVOR installations. A power down cycle
in case of mains failure is initiated as follows:
After mains failure, first the remaining battery capacity is calculated from the LCP processor by mea-
suring the current drawn by the load. The result is compared with software−set user−defined battery
capacity limits (Ah). If these limits are reached the transmitter supplies CVOR/DVOR and the ASU sup-
ply (DVOR) are switched off first by a digital command of the LCP processor. The batteries are relieved
as a result. Next the ACC modules of the BCPS are shutdown via optocoupler input with the LCP mes-
sage line Addout2. Jumper X26 on the CSL can interrupt the line to the BCPS.
To prevent cut off by the over−discharge protection circuit on the CSL (V36) the battery voltage is
compared with a jumper−set user−defined value. If this value is reached the LCP processor switches
off the LRCI and Monitor supply via solid state relay K1 with command Addout1 just before the over−
discharge protection is enabled. The hold−in circuit and the over−discharge protection circuit on the
CSL remain operational. If mains is restored before the batteries are cut off by the CSL the hold−in
circuit on the CSL (V35) switches on the solid state relay K1. The LRCI, that is LCP and modem, be-
come operational and the CVOR/DVOR can be maintained via remote control.
battery battery fuse to DME

room switch
S1 BCPSS1
TX1
BCPSS2
MON BCPSS3
S3 LRCI
K1 CSL BCPSS4
H1 F2 BFUSE+ (Addin1)
S2
BFUSE−
TX2 BCPS 0ff (Addout2)
H3
Addout1
Addout3
54 VDC
H2 Addout4 Data
to CSL (48 V)
+ 2 mohms 2 mohms F1 LCP
0V
X26
Hold−in circuit
PF54
V35
−
BCPS back panel
over discharge
protection
H1,2,3
V36
ILOAD+
0V ILOAD−
IBAT−
PMM IBAT+
UBAT2+
UBAT1+
UBAT−
CSL
Navaids cabinet
Fig. 2−42 Power management Navaids with PMM, overview
Ed. 07.04 48SB 2−57

DVOR 432
2.3.6.8 AC/DC Converter (ACC−54)

See Fig. 2−43.
The mains unit ACC−54 acts as a AC/DC converter, which generates a stabilized 54 VDC voltage ob-
tained from the mains voltage (wide range input: 115 VAC to 230 VAC, ±15 %). It takes the form of
a push pull switched−mode converter with electrical isolation of the input and output. Up to four
mains units connected in parallel buffer a 48V battery (24 lead cells), which can supply the connected
navigation system with voltage for several hours in case of a mains power failure.
The output voltage is 54 V. This ensures that the battery charge is permanently maintained (2.25 V
per cell, standby parallel operation). The supply to the navigation system from the mains and the bat-
tery trickle charge is still ensured in case of a power subrack failure. A power switch, a fuse, an LED
and two test jacks for the voltage ahead of the isolating diode are located on the front panel. The LED
signals the presence of the equipment output voltage, but not of the battery voltage. The AC/DC con-
verter consists mainly of the following functional groups:
− Input section (primary) with noise suppression filter for AC

− Power section (primary/secondary)
− Flux converter controller (primary/secondary)
− DC/DC controller (primary/secondary)
− Output section (secondary)
In the input section the input voltage of 230 VAC passes a fuse, an overvoltage protector and an RF
filter to prevent RF interference voltages, is rectified with a bridge−connected rectifier and smoothed
by an electrolytic capacitor. The subassembly also contains a resistor which limits the current inrush.
This resistor is short−circuited by a relay contact (K1A) following current stabilization.
The DC voltage generated in the mains board is chopped in the power pc board with the aid of a push
pull power circuit with a frequency of 20 kHz. The square wave voltage generated in this way is
stepped down in a transformer and rectified. The input and output of the devices are electrically iso-
lated with the aid of this transformer. The DC voltage generated in this way is then smoothed with the
aid of a number of chokes and filter capacitors. The voltage is fed via an RF output filter to prevent
RF interference voltages and a further fuse to the output terminals.
The output voltage is regulated by modifying the pulse width for driving the switching transistor. The
20 kHz control pulses for the transistor chopper are generated in the flux converter controller. The
output current is measured by means of the series resistor in the output line. The voltage drop at this
resistor, which is a measure of the current flow, passes to the monitor DC/DC converter, where it
serves as the actual value for current limiting. The clock generator (oscillator frequency 400 kHz) sup-
plies after division of the frequency the generation of the auxiliary voltage and the controller DC/DC
converter.
An appropriate circuit enables the pulse width to be modified so that the output voltage can remain
roughly constant until the maximum output current of 12 A is reached. When this current is reached,
the pulse width is reduced accordingly. The resulting output characteristic is thus almost rectangular.
The input quantities received by the controller are the output voltage of 54 V and the voltage drop at
a series resistor. These quantities are used to control the pulse width by means of a nominal/actual
comparison. A further circuit interrupts generation of the control pulses in case of an over−voltage
62 V at the output of the power pc board. In such cases the output voltage is also interrupted.
2−58 48SB Ed. 07.04

DVOR 432
Any fault which occurs in the power supply triggers a BIT signal to the navigation system e.g.:
− failure of one of the subracks connected in parallel,
− under−voltage 45 V in one subrack,
− over−voltage 62 V,
− total failure of the power supply or mains.
The appropriate WARNING is displayed for as long as the system is supplied with power by the bat-
tery. The fault can be localized following manual input of a fault interrogation.
Power section OK LED

Front panel
test jack
push pull converter front panel
F/6.3A +Vout
F/5A
L K1A Filter +
Filter
230 VAC 54 VDC
N −
PE F/1A
−Vout
PE
voltage measurement UDC

driver TEMP
current measurement IDC
Temperature
PCFI
heat sink
Control
current measurement
control of setup relais
control driver/bridge
bridge current PDCI
section
voltage AC PFCAC
voltage AC ACVLO
voltage DC PFCV
PFCG
Flux converter DC/DC converter DC/DC converter DC/DC converter

controller controller controller monitor
Primary Primary Secondary Secondary
Primary monitoring setpoint control output voltage
pulse modulation output current
overvoltage
PFCENA driver Temperature
Synchronization
auxiliary voltage
Synchronization
R32
Flux converter
DC converter
PFCSync
Primäary
DCSYNC
Fine adjustment
output voltage
for optimization of
charging voltage
clock generator
divider
400 kHz
Secondary
auxiliary voltage
auxiliary voltage Remote
converter On/Off Status
5 V/10 mA closed contact BIT−Signal

potential free potential free
Optocoupler in BCPSx (x= 1..4)
Fig. 2−43 AC/DC converter (ACC−54), block diagram
Ed. 07.04 48SB 2−59

DVOR 432
2−60 48SB Ed. 07.04

DVOR 432
Equipment Description ASU Subassemblies
2.4 DESCRIPTION OF ASU SUBASSEMBLIES
2.4.1 General
All plug−in or screw−on subassemblies (printed circuit boards) in the transmitter rack which belong
to the antenna switching unit function are described in Section 2.4. Their task is described and illus-
trated with the aid of simplified block diagrams. The integration within the complete system is shown
in block diagram Fig. 1−30. More details about the subassemblies (printed circuit boards), which may
exceed the information given in the following description part and figures, may be taken from the cir-
cuit diagrams listed in Fig. 2−45. A functional overview is given in Fig. 2−44.
A49
Part of RF−Duplexer boards A02
ASU−C a
MOD−SBB
Carrier (CSB) CSB ASM
Z8
SIN hi SP12T
Circ.
USB (SB1) DPDT
USB switch A24
Z6
Circ. Z3 COS even A26
LSB (SB2)
LSB
Z5 ASM
Z4
lo SP12T
MOD−SBB A48
A01
SIN ASU−C b
DPDT
switch ASM
odd SP12T
COS hi
A23
A25
8+4 bit ASM

TX1 SP12T
Control Data 30HZE lo
CSL PMC−D BSG−D
(incl. ASU interface) 30 Hz Sync. (incl. switch control) 30HZO
TX2 A47
to/from ASU−INT 48V
DC−Converter +5 V
48V +5/+15/−15 V
ASU−CIF −15 V
Transmitter cabinet Antenna Switch Control Outdoor mounting PDSU
Fig. 2−44 ASU subassemblies, functional overview
2.4.2 Overview ASU−Subassemblies
SUBASSEMBLY DESIGNATION CODE NUMBER*) REFERENCE

Transmitter rack (indoor)
Phase Monitor and Control (PMC−D) 83135 31200 2.4.3
Modulator Sideband Blending (MOD−SBB) 83135 31100 2.4.4
Blending Signal Generator (BSG−D) 83135 31301 2.4.5
incl. DC−Converter
PDSU, outdoor mounting
PIN−Diode Switching Unit (PDSU) 83011 43900 2.4.6
− ASU−Commutator (ASU−C) 83135 31500 2.4.6.2
− ASU−Commutator Interface (ASU−CIF) 83135 31400 2.4.6.1
*) In individual cases, the item numbers given here may differ from those of the system which is supplied. In cases of this
kind, the valid item number is that given in the delivery list for the system or in the documentation set.
Fig. 2−45 Circuit diagrams of subassemblies of the Antenna Switching Unit (ASU) function
Ed. 07.04 48SB 2−61

DVOR 432
ASU Subassemblies Equipment Description
2.4.3 Phase Monitoring and Control (PMC−D)

See Fig. 2−46.
The PMC−D subassembly combines the following functional circuits:
− phase monitoring and control
− phase measurement
− SB antenna monitoring
− ASU−interface function
The location of the PMC−D in the transmitter cabinet is shown in Fig. 2−6.
2.4.3.1 Phase Monitoring and Control

With the phase monitoring and control function, it generates control signals for the RF relationship
between the carrier and the two sidebands as well as monitoring signals for RF phasing of the DVOR
installation in the farfield. In addition matching of the middle antenna (carrier signal) can be interro-
gated via the BIT routine and the functioning of the 48 sideband antennas monitored. The CSB, SB1
and SB2 signals are supplied to the PMC−D via the RF Duplexer RFD1−C and RFD2−SB. Signal
components are coupled out via couplers Z8 (CSB), Z3 (SB1) and Z4 (SB2) for phase control of the
sidebands in the modulators MOD−110P and for monitoring the antenna system and the RF phasing.
Circulators Z5 and Z6 prevent the return signals of SB1 and SB2 from reaching the transmitter.
The SB1 forward signal is coupled out via Z3, then split. One path is supplied to mixer U3. It is mixed
to the CSB signal of N3 for generation of a 9960 Hz signal for RF phase control (R1−10kHz). The other
path is supplied to mixer U2 and mixed with the return signal from Z3. This return signal incorporates
the carrier radiated by the center antenna and received by the sideband antennas. A 9960 Hz voltage
is supplied from the forward and return signals of SB1 for monitoring of the antenna and phasing.
The SB2 forward signal is coupled out via Z4, then split. One path is supplied to mixer U4. It is mixed
to the CSB signal of N3 for generation of a 9960 Hz signal for RF phase control (R2−10kHz). The other
path is supplied to mixer U1 and mixed with the return signal from Z4. This return signal incorporates
the carrier radiated by the center antenna and received by the sideband antennas. A 9960 Hz voltage
is supplied from the forward and return signals of SB2 for monitoring of the antenna and phasing.
The phase measuring circuit, built by D6, takes the form of a synchronous control unit, which mea-
sures the time difference between the two leading edges of the 9960 Hz measurement signals and
stores the result in a latch. This circuit operates independently of the processor and asynchronously
with regard to it. The MSG−C processor disables writing to the latch at the instants at which data is
transferred, in order to prevent the measured value being updated during this transfer. The latch is
the output register for the digital phase measured value supplied to the two MSG−C processors. The
processor of the passive transmitter (i.e. that which is not switched to the antenna) is interested only
in the measured values for the monitor phase. The processor of the active transmitter determines
when the multiplexer through−connects the signals for measuring the sideband phase and when it
through−connects the signals for measuring the monitor phase to the phase measuring circuit. If the
signals for measuring the monitor phase are supplied to the measuring circuit, the processor of the
passive transmitter will be informed to ensure that it only accepts monitor phase measured values.
These roles are exchanged when the transmitter is changed.
The PMC−D contains a reference voltage source, which supplies the D/A converter in the phase mea-
suring circuit and the sideband antenna monitoring with a temperature−stable reference voltage of
10 VDC.
2−62 48SB Ed. 07.04

DVOR 432
Z8
CSB A49 (carrier antenna)
circulator
Z3
SB1/USB Z5 MOD−SBB
circulator
Z4
SB2/LSB Z6 MOD−SBB
return forward forward return forward
Phase control
3 dB 3 dB 3 dB
N4 N3 N5
RF RF RF
U2 U3 U4 RF
U1
lo lo lo
mixer mixer mixer lo
IF IF IF mixer
X22 X23 X24 X21 IF
Filter Filter Filter Filter

10 kHz 10 kHz 10 kHz 10 kHz
BIT signals USB/LSB

(return signal ok or not ok) SB1 SB1 SB2 SB2
9960 Hz monitoring
9960 Hz monitoring RF phase control
SB−antenna monitoring
low pass
+ MO 10kHz
to MSP−CD SBMON N23 −
ME 10kHz
to MSP−CD: 10kHz
Individual antenna fault (BIT), D5
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
M_ANT_DV +
antenna fault (BIT) −
M_ANT D cw N15
ÍÍÍÍÍÍ
N16,28 3 2 1
X10
ÍÍÍÍÍÍ
SBMON Compare level
to Mon1 Tx/Rx
to MSP−CD
ÍÍÍÍÍÍ
to Mon2 D12,13
D16 SB ant. SB ant. D15
ÍÍÍÍÍÍ
monitor. 5.8982 monitor.
D/A threshold MHz window
dedicated antenna fault comp. SB Mon compare
ÍÍÍÍÍÍ
N26 30Hz position
recognition SB antenna threshold sync. control
(option; not implemented) N27
Compare out
Phase measurement ME 10kHz D6
clk 5 MHz Mon Stop Phase
Uref phase R1−10kHz
counter
9960 Hz XMT Start Phase
MUX
R2−10kHz
to TX1 Tx/Rx XMT Stop Phase
Phase measurement decoder
values for monitor D5,6 latch MO 10kHz
to TX2 RF phase data bus A0...7 Mon Start Phase
Clock signal 30 Hz from CSL

MUX Driver BSG
D1 D8 setting data
2x
MUX Driver 8 bit data
control data
D2 D9
Control signals from MSG−C
(TX1 or TX2) MUX Driver 4 bit control BSG−D
control bus D3 D10
address bus
MUX Driver
D4 D11 Demultiplexer
Change over from CSL Select Tx
TX1/TX2 DC converter
Control signals
N1,N2
DC−supply ±15VT1/T2 = ±12 V
+5VT1/T2 5V =
BSG−D DC−Converter On
ASU−interface
Fig. 2−46 Phase Monitor and Control (PMC−D) including ASU interface, block diagram
Ed. 07.04 48SB 2−63

DVOR 432
2.4.3.2 Sideband Antenna Monitoring
The standard SB antenna monitoring circuit, built by N15,16,28 and D5, permits an additional moni-
toring to detect missing sideband antennas. Its function is to supply a low−frequency analog signal
which changes in the event of a failure in one or more of the sideband antennas; the harmonic spec-
trum of this signal (30, 60, 90, 120 and 150 Hz) is evaluated by the DFT. It initiates a BIT alarm if a certain
harmonic component is exceeded. The alarm or warning limits can be set. To reduce the 30 Hz com-
ponent from the carrier modulation both 9960 Hz sideband signals are substracted. If one sideband
aerial is missing mainly a 60 Hz frequency component remains. The software of the signal processing
is adapted in a way not to pass the 30 Hz low pass filter on the MSP. Besides this signal derived from
the SB1 and SB2 processing also the actual processing of the 9960 Hz monitor signal remains.
An optional antenna monitoring circuitry (Fig. 2−46, hatched gray), built by D15,16 and N26,27, al-
lows to define the faulty antenna individually. The sideband antenna monitoring logic provides a shift-
able sample window signal centered around the expected maximum output power of the sideband
antennas (determined through the shape of the blending signals). The TX−software sets the sample
window point according to the sideband antenna it actually intents to monitor. Shifting the window
through all expected sideband antenna maxima, it can check the correct function of all sideband an-
tennas. The sample signal starts 64 clock pulses before and stops 64 clock pulses after the expected
maximum. It controls a comparator with two inputs:
− reference input signal (threshold, adjustable by the D/A converter set once during system installa-
tion, controlled by the TX−SW)
− envelope of the 10kHz sideband antenna signal ME−10K
If the comparator is enabled it compares two signals. If IN− is below IN+ the non inverting logical
output goes high. This will be detected by the monitoring logic and the antenna fault flag will be set.
The TX SW will evaluate this flag and determine which sideband antenna is concerned.
At time this function is not implemented.
2.4.3.3 ASU−Interface
The ASU−interface section is a part of the PMC−D subassembly, but comprises individual tasks. To-
gether with the BSG−D subassembly, the ASU−interface forms the data link between the DVOR
transmitter and the ASU subassemblies. The data communicated on this link includes control infor-
mation for the ASU subassemblies and information for transferring the phase values measured for
SB1 and SB2 − referred to the carrier − after they have been digitized and BIT signals. The ASU−in-
terface contains a multiplexer block (D1...D4) and interface drivers (D8...D11), which are used to con-
nect the control lines for the ASU. In the opposite direction, the measured phase values are supplied
from the ASU to the monitor processor (MSP−CD) via V.24 receivers (D5/6). A connected decoder
detects when the active monitor (in other words the monitor whose transmitter is currently switched
to the antenna) receives a phase value from the ASU.
2−64 48SB Ed. 07.04

DVOR 432
2.4.4 Modulator Sideband Blending (MOD−SBB)
See Fig. 2−47.
The blending modulators MOD−SBB are used to modulate the DVOR sideband signals SB1 (USB)
and SB2 (LSB) which are supplied by the MOD−110 in the transmitter rack as an unmodulated RF−
signal (cw) with a defined envelope (blending function: sine/cosine).
The two blending modulators generate four RF−signals, even high/even low and odd high/odd low,
which are distributed via an implemented 2P2T−switch to the commutator boards (ASU−C a,b)
within the PIN−Diode Switching Unit (PDSU) to supply the 48 SB−antennas. The MOD−SBB com-
prises:
− a power divider (−3 dB)
− two 90°−hybrids
− 2 RF−modulators
− actual−value measuring circuits (N1, N2)
− AGC amplifier (N7,5; N6,8)
− BIT signal demodulators
− peak detector circuits
− 2x 2P2T−switch
The incoming sideband signals USB and LSB are divided each in the correspondent MOD−SBB into
two equal components. One component of the e.g. USB is amplitude−modulated independently of
each other in two loss modulators with the "sine" envelpope, the other with the "cosine" envelope.
This modulation type is known as a blending function. It serves to reduce to a minimum the spurious
modulation caused by the commutation process from one sideband antenna to another. Ideally the
commutation process should simulate rotation of an omnidirectional radiator on the sideband anten-
na circle around the middle antenna. The blending function used is a modified version of a sine or
cosine function. The setpoint of the blending function is supplied by the BSG−D subassembly.
The "sine"−modulated signals of both MOD−SBB, e.g. even high and even low, are distributed via
the implemented 2P2T−switch to the PDSU. A delay line is located between the sine−hybrid output
and the 2P2T−switch for compensation of the RF phases between the two signals. The delay line
compensates the phase difference to the incoming RF−signal of the other MOD−SBB which is origi-
nated by its longer supply line.
The RF−signal is amplitude modulated in locked phase relation. Each RF−modulator incorporates
the following functions:
− bridge circuit with PIN diodes
− AGC amplifier and with setpoint/actual value comparison
− driver stages for the control current and the linearization network
− demodulator circuits
The voltage waveform generated at the RF−output is variable from its maximum level to its zero;
phase inversion is however not possible. Since there is a highly non−linear relationship between the
control current and the RF output voltage, a linearization network is required. It is driven by the AGC
amplifier, which compares the actual value from the demodulator (N1 or N3) with the setpoint from
the BSG−D.
Additional BIT−information is derived from the envelope signals. The output signals of the RF modu-
lators supply peak detectors. The signal is amplified and rectified to a BIT signal. The BIT−signals
are fed to a multiplexer circuit on the BSG−D and supplied to the MSG−S (MUX1) in the transmitter.
A further peak detector feeds the input signal URF to comparators which compare the peak value of
the demodulated signal (X SB sin or X SB cos) with the RF−input signal value. To avoid overload
Ed. 07.04 48SB 2−65

DVOR 432
which may occur by a high ratio cw−power/SB power a correction signal is sent to the BSG−D which
achieves an optimization of the ratio. Jumper X3, X4, X5 allow to adjust the comparison level of URF.
The definition of each MOD−SBB to be dedicated to USB or LSB is achieved by jumper X8 and X9
which feed the input sine or cosine blending signals to the RF1 or RF2 modulator path.
The location of both MOD−SBB is shown in Fig. 2−6.
V3
BIT signal
XSB SIN CON to BSG−D
actual value DEM XSB SIN
RF Modulator 1
demodulator
− U pin1 Rf
setpoint X ANT SEL USB/LSB
control from BSG−D
3 + N7,5 V23,24
Sine blending X9* AGC amplifier 0° N1
from BSG−D 1 W3
X HI out
to PDSU
sin
delay line W2
90°−Hybrid from MOD−SBB 2
XSB RF in
coupler 20 dB
W4
2P2T switch X LO out
to PDSU
90°
peak detector UDEM XSB SIN to BSG−D
Rf
to BSG−D
V25,26 comparator RF peak correction
N16,19
−3 dB N10 cw/SB power
divider peak detector
U RF offset cw/SB power
W1 X5 X4 X3 select
RF IN USB (LSB)
N2 demodulator N14,20
peak detector to BSG−D
from RFD2−SB comparator RF peak correction
1 N9 CW/SB power
−3 dB
Rf N11,21
UDEM XSB COS
to BSG−D
V27,28 V1
0° to BSG−D
B XSB RF CON
cos coupler 20 dB W5
90°−Hybrid to MOD−SBB 2
XSB RF out
Cosine blending X8* AGC amplifier 90°

from BSG−D 1
setpoint + Rf
N3
− N6,8 U pin2 V29,30
demodulator
RF Modulator 2
DEM XSB COS
V2
actual value BIT signal
XSB COS CON to BSG−D
X e.g. in "X LO out" means even or odd, or USB or LSB

* configuration of the MOD−SBB to USB or LSB operation
Fig. 2−47 Modulator Sideband Blending (MOD−SBB), block diagram
2−66 48SB Ed. 07.04

DVOR 432
2.4.5 Blending Signal Generator (BSG−D)
See Fig. 2−48.
The BSG−D represents the "control centre"in the ASU function. The BSG−D generates and pro-
cesses the blending signals, performs the control of the antenna switches and provides the dc power
supply for the ASU subassemblies. The tasks performed by the BSG−D are as follows:
− transmitter interface
− analog BIT signal selection
− blending signal generation
− blending signals amplitude control
− antenna select signal generation
− driver interface even antenna select signals
− driver interface odd antenna select signals
− dc power supply for ASU subassemblies
The blending signal generation is as follows: A crystal oscillator drives a 1:16 divider. This divider sup-
plies 368.640 kHz clock pulses to the 9 bit address counter (D17). The address counter controls the
start time with the data got from the BSG−D bus. It is used to read the precise shape of the "sine"
and "cosine" envelopes (blending function) stored in digital form in EPROM D1. It also controls trans-
fer of the data to the d/a converter memories. The repetition rate for the complete counter cycle is 720
Hz. The divider as well as the address counter is reset every 30 Hz cycle by the 30 Hz synchronisation
signal from the CSL fed by the PMC−D.
The EPROM stores 8 waveforms. Two of them are used and selected by software and load to two 8
bit latches. The blending waveform for the even antennas starts with the leading edge, the one for
the odd antennas with the trailing edge of the 720 Hz cycle frequency. The data from the latches are
d/a converted and fed to four further d/a converters used as amplitude control for the four control sig-
nals (USB SIN/COS and LSB SIN/COS) which are fed to the blending modulators MOD−SBB. The
amplitude of the four functions is set digitally via the appropriate latch settings. According to the set-
ting data for the blending waveform the multiplying d/a converters change the amplitude modulation
of the 9960 Hz components.
These values for setting the amplitude and all other setting functions for control are selected by the
MSG−C whose transmitter is switched to the antenna. The data signals are received via the PM−C
and forwarded to registers (data bus BSG−D). The control signals are received and decoded. The
selected register accepts the data from the bus synchronously with the internal clock. In addition to
the data for setting the amplitudes of the 4 blending functions the MSG−C also transmits the select
information for through−connection of the BIT signals, the antenna control code and the control sig-
nals for the phase measuring circuit.
The 4−bit code decoded in D18 determines which of the 16 analog BIT channels of the ASU is se-
lected by the analog multiplexer D8. The ADVOR output signal is supplied via the PMC−D (ASU−in-
terface) and distributed to the MSP−CD (1 and 2) for measured value acquisition. The MSP−CD of
the active transmitter (i.e. that switched to the antenna) evaluates these BIT signals. The selection
pattern for the 16 BIT channels of the antenna switching unit is laid down in the software; measure-
ments are performed cyclically.
The principle of double sideband switching used involves simultaneous radiation of the upper and
lower sidebands by diametrically opposite sideband antennas. In addition, the individual sideband
Ed. 07.04 48SB 2−67

DVOR 432
antennas are controlled in such a manner that when one radiator reaches its radiation peak, the adja-
cent radiator is energized to ensure that the point of concentrated radiation rotates as continuously
and smoothly as possible. Four sideband antennas are thus energized simultaneously at any given
instant.
This sequence is controlled and initiated by the antenna counter. The antenna counter counts cycli-
cally from 0 to 23, and is reset automatically to 0 when a count of 24 is reached. The control signal
for the counter is the 720 Hz clock and the 30 Hz synchronization signal. The 30 Hz sync. signal is
derived from the 30 Hz clock of the MSG functional group; it is used to synchronize the 30 Hz antenna
rotation with the 30 Hz amplitude modulation of the carrier signal. A unique phase relation is thus de-
fined between the 30 Hz AM and the 30 Hz FM. The availability of the 720 Hz signal and the 30 Hz
sync. signal is indicated by LED H2 and H1 in front of the BSG−D.
To set the antenna counter (D18, D19) further control bus signals are used. The antenna counter deliv-
ers two control signal outputs, one for the even numbered and one for the odd numbered SB anten-
nas. It drives the SB antennas via bus driver and line drivers which include overvoltage protection.
A provision ( PLD D20) is made for possibly needed corrections (e.g. time delay for USB or LSB select
signals) if the zero point of the modulation deviates from the switching moment caused by delays.
The 30 Hz output signal of the antenna counter (30HZE, 30HZO) is used for control of the 2P2T
switches on the MOD−SBB.
Various control modes of the 48 sideband antennas are available to the user. They can be selected
by entering the appropriate software commands. All measurements necessary during the startup
phase and for repairs and maintenance are supported.
The location of the BSG−D is shown in Fig. 2−6.
2−68 48SB Ed. 07.04

DVOR 432
48 V dc
ASU On/Off DC supply on/off

from PMC−D
DC DC DC
converter converter converter
+5 V +15 V −15 V
DC supply ASU
+5 V
+15 V
−15 V
+5 V +15 V −15 V
Data+Control
B0..7, C0..3 Buffer
from PMC−D Data bus BSG−D +5 V
(ASU interface) H1 H2
30 Hz Synch.
30 Hz Synch.
from PMC−D 100 ms / 30 Hz BIT
even antennas 5 ms / 720 Hz BIT

Control C4...7 Chip select divider 5.89824
from PMC−D MHz
Decoder 1:16
G1
odd antennas
CS 720 Hz 30 Hz
address counter antenna counter
Blending signal and
generation control control logic
D17 D19,20
E
F
720 Hz
Blending function selection additional
address
Reference EPROM decoder
voltage signal shape Decoder D18
10 V (sin/cos) D1
8 Bit
sin A Latch Latch D cos

D 8 bit 8 bit A
N9 N10
Blending signal generation
8 bit control data
CS CS CS CS analog BIT
selection
c0...3 control signal control signal
Latch Latch Latch Latch even antennas odd antennas
2,4,...,48 1,3,...,47
A B C D
D D D D Analog.
A A A A Mux. driver driver
N8 N7 N6 N5 D8 D7 D6
Blending signal Blending signal
amplitude control amplitude control
USB SIN USB COS LSB SIN LSB COS analog BIT signals BIT antenna switch 30HZE 30HZO
to MOD−SBB/1 to MOD−SBB/2 (ASU intern) signal control to MOD−SBB
to PMC−D/TX to PDSU
Fig. 2−48 Blending Signal Generator (BSG−D), block diagram
Ed. 07.04 48SB 2−69

DVOR 432
2.4.6 PIN−Diode Switching Unit

The PIN−Diode Switching Unit (PDSU) comprises the commutator boards ASU−C (2x) and the con-
trol and DC supply interface board ASU−CIF. Both are mounted with the RF and NF connectors to
a cover plate incorporated in a housing which is mounted outdoor below the counterpoise. From the
transmitter cabinet four RF cables and the NF control and dc supply cable are fed to the PDSU. The
PDSU is connected to the 48 SB antennas with 48 equal distant RF cables. The RF cable to the carrier
antenna is directly fed from the transmitter cabinet to the carrier antenna (49). The location of the
ASU−C and ASU−CIF in the PDSU is shown in Fig. 2−8.
2.4.6.1 ASU−Commutator Interface (ASU−CIF)

See Fig. 2−49.
The ASU−CIF is the interface between the control signals from the transmitter and the PDSU commu-
tator boards. It serves for lightning protection and optocoupler isolation of the control lines and its
signals. In addition it contains two DC/DC converter which supply the PDSU boards and its compo-
nents with the required +5 and −15 V. The "ASU−On" command from the BSG−D is used to start
operation. Two jumper on the ASU−CIF are used to activate or deactivate a 50 ohm termination of
the RF switches on the ASU−C.
BSG−D ASU−CIF J27 H/L ASU−C

5V
DC Converter J28
GND
48 V N1
+5V
N2 −15 V
48 RF
ASU On lightning protection
Control Control
Fig. 2−49 Antenna Commutator Interface (ASU−CIF), block diagram
2.4.6.2 Antenna Switching Unit Commutator (ASU−C)

See Fig. 2−50.
The ASU−C is a component of the RF distributor network, which serves to distribute the sideband
signals EVHI/EVLO and ODHI/ODLO conditioned and distributed in the blending modulators MOD−
SBB among the 48 sideband antennas. Two ASU−C boards with 2x 12 switches each are required
to supply the 48 sideband antennas. The main features of the ASU−C are as follows:
− PIN diode switches in the RF stages and the associated driver
− capability to deactivate 50 ohm termination of the RF switches with jumper setting
Each ASU−C subassembly has two RF inputs and 2x 12 RF outputs. The boards have a modular
design. Input 1 (e.g. EVHI) or 2 (e.g. EVLO) is fed to the star connection point A. The RF−signal is
then through−connected to the corresponding output via a PIN diode switche in accordance with
the driver stage activated (high level at P1). The activation is defined by the control signal from the
BSG−D, decoded and distributed with decoders U16,17 and U18. Non−conducting branches of the
output diode switch have a reverse 50 termination (component of the driver stages) which can be
deactivated via input P2 setting jumper J27 (H) instead of J28 (L). Jumper J3 is used only for test.
2−70 48SB Ed. 07.04

DVOR 432
to SB antennas
OUT2 OUT4 OUT24
12 D2...4 D2...4 D2...4

RF stage RF stage RF stage
D1 2 4 24
from D1 P1 P2 P1 P2 P1 P2
MOD−SBB A
RF IN (EVLO) 12x
Driver Driver Driver

D1
50 ohm termination
inactive(H)/active (L) H/L H/L H/L
J28
GND
from H/L J3
J27 Vcc
BSG−D 5V Decoder
Control U16,17
Decoder
D0...3 4 U18
ASU−CIF
DC supply
48 V +5/−15 V
DC on
Control
H/L H/L H/L
NOTE: J27, J28 must not be set 12
at the same time! Driver Driver Driver
D1
from D1
MOD−SBB A
12x P1 P2 P1 P2 P1 P2
RF IN (EVHI)
D1 D2...4 D2...4 D2...4

RF stage RF stage RF stage
26 28 48
OUT26 OUT28 OUT48

ASU−C a to SB antennas
to SB antennas
OUT1 OUT3 OUT23
from H/L
MOD−SBB RF
RF IN (ODLO)
Vcc J3
Decoder
U16,17
Decoder
D0...3 4 U18
DC supply
+5/−15 V
from
MOD−SBB RF
RF IN (ODHI)
OUT25 OUT29 OUT47
ASU−C b to SB antennas
Fig. 2−50 Antenna commutator (ASU−C), block diagram
Ed. 07.04 48SB 2−71

DVOR 432
2−72 48SB Ed. 07.04

DVOR 432
Equipment Description Description Antenna System
CHAPTER 3
TECHNICAL DESCRIPTION ANTENNA SYSTEM
3.1 GENERAL
See Fig. 2−1, 3−1.
The DVOR antenna system comprises the following system components:
− Antenna counterpoise with supports and framework, framework decking and antenna circle
(circle used during assembly for securing the sideband antennas)
− 48 sideband antennas
− 1 carrier antenna
− Cabling
− Monitor dipole
Sideband antennas (48) Carrier antenna (1) DME antenna (optional)
Building for transmitter cabinet, ASU cabinet Counterpoise
Fig. 3−1 DVOR antenna installation (example)
3.2 SYSTEM CHARACTERISTICS
The electronic simulation of the antenna movement is described in Section 1.2.2.2.2 . In order for the
procedure to be implemented, antennas which are installed close together must be activated and fed
consecutively. This gives rise to the following problems concerning the antennas:
− Parasitic radiation coupled in from neighbouring antennas causes the radiation pattern to change
and results in spurious spectral components in the DVOR signals.
Ed. 07.04 48 SB 3−1

DVOR 432
Description Antenna System Equipment Description
− If a receiver (aircraft) is located within the space, heterodyning (vectorial addition) of the waves
transmitted by the adjacent sideband antennas occurs as a result of the successive feeding
method used for these antennas in order to simulate the antenna rotation effect, whereby two adja-
cent antenna are always fed at the same time. The simulated rotation causes the positions of the
neighbouring sideband antennas which are fed to change periodically relative to the receiver, so
that the heterodyning conditions also change. A spurious 60 Hz modulation is consequently gen-
erated in the sideband signal received in the aircraft.
Thales ATM makes optionally available the following components, in an attempt to solve these two
problems; the installation without these features is delivered as standard version:
− The parasitic excitation of the sideband antennas caused by the coupled radiation is reduced to
a negligible system value (< −20 dB). This is achieved by inserting an optional Matcher in every
feeder to the sideband antennas. This lossy subassembly has the usual characteristic−imped-
ance matching in the forward direction (transmitter antenna); in the return direction (antenna
transmitter) however its impedance deviates considerably from the characteristic impedance (50
ohms). The antennas are loaded with a high impedance at the feeding points, with the aid of imped-
ance transformation, and can thus no longer be excited parasitically by the radiation.
− In addition an installation is available which uses an optional Decoupling Module and additional
coupling cables between antennas 1 to 48. The spurious 60 Hz modulation caused by the rotation
of the radiation is reduced to a negligible value by feeding antennas which are not directly adjacent
in defined groups. This is achieved by "subfeeding" the next−but−one sideband antenna in each
direction (N+ 2, N−2) with a small portion of the sideband power that is being used at the same
time to feed the main sideband antenna in the module (N). A power divider is required to do so;
it is incorporated in the Decoupling Module. This group feeding method results in a more or less
elliptical sum pattern, the principal axis of which is tangential to the rotation of the sideband anten-
nas. This reduces the spurious, system−related 60 Hz modulation caused by simulating the rota-
tion of the sideband radiation to a minimum.
3.3 SIDEBAND AND CARRIER ANTENNAS

3.3.1 Sideband Antenna
See Fig. 3−2 to 3−11.
The sideband antenna comprises 48 individual antennas (individual radiators) mounted on an an-
tenna circle (holder for these 48 individual antennas on the framework or framework decking) such
that the 48 individual antennas are equally spaced at 7.5° with respect to one another as seen from
the center antenna (carrier antenna). The relevant installation instructions are contained in Part 2 of
the Technical Manual. The external mechanical details of this type of individual antenna are shown
in Fig. 3−10. The cables are connected directly to the individual antenna or, optionally, at the Matcher
(or Decoupling Module), which is accessible via the installation hole in the vertical pipe (Fig. 3−10/3).
In order to get access to the antenna connector (or the optional matcher or decoupling module), the
cover (3−10/3) should be pressed back at the bottom and pushed down. Fig. 3−4 is the connection
diagram for the individual radiators of the sideband antenna.
The optional group feeding method is implemented by supplying the two next−but−one antennas
in parallel with the main antenna. These two secondary antennas must of course also be capable of
acting as the main antennas as the rotation of the radiation continues. Consequently, all the optional
Decoupling Modules of the even−numbered sideband antennas and all those of the odd−numbered
antennas are connected together by cables (optional) having a defined length. This length must be
selected so that the correct phase displacement is generated for the group pattern. The correct ampli-
tude is ensured by the power divider function integrated in every Decoupling Module. The divider is
in series with the divider at the input of the next Decoupling Module.
3−2 48 SB Ed. 07.04

DVOR 432
The oblong holes in the upper section of the vertical pipe (3−10/2,4) provide a facility for adjusting
the lower section of the antenna dome (3−10/1) on the vertical pipe. In their installed state the antenna
elements in the lower section of the antenna dome (Fig. 3−11) are protected against the weather by
means of a fibreglass−reinforced polyester cover.
The individual radiators of the sideband antenna take the form of horizontally polarized omnidirec-
tional radiators (Alford loop antenna). The antenna elements of each individual radiator comprise 4
sheet metal strips which form a square frame (loop antenna), and which are embedded in a polysty-
rene frame (Fig. 3−11). The polystyrene frame forms the lower section of the antenna dome. It en-
ables the antenna elements to keep their shape, which ensures optimum electrical matching in the
entire sideband antenna.
Adjustable capacitors are provided at 2 of the diagonally opposite ends of the loop (supply points)
(Fig. 3−11). They are used to set the resonance of the loop in the 108 ... 118 MHz frequency range.
This resonance setting ensures a uniform current distribution (Fig. 3−2), and thus a perfect omnidi-
rectional pattern. The spacing of the capacitor plates (Fig. 3−2) as a function of the desired operating
frequency is shown in Fig. 3−3.
The RF is supplied symmetrically via crossed supply lines at the ends of the 4 loop sections. The re-
sulting alternating polarity ensures a uniform direction of current flow all round (Fig. 3−2). Each of
the 4 outer faces of the loop is approx. 550 mm (0.2 ) long. The optional Matcher or Decoupling Mo-
dule output (3−10/5) is connected to the balance−to−unbalance and matching transformer (see
Section 3.3.1.1).
ËËËËËËËËËË
+
ÊÊÊ
ÊÊÊ ÊÊÊÊ
ÊÊÊÊ Adjustable capacitor
ÊÊÊ ÊÊÊÊ
CA
ÊÊÊ ÊÊÊÊ
ÊÊÊ
ÊÊÊ ÊÊÊÊ
ÊÊÊÊ
Supply point
Current distribution
ÊÊÊ ÊÊÊÊ
−
−
ÊÊÊ
ÊÊÊ ÊÊÊÊ
ÊÊÊÊ
ÊÊÊ ÊÊÊÊ
ËËËËËËËËËËË
Spacing a
+
Fig. 3−2 Current distribution and setting of the capacitors
Ed. 07.04 48 SB 3−3

DVOR 432
CA
[mm]
14
13
12
11
CA
10
Frame
9
0
108 109 110 111 112 113 114 115 116 117 118 119 MHz
Fig. 3−3 Spacing of the capacitor plates as a function of the operating frequency
optional assemblies:
Antenna A3
Matcher
A48 A1 A2 A3 A4 A5 A6
from ASU
*** *** Antenna A3
*** ***
Decoupling
Module
optional
ASU−C a ASU−C b ASU−C a ASU−C b

(1...23) (25...47) (2...24) (26...48)
Antenna A1** Antenna A5**

PDSU from ASU
** Optional connectors if coupling between antennas 1 to 48 is used

*** Coupling cables (optional)
Fig. 3−4 Connection diagram of individual radiators of the sideband antenna
3−4 48 SB Ed. 07.04

DVOR 432
3.3.1.1 Balance−to−Unbalance and Matching Transformer
The balance−to−unbalance and matching transformer (Fig. 3−5/Z) is a component of the lower sec-
tion of the antenna dome (3−10/1); it comprises a pipe containing 2 inversely connected coaxial
cables (Z= 50 ohms). The result is automatically a balanced condition (see Fig. 3−5). If the cables
in this layout are twice terminated with Z, the transformer will be wideband and independent of the
length within limits (/8). The loop resistance provided is transformed to the desired input resistance
Z=50 ohms by selecting suitable lengths for the two cables. The glass−tube trimmer (3−5/CTr) at
the cable input of the transformer permits additional parallel transformation.
It is possible to set the optimum matching for each frequency of 108 ... 118 MHz by adjusting the spa-
cing of the capacitor plates (3−5/CA) and by adjusting the glass−tube trimmer CTr. In order to fulfill
the requirement for an active return loss of 26 dB, it should normally be sufficient to set CA as shown
in Fig. 3−3 and CTr as shown in Fig. 3−6. The short coaxial cable with a fixed length (approx. 90°),
which is located ahead of the balance−to−unbalance and matching transformer, is fed to the optional
Decoupling Module, which is accessible via the installation hole in the vertical pipe (Fig. 3−10/6).
The radiation pattern of the loop antenna is circular with a maximum deviation of ±0.5 dB. The vertical
pattern is shown in Fig. 3−7.
Loop resistance RA
Input resistance RA for CA 5 mm Ctr 0 turn
CA
RA
CA
Z CTr Z
Fig. 3−5 Resistance behaviour of the balance−to−unbalance and matching transformer
Ed. 07.04 48 SB 3−5

DVOR 432
CTr
Rotations
26
24
22
20
18
16
14
12
10
CTr
8
matching transformer
108 109 110 111 112 113 114 115 116 117 118 119 MHz
Fig. 3−6 Setting trimming capacitor CTr
Fig. 3−7 Vertical pattern of a DVOR loop antenna
3−6 48 SB Ed. 07.04

DVOR 432
3.3.1.2 Options: Matcher and Decoupling Module
See Fig. 3−8, 3−9, 3−10.
The functions of the Matcher and the Decoupling Module have already been described above in chap-
ters 3.2 and 3.3.1. The Matcher (or the Decoupling Module) has an input X1, which is connected to
the antenna switching unit (ASU), and an output X2, which is connected to the main antenna being
fed. The optional Decoupling Module is assembled with two additional outputs X3 and X4 (Fig. 3−8)
for "subfeeding" the next−but−one antennas (group feeding method). The coaxial cable W1 pro-
vides impedance transformation in the direction of the antenna. The capacitor C5 is used for fine tun-
ing to the desired operating frequency (Fig. 3−9).
X3
R1 R1
L4 L4
L2
C3 C3
C2 L1 W1 C2 L1 W1
X1 X2 X1 X2
C1 C4 C1 C4
C5 L3 C5
L5 L5
R2 R2
X4
Matcher (Ref.No. 83134 00103) Decoupling Module (Ref.No. 83134 00101), optional
Fig. 3−8 Optional Matcher and Decoupling Module, circuit diagram

C5
Rotations
16
14
12
10
8
C5
6 Matcher/Decoupling Module
108 109 110 111 112 113 114 115 116 117 118 119 MHz
Fig. 3−9 Setting trimming capacitor C5
Ed. 07.04 48 SB 3−7

DVOR 432
3.3.2 Carrier Antenna

The carrier antenna has a design identical to that of an individual radiator of the sideband antenna.
It contains the following components:
− Vertical pipe,
− Antenna dome with
− Antenna elements (loop antenna),
− Calibration capacitors (on the loop antenna and balance−to−unbalance and matching trans-
former);
The carrier antenna however has no matcher/decoupling module, which means that the supply cable
is connected directly to the balance−to−unbalance and matching transformer (component of the
lower section of the antenna dome).
3
4
2 5
10 10
1 6
7
8
9
Direct feed (standard)
Decoupling Module (optional) Matcher (optional)

1 Cover plate for access to matcher/decoupling module 6 Matcher/Decoupling Module
2 Screws (3), for adjustment antenna dome, lower section/vertical pipe 7 Supply cable to/from antenna 4 (X3)
3 Antenna dome, lower section 8 Supply cable for antenna 2 from ASU (X1)
4 Vertical pipe 9 Supply cable to/from antenna 50 (X4)
5 Output to antenna (X2) 10 Trimmer C5
Fig. 3−10 Single radiator on sideband antenna
Twist drill
Preadjustment of the capacitors with the aid of a twist drill neck
Fig. 3−11 Single antenna, cover removed
3−8 48 SB Ed. 07.04

DVOR 432
3.4 ANTENNA COUNTERPOISE (SUPPORT AND SCAFFOLDING)
See Fig. 3−12, 3−13.
An antenna counterpoise is available for overall system heights of 3, 5, 7 and 10 m. The structure is
designed for a maximum wind velocity of 200 km/h (operation: up to 160 km/h). All parts other than
the plastic or steel RF cable conduits underneath the platform are made of hot−dip−galvanized steel.
The framework (Fig. 3−12) is a twelve−sided structure with a diameter of 30 m. It is supported at 24
points. The supports are arranged in two circles with a diameter of 13.5 m and 24 m. 4 x 4 main sup-
ports are secured together by means of additional braces. The round supports have a diameter of
120 mm and walls 3 mm thick.
The 48 SB antenna feeders are routed to the center of the counterpoise and fed to the PDSU−housing
which is mounted below the counterpoise near to the U−shaped girder in the center of the counter-
poise as standard. From the PDSU, the 4 RF feeders and the control−cable are routed down the U−
shaped girder together with the center antenna feeder and laid via a cable box to the terminal plate
at the shelter. The shelter is located directly adjacent to the cable box one meter from the center.
In addition to acting as an electrical counterpoise, the framework serves as a mechanical supporting
structure for the antenna ring with the 50 sideband antennas and is also used to secure the central
carrier antenna. The centrically aligned antenna ring has a diameter of 13.5 m. It is subdivided into
12 separate elements to facilitate transportation. Each of these elements consists of two curved
65 mm U−shaped girders, welded together at equal intervals of 170 mm. The profiled inner sides are
always installed facing one another. The fold−down access hatch, which is accessible via a ladder,
is approximately 6 m from the center. The entire counterpoise platform is covered with 6 mm thick,
hot−dip−galvanized structural steel mats with a mesh width of 100 x 100 [mm]. The mats are bolted
together with grips at intervals of 300 mm. U−shaped brackets are used to secure them to the steel
girders. The mats are mounted on the girders with flat steel strips at the outer edge of the platform.
Framework Antenna ring Mounting device for carrier antenna Entry and ladder
Supports Braces Mounting area for the PDSU housing below counterpoise near the entry
Fig. 3−12 Supports and framework, example installation
Ed. 07.04 48 SB 3−9

DVOR 432
Sideband antennas
on antenna circle
Carrier antenna (centre)
Fig. 3−13 Framework decking and antenna circle with carrier antenna and sideband antennas
3.5 MONITOR DIPOLE (NEARFIELD)

See Fig. 2−1, 3−14.
The monitor dipole is a passive subassembly. Its main components are as follows:
− 1 dipole (2 x 65 cm = 130 cm equivalent /2 at 113 MHz)
− 1 reflector
− 1 director
The monitor dipole is mounted on a mast (wooden or metal) at a height of 1.3 m above the antenna
counterpoise. It should be installed at a distance of approx. 200 m from the center of the counterpoise.
The installation location can be selected at any azimuth. A solution at reasonable cost may be se-
lected with respect to the infrastrutcture, topography and accessibility etc. The received RF is sup-
plied via a coaxial cable to a divider in the shelter (Fig. 2−1), then divided into two identical signals
and supplied to monitors 1 and 2.
Dipole
Mast
Mast mounting on foundation
Fig. 3−14 Mast with monitor dipole (example)
3−10 48 SB Ed. 07.04

DVOR NAV 400
Equipment Description Emergency Power Supply
CHAPTER 4
EMERGENCY POWER SUPPLY
4.1 GENERAL
For use in Navaids 400, a set of lead batteries, comprising four bloc batteries, is connected in parallel
to the DC voltage supply from the mains unit BCPS. In case of a mains failure or disconnection of the
primary voltage for maintenance purposes, it is used to supply the Thales navigation installation. Bat-
teries, which are maintained at a permanent cell voltage of 2.25 V (standby parallel operation) by the
BCPS, are supplied by Thales as standard for NAV−installations (Navaids 400). Battery sets are avail-
able as lead acid batteries (type Vb...) or maintenance free lead batteries (type 12 VE...) using an elec-
trolyte which is fixed as a gel. The recommended battery type has a capacity tailored to the require-
ments of the Thales navigation installation. In such case should be noted, that the 54 V trickle charge
voltage supplied by the BCPS is a fixed output and can not be changed therefore.
NOTE: Alkaline batteries, e.g. Nickel Cadmium batteries, require a different charging method,
and cannot therefore be used in conjunction with the power supply BCPS
(module ACC 54, Ref. No. 58341 20100).
Batteries supplied by the customer have to correspond to the specification of recommended battery
sets. The following battery types are recommended for DVOR−installations:
System Mode Current at 48 V Capacity Type * No. of Thales Ref. No.
batt. operation bloc batteries for battery set
DVOR 50 W cold stdby ca. 11.25 A 54 Ah Vb 12144 4x 12 V bloc 83131 72242
56 Ah 12 VE 60 4x 12 V bloc 83131 72252
DVOR 50 W + cold stdby ca. 15 A 72 Ah Vb 12146 4x 12 V bloc 83131 72243
DME435 68 Ah 12 VE 75 4x 12 V bloc 83131 72253
DVOR 100 W cold stdby ca. 15.83 A 72 Ah Vb 12146 4x 12 V bloc 83131 72243
79 Ah 12 VE 90 4x 12 V bloc 83131 72254
DVOR 100 W + cold stdby ca. 19.58 A 72 Ah Vb 12146 4x 12 V bloc 83131 72243
DME435 102 Ah 6 VE 110 8x 6 V bloc 83131 72255
* Vb = lead acid batterie; 12 VE xx= maintenance free battery
Dimensions and weight of the recommended bloc batteries:

Type Dimension [ L x D x H] Weight [kg] Weight of acid Remarks
Vb 12144 311 x 176 x 277 33.7 7.8 −
Vb 12146 389 x 176 x 277 45.6 9.7 −
12 VE 60 271 x 164 x 220 22.9 − −
12 VE 75 314 x 164 x 220 26.7 − −
12 VE 90 360 x 164 x 227 31.1 − −
6 VE 110 191 x 206 x 336 21.4 − −
Discharge times (guiding values) by use of the recommended battery set:

System Mode Type Discharge time * Remarks
DVOR 50 W Vb 12144 ca. 4.2 h Times down to reaching the nominal over−di-
12 VE 60 ca. 4.3 h scharge limit of the battery (manufacturer in-
+ DME Vb 12146 ca. 4.4 h struction)
12 VE 75 ca. 4.1 h
DVOR 100 W Vb 12146 ca. 4.0 h
12 VE 90 ca. 4.2 h
+DME Vb 12146 ca. 4.4 h
6 VE 110 ca. 4.1 h
*) The discharge times are valid for an environmental temperature of approx. 20 °C. At lower temperature the discharge times are
decreased accordingly.
Ed. 09.05 4−1

NAV 400 DVOR
Emergency Power Supply Equipment Description
4.2 CONNECTION OF BATTERIES
CAUTION
Before the battery is connected the power supply unit BCPS must be connected to the
mains, and the output voltage must have reached its rated value; the reaching of this level
is displayed by lighting LED’s at the front panels of the AC/DC−converter in the cabinet.
The battery set is connected via two PVC−insulated cables as per DIN 57281, 16 mm2 (red and black
or blue). The length of this connection is restricted to a maximum of 10 m for electrical reasons. The
red cable should be connected to the positive terminal of the battery set (+), and the black cable to
the minus terminal (−). It should be connected to the transmitter rack corresponding the polarity at
the "B+" and "B−" terminals. The cables of "B+" and "B−" are fed via the fuse switch F20 (50 A) in
the fuse box to protect the batteries.
For monitoring purposes, the battery is connected via a measuring cable (5x 1.5 mm2) to the BCPS
(terminals 2, 1, F, F, 0). This cable is connected on one hand to the terminals BAT0, BAT1 and BAT2
in the battery fuse box, and connects on the other hand the auxiliary contact (BFUSE) at the fuse
switch F20 to terminals F, F. The measuring cables BAT0, BAT1, BAT2 are protected by the fuse switch
F21 (0.2 A).
The terminal signs for battery monitoring mean:
BAT0 (0) 0 V or −
BAT1 (1) 24 V (half battery voltage; not used in ILS 420)
BAT2 (2) 48 V or +
The test procedure for the battery measurement is described in the Technical Manual, Part 2, chapter
6, Maintenance (ILS), or chapter 5, Maintenance (CVOR/DVOR). The discharge times of the recom-
mended batteries related to the NAV−systems concerned are listed in the table in section 4.1.
CAUTION
Maintenance−free batteries have to be set into operation within a half year after delivery
to prevent drawback in lifetime of battery.
4−2 Ed. 09.05

NAVAIDS
Equipment Description RMMC
CHAPTER 5
REMOTE MAINTENANCE AND MONITORING CONFIGURATION
(RMMC)
5.1 APPLICATION AND DESIGN
The Remote Maintenance and Monitoring Configuration (RMMC) is used for remote monitoring, oper-
ation and maintenance of all the connected navigation systems. The network has a radially configured
architecture based on communication between the system components via switched or private lines
in the public network and dedicated lines in private networks.
The remote control system components allow all the networked navigation systems to be operated
optionally from central points, from normal operation of the dual systems with automatic changeover
in the event of a fault through manual operation to measurement and setting of all the possible signal
parameters, as well as detailed fault analyses on the basis of a wide range of measured values. They
facilitate new maintenance strategies, whereby importance is placed firstly on concentrating logistics
and qualified personnel, and secondly on responding to specific failures with systematic mainte-
nance activities rather than relying on periodic precautionary measures. This considerably improves
both maintenance efficiency and the economic efficiency of the systems throughout their service life.
Although these advantages only apply to the modern generation of air traffic control systems devel-
oped by Thales ATM, with the navigational aids, namely the enroute navigational systems CVOR and
DVOR, the approach and landing systems ILS and MLS, the ILS farfield monitor (FFM) for Localiser,
the TACAN 453 and the electronic TACAN antenna (ELTA 200), the DME 415/435, and the NDB 436
radio beacons, the extensive range of interface boards makes it possible to incorporate other collo-
cated systems in the remote control and monitoring strategy if desired.
RMC 443
Remote Maintenance Center
ÊÊÊ
RCSE 443
ÊÊÊ
INC
REU
PSTN
RCMS 443
Remote Control and Monitoring System
Ê
ÊÊÊ
RCSE 443
ÊÊÊ
Ê
INC
REU
RCMS 443
RCMS 443 Stations

Other systems
Fig. 5−1 RMMC, overview
Ed. 07.04 5−1

NAVAIDS
RMMC Equipment Description
5.1.1 Hierarchy of RMMC Remote Control System Components
At the top, the Remote Maintenance Center (RMC−C) is used as central point to obtain an overview
of the status of all available systems. The RMC−C is connected via dialing modems to the public PTT
network to obtain serial data from the RMC−R, LCU 443 or RCMS 443.
At the RMC−R the main status of all en−route equipment (CVOR, DME−Transponder and TACAN−
ground stations) of one defined region are displayed continuously at the indication and control panel
(INC) of the RMC and at installed optional Remote Status Units (RSU) to the controller for en−route.
Besides en−route subsystems, the main status of the Landing Systems ILS and MLS are also dis-
played for maintenance purposes. The RMC−R is also connected to the PTT network via autodialing
modems. For special applications a fixed line interface may be provided. For maintenance activities
at the screen of the Personal Computer maintenance data are displayed. The maintenance technician
obtains all the data from the subsystems configured for this region with defined menus on the screen
of the data terminal (PC). It is possible to use the ADRACS software (Automatic Data Recording And
Control System) for maintenance purposes to control Navaids 400 family or System 4000 equipment
at the remote site. For MLS the MLS−menu technique is employed as well as respective ELTA−,
DME−, or TACAN−PC supervisory programs.
The RCMS 443 and the NAV LCU 443 are link control units and provide central points for communica-
tion between RMC’s and the navaids systems. While the RCMS is connected via twisted telephone
line pairs and modems to the ILS/MLS−equipment the NAV LCU 443 has direct RS−232/422 inter-
faces to the CVOR, DVOR, TACAN and ELTA−equipment, and DME. For small projects, it is possible
to connect the NAV LCU of en−route navigation systems via switched lines to an RCMS.
RMC−C Remote Maintenance Center

CENTRAL
Remote Maintenance Center
REGIONAL
RMC−R RMC−R RMC−R
PTT
network
RMS RCMS 443 ILS
LCU 443 VOR

LOC GS MM
LCP
VOR VOR 431

4000 TAC ELTA RCMS 443 MLS
TAC ELTA
AZ EL DME/P
Fig. 5−2 Hierarchy of the RMMC system components
5−2 Ed. 07.04

NAVAIDS
5.1.2 System Configuration
5.1.2.1 Local Remote Control Interface
The NAV stations communicate with the remote control system in different ways. The remote control
interfaces which are provided locally vary according to the type of installation:
Type Modem Baudrate Remark
Dedicated line ZU1 600 bd System 4000 (until ’92)
ZUA29 1200 bd (V.23) System 4000 (since 1993),

AN 400 (until 1999)
LGM1200MD 600/1200 bd (V.23) SYSTEM 4000, AN 400

party line (since 1999)
LGM9600H1 1200 bd (V.23), half duplex ILS MK20A
LGM14.4 1200...19200 bd (V.32) AN 400 (up to end 1999)

LGM28.8 1200...38400 bd (V.34) AN 400 (since 1999)
Std. bus modem 1200, 2400, 4800, 9600 DME 415, 435, TAC 453
LGMa724,a(desktop) 2400 bd (V.22bis) ELTA−200
Switched line LGM14.4 up to 14.4 kbd LCU 443

LGM28.8 up to 28.8 kbd
LGM64K (ISDN) 64 kbd
5.1.2.2 Remote Control and Status Equipment RCSE 443

The RCSE is an REU with a control and indication panel (INC). It can be used as a simple, yet com-
plete, remote control unit. The INC indicates the states of up to eight substations with the following
LED displays: ALARM, WARNING, NORMAL, DATA COMmunication and MAINTENance.
An alarm tone is sounded if a status changes. Each station can be selected by pressing a membrane
button, in order to activate the EQUIPment ON, OFF and CHANGEOVER functions and to indicate
specific monitor alarms. The same status indications can also be provided by a remote status unit
(RSU) at a distant location, though it cannot be used for control functions. An additional status indica-
tion device is the control tower unit (CTU), which however, only indicates the NORMAL, WARNING
and ALARM operating states of up to eight NAV stations. Its display brightness is adjustable to permit
adaptation to the varying light conditions in the control tower. The CTU can be used in conjunction
with a runway selector (RWY−SELECT), which activates the ILS systems in one approach direction
and switches the other direction to a dummy load. This panel also indicates the general status of the
two ILS systems (OPERATIONAL, DEGRADED, SHUT DOWN) and their availability (ENABLE) to air-
craft as a landing aid.
A variety of interface boards is available for serial or parallel data I/O, installing an ETHERNET inter-
face, connecting a PC and autodialing via the public network, so that the system has a considerable
potential for expansion. The connections to the NAV stations are set up via modems and telephone
lines (600 ohms). The control and indication panels are connected by means of serial RS422 inter-
faces.
Ed. 07.04 5−3

NAVAIDS
5.1.2.3 Remote Control and Monitoring System RCMS 443
The maintenance, fault analysis and documentation functions of the RMMC are implemented by con-
necting a PC system to the RCSE and installing the RMS or RCMS application software on it. The
difference in the names is a reflection of the definitions laid down by the U.S. FAA. An RMS designed
for maintenance purposes has direct, permanent access to the navigation systems via separate cable
connections, and is operated independently of the Remote Control and Status Equipment (RCSE),
while an RCMS uses the same communication paths for the maintenance functions as it does for re-
mote control and monitoring. The following functions are provided:
− System status indication for each connected system

− Permanent indication of the general status of all systems
− Permanent indication of the current date and time
− Detailed status indications for a selected system
− Polling, display and setting of system parameters
− Polling of internal measured values (BIT)
− Continuous monitoring of parameters (either printout if a programmable limit value is reached or
periodic polling)
− 5−level password protection
− Configuration of the remote maintenance and monitoring system
− Loading and saving of setups for operation
− Logbook function, status and alarm history memories
− Selection of data to be printed out
5.1.2.4 Local Communication Unit LCU
The local communication unit (LCU) comprises a remote control electronic unit (REU), which is
equipped according to the specific requirements of the NAV station. It serves as a communication
interface between the connected equipment and the public switched network, and as a common
point for connecting a service terminal (Laptop PC) for commissioning and maintenance purposes.
NOTE: In AN 400 en−route navigation systems (e.g. CVOR 431) no separate LCU device has
to be used as local communication interface. The LCU functionality is integrated in the
NAV 400 subrack, i.e. the LCU software is running on the already existing LCP board,
additional modems are used for communication purposes.
5.1.2.5 Remote Maintenance Center RMC 443
If a maintenance center is installed, it is possible to connect several different remote control systems
to a central REU via switched lines. The general status of all the remote control systems in the network
is indicated permanently on one or more INC panels. Any change in a status causes a connection
to be set up automatically from the LCU or the RCSE to the responsible center and all the current
status information to be transmitted. The center can also be set up to poll the regional stations periodi-
cally.
The center is fully equipped to exchange such data with the networked systems which is necessary
for it to be able to perform a detailed fault diagnosis. It communicates either directly with en−route
navigation systems via switched connections or with ILS substations via the Remote Control and Sta-
tus Equipment (RCSE) at each airfield.
5−4 Ed. 07.04

NAVAIDS
TO MAINTENANCE CENTER ETHERNET (LAN)

PTT−LINE
RCMS
RCSE
ADDITIONAL
MODEM
PANELS
CTU RWY
Ê
ÊÊÊ
SELECT
REU
INC
LCU
MODEM MODEM IOM MODEM MODEM KDI IOM CU
FFM ELTA
Marker
VOR DME
DVOR TACAN
LOC GS DME
SYSTEM 2 (S 4000)
MODEM MODEM Modem MODEM MODEM LCP CSB CU
FFM ELTA
Marker
DME
CVOR TACAN
LOC GS DME DVOR
SYSTEM 1 (NAV 400)
Fig. 5−3 Example Configuration: RCMS 443 for two ILS and VOR/DME/TACAN
Ed. 07.04 5−5

NAVAIDS
5−6 Ed. 07.04

Annex Nextfield DVOR 432
Equipment Description General
Annex
DVOR Nextfield Monitoring

Introduction and Subassembly Description
Ed. 07.04 48 SB A
DVOR 432 Annex Nextfield
General Equipment Description
Table of effective pages

Basic edition: 07.04
Pages Ed.−No. Remarks
A to B 07.04
AN−1 to 16 07.04
Trademarks Microsoft and MS−DOS are registered trademarks, WINDOWS is a trademark of the Microsoft Corporation. IBM is a registered trademark of the
International Business Corporation. Pentium is a registered trademark of the Intel Corporation.
B 48 SB Ed. 07.04
Equipment Description Introduction
CHAPTER 1
DVOR NEXTFIELD MONITORING, INTRODUCTION
1.1 GENERAL
This annex describes the principal function and the subassemblies of the option "Nextfield Monito-
ring", which are different to that of the standard description part of the DVOR monitoring using the
remote nearfield dipole. The following changed or new subassemblies are essentially used for the
option Nextfield Monitoring:
− Monitor dipole (max. 4) near counterpoise edge Ref.No. 58317 24017 and 88131 72411
− Monitor Signal Processor (MSP−CD) Ref.No. 83135 22301
− Monitor Divider Switch (MDS−D) Ref.No. 83134 20501
− RF−Duplexer, 2nd coupling out (RFD1−C) Ref.No. 58341 00840
− 2nd coupling out (RFD2−SB) Ref.No. 58341 00830
The signals picked up with 1 or max. 4 monitor dipoles located at the counterpoise edge are suitable
processed, and following fed to the inputs of the multiplexer on the MSP−CD.
1.2 NEXTFIELD MONITORING PRINCIPLE

See Fig. 1−1.
A cardinal problem is to evaluate correctly a signal of a nextfield dipole which is mounted at the coun-
terpoise edge in the Monitor Signal Processor (MSP−CD): The field strength of the received 9960 Hz
sideband signal is highly different due to the large distance between the front and rear sideband an-
tennas. The RF phase delays of the radiator signals of the circular group are falsified caused by differ-
ent propagation times and therefore not equivalent to the farfield. In the nextfield, the correct fre-
quency modulation is not achieved by superposition of both sideband signals caused by the falsified
phase delays of upper and lower sideband signals on the 9960 Hz auxiliary carrier. In single sideband
operation (SSB) of the DVOR however the 30 Hz frequency modulation is clearly evaluable also in
the nextfield. Therefore the principle of nextfield monitoring is, on the one hand to convert the received
nextfield signal to a SSB−signal and thus to evaluate the 30 Hz FM, on the other hand to determine
the 9960 Hz modulation depth (9960 Hz AM) by evaluation of the upper and lower sideband signals
(USB+LSB), which are received and superimposed from the middle antenna (carrier).
Monitor dipol (typically distance 200 m) DME−antenna (optional)
Middle antenna (carrier) Nextfield dipol 2

Nextfield dipol 1
Counterpoise
circle of 48 SB antennas
Fig. 1−1 Arrangement of nearfield and nextfield monitor dipoles of the DVOR−antenna
Ed. 07.04 48 SB AN−1

Introduction Equipment Description
1.2.1 Signal Processing MSP−CD (standard processing)

See Fig. 1−2.
The monitor antenna signal is supplied via a RF−bandpass filter (108 to 118 MHz) with steep edges
to an amplifier with a processor−controlled attenuator. This controlled amplifier amplifies the RF level
up to 6 dBm. The composite DVOR signal is demodulated by the precision demodulator, whereby
the DC and AC signal components map ideally the level and modulation depth of the received monitor
antenna signal. Due to the design specification the Monitor Signal Processor (MSP) for the VOR and
the Doppler DVOR is identical and provisions are provided for the DVOR antenna monitoring. First
the processor−controlled analog switch (Multiplexer 1) selects one of the two signal sources (mea-
surement signal or test generator signal) for the following hardware processing. The monitor signal
level is normalized with the AGC presetting of the monitor processor, then demodulated and fed to
Multiplexer 1. Usually, Multiplexer 1 switches through the demodulated and normalized signal of the
monitor dipole for signal processing. The evaluation of the signal to be monitored is achieved by a
Discrete Fourier Transform (DFT) of 30 Hz harmonics, in which the individual 30 Hz signals are multi-
plexed. The evaluation in (D)VOR is based on time intervals of 64 x 1/960 s. This is the duration of
a so called monitor channel. The last 32 measurement values are evaluated after conversion from
analog to digital. The 30 Hz FM signal is detected by a FM demodulator. Controlled by the processor,
Multiplexer 2 selects and feeds through the monitor channel to be monitored for further processing.
The essential DFT evaluation cycles are:
1 Envelope of the 9960 Hz signal (for later evaluation of the 9960 Hz modulation depth)
2 Demodulated 30 Hz FM (for evaluation of the FM−deviation and later evaluation of azimuth)
3 DC−component 30 Hz AM (for evaluation of RF−level, 30 Hz AM and the azimuth (angle difference
of vectors 30 Hz FM to 30 Hz AM)
Multiplexer 3 allows the additional measurement of BIT signals such as the supply voltages of the
transmitter. The expansion of the multiplex operation of the DFT evaluation with additional monitor
channels allows to evaluate the DVOR−ASU signals in addition to the signal of the test generator.
12 bit D/A
converter
Monitor dipole
AGC
HF−bandpass
filter Precision ID−discriminator
controlled amplifier demodulator
Peak
1020 Hz filter detector Processor 80C186
4 BIT−signals
III incl.
memory/peripherals/
Measurement signal
0 150 Hz low pass control circuitry
Testgenerator Sample
filter 0 &
signal Hold
1 60 Hz
low pass 12 bit A/D−
ASU DIF 10 kHz high pass Peak I Converter
to measure USB/LSB 2 detector filter
level filter 2
ASU SSB
to measure LSB level 3 II
FM−
10 kHz filter demodulator
1
ATE5
3
Multiplexer 1 Multiplexer 2 Multiplexer 3
Monitor data to Status to/from

LRCI Co−Monitor
Fig. 1−2 Overview MSP−CD, standard processing
AN−2 48 SB Ed. 07.04

1.2.2 Signal Processing DVOR−Nextfield
See Fig. 1−3, 1−4.
The processing of the nextfield signals is performed in the Monitor Divider Switch (MDS−D), which
is an additional subassembly in relation to the standard version. The MDS−D obtains on the one hand
the signals of 2 nextfield monitor dipoles (extendable up to 4), on the other hand the signals out of
the couplers, which are inserted in the RF feeding lines for the CSB, USB and LSB signal processed
in the PMC−D of the ASU subassemblies. A divider in the forward path within each couplers supplies
a portion of the RF signal to the MDS−D. With respect to the carrier signal the return port of the CSB
coupler, which is normally terminated, is also fed to the MDS−D. The MSP−CD/1 and the MSP−CD/2
obtain the RF−input signals and 3 AF−signals from the MDS−D for evaluation. The 3 dB couplers
on the MDS−D distribute the signals used in the MSP’s in a way, that both MSP evaluate identical
signals. The multiplexer allows the selection of up to six monitor signals. Fig. 1−4 shows the signal
flow of the nextfield monitoring for one nextfield dipole.
to carrier
antenna 49
PMC−D
USB+LSB
CSB Mon.Meas.In
Norm.Out (A)
USB MSP−CD/1
LSB 9960 Hz AM
30 Hz FM−Level
30 Hz FM (ATE5)
R F R F R F
MDS−D
to MOD−SBB to MOD−SBB
Mon.Meas.In
from RFD: CSB USB LSB Norm.Out (A)
MSP−CD/2
Nextfield dipole 1 9960 Hz AM
Nextfield dipole 2 30 Hz FM−Level
Nextfield dipole 3* 30 Hz FM (ATE5)
Nextfield dipole 4*
alt. nearfield dipole * optional
Fig. 1−3 Extensions for the nextfield monitor signal, block schematic
The signal of the nextfield dipole has to be processed in a special way, before the signals 30 Hz FM
and the 9960 Hz modulation depth can be evaluated. An RF switch assembled with 3 inputs in mini-
mum is connected in series to the input of the MSP−CD in order to select the necessary RF−signals.
The levels of these RF−signals are matched by the processor controlled attenuator on the following
MSP. The 3 RF−signals are: Nearfield dipoles, USB+LSB, and CSB internal. An output line with 3 dB
coupler for the level normalized sensor signal A is added to the MSP−CD standard version. The signal
for the DFT1 evaluation (envelope of the 9960 Hz signal) is extracted from the sideband signals re-
ceived from the middle antenna :
[ USB ] + [LSB ] − [ signal of return port in the carrier line ]
Mixing this signal with the carrier frequency (limited CSB), the carrier with upper and lower sideband
is achieved. This 9960 Hz signal of mixer 1 (M1) is supplied to multiplexer 1 and evaluated well known
as standard. Attention is paid to the fact that the carrier signal has the correct RF−phase relationship
to the vector sum of the signals USB+LSB. It is adjusted with a phase shifter on the MDS−D using
a potentiometer each. Besides the sideband signal USB+LSB, also the carrier signal reflected by the
middle antenna is derived as interference signal from the directional coupler in the carrier branch. This
interference signal is in minimum 20 dB greater than the wanted signal USB+LSB. The middle an-
tenna therefore has carefully to be matched >20 dB (better 26 dB). The signals for evaluations of
DFT2a/b (30 Hz FM of USB and LSB) are derived from mixer 2 (M2).
Ed. 07.04 48 SB AN−3

These signals are mixed downwards to the frequency of 2 x 9960 Hz = 19920 Hz and supplied to
multiplexer 2 of the MSP−CD after FM−demodulation. The microprocessor determines the desired
sideband with control signal ’SB Select’. Besides the desired SB signal, the output signal of mixer 2
supplies the carrier signal level in the form of a 9960 Hz oscillation amplitude. This signal is also fed
via the envelope evaluation consisting of a 10 kHz high pass filter and a peak detector. Using the DFT
the dc−component can be measured as RF−level.
The signal for evaluation DFT 3 (30 Hz AM) is supplied as carrier forward signal in the default signal
path and using the default evaluation. The dc−component of this DFT is not further processed as
RF−level because the signal has passed through transmitter internal signal paths only. Instead of this
the radiated transmitting power is determined from the signal of the nextfield dipole. The signal for
a DFT 4 (Nearfield RF−level) is derived from the evaluation of the nextfield dipole signal using the
default evaluation process via envelope demodulation. The other DVOR specific monitor channels
are maintained unaltered. The carrier signal received from the SB−antennas is evaluated for the fail-
ure monitoring of the SB−antennas. The DFT dc−components of the detected SB−signals corre-
spond to the carrier signal level, but it is not evaluated by the processor at time. Only one of the two
sideband signals is supplied from the ASU to the MSP−CD.
Nextfield dipole 1 Channel select
MDS−D MSP−CD
Return 12 bit D/A
USB+LSB converter
from
middle antenna AGC
Delta PH
f HF−Band pass
3 dB Filter ID−Discriminator
Precision
controled amplifier demodulator
to
Co−Monitor Signal A
Memory, peripherals, control circuits

3 dB
Peak
1020 Hz Filter rider
Prozessor 80C186 inkl.

4 BIT−Signals
CSB 3 dB Limiter 30 Hz AM,ID, III
forward RF level int.
Lo 0 150 Hz low pass
RF Filter 0 Sample
9960 Hz AM 60 Hz &
3 dB M1 Tiefpass Hold
TEG−Signal 10 kHz high pass peak
to Filter I 12 bit A/D−
Filter rider 2
Co−Monitor ASU DIF Converter
ASU SSB
3 dB II
RF−level Dipole FM−
via 9960 Hz 10 kHz Filter Demodulator
USB SPDT Lo 1
RF Filter FM
LSB 20 kHz Demod. ATE5 30 Hz FM USB 3
M2 30 Hz FM LSB
3 dB 30 Hz FM
(altern. USB,LSB) Multiplexer 1 Multiplexer 2 Multiplexer 3
SB−Select
to Monitor data to LRCI
Co−Monitor
Status to/from Co−Monitor
Fig. 1−4 Nextfield signal processing and MSP−CD
1.2.3 Evaluation Channels

The following evaluations are provided for nextfield monitoring:
Calculation/Evaluation Signal Source
30 Hz AM forw. CSB-coupler
Nearfield 30 Hz FM LSB: Mixing radiated LSB incl. FM with USB−forw. Nextfield dipole
Nearfield 30 Hz FM USB: Mixing radiated USB incl. FM with LSB−forw. Nextfield dipole
10 kHz Mod. depth return CSB-coupler
Nearfield CSB RF−level Nextfield dipole
RF−Level Nearfield: from 10 kHz per mixing LSB with CSB Nextfield dipole
RF−Level Nearfield: from 10 kHz per mixing USB with CSB Nextfield dipole
AN−4 48 SB Ed. 07.04

1.2.4 Altered Channel Pattern of Evaluation (DFT)
Due to the accommodation to four nextfield dipoles a grouping is provided which consists of five
channels each (each with 64 interrupts) and therefore contains four groups. The four groups for evalu-
ation of the four dipoles are repeated every 1.33 s.
If fewer than four dipoles are specified, the existing dipole signals are more frequently evaluated corre-
spondingly. The measurement refreshing rate of the signals is therefore 1.33 s (more frequently only
for 30 Hz AM) for four dipoles. The evaluation of the 30 Hz AM occurs every second group. That means
that for example the actual azimuth is calculated every 666 ms using two nextfield dipoles only.
The 9960 Hz AM, the testgenerator signal and the signals of the ASU subassemblies are only evalu-
ated every 1.33 s. The BIT measurements are evaluated in the forward signal. The evaluation groups
are identically built in principle. The timing sequence is graded as follows:
1. Group from 0 s to 1.33 s
2. Group from 1.33 s to 2.66 s
3. Group from 2.66 s to 4.0 s
The following table shows the evaluation sequence.
Channel No. Evaluation Signal Source

Channel 1.1: Calculation of Nearfield 1 − 30 Hz FM LSB Nearfield Dipole
Channel 1.2: Calculation of Nearfield 1 − 30 Hz FM USB Nearfield Dipole
Channel 1.3: Calculation of Nearfield 1 − CSB RF−Level Nearfield Dipole
Channel 1.4: Calculation of internal 30 Hz AM Forward CSB Coupler
Channel 1.5: Calculation of Test signal 30 Hz AM and DC Test signal generator
Channel 2.3: Calculation of Nearfield 2− CSB RF−Level Nearfield Dipole
Channel 2.4: Calculation of 10 kHz Mod. depth Return CSB Coupler
Channel 2.5: Calculation of Test signal 30 Hz FM Test signal generator
Channel 3.4: Calculation of internal 30 Hz AM Forward CSB Coupler
Channel 3.5: Calculation of Test signal 9960 Hz AM Test signal generator
Channel 4.4: Calculation of DVOR ASU differential signal USB − LSB Return CSB Coupler
Channel 4.5 Calculation of DVOR ASU Lower Sideband (LSB) DVOR ASU
Fig. 1−5 Evaluation channel pattern
Ed. 07.04 48 SB AN−5

1.2.5 Evaluation and Indication of the Monitor Signals
The indication of alarms remains unchanged. This is, that the results of the monitoring for azimuth
and RF−level are linked in an OR−function for more than one nextfield dipole. The results of the evalu-
ation of 30 Hz FM for LSB and USB are not edited individually, but an addition of both 30 Hz FM vectors
is performed with the result of a sum of 30 Hz FM for the indication of the measurement value for the
30 Hz FM deviation and also for azimuth calculation.
The calculation of the 30 Hz AM is performed with the dc component of the same DFT−evaluation,
not related to the RF−level of a nextfield dipole.
The calculation of the 9960 Hz AM is performed with the 9960 Hz sidebands received from the middle
antenna which are related to the dc−component of the CSB forward signal. The measurement value
outputs are:
− Azimuth Dipole 1 (default: Azimuth)

− Azimuth Dipole 2 (new)
− RF−Level average (default: RF−Level)
Individual inputs for upper and lower limits are to be performed for the new azimuth measurement
values. The measurement values for the RF−level of the four dipoles are equal to a large extent. They
all use the same AGC−adjusting value. On this premise the RF−level have the identical alarm limits
(UL/LL).
Mixed operation with field and nextfield dipole evaluation is not provided in multiplex mode. For near-
field or nextfield evaluation a new command is available (either/or, only alternatively selectable). The
number of nextfield dipoles is selectable. In this way the four inputs of the MDS−CD can be used for
up to 4 nextfield dipoles or for 3 nextfield dipoles and 1 field dipole. The monitor, LRCI and ADRACS
software are extended with the previous mentioned parameter and commands. At time both process
max. 2 nextfield dipoles or one field dipole.
AN−6 48 SB Ed. 07.04

Equipment Description Technical Description
CHAPTER 2
TECHNICAL DESCRIPTION NEXTFIELD
2.1 GENERAL
2.1.1 System Overview
See Fig. 2−1.
The DVOR installation including Nextfield Monitoring comprises additional components and supplies
for the antenna system. The monitoring system (consisting of 1 or to monitors) is supplied with exter-
nal signals, which are obtained via 1 or optionally 2 separately mounted nearfield dipoles or/and 1
or up to 4 nextfield dipoles at the edge of the counterpoise. If the nextfield dipoles are used, the signals
are supplied via suitable cables to the connectors on top of the DVOR−transmitter rack.
approx. 200 m (typical)

DVOR−antenna system (1)
2
counterpoise edge
8 A24 8
A48 ** **
A16
A48 A49 carrier antenna A14
** A1 A13
A47 **
A2 A12 A15
** A3 A4 A10 A11
A5 A6 A7 A8 A9
**
** ** ** ** ** ** **
** ** **
** ** **
1...48 A15...A47
49 1
4
Control 2
4
* optional
** Coupling cables between antennas 1...50 and the correspondent decoupling module SB1/2 DVOR−Shelter
are optionally available; the standard version uses a matcher module without coupling cables
Carrier
Tower
5
6
7
1 Antenna system: 48 sideband antennas, 1 carrier antenna 5 DVOR−transmitter rack

2 Monitor dipole (1 or 2) 6 Battery for emergency power supply
3 ommitted 7 Remote control
4 PIN−Diode Switching Unit (PDSU) 8 Nextfield dipoles 1 and 2 (max. 4)
Fig. 2−1 DVOR 432 with nextfield dipoles, system overview
Ed. 07.04 48 SB AN−7

Technical Description Equipment Description
2.2 MECHANICAL DESIGN

2.2.1 DVOR−Transmitter Rack
See Fig. 2−2.
The RF−outputs to the PDSU/antenna and the monitor inputs for nearfield and nextfield dipoles are
located on top of the transmitter rack. The rack is additionally assembled with the subassembly
MDS−D.
2.2.2 Fitting the Hardware and Cabinet Cabling
Compared with the standard version of the DVOR 432 with nearfield dipole the three additional out-
puts of the existing directional couplers located on the RFD1−C or RFD2−SB are used. The termina-
tion of the return path of coupler Z8 (CSB) is removed, because the outout is also used for the nextfield
feature. These four outputs are passed to the MDS−D. Furthermore there are 4 RF supply lines from
the connector board on top of the cabinet to the MDS−D, and 2 RF lines each between MDS−D and
both MSP. Also there are changes in use of the MSP−CD (additional 3 dB couplers and signal connec-
tions for ATE2/3) and changes of backpanel BP−CD (2 x 4 additional connection lines).
The wall entrance in the shelter contains 3 further connections for the monitor cables, has 4 monitor
connections altogether.
AN−8 48 SB Ed. 07.04

Connector panel
Ê Í ËË Ê Ê Ê
Ê Í ËË Ê Ê Ê
Ê Í ËË Ê Ê Ê
Monitor & Control
USB
LSB
Circulators
Modem*
Modem*
Modem*
BP−C
ASU control
Ê Í ËË Ê Ê Ê
VAM*
LCP USB
RFD Components:
Ê Í Ê Ê Ê
MDS−D
PMC−D
CSB
MSP−1
MSP−2
RF−coupler Dummy loads RF−coupler

−−
DCC−3−05
CSL
RF−filter/Relays
Ê Í Ê Ê Ê
LSB
LSB
USB
Ê
Ê Í Ê
Ê Ê
Ê Ê
Ê
Ê Ê Ê Ê
cooling baffle
Ê Ê Ê Ê
Ê Ê Ê Ê
MOD−110P***
Ê Ê Transmitter 1 ÊËËËËËËËËËËËÊ
MOD−110 or
BP−T /TX1
MOD−110
MOD−110
DCC−MV
MSG−C
MSG−S
Ê Ê Ê Ê
SYN
CCP
Ê Ê Ê Ê
Ê Ê Ê Ê
Ê Ê Ê Ê
CA−100/1
Transmitter 2**
Ê Ê Ê Ê
MOD−110** or
MOD−110P***
MOD−110**
MOD−110**
DCC−MV**
Ê Ê Ê Ê
MSG−C**
MSG−S**
SYN**
CCP**
Ê Ê Ê Ê
BP−T /TX2**
Ê Ê Ê Ê
Ê
Ê Ê Ê Ê
ËËË Ê
ËË Ê Ê
PMM PMM
Ê ËËË Ê
ËËËËË Ê
ÊËËËËËËËËËËËÊ
DC/DC conv. 100 W
BP−DC
Ê Ê
ËË Ê
MOD−SBB
MOD−SBB
Ê ËËË Ê
ËË Ê Ê
DCC−28**
BSG−D
ASU control
DCC−28
Ê Ê
ËËËËË Ê Ê
ËËËËËËËËËËË CA−100/2**
Ê
Ê Ê
ËËËËË
Ê Ê
Ê Ê
Ê
Ê Ê Ê Ê
AC/DC converter
Ê Ê Ê Ê
Battery and power supply connection
ACC**
Ê Ê Ê Ê
ACC
ACC
−−
Ê
Ê Ê
Ê Ê
Ê Ê
Ê
BP−BCPS
Subracks:
Mains connection and mains filter
ËËË ÍÍ Front Rear
ËËË
NOTE:
Version 100 W
ÍÍ Nextfield option
The diagram shows the locations of the plug−in and screw−on subassemblies (printed circuit boards). The mo-
* optional ** not used in single version
dule assignment for DVOR is shown in greater detail in Fig. 2−3.
Fig. 2−2 Locations in the DVOR transmitter rack in the 50 W and up to 100 W versions
Ed. 07.04 48 SB AN−9

TYPE OF INSTALLATION: DVOR 50W, 100 W; Dual version TYPE OF INSTALLATION: DVOR 50W, 100 W; Single version
SUBRACK Subassemblies used SUBRACK Subassemblies used
View from left to right Cabinet, preassembled assign. to Cabinet, preassembled
Front door LCP LCP
Cabinet on top Connector panel Connector panel
Cabinet, rear, left, top 1x coupler; CSB 1x coupler; 1x RF−Filter CSB
RFD1−D: load, 1x relay, −
1x RF−Filter
Cabinet, rear, right, top 2x coupler, 2x circulator; SB1/SB2 2x coupler; 2x circulator; SB1/SB2
RFD2−D: 2x relay; load, 2x RF−Filter
2x RF−Filter
Monitor&Control, left CSL CSL
MSP−CD Mon1 MSP−CD Mon1
MSP−CD Mon2 − −
MDS−D Nextfield − −
PMC−D ASU PMC−D ASU
− − −
Monitor&Control, upper VAM*/** (100 W) VAM*/** (100 W)
right − −
Monitor&Control, lower DCC−3−05 LCP DCC−3−05 LCP
right Mon1 Mon1
Mon2 −
Transmitter 1 MOD−110 SB1 MOD−110 SB1
MOD−110 SB2 MOD−110 SB2
SYN−D SYN−V
MSG−S MSG−S
MSG−C MSG−C
CCP−D CCP−V
MOD−110**/110P*** CSB MOD−110**/110P*** CSB
DCC−MV TX1 DCC−MV TX1
Cabinet, rear side CA−100** TX1 CA−100** TX1
Transmitter 2 MOD−110 SB1 not assembled
MOD−110 SB2
SYN−D
MSG−S
MSG−C
CCP−D
MOD−110**/110P*** CSB
DCC−MV TX2
Power Management PMM PMM
Cabinet, rear side CA−100** TX2 not assembled −
DC/DC−Converter MOD−SBB ASU MOD−SBB ASU
MOD−SBB ASU MOD−SBB ASU
BSG−D ASU BSG−D ASU
DCC−28** TX2 − −
DCC−28** TX1 DCC−28** TX1
AC/DC−Converter − −
ACC −
ACC ACC
ACC ACC
Cabinet rear, bottom Battery and power supply Battery and power supply
connection, mains filter connection, mains filter
* optional ** 100 W version only *** 50 W version only 1) Nextfield option
Fig. 2−3 Assignment and scheme of subassemblies for DVOR
AN−10 48 SB Ed. 07.04

2.3 DESCRIPTION OF SUBASSEMBLIES
2.3.1 Overview Subassemblies Nextfield Monitoring
See Fig. 2−4, 2−5.
The following subassemblies are used or new for DVOR nextfield monitoring with regard to the stan-
dard version. Fig. 2−5 shows the addition with MDS−D and the nextfield dipoles.
SUBASSEMBLY ASSIGNMENT CODE NUMBER*) REFERENCE

Transmitter
RF−Duplexer 1 (RFD1−C) 58341 00840 2.3.2.1
RF−Duplexer 1 (RFD2−SB) 58341 00830
Monitor:
Monitor Signal Processor (MSP−CD) 83135 22301 2.3.3.1
Monitor Divider Switch DVOR (MDS−D) 83135 20500 2.3.3.2
*) The code numbers given may differ to those of the delivered installation in individual cases. In such case the actual code
number can be taken from the delivery list of the installation or the drawing set.
Fig. 2−4 Subassemblies for nextfield monitoring
from Transmitter 2 Nextfield monitor 1...4 or
1...3 and field dipole ASU subassemblies PDSU
CSB
SB2
SB1
Carrier antenna 49
Transmitter 2 RF duplexer CSB
to sideband antennas A1 to 48; centre antenna 49

components
Monitor 1 inside cabinet rear
CSB SB1S
CSB RFD1−C USB sin
MOD−SBB DPDT
SB1 SB1 Circ. cos
SB2S
RFD2−SB LSB sin

SB1C
SB2 SB2 Circ.
MOD−SBB DPDT
cos
SB2C
Phase values
Control
30HZO 30HZE
USB+LSB CSB USB LSB
MDS−D
Control/BIT
Monitor Divider Switch TX1 PMC−D BSG−D
ASU interface t/f ASU int.
Control line
Signal source selection

AF signal processing TX2 30HZ sync.
+5V
Monitor channel
Monitor channel
+15V
Norm. Signal A
DCC05/15
Norm. Signal A
Antenna switch
control and 30HZ sync. −15V control
DC 48 V On/Off from CSL

0...5
0...5
BIT
signals BIT signals
MSP−CD MSP−CD
Monitor Signal Processor Monitor Signal Processor
CSL
(TEG)
V.24 / RS232 V.24 / RS232 Transmitter 2 and Monitor 2
Fig. 2−5 DVOR, nextfield supplement (excerpt from part 1, Fig. 1−30)
Ed. 07.04 48 SB AN−11

2.3.2 Transmitter Subassemblies

2.3.2.1 RF−Duplexer (RFD1−D, RFD2−D)
See Fig. 2−6.
The RF signals of TX1 or TX2 are distributed to the components of the ASU by means of the discrete
RF−Duplexers RFD1−C (CSB) and RFD2−SB (SB1/2), with following components:
− 3 coaxial antenna switching relays
− 3 harmonic filters Z7, Z1, Z2 (low−pass)
− Dummy load resistors and attenuators (2x)
In addition, there are RF−components in the following RF−signal path located on the RF−Duplexer
mounting plate. Its operation belongs to the phase monitoring function of the antenna switching con-
trol. These components are:
− 3 couplers (Z8, Z3, Z4)
− 2 circulators (Z6, Z5)
The function of the various components of the RF−Duplexer is to switch the antenna system over to
transmitter 1 or 2. The signals of the transmitter which is currently switched to the antenna by the coax-
ial antenna switching relays K1 (CSB) and K1/K2 (SB1, SB2) each pass through a harmonic filter, be-
fore being fed to the RF−components, the antenna switching control and RF−supply (MOD−SBB)
of the ASU−function. Any harmonics in the signals are filtered out by filters for CSB and SB1, SB2.
The transmitter which is active, but not switched to the antenna, is connected to a dummy load. The
changeover signals received from the monitor signal processor (MSP−CD) control the relays K1
(CSB) and K1/K2 (SB1, SB2). The relay position is fed back to the MSP−CD via the CSL. For the next-
field option Z8, Z3, Z4 are used to couple out signal components of CSB, USB, LSB to the MDS−D.
The location of the RF−Duplexer and ASU RF−components is shown in Fig. 2−2.
to outdoor PIN−Diode Switching Unit (PDSU)
TX−cabinet EVLO EVHI ODLO ODHI
MOD−SBB MOD−SBB
20 dB
26 dB 20 dB Z4
Z8 Z3
1 1
Circulator Circulator
PMC−D USB 2 LSB 2
Z6 3 Z5 3
TX1 Control TX2
CSB RFD1−C SB1 RFD2−SB SB2
Harmonic filter Harmonic filter Harmonic filter
CSB via MDS−D USB LSB
Z7 to MSP−CD Z1 Z2
50 Ohm/100 W/30 dB
50 Ohm/100 W/30 dB
50 Ohm/100 W
Antenna Antenna Antenna

changeover from MSP−CD changeover changeover
relay via CSL relay relay
K1 K1 K2
CSB/TX1 CSB/TX2 relay position SB1/TX1 SB1/TX2 SB2/TX1 SB2/TX2
Side wall, left, rear view changeover signals Side wall, right, rear view
Fig. 2−6 RF−Duplexer (RFD1−D, RFD2−D), block diagram
AN−12 48 SB Ed. 07.04

2.3.3 Monitor Subassemblies
2.3.3.1 Monitor Signal Processor MSP−CD
See Fig. 2−7.
The MSP−CD is used both for standard DVOR and DVOR with option nextfield monitoring. For DVOR
with nextfield monitoring, the monitor signals of the nextfield dipoles are evaluated in an other way
than in the standard version. The selection of measurement signals is performed via the signal source
switch MDS−D. The MSP−CD supplies the normalized RF−signal (norm. Signal A) to the MDS−D.
The signal is coupled out in an additional 3 dB coupler following amplifier N13,14 before the detector
and fed to the MDS−D. MUX 1 and 2 obtain additional measurement signals for evaluation, which
are processed on the MDS−D. The other circuitry conform to that of the standard.
The evaluation of the identity (ID) is not performed for nextfield monitoring via path N18,21,22, be-
cause the composite signal allows no clear recognition in the standard form due to the processing
on the MDS−D. The presence of identity is checked for the next field monitoring version via the BIT
signal of the transmitter.
The location of the two MSP−CD (transmitter 1 and 2) is shown in Fig. 2−2.
UREF_10V 0
AGC coupler
0/16 dB 3 dB
N4 N1 Reserve
A A (used for ILS)
RF−MON V26,27 OUT
108...118
MHz 0...16 dB N13,14 N15,16 D D 16 Bit
Register SH P
N2,8,9 N10...12 CS−GA CLK EE
to MDS−D EN SER EE
norm Signal A DAT IN EE
0
Analog ID discrim. CS−ATT
TEG ATE1 1 CS
ME10KHZ 2 MUX 1 D24,25
ASU MO10KHZ 3 OUT 1020 Hz 10 Hz N22
RF−Level 4 N21
MDS
to MSP−VD/x
9960 Hz AM FAUREC2
5 N18 N22 0 MAINAL1
6,7 N6 SEL Morse−indicator TEGAL1*
DC−keyed, conform to OUT FIRAL1
Morse code 16 Bit SECAL1*
ATIS Register NFIAL1*
Output DC+30 Hz AM TESTAL1*
voice X12 MON_EXIXST1
TX1 ON
600 Ohm N7 30 Hz TX1 OFF
3.5 mm jack bush TP10
to CSL
TX2 ON
for 30 Hz FM TX2 OFF
DC Offset+30 Hz FM measurements only TX1 AERIAL
TX2 AERIAL
CS POWER OFF
D17,18
POWER ON
from MSP−VD/x
2 MAINAL2
Limiter 9960 Hz 30 Hz FM X28 5 kHz 0 TEGAL2*
FIRAL2
V46 N19,20 V17..21,N23 N26 SECAL2*
3 NFIAL2*
from MDS−D TESTAL2*
30 Hz FM USB/LSB IN !MOFAU2
0 SEL 16 Bit !MOFAU1
DC + Interference 1 OUT Register RFR1/1
Analog RFR1/2
from CSL
2 MUX 2 16 Bit RFR2/1

9960 Hz AM−Dem. 3 Register RFR2/2
4 OUT MUX/ RFR3/1
N25 RFR3/2
N17,V24,25 unbenutzt 5..7 attenuat. CS
N24 control D20,21 RFR4/1
RFR4/2
D28,29 CS
AF−signal 60 Hz 2
D/A control
5VT1 0 Decoder Watch dog trig.
15Vt1
SEL zu D14
−1
4 D23 Interfer. control
15VNT1
28VT11 6
28VT21
BIT−Signals 5VM1 4 STS AD
0
from SYN1/2
5VT2 3 Morse Code

DC−converter 15VT2 OUT
−1 BLPLL0/1
15VNT2 BLPLL1/1
28VT12 12 Bit BLPLL2/1
28VT22 Analog A BLPLL0/2
5VM2 MUX 3 S&H IN BLPLL1/2
ABAT BLPLL2/2
N29 D 16 Bit
UREF_10V N28 Register BTX1/T1
BTX2/T1
from CSL
N30 BTX3/T1
BTX1/T2
4
960 Hz
BTX2/T2
* not used for DVOR
Fig. 2−7 Monitor Signal Processor (MSP−CD), excerpt from block diagram
Ed. 07.04 48 SB AN−13

2.3.3.2 Monitor Divider Switch DVOR (MDS−D)

See Fig. 2−8.
The MDS−D processes the nextfield signal of the nextfield dipoles in a way that it can be evaluated
for the monitoring process. The following signals are supplied to the MDS−D, which are needed for
monitoring:
− external : RF−signal from nextfield dipole 1...3+4 (the 4. input is also used for the field dipole)
− internal : CSB−forward, CSB−return (USB+LSB), USB (SB1), LSB (SB2)
The signals are derived from the 1 to 4 nextfield monitoring dipoles and from bidirectional couplers,
which are inserted in the supply lines to the ASU subassemblies. Each input signal passes a 3 dB
coupler (N55...N65), is attenuated and put to an integrated RF−switch. The attenuators adapt the
RF−level and reduce possible reactive effects of the following switches. Each signal passes an On/
Off−switch (N32...N39, 46...51) with an attenuation band >70 dB, before it is selected by the following
channel switches. Each MSP controls independent from another its signal path via a decoder (D1,2),
to call the signals for evaluation over the channel select switches. The decoder selects one of up to
8 individual monitor signals and connect this signal path to the MSP−CD/1 and MSP−CD/2. Because
of the series connected channel switches on the MDS−D the required RF−signals (dipole 1...4, CSB,
USB+LSB) can be normalized in level by the RF−attenuator of the MSP. The normalized RF−signal
(M1_RF, M2_RF) is led from the MSP via coupler N64, N66 back to the MDS−D and used for signal
processing.
Following the evaluation path each for nextfield dipole 1 and MSP−CD/1 are described in short form.
With regard to MSP−CD/2 the path behind the input couplers proceed accordingly (see Fig. 2−8).
− Calculation 30 Hz AM
The CSB−signal (forward) passes via N55, N56, N32, N29 to switch N27. From here it is fed via
Z1 for evaluation to the RF−input of the MSP−D. After demodulation it is led to multiplexer 1.
− Calculation nextfield 30 Hz LSB
The signal of the nextfield dipole (1) passes via N61, N37, N31, N28 to switch N27. From here it
is fed via the phase shifter with Z1 for evaluation to the RF−input of the MSP−CD and returns as
signal M1_RF to N64 before demodulation. From here it is fed in one branch to mixer U2, where
it is mixed with the LSB−signal. The LSB−signal is supplied via N62, N38, N40. The output signal
of U2 passes via N69,70 to switch N13, and from here via bandpass filter N72,71 to the FM detector,
consisting of V34,35, V43, N3. Reference voltages derived from N25 are supplied to the detector
with N1,2. The output voltage of N3 is adjusted with Uref (M1_UREF_10VN) from N1 such, that the
result is a range of 3,58...4,59 V, which is interpreted for processing in the MSP−D. From output
of amplifier/adder N3/1 the LSB−signal (MDSD_30_HZ_FM_M1) is supplied to multiplexer 2 on
the MSP−CD.
− Calculation nextfield 30 Hz USB
is fed via the phase shifter with Z1 for evaluation to the RF−input of the MSP−CD and returns as
signal M1_RF to N64 before demodulation. From here it is fed in one branch to mixer U2, where
it is mixed with the USB−signal. The USB−signal is supplied via N63, N39, N40. The output signal
of U2 passes via N69,70 to switch N13, and from here via bandpass filter N72,71 to the FM detector,
consisting of V34,35, V43, N3. Reference voltages derived from N25 are supplied to the detector
with N1,2. The output voltage of N3 is adjusted with Uref (M1_UREF_10VN) from N1 such, that the
result is a range of 3,58...4,59 V, which is interpreted for processing in the MSP−D. From output
of amplifier/adder N3/1 the USB−signal (MDSD_30_HZ_FM_M1) is supplied to multiplexer 2 on
the MSP−CD.
AN−14 48 SB Ed. 07.04

channel select
3 dB
NF−Dipol1 N37
N61 Decoder
N8 N10 Control
3 dB −U D1 from
−U MSP−CD/1
NF−Dipol2 N36
N60 N31
3 dB
N28
NF−Dipol3 N35
N59 N30
3 dB
N34 N12
NF−Dipol4 −U
N58
channel select
3 dB
N51 Decoder
N16 control
−U D2 from
N19
3 dB −U MSP−CD/2
N45
N50
N42
3 dB
N44
N49
M2RF from
U5
MSP−CD/2 3 dB
RF IF MDSD_9960_HZ_AM_M2
N77,78
4 dB N66
Lo
N48 N18
−U MDSD_9960_HZ_RF_M2
U6
M1RF from RF IF
N75,76
MSP−CD/1 Lo
4 dB N64 U3
control
RF IF N67,68 MDSD_9960_HZ_AM_M1
Limiter Lo
M1CSB U1
U2 MDSD_9960_HZ_RF_M1
N56 channel select RF IF N69,70
Lo
16 dB
6 dB Control
UPHM1 Uref
CSB N32 +15V
N55 Limiter N25
forward
U4
N11 N9 f Uref. 10V
M2CSB 14 dB −U V100,101
−U R409
N65 N33
N29 to
10 dB MSP−cd/1
Z1 RF−MON1
USB_LSB N27
N38 19,92 kHz
CSB N57 BPINM1M2 N1,2 Uref 10V
return 10 dB N72
BPISELM1
19,92 kHz FM detector
6 dB V34,35
N14 N40 N71 V43,44 N3
N39 −U N13 BP2SELM1
LSB N62
forward MDSD_30_HZ_FM_M1
channel select
6 dB
16dB
USB N63 UPHM2 Uref
+15V
forward N26
N46
N17 N15 f
14 dB Uref. 10V
−U V102,103
−U R414
N47 to
N43 MSP−CD/2
10 dB RF−MON2
Z2
N41
19,92 kHz
N54 BPINM1M2 N4,5 Uref 10V
N73
BPISELM2
10 dB 19,92 kHz FM detector
V39,40
BP2SELM2
N74 V45,46 N6
N52 N20
Signal path for MSP−D/2 N53 MDSD_30_HZ_FM_M2
Fig. 2−8 Monitor Divider Switch (MDS−D), block diagram
Ed. 07.04 48 SB AN−15

− Calculation 10 kHz AM
The signal USB+LSB (from middle antenna) passes via N57, N33, N29 to switch N27. From here
it is fed via the phase shifter (V100,101) with Z1 for evaluation to the RF−input of the MSP−CD
and returns as signal M1_RF to N64 before demodulation. From here it is fed in one branch to mixer
U3, where it is mixed with the CSB−signal. The CSB−signal is supplied via N55, N56 and limiter
U1 to U3. The output signal of U3 is supplied as signal MDSD_9960_HZ_AM_M1 via N67,68 to mul-
tiplexer 1 on the MSP−CD.
− Calculation nextfield carrier RF−level
is fed via Z1 for evaluation to the RF−input of the MSP−CD and supplied after demodulation to
multiplexer 1.
− Calculation USB nextfield RF−level from 10 kHz with mixing LSB
is fed via Z1 for evaluation to the RF−input of the MSP−CD and returns as signal M1_RF to N64
before demodulation. From here it is fed in one branch to mixer U2, where it is mixed with the LSB−
signal. The LSB−signal is supplied via N62, N38, N40. The output signal of U2 is supplied via
N69,70 as signal MDSD_9960_HZ_RF_M1 to multiplexer 1 on the MSP−CD.
− Calculation LSB nextfield RF−level from 10 kHz with mixing USB
is fed via Z1 for evaluation to the RF−input of the MSP−CD and returns as signal M1_RF to N64
before demodulation. From here it is fed in one branch to mixer U2, where it is mixed with the USB−
signal. The USB−signal is supplied via N63, N39, N40. The output signal of U2 is supplied via
N69,70 as signal MDSD_9960_HZ_RF_M1 to multiplexer 1 on the MSP−CD.
The phase of signals RF−MON1, RF−MON2 is adjusted non−recurrently with R409 and R414 during
first alignment.
The location of the MDS−D is shown in Fig. 2−2.
AN−16 48 SB Ed. 07.04

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Reference No.

VHF Omnidirectional Radio Range

As for details, the electrical and mechanical information given in the

All rights reserved

The equipment documentation comprises:

Part Technical Manuals Code No.

Volume Drawing Set Code No.

PART CONTENTS CODE NO.

Cautions call attention to methods Warnings call attention to methods,

NOTE or REMARK : For more information about operations.

Table of effective pages

Pages Ed.−No. Remarks

Annex 07.04 DVOR Nextfield (optional)

CHAPTER 1 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1

1.4.2 Handling Subassemblies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−15

1.9.2 Startup Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−45

CHAPTER 2 TECHNICAL DESCRIPTION DVOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1

Ed. 07.04 48 SB III

2.3.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−15

2.4.3.2 Sideband Antenna Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−64

CHAPTER 3 TECHNICAL DESCRIPTION ANTENNA SYSTEM . . . . . . . . . . . . . . . . . . . . . . . 3−1

CHAPTER 4 EMERGENCY POWER SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−1

CHAPTER 5 REMOTE MAINTENANCE AND MONITORING CONFIGURATION (RMMC) . 5−1

Ed. 07.04 48 SB VII

VIII 48 SB Ed. 07.04

Ed. 07.04 AV−1

AV−2 Ed. 07.04

Ed. 07.04 AV−3

AV−4 Ed. 07.04

Ed. 07.04 AV−5

FAA Federal Aviation Administration

AV−6 Ed. 07.04

Ed. 07.04 AV−7

AV−8 Ed. 07.04

Ed. 07.04 AV−9

AV−10 Ed. 07.04

Ed. 07.04 AV−11

AV−12 Ed. 07.04

Ed. 07.04 AV−13

AV−14 Ed. 07.04

Ed. 07.04 AV−15

AV−16 Ed. 07.04

Fig. 1−1 Enroute navigation with DVOR, principle

Ed. 07.04 48 SB 1−1

− Available as single or dual equipment with power up to 50 W or 100 W

1−2 48 SB Ed. 07.04

Ed. 07.04 48 SB 1−3

1.2.2.2 DVOR Method

Fig. 1−3 Azimuth as a function of the phase angle

1−4 48 SB Ed. 07.04

B1 and B2 are reception

Fig. 1−4 Generation of the direction−dependent FM

Ed. 07.04 48 SB 1−5

Fig. 1−6 (D)VOR signal amplitude modulated with 30 Hz and 9960 Hz

1.2.2.2.2 Electronic Simulation of the Antenna Movement

1−6 48 SB Ed. 07.04

Fig. 1−7 Switching of the sideband antennas in the DVOR

Ed. 07.04 48 SB 1−7

1−8 48 SB Ed. 07.04

1.3.2 Power Supply

1.3.3 Environmental Conditions

1.3.4 System Data

Ed. 07.04 48 SB 1−9