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Set 3
1
What Is An Assembler?
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Data Representation
Binary 0-1 Word - 16 Bits
represents the state of Each architecture may
electronic components define its own “wordsize”
used in computer systems Doubleword - 32 Bits
Bit - Binary digit Quadword - 64 Bits
Byte (octet) - 8 Bits Nybble (nibble) - 4 Bits
smallest addressable
memory location (on the
IBM-PC)
Numbering Systems
Binary - Base 2 Raw Binary format
0, 1 All information is coded
Octal - Base 8 for internal storage
0, 1, 2, … 7 Externally, we may
choose to express the
Decimal - Base 10 information in any
0, 1, 2, …, 9 numeration system, or in a
Hexadecimal (Hex) decoded form using other
symbols
0, 1, …, 9, A, B, …, F
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Decoding a Byte
Raw Machine Instruction
Push AX (store value of AX in stack)
01010000b
Hex ASCII Character code
‘P’ or “P”
50h
Octal Integer
80 (eighty)
1208
Decimal BCD (binary-coded decimal)
50 (fifty)
80d
Custom code ???
Message encrypting
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IBM-PC Instruction Example
1011000000000101b or B005h
OpCode = 10110000b
Copies a byte into AL (a register)
The byte is found in the second half of the instruction:
00000101b
The Operation Code (opcode) identifies the type of
instruction and provides some information about the
instruction length
Opcode specifies the exact operation to be executed
Operand is a value on which the instruction operates
Exp: MOV DS, AX
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Assembly Language Instructions
Mnemonics represent Machine Instructions (opcode)
Each mnemonic used represents a single machine instruction
Mnemonics may differ between different processor designs
The assembler performs the translation
Some mnemonics require operands
Operands provide additional information
z register, constant, address, or variable
Assembler Directives
Allows to take special programming actions during assembly
process
Directive names begin with a period (.) to distinguish from
machine instruction opcodes
Program Statements
name operation operand(s) comment
Operation is a predefined or reserved word
mnemonic - symbolic operation code
directive - pseudo-operation code
Space or tab separates initial fields
Comments begin with semicolon (;)
Most assemblers are not case sensitive
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Program Data and Storage
Pseudo-ops to define These directives require
data or reserve storage one or more operands
DB - byte(s) define memory contents
DW - word(s) specify amount of storage
DD - doubleword(s) to reserve for run-time
DQ - quadword(s) data
DT - tenbyte(s)
Defining Data
Numeric data values A list of values may be
100 - decimal used - the following
100B - binary creates 4 consecutive
100H - hexadecimal words
'100' - ASCII DW 40CH,10B,-13,0
"100" - ASCII A ? represents an
Use the appropriate uninitialized storage
DEFINE directive (byte, location
word, etc.) DB 255,?,-128,'X'
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Naming Storage Locations
Names can be associated ANum refers to a byte
with storage locations storage location,
ANum DB -4 initialized to FCh
DW 17 The next word has no
ONE
associated name
UNO DW 1
X DD ? ONE and UNO refer to
These names are called the same word
variables X is an unitialized
doubleword
Arrays
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DUP
Word Storage
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Named Constants
Symbolic name associated with storage location
represent an address
Named constant is a meaningful name that takes the
place of a number, string or other expression
It is similar to a variable, but cannot be modified
name = expression
expression must be numeric
these symbols may be redefined during assembly time
maxint = 7FFFh
count = 1
DW count
count = count * 2
DW count
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EQU Directive
program
sample EQU 7Fh
aString EQU <1.234>
message EQU <This is a message>
Addressing Modes
Addressing Register-file Memory
Operand field
mode contents contents
Immediate Data
Data
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8086 Programming Model
General Purpose Registers Segment Registers
Accumulator AX AH AL Code Segment CS
Base BX BH BL Data Segment DS
Count CX CH CL Extra Segment ES
Data DX DH DL Stack Segment SS
Pointer Registers Flag Register
Stack Pointer SP Status and
Control Flags FlagsH FlagsL
Base Pointer BP
Index Registers Instruction Register
Source Index SI Instruction IP
Destination Index DI Pointer
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Instruction rules
Source operand can be memory, register or constant
Destination can be memory or non-segment register
Only one of source and destination can be memory
Source and destination must be same size
Segment register:
A register that points to the base of the current segment being addressed
Non-segment register:
- Pointer register, general purpose register, IP, Flag register, etc.
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Addresses with Displacements
b db 4Fh, 20h, 3Ch The assembler
w dw 2048, -100, 0 computes an address
based on the
mov bx, w+2 expression
mov b+1, ah NOTE: These are
mov ah, b+5 address computations
mov dx, w-3 done at assembly time
MOV ax, b-1
Type checking is still in will not subtract 1 from
effect the value stored at b
Exchange instruction
XCHG target, source This provides an efficient
reg, reg means to swap the
reg, mem operands
mem, reg No temporary storage is
needed
MOV and XCHG cannot
perform memory to Sorting often requires this
type of operation
memory moves
This works only with the
general registers
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Arithmetic Instructions
ADD dest, source source can be a general
SUB dest, source register, memory
INC dest location, or constant
DEC dest dest can be a register or
memory location
NEG dest
except operands cannot
Operands must be of the both be memory
same size
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Memory Models
.model memory_model
tiny: code+data <= 64K (.com program)
small: code<=64K, data<=64K, one of each
medium: data<=64K, one data segment
compact: code<=64K, one code segment
large: multiple code and data segments
huge: allows individual arrays to exceed 64K
flat: no segments, 32-bit addresses, protected mode
only (80386 and higher)
Program Skeleton
.model small Select a memory model
.stack 100H Define the stack size
.data Declare variables
;declarations Write code
.code organize into procedures
main proc Mark the end of the source
;code file
optionally, define the entry
main endp point
;other procs
end main
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Micro-controller Assembly
Language
Microprocessor:
Requires ‘external’ support hardware
E.g., External RAM, ROM, Peripherals
Microcontroller:
Very little external support hardware.
Most RAM, ROM and peripherals on chip.
“Computer on a chip”, or “System on chip” (SOC)
E.g., PIC = Peripheral Interface Controller
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Harvard Architecture
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PIC Architecture: Background
Memory Memory
(Data) 8
CPU 12
(Program)
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16
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PIC Architecture: Background
PICs and most Harvard chips are “RISC”
Reduced Instruction Set Computer (RISC)
Used in: SPARC, ALPHA, Atmel AVR, etc.
Few instructions (usually < 50)
Only a few addressing modes
Executes 1 instruction in 1 internal clock cycle (Tcyc)
Example:
1 word, 1 cycle
Example PIC: 12C508 Block Diagram
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The PIC Family: Program Memory
PIC program space is different for each chip.
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The PIC Family: Program Memory
PICs have two different types of program
storage:
2. FLASH
Re-writable (even by chip itself)
Much faster to develop on!
Finite number of writes (~100k Writes)
PIC Examples: Any ‘F’ part: 16F84, 16F87x, 18Fxxx
(future)
NOTE: programs are stored in program space (not in data space), so low RAM values are OK.
22
The PIC Family: Control Registers
PICs use a series of “special function registers”
for controlling peripherals and PIC behaviors.
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PIC Peripherals: Ports (Digital I/O)
All PICs have digital I/O pins, called ‘Ports’
the 8pin 12C508 has 1 Port with 4 digital I/O pins
the 68pin 17C766 has 9 Ports with 66 digital I/O pins
Ports have 2 control registers
TRISx sets whether each pin is an input or output
PORTx sets their output bit levels
Most pins have 25mA source/sink (directly drives LEDs)
WARNING: Other peripherals SHARE pins!
Software: Introduction
In this course, we’ll only talk about PIC assembly language as
used in the MPLAB assembler.
MPLAB is FREE (score): see http://www.microchip.com/
compact.
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Software: Programmers Model
Hardware Stack
<- 12/14/16 bits -> Stores addresses for
subroutines
Program Memory
(PCH) Program Counter-PCL
“Burned” in by
programmer (can’t <- 8 bits ->
change during Status
execution). Stored
instructions, Special Purpose
addresses and Registers
“literals” (numbers)
I/O pin states,
peripheral
W “Register” registers, etc.
General Purpose
Registers
RAM or “data
memory”. Variables
are stored here
Move (“mov”) the number (“l” for “literal”) 0xFF - that’s 256
in decimal- into the working register (“w”).
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Software: Programmers Model
Hardware Stack
<- 12/14/16 ->
Program Memory
(PCH) Program Counter-PCL
<- 8 bits ->
Status
Special Purpose
Registers
0xFF
W “Register”
General Purpose
Registers
Move (“mov”) the working register (“w”) into the file register
(“f”) named PORTA.
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Software: Programmers Model
Hardware Stack
<- 12/14/16 ->
Program Memory
(PCH) Program Counter-PCL
Special Purpose
Registers
Value in W PORTA
W “Register”
General Purpose
Registers
Move (“mov”) the the value of the file register (“f”) named
PORTA into the working register (“w”) .
27
Software: Programmers Model
Hardware Stack
<- 12/14/16 ->
Program Memory
(PCH) Program Counter-PCL
Special Purpose
Registers
Value in PORTA PORTA
W “Register”
General Purpose
Registers
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Software: Branches
All branches are “Bit Tests”
All branches only skip one instruction
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Software: Direct Addressing
All file registers (RAM) are accessed by an address. This is
called direct addressing.
For example,
movlw 0xFF
movwf 0x06
loads W with FF, and then loads W into GPIO (address 0x06).
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Software: Relative Addressing
Example of Relative Addressing (using a table):
; Here’s a simple lookup table which is called as a
; subroutine. Expects the tbl offset to be loaded in W.
; An example call looks like this:
; movlw 0x04 ; Load W with 4
; call Table ; Call the table subroutine
; movwf Result ; Store result from the table
31
Software: Banking
RAM in the PICs is banked, especially
special function registers. Use the bank
select commands to choose the bank.
Either:
bsf STATUS, RP0
bcf STATUS, RPO
Assembler Design
32
How Assembler Works
The essential task of an assembler is to convert
symbolic text into binary values that are loaded into
successive bytes of memory
There are two major components of this task
Allocating and initializing data storage
Resolving addresses
Memory Allocation
Memory allocation is handled by assembler directives:
.data
X: - word 42
msg: - ascii “Hello, world”
- align 2
array: - space 40
foo: - word 0xdcadbccf
When the assembler encounters label declarations while scanning a source
file, it creates a SYMBOL table entry to keep track of its location:
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Encoding Mnemonic
34
Resolving Addresses: Pass 2
35
Macros and Macro Processors
A unit of specification for program generation through expansion
Purpose: increase program efficiency
Some language support in-built macro writing facilities
C, C++, Ada
If macro facility is not in-built
Equivalent effect achieved by software tools like Awk in UNIX
Macro expansion: the use of a macro name with a set of actual
parameters is replaced by some code generated from its body
Lexical expansion: replacement of a character string by another character
string during program generation
Semantic expansion: generation of instructions tailored to the
requirements of a specific usage
Macro vs. sub-routine:
Macro: Macro name in the mnemonic field leads to expansion
Subroutine name call leads to its execution
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Macro call
INCR A, B, AREG
Formal parameter value
mem_val A
incr_val B
REG AREG
Lexical expansion of the model statements
+ MOVER AREG, A
+ ADD AREG, B
+ MOVEM AREG, A
Default specification of parameters
In the absence of explicit specification by the programmer
incr_d incr_val=B, mem_val=A ; default REG will be used
for the increment oprtaion
incr_d mem_val=B,mem_val=A,reg=BREG ; BREG will be used
MACRO
compute &first, &second ; X, Y
movem BREG, TMP
incr_d &first, &second reg=BREG ; inner macro
mover BREG, TMP
MEND
Lexical expansion of the model statements
+ MOVEM BREG, TMP + MOVER BREG,X
COMPUTE X,Y + INCR_D X, Y + ADD BREG,Y
+ MOVER BREG, TMP + MOVEM BREG,X
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