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Assembly Language

Programming & Assembler

Set 3

What Is Assembly Language


Š Machine-Specific Programming Language
„ one-one correspondence between statements and
native machine language
„ matches machine instruction set and architecture
Š IBM-PC Assembly Language
„ refers to 8086, 8088, 80186, 80286, 80386, 80486,
and Pentium Processors

1
What Is An Assembler?

Š Systems Level Program


„ translates assembly language source code to
machine language
z object file - contains machine instructions (called
binaries), initial data, and information used when loading
the program
z listing file - contains a record of the translation process,
line numbers, addresses, generated code and data, and a
symbol table

Why Learn Assembly Language?


Š Learn how a processor Š Allows creation of small
works and efficient programs
Š Understand basic Š Allows programmers to
computer architecture bypass high-level
Š Explore the internal language restrictions
representation of data Š Might be necessary to
and instructions accomplish certain
Š Gain insight into operations
hardware concepts

2
Data Representation
Š Binary 0-1 Š Word - 16 Bits
„ represents the state of „ Each architecture may
electronic components define its own “wordsize”
used in computer systems Š Doubleword - 32 Bits
Š Bit - Binary digit Š Quadword - 64 Bits
Š Byte (octet) - 8 Bits Š Nybble (nibble) - 4 Bits
„ smallest addressable
memory location (on the
IBM-PC)

Numbering Systems
Š Binary - Base 2 Š Raw Binary format
„ 0, 1 „ All information is coded
Š Octal - Base 8 for internal storage
„ 0, 1, 2, … 7 „ Externally, we may
choose to express the
Š Decimal - Base 10 information in any
„ 0, 1, 2, …, 9 numeration system, or in a
Š Hexadecimal (Hex) decoded form using other
symbols
„ 0, 1, …, 9, A, B, …, F

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Decoding a Byte
Š Raw Š Machine Instruction
„ Push AX (store value of AX in stack)
„ 01010000b
Š Hex Š ASCII Character code
„ ‘P’ or “P”
„ 50h
Š Octal Š Integer
„ 80 (eighty)
„ 1208
Š Decimal Š BCD (binary-coded decimal)
„ 50 (fifty)
„ 80d
Š Custom code ???
„ Message encrypting

Machine Language (Code)

Š A language of numbers, called the Processor’s


Instruction Set
„ The set of basic operations a CPU can perform
Š Each instruction is coded as a number
Š Instructions may be one or more bytes
Š Every number corresponds to an instruction

4
IBM-PC Instruction Example
Š 1011000000000101b or B005h
Š OpCode = 10110000b
„ Copies a byte into AL (a register)
„ The byte is found in the second half of the instruction:
00000101b
Š The Operation Code (opcode) identifies the type of
instruction and provides some information about the
instruction length
Š Opcode specifies the exact operation to be executed
Š Operand is a value on which the instruction operates
„ Exp: MOV DS, AX

Assembly Language vs Machine Language


Programming
Š Machine Language Programming
„ Writing a list of numbers representing the bytes of
machine instructions to be executed and data
constants to be used by the program
Š Assembly Language Programming
„ Using symbolic instructions to represent the raw data
that will form the machine language program and
initial data constants

5
Assembly Language Instructions
Š Mnemonics represent Machine Instructions (opcode)
„ Each mnemonic used represents a single machine instruction
„ Mnemonics may differ between different processor designs
„ The assembler performs the translation
Š Some mnemonics require operands
„ Operands provide additional information
z register, constant, address, or variable

Š Assembler Directives
„ Allows to take special programming actions during assembly
process
„ Directive names begin with a period (.) to distinguish from
machine instruction opcodes

Program Statements
name operation operand(s) comment
Š Operation is a predefined or reserved word
„ mnemonic - symbolic operation code
„ directive - pseudo-operation code
Š Space or tab separates initial fields
Š Comments begin with semicolon (;)
Š Most assemblers are not case sensitive

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Program Data and Storage
Š Pseudo-ops to define Š These directives require
data or reserve storage one or more operands
„ DB - byte(s) „ define memory contents
„ DW - word(s) „ specify amount of storage
„ DD - doubleword(s) to reserve for run-time
„ DQ - quadword(s) data
„ DT - tenbyte(s)

Defining Data
Š Numeric data values Š A list of values may be
„ 100 - decimal used - the following
„ 100B - binary creates 4 consecutive
„ 100H - hexadecimal words
„ '100' - ASCII DW 40CH,10B,-13,0
„ "100" - ASCII Š A ? represents an
Š Use the appropriate uninitialized storage
DEFINE directive (byte, location
word, etc.) DB 255,?,-128,'X'

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Naming Storage Locations
Š Names can be associated Š ANum refers to a byte
with storage locations storage location,
ANum DB -4 initialized to FCh
DW 17 Š The next word has no
ONE
associated name
UNO DW 1
X DD ? Š ONE and UNO refer to
Š These names are called the same word
variables Š X is an unitialized
doubleword

Arrays

Š Any consecutive storage locations of the same


size can be called an array
X DW 40CH,10B,-13,0
Y DB 'This is an array'
Z DD -109236, FFFFFFFFH, -1, 100B
Š Components of X are at X, X+2, X+4, X+6
Š Components of Y are at Y, Y+1, …, Y+15
Š Components of Z are at Z, Z+4, Z+8, Z+12

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DUP

Š Allows a sequence of storage locations to be


defined or reserved
Š Only used as an operand of a define directive
DB 40 DUP (?)
DW 10h DUP (0)
DB 3 dup ("ABC")
db 4 dup(3 dup (0,1), 2 dup('$'))

Word Storage

Š Word, doubleword, and quadword data are


stored in reverse byte order (in memory)
Directive Bytes in Storage
DW 256 00 01
DD 1234567H 67 45 23 01
DQ 10 0A 00 00 00 00 00 00 00
X DW 35DAh DA 35
Low byte of X is at X, high byte of X is at X+1

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Named Constants
Š Symbolic name associated with storage location
represent an address
Š Named constant is a meaningful name that takes the
place of a number, string or other expression
„ It is similar to a variable, but cannot be modified

„ It has global scope, i.e., can be used in any macro

„ Some named constants can be redefined

„ No storage is allocated for these values (in contrast

with data allocation directives)

Equal Sign Directive

Š name = expression
„ expression must be numeric
„ these symbols may be redefined during assembly time

maxint = 7FFFh
count = 1
DW count
count = count * 2
DW count

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EQU Directive

Š name EQU expression


„ expression can be string or numeric
„ Use < and > to specify a string EQU

„ these symbols cannot be redefined later in the

program
sample EQU 7Fh
aString EQU <1.234>
message EQU <This is a message>

Addressing Modes
Addressing Register-file Memory
Operand field
mode contents contents

Immediate Data

Register- Register address Data


direct
Register Register address Memory address Data
indirect
Direct Memory address Data

Indirect Memory address Memory address

Data

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8086 Programming Model
General Purpose Registers Segment Registers
Accumulator AX AH AL Code Segment CS
Base BX BH BL Data Segment DS
Count CX CH CL Extra Segment ES
Data DX DH DL Stack Segment SS
Pointer Registers Flag Register
Stack Pointer SP Status and
Control Flags FlagsH FlagsL
Base Pointer BP
Index Registers Instruction Register
Source Index SI Instruction IP
Destination Index DI Pointer

Except in data group, all registers are 16 bits (2 bytes) long

Data Transfer Instructions


Š MOV target, source Š reg can be any non-segment
„ reg, reg register except IP or program
„ mem, reg Counter (PC) cannot be the
„ reg, mem target register
„ mem, immed Š MOV's between a segment
„ reg, immed register and memory or a 16-
bit register are possible
Program Counter or IP or address register or instruction register:
Depending on the architecture, PC holds either the address of the
instruction being executed, or the address of the next instruction to be
executed

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Instruction rules
„ Source operand can be memory, register or constant
„ Destination can be memory or non-segment register
„ Only one of source and destination can be memory
„ Source and destination must be same size

Segment register:
A register that points to the base of the current segment being addressed
Non-segment register:
- Pointer register, general purpose register, IP, Flag register, etc.

Sample MOV Instructions


b db 4Fh Š When a variable is created with a
w dw 2048 define directive, it is assigned a
default size attribute (byte, word, etc.)
mov bl,dh Š You can assign a size attribute using
LABEL
mov ax,w
LoByte LABEL BYTE
mov ch,b aWord DW 97F2h
mov al,255
mov w,-100
mov b,0

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Addresses with Displacements
b db 4Fh, 20h, 3Ch Š The assembler
w dw 2048, -100, 0 computes an address
based on the
mov bx, w+2 expression
mov b+1, ah Š NOTE: These are
mov ah, b+5 address computations
mov dx, w-3 done at assembly time
MOV ax, b-1
Š Type checking is still in will not subtract 1 from
effect the value stored at b

Exchange instruction
Š XCHG target, source Š This provides an efficient
„ reg, reg means to swap the
„ reg, mem operands
„ mem, reg „ No temporary storage is
needed
Š MOV and XCHG cannot
perform memory to „ Sorting often requires this
type of operation
memory moves
„ This works only with the
general registers

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Arithmetic Instructions
ADD dest, source Š source can be a general
SUB dest, source register, memory
INC dest location, or constant
DEC dest Š dest can be a register or
memory location
NEG dest
„ except operands cannot
Š Operands must be of the both be memory
same size

Program Segment Structure


(Segment Registers)
Š Data Segments Š Stack Segment
„ Storage for variables „ used to set aside storage
„ Variable addresses are for the stack
computed as offsets from „ Stack addresses are
start of this segment computed as offsets into
Š Code Segment this segment
„ contains executable Š Segment directives
instructions .data
.code
.stack size

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Memory Models

Š .model memory_model
„ tiny: code+data <= 64K (.com program)
„ small: code<=64K, data<=64K, one of each
„ medium: data<=64K, one data segment
„ compact: code<=64K, one code segment
„ large: multiple code and data segments
„ huge: allows individual arrays to exceed 64K
„ flat: no segments, 32-bit addresses, protected mode
only (80386 and higher)

Program Skeleton
.model small Š Select a memory model
.stack 100H Š Define the stack size
.data Š Declare variables
;declarations Š Write code
.code „ organize into procedures
main proc Š Mark the end of the source
;code file
„ optionally, define the entry
main endp point
;other procs
end main

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Micro-controller Assembly
Language

PIC Architecture: Background

Microprocessor:
ƒ Requires ‘external’ support hardware
ƒ E.g., External RAM, ROM, Peripherals

Microcontroller:
ƒ Very little external support hardware.
ƒ Most RAM, ROM and peripherals on chip.
ƒ “Computer on a chip”, or “System on chip” (SOC)
ƒ E.g., PIC = Peripheral Interface Controller

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Harvard Architecture

Š Harvard architecture has the program memory and data memory as


separate memories and are accessed from separate buses.
Š This improves bandwidth over traditional von Neumann architecture in
which program and data are fetched from the same memory using the
same bus.
Š To execute an instruction, a von Neumann machine must make one or
more (generally more) accesses across the 8-bit bus to fetch the
instruction.Then data may need to be fetched, operated on, and
possibly written.
Š With a Harvard architecture, the instruction is fetched in a single
instruction cycle (all 14-bits). As can be seen from this description, that
bus can be extremely congested.

PIC Architecture: Background

The Von-Neuman Architecture is used in many cases

ƒ Used in: 80X86 (PCs), 8051, 68HC11, etc.)


ƒ Only one bus between CPU and memory
ƒ RAM and program memory share the same bus and the same memory,
and so must have the same bit width
ƒ Bottleneck: Getting instructions interferes with accessing RAM
Memory
CPU 8
(Program
& Data)

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PIC Architecture: Background

PICs use the Harvard Architecture

ƒ Used mostly in RISC CPUs (we’ll get there)


ƒ Separate program bus and data bus: can be different widths!
ƒ For example, PICs use:
„ Data memory (RAM): a small number of 8bit registers
„ Program memory (ROM): 12bit, 14bit or 16bit wide
(in EPROM, FLASH, or ROM)

Memory Memory
(Data) 8
CPU 12
(Program)
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PIC Architecture: Background


Traditionally, CPUs are “CISC”
ƒ Complex Instruction Set Computer (CISC)
ƒ Used in: 80X86, 8051, 68HC11, etc.
ƒ Many instructions (usually > 100)
ƒ Many, many addressing modes
ƒ Usually takes more than 1 internal clock cycle (Tcyc) to execute
ƒ Example:

MC68HC05: LDAA 0x55 1000 1100


2 bytes, 2 cycles
01010101

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PIC Architecture: Background
PICs and most Harvard chips are “RISC”
ƒ Reduced Instruction Set Computer (RISC)
ƒ Used in: SPARC, ALPHA, Atmel AVR, etc.
ƒ Few instructions (usually < 50)
ƒ Only a few addressing modes
ƒ Executes 1 instruction in 1 internal clock cycle (Tcyc)
ƒ Example:

PIC16CXXX: MOVLW 0x55 1100XX 01010101

1 word, 1 cycle
Example PIC: 12C508 Block Diagram

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The PIC Family: Program Memory
PIC program space is different for each chip.

Some examples are:

12C508 512 12bit instructions


16C71C 1024 (1k) 14bit instructions
16F877 8192 (8k) 14bit instructions
17C766 16384 (16k) 16bit instructions

The PIC Family: Program Memory


PICs have two different types of program storage:

1. EPROM (Erasable Programmable Read Only Memory)


ƒ Needs high voltage from a programmer to program (~13V)
ƒ Needs windowed chips and UV light to erase
ƒ Note: One Time Programmable (OTP) chips are EPROM chips,
but with no window!
ƒ PIC Examples: Any ‘C’ part: 12C50x, 17C7xx, etc.

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The PIC Family: Program Memory
PICs have two different types of program
storage:

2. FLASH
ƒ Re-writable (even by chip itself)
ƒ Much faster to develop on!
ƒ Finite number of writes (~100k Writes)
ƒ PIC Examples: Any ‘F’ part: 16F84, 16F87x, 18Fxxx
(future)

The PIC Family: Data Memory


PICs use general purpose “file registers” for RAM
(each register is 8bits for all PICs)

Some examples are:

12C508 25 Bytes RAM


16C71C 36 Bytes RAM
16F877 368 Bytes (plus 256 Bytes of nonvolatile EEPROM)
17C766 902 Bytes RAM

Š NOTE: programs are stored in program space (not in data space), so low RAM values are OK.

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The PIC Family: Control Registers
PICs use a series of “special function registers”
for controlling peripherals and PIC behaviors.

Some examples are:

STATUS Bank select bits, ALU bits (zero, borrow, carry)


INTCON Interrupt control: interrupt enables, flags, etc.
TRIS Tristate control for digital I/O: which pins are
‘floating’
TXREG UART transmit register: the next byte to transmit

The PIC Family: Peripherals


Different PICs have different on-board peripherals

Some common peripherals are:


„ Tri-state (“floatable”) digital I/O pins
„ Analog to Digital Converters (ADC) (8, 10 and 12bit, 50ksps)
„ Serial communications: UART (RS-232C), SPI, I2C, CAN
„ Pulse Width Modulation (PWM) (10bit)
„ Timers and counters (8 and 16bit)
„ Watchdog timers, Brown out detect, LCD drivers

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PIC Peripherals: Ports (Digital I/O)
Š All PICs have digital I/O pins, called ‘Ports’
„ the 8pin 12C508 has 1 Port with 4 digital I/O pins
„ the 68pin 17C766 has 9 Ports with 66 digital I/O pins
Š Ports have 2 control registers
„ TRISx sets whether each pin is an input or output
„ PORTx sets their output bit levels
Š Most pins have 25mA source/sink (directly drives LEDs)
Š WARNING: Other peripherals SHARE pins!

Software: Introduction
Š In this course, we’ll only talk about PIC assembly language as
used in the MPLAB assembler.
„ MPLAB is FREE (score): see http://www.microchip.com/

„ Assembly is a bit harder to code, but faster and more

compact.

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Software: Programmers Model
Hardware Stack
<- 12/14/16 bits -> Stores addresses for
subroutines
Program Memory
(PCH) Program Counter-PCL
“Burned” in by
programmer (can’t <- 8 bits ->
change during Status
execution). Stored
instructions, Special Purpose
addresses and Registers
“literals” (numbers)
I/O pin states,
peripheral
W “Register” registers, etc.
General Purpose
Registers

RAM or “data
memory”. Variables
are stored here

Software: Instruction Examples


movlw 0xFF

Move (“mov”) the number (“l” for “literal”) 0xFF - that’s 256
in decimal- into the working register (“w”).

In other words, load W with the value 0xFF.

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Software: Programmers Model

Hardware Stack
<- 12/14/16 ->
Program Memory
(PCH) Program Counter-PCL
<- 8 bits ->
Status

Special Purpose
Registers
0xFF

W “Register”
General Purpose
Registers

Software: Instruction Examples


movwf PORTA

Move (“mov”) the working register (“w”) into the file register
(“f”) named PORTA.

In other words, load the register called PORTA with whatever


number is in the W register.

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Software: Programmers Model
Hardware Stack
<- 12/14/16 ->
Program Memory
(PCH) Program Counter-PCL

<- 8 bits ->


Status

Special Purpose
Registers

Value in W PORTA

W “Register”
General Purpose
Registers

Software: Instruction Examples


movf PORTA, W

Move (“mov”) the the value of the file register (“f”) named
PORTA into the working register (“w”) .

In other words, load W with the whatever number is in PORTA.

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Software: Programmers Model
Hardware Stack
<- 12/14/16 ->
Program Memory
(PCH) Program Counter-PCL

<- 8 bits ->


Status

Special Purpose
Registers
Value in PORTA PORTA

W “Register”
General Purpose
Registers

Software: Assembly Format


Š First column: Labels
Š Second column: opcodes and assembler directives
Š Third Columns & more: operands

; This is a comments since it starts with a “;”


; This program puts out a square wave on PORTA Pin 0

clrf PORTA ; Clear PORTA register


clrf TRISA ; Make PORTA all outputs
Loop bsf PORTA,0 ; Turn on PORTA Pin 0
nop ; Match ‘goto’ delay
nop ; “ “ “
bcf PORTA,0 ; Turn off PORTA Pin 0
goto Loop ; If not zero, loop back

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Software: Branches
Š All branches are “Bit Tests”
Š All branches only skip one instruction

; Set EqualFlag if PORTA = PORTB

bcf EqualFlag, 7 ; First, clear the flag


movf PORTA, W ; Move PORTA -> W
subwf PORTB, W ; W - PORTB -> W
btfsc STATUS, Z ; Check Z bit (see STATUS)
bsf EqualFlag, 7 ; Ports equal; set flag
STATUS Register

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Software: Direct Addressing
Š All file registers (RAM) are accessed by an address. This is
called direct addressing.

Š For example,

movlw 0xFF
movwf 0x06

loads W with FF, and then loads W into GPIO (address 0x06).

Š Thankfully, we can use labels instead of addresses:

GPIO equ 0x06


movwf GPIO

Software: Relative Addressing


Š PCL = Low byte of the Program Counter
Š Can be read and written.
Š Writing to it sets the address of the next instruction to be
executed.

12bit core 14bit core

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Software: Relative Addressing
‹Example of Relative Addressing (using a table):
; Here’s a simple lookup table which is called as a
; subroutine. Expects the tbl offset to be loaded in W.
; An example call looks like this:
; movlw 0x04 ; Load W with 4
; call Table ; Call the table subroutine
; movwf Result ; Store result from the table

Table addwf PCL, W ; Jump to (current PCL) + W


retlw 0x00 ; Return with 0x00 in W
retlw 0x23 ; Return with 0x23 in W
retlw 0x33 ; etc.
retlw 0x88

Software: Indirect Addressing

00h INDF Š Load indirect address into FSR


Š Reading/Writing to INDF acts on
address stored in FSR
04h FSR
Š Example code to clear 0x20 - 7F:
movlw 0x20
movwf FSR

loop clrf INDF


incf FSR,F
btfssFSR,7
7Fh
Register File goto loop

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Software: Banking
RAM in the PICs is banked, especially
special function registers. Use the bank
select commands to choose the bank.

Either:
bsf STATUS, RP0
bcf STATUS, RPO

Or use the assembler directive:


Banksel <registername>

Assembler Design

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How Assembler Works
Š The essential task of an assembler is to convert
symbolic text into binary values that are loaded into
successive bytes of memory
Š There are two major components of this task
„ Allocating and initializing data storage

„ Conversion of mnemonics to binary instructions

„ Resolving addresses

Š An assembler scans through a file maintaining a set of


location pointers for next available byte of each
segment

Memory Allocation
Š Memory allocation is handled by assembler directives:
.data
X: - word 42
msg: - ascii “Hello, world”
- align 2
array: - space 40
foo: - word 0xdcadbccf
Š When the assembler encounters label declarations while scanning a source
file, it creates a SYMBOL table entry to keep track of its location:

SYMBOL SEGMENT Location pointer offset


X data 0
msg data 4
array data 20
foo data 60

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Encoding Mnemonic

SYMBOL SEGMENT Location pointer offset


X data 0
msg data 4
array data 20
foo data 60
main text 0
bitrev ? ?

Resolving Addresses: Pass 1

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Resolving Addresses: Pass 2

Single Pass Assembler

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Macros and Macro Processors
Š A unit of specification for program generation through expansion
„ Purpose: increase program efficiency
Š Some language support in-built macro writing facilities
„ C, C++, Ada
Š If macro facility is not in-built
„ Equivalent effect achieved by software tools like Awk in UNIX
Š Macro expansion: the use of a macro name with a set of actual
parameters is replaced by some code generated from its body
„ Lexical expansion: replacement of a character string by another character
string during program generation
„ Semantic expansion: generation of instructions tailored to the
requirements of a specific usage
Š Macro vs. sub-routine:
„ Macro: Macro name in the mnemonic field leads to expansion
„ Subroutine name call leads to its execution

Macro definition and call


Š Macro header Æ macro definition Æ macro end
Š Macro definition:
„ Macro prototype statement: macro name, names and kind of parameters
„ Model statements: from which an assembly language statement may be
generated by macro expansion
„ Macro preprocessor statements: perform auxiliary functions during macro
expansion -- optional

Example: macro definition


MACRO ; macro header
incr &mem_val,&incr_val,&reg ; macro prototype statement
mover &reg, &mem_val ; model statement
add &reg, &incr_val ; model statement
movem &reg, &mem_val ; model statement
MEND ; macro end

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Macro call
Š INCR A, B, AREG
Formal parameter value
mem_val A
incr_val B
REG AREG
Š Lexical expansion of the model statements
+ MOVER AREG, A
+ ADD AREG, B
+ MOVEM AREG, A
Š Default specification of parameters
„ In the absence of explicit specification by the programmer
incr_d incr_val=B, mem_val=A ; default REG will be used
for the increment oprtaion
incr_d mem_val=B,mem_val=A,reg=BREG ; BREG will be used

Nested macro call


Š A model statement in a macro may constitute a call on another
macro
„ Outer macro, inner macro
„ Expansion: LIFO rule

MACRO
compute &first, &second ; X, Y
movem BREG, TMP
incr_d &first, &second reg=BREG ; inner macro
mover BREG, TMP
MEND
Š Lexical expansion of the model statements
+ MOVEM BREG, TMP + MOVER BREG,X
COMPUTE X,Y + INCR_D X, Y + ADD BREG,Y
+ MOVER BREG, TMP + MOVEM BREG,X

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