Module 4 - Instruction Set Architecture (ISA) v2 (Student) PDF

SCSR2033 - Computer Architecture and Organization
SCSR2033
Computer Organization
and Architecture
Lecture slides prepared by “Computer Organization and Architecture”, 9/e, by William Stallings, 2013.
1
Module 4
Instruction Set Architecture
(ISA)
Objectives:
q To provide a more detailed look at machine
instruction sets.
q To look at different instruction types and
operand types, and how instructions access
data in memory.
q To understanding how instruction sets are designed and
how their function can help to understand the more
intricate details of the architecture of the machine itself.
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Module 4
(ISA)
4.1 Introduction
4.2 Machine Instruction Characteristics
4.3 Types of Operands
4.4 Addressing Modes
4.5 Instruction Formats
4.6 Summary
Module 4
(ISA)
4.1 Introduction q Overview

Hierarchy of Computer Languages
4.2 Machine InstructionqCharacteristics
4.3 Types of Operandsq General Concepts:
4.4 Addressing Modes x86 Processor Architecture
4.5 Instruction Formatsq Design Decisions for Instruction Sets
4.6 Summary q ISA Level
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Overview
ALU (Arithmetic Logic Unit)
n One boundary where the computer designer and the computer

programmer can view the same machine is the machine
instruction set.
n Implementing the processor is a task that in large part involves
implementing the _______________________.
n The user who chooses to program in machine language
(actually, in assembly language) becomes aware of the register
and memory structure, the types of data directly supported by
the machine, and the functioning of the ALU.
William Stallings (2013). Computer Organization and Architecture: Designing for Performance (9th Edition). United States: Pearson Education Limited, p.248. 5
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Some important questions to ask:
n What is assembly language?
n Why learn assembly language?
n What is machine language?
n How is assembly related to machine language?
n What is an assembler?
n How is assembly related to high-level language?
n Is assembly language portable?
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Hierarchy of Computer Languages
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Assembly and Machine Languages
Machine language: Assembly language:

n Native to a processor: n A programming language that uses
executed directly by symbolic names to represent
hardware. ___________, ___________ and
n Instructions consist of ___________ locations.
binary code: 1s and 0s n Slightly higher-level language.
n Readability of instructions is better
than machine language.
n One-to-one correspondence with
machine language instructions.
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Compiler and Assembler
__________ translate high-level programs __________ translate

to machine code assembly to machine
à either directly, or Indirectly via an code.
assembler. 9
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High-Level Languages: Advantages
Program development is ________: fewer instructions to code.
Program maintenance is _________: same reasons as above.
Programs are portable:

q Contain few machine-dependent details à Can be used
with little or no modifications on different machines.
q Compiler translates to the target machine language.
q However, Assembly language programs are not portable.
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Why Assembly Languages?
Accessibility to system hardware:

q Assembly language is useful for implementing system
software.
q Also useful for small embedded system applications.
Space and Time efficiency:

q Understanding sources of program inefficiency.
q Tuning program performance.
q Writing compact code.
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HLL (High Level Language)
Writing assembly programs gives the computer designer the

needed deep understanding of the instruction set and how to
design one.
To be able to write compilers for HLLs, we need to be expert

with the machine language. Assembly programming provides
this experience.
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General Concepts:
X86 Processor Architecture
n This section describes the architecture of the x86 processor

family and its host computer system from a programmer’s point
of view.
n _____________________ is a great tool for learning how a
computer works, and it requires you to have a working
knowledge of computer hardware.
n The concepts in this section will help to understand the
assembly language code that be written.
Irvine, K.R. (2011). Assembly Language for x86 Processors (6th Edition). New Jersey: Pearson Education Limited, p.29. 13
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Basic Microcomputer Design
(Section 5.2)
n One
Registers
Figure: Block diagram of a microcomputer.

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CPU (Central Processing Unit)
n The CPU does the ___________ and _________________ à contains

a limited number of storage locations as follow:
Elements Description
Clock o synchronizes the internal CPU operations.
Control Unit (CU) o coordinates sequence of execution steps.
Arithmetic Logic o performs arithmetic and bitwise
Unit (ALU). processing.
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Clock
n synchronizes all CPU and BUS operations.

n machine (clock) cycle measures time of a single operation.
n clock is used to trigger events
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Instruction 4
Execution Cycle
Registers
n ___________
ALU
n ___________
n ___________
n ___________
n Store output Figure: Simplified
CPU block diagram.
Irvine, K.R. (2011). Assembly Language for x86 Processors
(6th Edition). New Jersey: Pearson Education Limited, p.31.
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Reading From Memory
Figure: Memory read cycle.

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n Multiple machine cycles are required when reading from
memory, because it responds much more slower than the
CPU.
n The steps are:
n Cycle 1: address placed on address bus (ADDR).
n Cycle 2: Read Line (RD) set low (0).
n Cycle 3: CPU waits one cycle for memory to respond.
n Cycle 4: Read Line (RD) goes to 1, indicating that the data

is on the data bus (DATA).
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How Program Run?
Assembling, Linking, and Running Programs
Link
Library
Step 2: Step 3: Step 4:
Source assembler Object linker Executable OS loader
Output
File File File
Listing Map
Step 1: text editor File File
n The diagram describes the steps from creating a source

program through executing the compiled program.
n If the source code is modified, Steps 2 through 4 must be
repeated.
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Listing File
n Use it to see how your program is compiled.
n Contains:
q source code
q addresses
q object code (machine language)
q segment names
q symbols (variables, procedures, and constants)
n Example: addSub.lst
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• 32-bit addresses
• indicate the relative byte
distance of each statement
from the beginning of the
program’s code area
• contain no executable
instructions
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• … directives,
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• assembly language instructions, each

5 bytes long
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• the hexadecimal values in the second
column, such as B8 00010000 are
the actual instruction bytes.
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Map File
n Information about each

program segment:
q starting address n Example: addSub.map
q ending address
q size
q segment type
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Design Decisions for Instruction Sets
n When a computer architecture is in the design phase, the

______________________________must be determined before
many other decisions can be made.
n Selecting this format is often quite difficult because the
instruction set must match the architecture.
n If the architecture is well designed, it could last for decades.
Linda Null and Julia Lobur (2003). The Essentials of Computer Organization and Architecture. United States: Jones and Bartlett Publishers. p.200. 27
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ISA Level
ISA (Instruction Set Architecture)
n ISA Level defines the interface between the ___________ (high

level language) and the ___________. It is the language that both
them understand.
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n Instruction set architectures (ISAs) are measured by several

different factors, including:
(1) the amount of space a program requires;

(2) the complexity of the instruction set;
(3) the length of the instructions; and
(4) the total number of instructions.
Linda Null and Julia Lobur (2003). The Essentials of Computer Organization and Architecture. United States: Jones and Bartlett Publishers. p.200. 29
Module 4
(ISA)
4.1 Introduction
4.2 Machine Instruction q Elements of a Machine
Characteristics Instruction
4.3 Types of Operands q Instruction Representation
4.4 Addressing Modes q Instruction Types
q Number of Addresses
4.6 Summary
q Instruction Set Design
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Elements of a Machine Instruction
n The operation of the processor is determined by the instructions

it executes, referred to as machine instructions or computer
instructions.
n The collection of different instructions that the processor can
execute is referred to as the processor’s ___________________.
n Each instruction must contain the information required by the

processor for execution.
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Table: The elements of a machine instruction.
Elements Description
Operation code o Specifies the operation to be performed a
binary code (e.g., MOV, ADD, SUB).
(___________)
Source operand o The operation may involve one or more
reference source operands, that is, operands that are
inputs for the operation.
Result operand o The operation may produce a result.
reference
(___________).
Next instruction o This tells the processor where to fetch the
reference next instruction after the execution of this
instruction is complete.
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Example 1:
Destination
Operand
Source Operand
Opcode 0000 MOV AX,total

0001 MOV BX,AX
0002 ADD AX,2
0003 TARGET Source
0004 CALL READINT Operand with
0005 MOV val,EAX Immediate
0006 ADD EBX,val value
0007 JMP TARGET
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n Source and result operands (___________) can be in one
of four areas:
o Main or virtual memory : memory address for both must be

supplied.
o Processor (CPU) registers : One or more registers that can
be referenced by instructions.
o Immediate : the value of the operand is contained in the
field in the instruction executed.
o I/O device – instruction specifies the I/O module and device
for the operation
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Example 2:
Operand: Memory
Operand: Register
Current Ins. : 0000 0000 MOV AX,TOTAL
Next Ins. : 0001 0001 MOV BX,AX
0002 ADD AX,2 Operand:
0003 TARGET Immediate value
0004 CALL READINT
0005 MOV VAL,EAX Operand: From
0006 ADD EBX,VAL I/O
Current Ins. : 0007 0007 JMP TARGET
Next Ins. : 0003
Next instruction is
where TARGET is
located = 0003
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Instruction Representation
n Each _______________ is represented by a sequence of bits that

divided into fields, corresponding to the constituent elements of
the instruction.
n Example of simple instruction format:
William Stallings (2013). Computer Organization and Architecture: Designing for Performance (9th Edition). United States: Pearson Education Limited, p.429-430. 36
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It is difficult for the programmer to

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deal with binary representations of
machine instructions.
n Thus, it has become common practice to use a symbolic

representation of machine instructions.
n _________________ are represented by abbreviations, called

mnemonics, that indicate the operation.
n Common examples:
n Example: 4
What the processor What the

(CPU) see. programmer see.
n During instruction execution:

o an instruction is read into an Instruction Register (IR) in the
processor.
o The processor must be able to extract the data from the
various instruction fields to perform the required operation.
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Instruction Types
n Consider a high-level
A single C instruction may require
language instruction that
3 machine instructions; This is
could be expressed in a typical of the relationship between
language such as C. a high-level language and a
n Example: machine language.
Total = Total + stuff
n In assembly language:
1) Load a register with the contents of memory (for Total)
2) Add the contents of memory (for stuff) to the register
3) Store the content of the register to memory location (for
Total)
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n Translating the language:
English: Total is assigned the sum of Total and stuff.
High-Level Language: Total = Total + stuff
A statement in a high-level language is translated

typically into several machine-level instructions
mov eax, Total A1 00404000

add eax, stuff 83 00404004
mov Total, eax A3 00404008
Intel Assembly Language: Intel Machine Code:

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Instruction
Types
Data Data Data

___________ _________ _________ Control
o Arithmetic and o Movement of o I/O o Test &

logic instructions data in/out instructions branch
register and/or instructions
memory
Figure: Categories of instruction types.

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Number of Addresses
n One of the traditional ways in describing processor architecture

is using the number of addresses contained in each instruction .
What is the maximum

number of addresses one
might need in an instruction?
n In most architectures, most instructions have one, two, or three

operand addresses.
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Example: Program to execute

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4 instructions
8 instructions
6 instructions
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How Many Addresses?
n Number of addresses per instruction is a basic design decision.
n More addresses: n Fewer addresses:

n More complex n Less complex (powerful?)
(powerful?) instructions. instructions.
n Fewer instructions per n More instructions per
program. program.
n More registers: n Faster fetch/execution of
à Inter-register operations instructions.
are quicker.
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Instruction Set Design
n The design of an instruction set is very complex because it

affects so many aspects of the computer system.
n The instruction set defines many of the functions performed by
the ___________.
n The instruction set is the programmer’s means of controlling the
processor. Thus, programmer requirements must be
considered in designing the instruction set.
n The most important of these fundamental design issues include

the following:
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o How many operations?
o What can they do?
Operation o How complex are they?
o The mode(s)
by which the
address of an Addressing Data Types
operand is
o The various
specified.
types of data.
Instruction
Registers
Formats
o Number of CPU registers available. o Length of opcode field.

o Which operations can be performed o Number of addresses.
on which registers?
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Module 4
(ISA)
4.1 Introduction
4.2 Machine Instruction q Overview
Characteristics
q Numbers
q Characters
4.4 Addressing Modes
4.5 Instruction Formats q Logical Data
4.6 Summary
4
Overview
n Assembly language built from two pieces:
MOV R1, R2
___________ : ___________
What to do with the data Where to get data (R2)
(ALU operation) and put the results (R1)
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n Machine instructions operate on data.

n The most important general categories of data:
Data
Addresses _________ __________ Logical Data
(Section 4.4)
Table: Type of operand for Pentium 4
50
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Numbers
n All machine languages include numeric data types.

n An important distinction between numbers used in ordinary
mathematics and numbers stored in a computer is that the latter
are limited: (2 reasons)
there is a limit to the a limit to the precision of

magnitude of numbers floating-point numbers.
representable on a machine.
n 3 types of numerical data:
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Example 3a: x86 numerical data types.
(Unsigned integers)
n The unsigned integers may be 16, 32, or 64 bits long.
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Example 3b: x86 numerical data types.
(Signed integers)
n The signed integers are in two’s complement representation and

may be 16, 32, or 64 bits long.
4
Example 3c: x86 numerical data types.
(Signed integers)
n The floating-point type actually refers to a set of types that are

used by the floating-point unit and operated on by floating-point
instructions à IEEE 754 standard.
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Characters
n A common form of data is __________ or __________________.

n Today, the most commonly used character à
United States as the American Standard Code for Information
Interchange (ASCII).
n Another code used to encode characters is the Extended Binary
Coded Decimal Interchange Code (EBCDIC); used on IBM
mainframes.
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Logical Data
n Normally, each word or other addressable unit (byte, halfword,

and so on) is treated as a single unit of data à n-bit unit.
n When data are viewed this way, they are considered to be
logical data.
n Two advantages to the bit-oriented view:
q Memory used efficiently to store an array of Boolean or
binary data items for either values 1 (true) and 0 (false).
q Easy to manipulate the bits of a data item.
n
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Module 4
(ISA)
q Overview
4.1 Introduction
4.2 Machine Instruction q Immediate Addressing
Characteristics q Direct Addressing
4.3 Types of Operands q Indirect Addressing
4.4 Addressing Modes q Register Addressing
q Register Indirect Addressing
4.6 Summary
q Displacement Addressing
4
Overview
n Two issues arise in specifying the operands addresses and

operations of instructions:
How the address of an How the bits of an

operand is specified? instruction are organized?
n A variety of addressing techniques has been employed to be

able to reference a large range of locations in main memory or,
for some systems, virtual memory.
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A = contents of
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an address field
in instruction.
R = contents of
an address field
in instruction
that refers to a
register.
EA = actual
(effective)
address of the
location
containing the
referenced
operand.
(X) = contents
of memory
location X or
Figure: Addressing modes. register X.
Table: Basic addressing modes.
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Immediate Addressing
n The simplest form of

addressing, in which the
operand value is present in the
instruction.
n Can defines and uses constant
or set initial values of variables.
n Saving one memory or The size of the number is

cache à No memory restricted to the size of the
reference other than the address field.
instruction fetch is required,
(faster).
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Direct Addressing
n The address field contains the

Effective Address (EA) of the
operand.
Requires only one It provides only a limited

memory reference and no address space
special calculation.
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Example 4: Direct addressing.
Address of
operand = 1011
AX = 10h
AX = 10h + 28h
= 38h
63
.data
val1 byte 10h

4
Example 5: Direct addressing. array1 word 2210h, 11
array2 dword 123h, 234h
.code
main PROC
al = __________h mov al,val1
mov bx,array1
bx = __________h
mov ecx,array2
ecx = 00000123h call dumpregs
exit
main ENDP
(DumpRegs)
EAX=7611ED10 EBX=7FFD2210 ECX=00000123 EDX=00401022
ESI=00000000 EDI=00000000 EBP=0012FF94 ESP=0012FF8C
EIP=0040102D EFL=00000246 CF=0 SF=0 ZF=1 OF=0
64
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Indirect Addressing
n Solution for the limitation of

the address range in direct
addressing à to have the
address field address of a
Look in A, find word in memory, full-length
address (A), and look address of the operand.
there for operand.
Three or more memory

references could be required
No particular advantage.
to fetch an operand; slower.
.data
array1 byte 10h

4
Example 6: Indirect addressing. array2 word 123h,234h
array3 dword 123456h
.code
main PROC
bl = __________h
mov bl,[array1]
cx = __________h mov cx,[array2]
mov edx,[array3]
edx = 00123456h mov ax,[array2+2]
ax = __________h call dumpregs
exit
main ENDP
(DumpRegs)
EAX=00000234 EBX=00000010 ECX=00000123 EDX=00123456
EIP=0040104C EFL=00000246 CF=0 SF=0 ZF=1 OF=0
66
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Register Addressing
n Similar to direct addressing,

except the address field refers to
a register rather than a main
memory address.
n The programmer need to decide
which values should remain in
registers and which should be
stored in main memory.
No time consuming It has limited number of

memory references needed registers à provides a
à faster. limited address space.
.data
.code
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Example 7: Register addressing.
main PROC
eax = 00000000h mov eax,0
ebx = 00002000h mov ebx,2000h
mov ecx,3000h
ecx = 00003000h
mov eax,ebx
eax = 00002000h add eax,ecx
eax = 00005000h call dumpregs
exit
main ENDP
(DumpRegs)
EAX=00005000 EBX=00002000 ECX=00003000 EDX=00401005
EIP=00401028 EFL=00000206 CF=0 SF=0 ZF=0 OF=0
68
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Register Indirect Addressing
n Similar to indirect addressing.
n The advantages and

limitations of register indirect
addressing are basically the
same as for indirect
addressing.
Register indirect addressing uses one less

memory reference than indirect addressing.
.data
array1 byte
array2 word
10h,11h,12h,13h
123h,234h
4
Example 8:
Register indirect addressing. .code Address of the data
that stored in register.
esi = 00404004h main PROC

mov esi,OFFSET array1
edi = 00404008h mov edi,OFFSET array2
mov bl,[esi]
bl = __________h
mov cx,[edi]
cx = __________h mov edx,(esi)
mov al,[esi+1]
edx = 00404004h call dumpregs
al = __________h exit
main ENDP
(DumpRegs)
EAX=00000011 EBX=00000010 ECX=00000123 EDX=00404004
70
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.data
array1 byte
array2 word
10h,11h,12h,13h
123h,234h
4
.code

mov esi,OFFSET array1
edi = 00404008h mov edi,OFFSET array2
mov bl,[esi]
mov cx,[edi]
mov al,[esi+1] mov edx,[esi]
mov al,[esi+2]
call dumpregs
al = 11h exit
main ENDP
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.data
.code
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Example 9:
Register indirect addressing. main PROC
mov ebx,404000h
ebx = 00404000h mov dl,[ebx]
inc ebx
dl = __________h mov cl,[ebx]
ebx = 00404001h
call dumpregs
cl = __________h exit
main ENDP
(DumpRegs)
EAX=00005000 EBX=00404001 ECX=00000055 EDX=00000024
72
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Displacement Addressing
n A very powerful mode of

addressing combines the
capabilities of direct
addressing and register
3 common displacement indirect addressing.
addressing technique:
n Address field hold two values:
Relative addressing o A = base value
o R = register that holds
Base-Register addressing
displacement
Indexed addressing (or vice versa)
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(a) Relative Addressing
n Also called PC-relative addressing, the implicitly referenced

register is the Program Counter (PC).
R = PC
EA = A + (PC)
n The next instruction address (shown in PC) is added to the

address field to produce the EA.
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Destination = target – source
Example 10:
how much to jump = where is L1 – PC
how much to jump = 28 – 39
4
= – EF
Displacement Addressing.
(a) Relative addressing
–(ve) because
00000014 B9 00000000 mov ecx,0 its jumping
00000019 BA 00000000 mov edx,0 backwards
0000001E B8 00000000 mov eax,0
00000023 B9 00000004 mov eax,4
00000028 L1:
00000028 66| 8B 98 mov bx,array2[eax]
00000008 R
PC=39:
PC = 39
0000002F 83 C0 02 add eax,2
00000032 E8 00000000 E call dumpregs Need to go to
00000037 E2 EF LOOP L1 L1 which is
in 00000028
exit
00000039 6A 00 * push +000000000h
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(b) Base-Register Addressing
EA = A + R
o A holds displacement.
o R holds pointer to base address.
o R may be explicit or implicit.
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Example 11:
.data
count
array1
dword 10h
byte 10h,11h,12h,13h
4
array2 word 123h,234h,345h,456h
array3 dword 123456h, 23456789h
(b) Base-register addressing Base-index
.code
addressing
main PROC
mov esi, offset array1
mov ebx,10h
mov ax, word ptr[ebx+esi]
add ebx, esi
mov cx, word ptr[ebx]
call dumpregs
exit
main ENDP Base
addressing
77
.data
count
array1
dword 10h
byte 10h,11h,12h,13h
4
array3 dword 123456h, 23456789h
.code
mov esi, offset array1
ebx = 00000010h mov ebx,10h
mov ax, word ptr[ebx+esi]
ax = __________h add ebx, esi
ebx = 00404014h mov cx, word ptr[ebx]
cx = __________h call dumpregs

exit
(DumpRegs) main ENDP
EAX=753E6789 EBX=00404014 ECX=00006789 EDX=00401005

EIP=00401028 EFL=00000206 CF=0 SF=0 ZF=0 OF=0
78
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(c) Indexed Addressing
EA = A + R
o A = base
o R = displacement
o Good for accessing arrays
4
Exercise 4.1:
Given three arrays with multiple initializer in assembly language

program. Complete the following diagram by. writing:
(a) the offset for all memory. Assume the first offset is 00404004.
(b) the value of the data stored using Little Endian Order.
.data
array1 byte 10h,11h,12h,13h
array3 dword 123456h, 23456789h
80
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Offset : Value: Offset : Value:
00404004:
81
Example 12:
.data
array1 byte 10h,11h,12h,13h
4
array3 dword 123456h, 23456789h
(c) Indexed addressing .code
main PROC
mov eax,0 Base
mov ecx,4
L1:
mov bx, array2[eax]
add eax,2
call dumpregs
LOOP L1
exit Displacement
mov bx,[array2+eax] main ENDP
Add eax,2
82
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.data
array1 byte 10h,11h,12h,13h 4
array3 dword 123456h, 23456789h
.code
main PROC
eax = 00000000h mov eax,0
ecx = 00000004h mov ecx,4
L1:
bx = __________h mov bx, array2[eax]
eax = 00000002h add eax,2
call dumpregs
ecx = 00000003h LOOP L1
exit mov bx,[array2+eax]
main ENDP
[00404008+00000000]
dec ecx à array2[00404008]
83
.data
array3 dword 123456h, 23456789h
2nd looping
.code
main PROC
mov eax,0
mov ecx,4
L1:
eax = 00000002h
00000004h add eax,2
call dumpregs
ecx = 00000003h
00000002h LOOP L1
main ENDP
[00404008+00000002]
dec ecx à array2[0040400A]
84
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.data
array3 dword 123456h, 23456789h
3rd looping
.code
main PROC
mov eax,0
mov ecx,4
L1:
00000004h
eax = 00000006h add eax,2
call dumpregs
ecx = 00000002h
00000001h LOOP L1
main ENDP
[00404008+00000004]
dec ecx à array2[0040400C]
85
.data
array3 dword 123456h, 23456789h
4th looping
.code
main PROC
Exit looping
mov eax,0
mov ecx,4
L1:
eax = 00000006h
00000008h add eax,2
call dumpregs
ecx = 00000001h
00000000h LOOP L1
main ENDP
[00404008+00000006]
dec ecx à array2[0040400E]
86
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The DumpRegs for the program: 4

EAX=00000002 EBX=00000123 ECX=00000004 EDX=00000000
EIP=00401047 EFL=00000202 CF=0 SF=0 ZF=0 OF=0
EAX=00000004 EBX=00000234 ECX=00000003 EDX=00000000

EIP=00401047 EFL=00000202 CF=0 SF=0 ZF=0 OF=0
EAX=00000006 EBX=00000345 ECX=00000002 EDX=00000000

EIP=00401047 EFL=00000202 CF=0 SF=0 ZF=0 OF=0
EAX=00000008 EBX=00000456 ECX=00000001 EDX=00000000

EIP=00401047 EFL=00000202 CF=0 SF=0 ZF=0 OF=0
87
Module 4
(ISA)
4.1 Introduction
4.2 Machine Instruction q Overview
Characteristics
q Instruction Length
4.4 Addressing Modes q Allocation Bits
4.5 Instruction Formats q Variable-Length Instructions

4.6 Summary
m @ Feb 2019 44
4
Overview
n An instruction format defines the layout of the bits of an

instruction, in terms of its constituent fields.
n An instruction format must include an opcode and, implicitly or
explicitly, zero or more operands.
n The format must, implicitly or explicitly, indicate the addressing
mode for each operand.
n For most instruction sets, more than one instruction format is
used.
4
n Four common instruction formats:
(a) Zero-address instruction.
(b) One-address instruction
(c) Two-address instruction.
(d) Three-address instruction.
90
m @ Feb 2019 45
4
Instruction Length
n This decision affects, and is affected by:

q memory size,
q memory organization,
q bus structure,
q processor complexity, and
q processor speed.
n Trade off between powerful instruction repertoire and saving

space.
n Other issues: Instruction length equal or multiple to memory

transfer length (bus system)?
4
Allocation of Bits
n We’ve looked at some of the factors that go into deciding the

length of the instruction format.
n An equally difficult issue is how to allocate the bits in that
format, and the trade-offs here are complex.
m @ Feb 2019 46
4
n The following interrelated factors go into determining the use of
the addressing bits:
q Number of addressing modes – if indicated implicitly exp:

certain op-odes might always call for indexing; if explicit –
one or more bits will be needed.
q Number of operands – typical instruction has 2 operands –

uses mode indicator for operand addresses.
q Register versus memory – single user register

(accumulator), one operand address is implicit and
consume no instruction bits; for multiple registers – a few
bits are need to specify the registers.
4
q Number of register sets – have one set of general purpose
registers with 32 or more registers in the set – for example
sets of 8 registers only 3 bits are needed to identify the
registers, opcode will implicitly determine which register set
is being referenced.
q Address range – the range of addresses that can be
referenced related to the number of bits.
q Address granularity – an address can reference a word or
byte a the designer s choice – byte addressing is
convenient for character manipulation.
m @ Feb 2019 47
4
Variable-Length Instructions
n Designer may choose instead to provide a variety of instruction

formats of different lengths.
n This tactic makes it easy to provide a large repertoire of
opcodes, with different opcode lengths.
n Addressing can be more flexible, with various combinations of
register and memory references plus addressing modes.
n With variable-length instructions, these many variations can be
provided efficiently and compactly
4.6 Summary 4
n This chapter discussed on what an instruction set does by

examining the types of operands and operations that may be
specified by machine instructions.
n Described the various types of addressing modes common in

instruction sets.
n Present an overview of essential characteristics of machine

instructions.
n Summarize the issues and trade-offs involved in designing an

instruction format.
William Stallings (2016). Computer Organization and Architecture: Designing for Performance (10th Edition). United States: Pearson Education Limited, p.413, 457. 96
m @ Feb 2019 48
Review Questions 4
4.1 What are the typical elements of a machine instruction?
4.2 What types of locations can hold source and destination

operands?
4.3 List and briefly explain five important instruction set design
issues.
4.4 What types of operands are typical in machine instruction

sets?
Review Questions 4
4.5 Briefly define:

a) immediate addressing.
b) direct addressing.
c) indirect addressing.
d) register addressing.
e) register indirect addressing.
f) displacement addressing.
g) relative addressing.
4.6 What are the advantages of using a variable-length

instruction format?
m @ Feb 2019 49

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SCSR2033 - Computer Architecture and Organization

4.1 Introduction q Overview

n One boundary where the computer designer and the computer

n What is assembly language?

n Why learn assembly language?

n What is machine language?

n How is assembly related to machine language?

n How is assembly related to high-level language?

n Is assembly language portable?

Machine language: Assembly language:

__________ translate high-level programs __________ translate

Program development is ________: fewer instructions to code.

Program maintenance is _________: same reasons as above.

Programs are portable:

Accessibility to system hardware:

Space and Time efficiency:

Writing assembly programs gives the computer designer the

To be able to write compilers for HLLs, we need to be expert

n This section describes the architecture of the x86 processor

Figure: Block diagram of a microcomputer.

n The CPU does the ___________ and _________________ à contains

n synchronizes all CPU and BUS operations.

Figure: Memory read cycle.

n Cycle 2: Read Line (RD) set low (0).

n Cycle 3: CPU waits one cycle for memory to respond.

n Cycle 4: Read Line (RD) goes to 1, indicating that the data

n The diagram describes the steps from creating a source

n Use it to see how your program is compiled.

• assembly language instructions, each

n Information about each

n When a computer architecture is in the design phase, the

n ISA Level defines the interface between the ___________ (high

n Instruction set architectures (ISAs) are measured by several

(1) the amount of space a program requires;

n The operation of the processor is determined by the instructions

n Each instruction must contain the information required by the

Opcode 0000 MOV AX,total

o Main or virtual memory : memory address for both must be

n Each _______________ is represented by a sequence of bits that

It is difficult for the programmer to

n Thus, it has become common practice to use a symbolic

n _________________ are represented by abbreviations, called

What the processor What the

n During instruction execution:

Total = Total + stuff

English: Total is assigned the sum of Total and stuff.

High-Level Language: Total = Total + stuff

A statement in a high-level language is translated

mov eax, Total A1 00404000

Intel Assembly Language: Intel Machine Code:

Data Data Data

o Arithmetic and o Movement of o I/O o Test &

Figure: Categories of instruction types.

n One of the traditional ways in describing processor architecture

What is the maximum

n In most architectures, most instructions have one, two, or three

Example: Program to execute

n Number of addresses per instruction is a basic design decision.

n More addresses: n Fewer addresses:

n The design of an instruction set is very complex because it

n The most important of these fundamental design issues include

o Number of CPU registers available. o Length of opcode field.

translate high-level programs translate

n The CPU does the _ and _______ à contains

Addresses _ __ Logical Data

n A common form of data is or ________.

Destination = target – source