A B C D E

1 1

Compal confidential 2

Schematics Document
Mobile Auburndale rPGA989 with
3 Intel PCH(Ibex Peak-M) core logic 3

2009-04-13

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev

http://laptop-motherboard-schematic.blogspot.com/
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom C alpella DI S LA4743P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: Monday, April 13, 2009 Sheet 1 of 49
A B C D E
 A B C D E

Compal confidential Fan conn Page 6 Calpella Consumer 13.3" UMA +Switchable
CK505 32QFN
Clock Generator
1
Mobile Arrandale SLG8SP585VTR 1

P19
Nvidia 2C CPU + GMCH
PCIE-Express 16X
NB10M-GE page 24,25,26,27
Socket-rPGA989
VRAM DDR3 DDR3 1066/1333 MHz 1.5V DDR3 SO-DIMM X2
BANK 0, 1, 2, 3 P17, 18
LCD Conn.
page 21 UMA Page 6,7,8,9,10
128/512MB
page 28,29 Dis Dis(UMA) Dual Channel
MUX

USB Card Reader

P33
CRT DMI X4
page 20
UMA
Dis Dis(UMA) USB conn x3
MUX P36

2 2

USB2.0 X12
BT Conn
P36

Dis
HDMI Conn. Level Shifter UMA Intel PCH USB Camera
page 23 page 23 P21
Azalia
Ibex Peak-M
SATA Master-1
PCI-E BUS*4 FCBGA 951 Finger print
P36
SATA Slave

Page 11,12,13,14,15,16
Audio CKT
Codec_IDT92HD81 Audio Jack
P34 P35
JMC261 (LAN Mini-Card Mini-Card SPI
New Card
+Card reader) WLAN WWAN
P31 P32 P32 P32 LPC BUS
3 3

P34
SPI ROM 16M
RJ45/11 CONN MX25L1605AM2C-15G
SATA HDD Connector
P31 P30
ENE
KB926 SATA ODD Connector
P30
P38

Touch Pad CONN. Int.KBD

RTC CKT. LED
P39 P38
P21 P36

SPI ROM USB Board Conn

ACCELEROMETER SST25VF080 USB conn x2 P33
ST P27 P37
4 4

K/B backlight Conn Capsense switch Conn

P36
P36

Security Classification Compal Secret Data Compal Electronics, Inc.

2006/02/13 2006/03/10 Title
DC/DC Interface CKT. Issued Date Deciphered Date
Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P38 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev

http://laptop-motherboard-schematic.blogspot.com/
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom C alpella DI S LA4743P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: Monday, April 13, 2009 Sheet 2 of 49
A B C D E
 A

Symbol Note :
Voltage Rails O MEANS ON X MEANS OFF USB assignment:
: means Digital Ground USB-0 Right side
USB-1 Right side
USB-2 Left side(with ESATA)
: means Analog Ground USB-3 X
power USB-4 Camera
plane
USB-5 WLAN
+B +5VALW +1.8V +5VS @ : means just reserve , no build USB-6 Bluetooth
+3VS USB-7 Finger Printer
+3VALW +1.5VS
45@ : means need be mounted when 45 level assy or rework stage. USB-8 MiniCard(WWAN/TV)
+0.9V BATT @ : means need be mounted when 45 level assy or rework stage. USB-9 Express card
State +VCCP USB-10 X
+CPU_CORE
CONN@ : means ME part USB-11 X
+2.5VS SG@ : means stuff when Switchable graphic
+1.8VS
UMA@ : means stuff when UMA skus PCIe assignment:
VRAM@ : X76 level PCIe-1 WWAN
S0 O O O O PCIe-2 WLAN
8111DL@ : Only for Giga LAN PCIe-3 LAN
S1 O O O O DEBUG@ : For debug PCIe-4 New card
PCIe-5 X
S3
Cypress@ : Only For Cypress Capacitor sensor board PCIe-6 X
O O O X
ENE@ : Only For ENE Capacitor sensor board
S5 S4/AC O O X X M3@ : Only For Intel DDR3 VREF SATA assignment:
S5 S4/ Battery only O X X X PA@ : Only For PA SATA0 HDD
SATA1 ODD
S5 S4/AC & Battery PR@ : Only For PR
don't exist X X X X SATA2 X
1
SATA3 X 1

SATA4 ESATA
SATA5 X

SMBUS Control Table PCH I2C / SMBUS ADDRESSING

NB10M NEW
Thermal WLAN Thermal NB10M-GE Cap sensor CARD G sensor
SOURCE XDP BATT Sensor SODIMM CLK CHIP WWAN board
Sensor DEVICE HEX ADDRESS
SMB_EC_CK1
SMB_EC_DA1
KB926 X V X X X X X X V X X DDR SO-DIMM 0 A0 10100000
DDR SO-DIMM 1 A4 10100100
SMB_EC_CK2
SMB_EC_DA2
KB926 X X X X X X X X X X X CLOCK GENERATOR (EXT.) D2 11010010

SMBCLK
SMBDATA
PCH V X X V V V X X X V V 45172932L01ΚSwitchable graphic
45172932L02ΚUMA only
SML0CLK
SML0DATA
PCH X X X X X X X X X X X
SML1CLK
SML1DATA
PCH X X X X X X X X X X X
+3VS +5VL +3VS +3VS +3VALW +5VL +3VALW +3VS

NB10M-GE SMBUS Control Table

SOURCE LVDS CRT HDMI

D_EDID_DATA
D_EDID_CLK
NB10M V X X
D_CRT_DDC_DATA
D_CRT_DDC_DATA
NB10M X V X
HDMIDAT_VGA
HDMICLK_VGA
NB10M X X V
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/28 2006/03/10 Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Do c ument Number Rev

http://laptop-motherboard-schematic.blogspot.com/
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Cu s tom C alpella DI S

Da te:
LA 4743P
Monday, April 13, 2009 Sheet 3 of 49
0 .1
 5 4 3 2 1

60mA
+3VAUX_BT

50mA
Finger printer

25mA +3VS_DVDD
1A ALC268
D
+V_BATTERY Dock con D

20mA
+3VALW_EC
35mA
MDC 1.5 10mA
SPI ROM
169mA
0.3A ICH9 1A
INVPWR_B+ LVDS CON New card
300mA
LAN 811mA
AC VIN PCH
1.7A 5.89A 3.39A
+3VALW +3VS 1.5A
2A +LCDVDD LVDS CON
B++ RT5158
250mA
+3VS_CK505
C
??mA C
Mini card 1A
Mini card (WLAN)
+1.5VS ???A
New card 1A
Mini card (TV tu/WWAN/Robeson)

0.58A 1.3A 35mA +VDDA

+5VALW +5VS IDT 9271B7
B+
7A 10mA
+5VAMP

1.8A
ODD

700mA
B
SATA B
3A
3.7 X 3=11.1V CPU
50mA
DC BATT PC Camera(4.75V)
8 A
1.9A 11.05A DDR3 800Mhz 4G x2
B+++ +1.5V
50mA
+0.75V

162mA
PCH
4.7A
1.05V_B+ +VCCP
??A
CPU

A A
2.59A
+1.05VS PCH

2A 10mA 38A/1.05V
CPU_B+ +VCC_CORE CPU Security Classification
2007/08/28
Compal Secret Data
2006/03/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power delevry
http://laptop-motherboard-schematic.blogspot.com/
Size Do cu me n t Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C Calpella DIS LA4743P 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: Mo n d a y, April 13, 2009 Sheet 4 of 49
5 4 3 2 1
 A

1 1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 2006/03/10 Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Do c ument Number Rev

http://laptop-motherboard-schematic.blogspot.com/
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Cu s tom C alpella DI S

Da te:
LA 4743P
Monday, April 13, 2009 Sheet 5 of 49
0 .1
 5 4 3 2 1
Layout rule Κ 10m il
width trace length < +VCCP
0.5", spacing 20mil JCPU1B
R1 1 2 20_0402_1% C O M P3 AT23
COMP3
A16 C L K _ C P U_BCLK J P1
XDP Connector X D P_TDI @ R2 1 2 51_0402_1%
BCLK C L K _ C P U_BCLK <14>

MISC
R3 1 2 20_0402_1% C O M P2 AT24 B16 C L K _ C P U_BCLK# 1 2 X DP_TMS @ R4 1 2 51_0402_1%
COMP2 BCLK# C L K _ C P U_BCLK# <14> GND0 GND1
X D P _PREQ# 3 4
OBSFN_A0 OBSFN_C0

CLOCKS
R5 1 2 49.9_0402_1% C O M P1 G16 AR30 C L K _ C PU_XDP X D P _ P R DY# 5 6 X D P _PREQ# @ R6 1 2 51_0402_1%
COMP1 BCLK_ITP C L K _ C PU_XDP# OBSFN_A1 OBSFN_C1
AT30 7 8
R7 1 BCLK_ITP# GND2 GND3
2 49.9_0402_1% C O M P0 AT26 X DP_BPM#0 9 10 X D P_TDO R8 1 2 51_0402_1%
COMP0 C L K_EXP X DP_BPM#1 OBSDATA_A0 OBSDATA_C0
E16 C LK_EXP <12> 11 12
PEG_CLK C LK_EXP# OBSDATA_A1 OBSDATA_C1
PEG_CLK#
D16 C LK_EXP# <12> OK 13
GND4 GND5
14 This shall place near CPU
P AD T1 T P _ S KTOCC# AH24 X DP_BPM#2 15 16
SKTOCC# +VCCP X DP_BPM#3 OBSDATA_A2 OBSDATA_C2 X D P_TCK @ R9 1
A18 17 18 2 51_0402_1%
DPLL_REF_SSCLK OBSDATA_A3 OBSDATA_C3
D DPLL_REF_SSCLK#
A17 eDP 19
GND6 GND7
20
D
H _ C A T E RR# AK14 21 22
CATERR# OBSFN_B0 OBSFN_D0

THERMAL
1 23 24
OBSFN_B1 OBSFN_D1
25 26
F6 @ C1 X DP_BPM#4 27 GND8 GND9 28
SM_DRAMRST# D R A M R ST# <17,18> OBSDATA_B0 OBSDATA_D0 +VCCP
R 10 1 2 H _ P E C I_ISO AT15 0 .1U_0402_16V4Z X DP_BPM#5 29 30
<14> H_PECI PECI 2 OBSDATA_B1 OBSDATA_D1
0_0402_5% AL1 S M _ R COMP0 31 32
SM_RCOMP[0] AM1 S M _ R COMP1 X DP_BPM#6 33 GND10 GND11 34
SM_RCOMP[1] S M _ R COMP2 R 13 X DP_BPM#7 OBSDATA_B2 OBSDATA_D2
AN1 35 36
H _ P R O C HOT# AN26 SM_RCOMP[2] 1K_0402_5% OBSDATA_B3 OBSDATA_D3
<46> H _ P R O C HOT# 37 38
PROCHOT# PM_EXTTS#0 H_CPUPWRGD H _ C P U P W R G D _R GND12 GND13 C L K _ C PU_XDP
AN15 T63 P A D 1 2 39 40
PM_EXT_TS#[0] PWRGOOD/HOOK0 ITPCLK/HOOK4

DDR3
MISC
AP15 PM_EXTTS#1 R 14 1 2 0_0402_5% <13> P M _ P W R B TN#_R P M _ P W R B TN#_R 41 42 C L K _ C PU_XDP# R 17
PM_EXT_TS#[1] P M_EXTTS#1_R <17,18> HOOK1 ITPCLK#/HOOK5
43 44 1K_0402_5%
R 15 H _ P W R G D _XDP R 1 61 VCC_OBS_AB VCC_OBS_CD
<14> H _ T H E R MTRIP# 1 2 H _ T H E R M TRIP#_R AK15 from DDR 2 0_0402_5% 45 46 X D P _RST#_R 1 2 H _ C P U R ST#
0_0402_5% THERMTRIP# HOOK2 RESET#/HOOK6 X D P _ D BRESET#_R 1
47 48 2 X D P _ D BRESET# <13>
49 HOOK3 DBR#/HOOK7 50 R18
X D P _ P R DY# GND14 GND15 X D P_TDO 0_0402_5%
AT28 51 52
PRDY# X D P _PREQ# SDA TD0 X D P_TRST#
AP27 53 54
PREQ# SCL TRST# X D P_TDI
55 56
AN28 X D P_TCK X D P_TCK 57 TCK1 TDI 58 X DP_TMS
H _ C P U R ST# R 19 H _ C P U R S T#_R TCK X DP_TMS TCK0 TMS + 3VS
1 2 AP26 AP28 59 60
RESET_OBS# TMS GND16 GND17

PWR MANAGEMENT
0_0402_5% AT27 X D P_TRST#
TRST#

JTAG & BPM

SAMTE_BSH-030-01-L-D-A C O NN@
R 20 1 2 H _ P M _ S Y N C_R AL15 AT29 X D P _TDI_R X D P _ D BRESET# R 603 1 2 1K_0402_5%
<13> H _ P M _ S Y NC PM_SYNC TDI
0_0402_5% AR27 X D P _TDO_R
TDO X D P_TDI_M
AR29
R 21 TDI_M @ R22
H_CPUPWRGD 1 2S Y S _ A G E N T _PWROK AN14 AP29 X D P_TDO_M X D P _RST#_R 1 2 0_0402_5% P L T_RST# <14,31,32>
0_0402_5% VCCPWRGOOD_1 TDO_M
AN25 X D P _ D BRESET#
R 23 V C C P W R G O OD_0 AN27 DBR#
<14> H _ C P U P W R G D 1 2
0_0402_5% VCCPWRGOOD_0
AJ22 X DP_BPM#0
R 24 1 2 V D D P W R G O O D _R AK13 BPM#[0] AK22 X DP_BPM#1
C<13> P M _ D R A M _ P WRGD 0_0402_5% SM_DRAMPWROK BPM#[1] X DP_BPM#2 C
AK24
From power BPM#[2] AJ24 X DP_BPM#3
BPM#[3] X DP_BPM#4
<44> V T T P W R GOOD AM15 AJ25
VTTPWRGOOD BPM#[4] X DP_BPM#5
AH22
BPM#[5] X DP_BPM#6
AK23
H _ P W R G D _XDP R 25 H _ P W R G D _XDP_R AM26 BPM#[6] X DP_BPM#7
1 2 AH23
0_0402_5% TAPPWRGOOD BPM#[7]

R 26 1 2 P L T_RST#_R AL14 + V C CP
<14> B U F _ PLT_RST# RSTIN#
1.5K_0402_1% PM_EXTTS#0 R27 1 2 10K_0402_5%
1

I C , A U B _ C F D_rPGA,R1P0 PM_EXTTS#1 R29 1 2 10K_0402_5%

R28 C ONN@
750_0402_1%
2

JTAG MAPPING

X D P _TDI_R R30 1 2 0_0402_5% X D P_TDI + 1.5V

V D D P W R G O O D _R R31 1 2 4.75K_0402_1%

X D P_TDO_M @ R32 1 2 0_0402_5% X D P_TDO R33 1 2 12K_0402_1%

+ V C CP
Processor Pullups
2

R34 CRB 0.9 R38 change to 1K

H _ C A T E RR# R 35 1 2 49.9_0402_1% 0_0402_5%

H _ C P U R S T#_R @ R 36 1 2 68_0402_5%
1

B B
H _ P R O C HOT# R 11 2 1 68_0402_5% X D P_TDI_M @ R 3 7 1 2 0_0402_5%

X D P _TDO_R R38 1 2 0_0402_5%

Fan Voltage Control circuit
SI-1 Change to voltage control circuit
DDR3 Compensation Signals + 5 VS
X D P_TRST# R39 1 2 51_0402_1%

S M _ R COMP0 R40 1 2 100_0402_1% + 3VS

1
C2 1
S M _ R COMP1 R41 1 2 24.9_0402_1% 2 .2U_0603_6.3V4Z C3

2
0 .1U_0402_16V4Z
S M _ R COMP2 R42 1 2 130_0402_1% R 678 U 32 2
10K_0402_5% 9 1 2 C ONN@
Thermal Pad VEN JFAN1
8 2
GND VIN + 5 V S _FAN
Layout Note:Please these 7 3 1

1
6 GND VO 4 F A N _ S P E ED 2 1 4
resistors near Processor GND VSET 1 2 G1
F A N _ S P E ED 5 3 5
<37> F A N _ S P E ED GND 3 G2
C 774
1 G 9 9 6 RD1U_TDFN8_3X3 2 .2U_0603_6.3V4Z ACES_85204-03001
C 775 2 + 5VS
1000P_0402_50V7K D1
<37> F A N _ S ET 3
2 Vcc
2
Line to be protected
1
GND
DLPT05-7-F_SOT23-3

A A

S ecurity Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/03/13 Deciphered Date 2009/05/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Auburndale(1/5)-Thermal/XDP
Size D o c u m ent Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
C u s t om Ca lp e lla DI S LA4 743P 0 .1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D a te: Monday, April 13, 2009 Sheet 6 of 49
5 4 3 2 1

http://laptop-motherboard-schematic.blogspot.com/
 5 4 3 2 1

Layout ruleΚ trace

length < 0.5"
J CPU1E

J CPU1A AJ13
EXP_ICOMPI R44 RSVD32
B26 1 2 49.9_0402_1% AJ12
PEG_ICOMPI RSVD33
A26
PEG_ICOMPO
<13> DMI_CRX_PTX_N0 A24 B27 AP25
DMI_RX#[0] PEG_RCOMPO EXP_RBIAS R45 RSVD1
<13> DMI_CRX_PTX_N1 C23 A25 1 2 750_0402_1% AL25 AH25
DMI_RX#[1] PEG_RBIAS RSVD2 RSVD34
<13> DMI_CRX_PTX_N2 B22 PCIE_CRX_GTX_N[0..15] <24> AL24 AK26
DMI_RX#[2] PCIE_CRX_GTX_N0 RSVD3 RSVD35
<13> DMI_CRX_PTX_N3 A21 K35 AL22
DMI_RX#[3] PEG_RX#[0] PCIE_CRX_GTX_N1 + V _ DDR_CPU_REF0 RSVD4
J34 AJ33 AL26
PEG_RX#[1] PCIE_CRX_GTX_N2 RSVD5 RSVD36
<13> DMI_CRX_PTX_P0 B24 J33 AG9 AR2
DMI_RX[0] PEG_RX#[2] PCIE_CRX_GTX_N3 + V _ DDR_CPU_REF1 RSVD6 RSVD_NCTF_37
<13> DMI_CRX_PTX_P1 D23 G35 M27
DMI_RX[1] PEG_RX#[3] RSVD7

DMI
D B23 G32 PCIE_CRX_GTX_N4 L28 AJ26 D
<13> DMI_CRX_PTX_P2 DMI_RX[2] PEG_RX#[4] RSVD8 RSVD38
<13> DMI_CRX_PTX_P3 A22 F34 PCIE_CRX_GTX_N5 J17 AJ27
DMI_RX[3] PEG_RX#[5] PCIE_CRX_GTX_N6 SA_DIMM_VREF RSVD39
F31 H17
PEG_RX#[6] PCIE_CRX_GTX_N7 SB_DIMM_VREF
<13> DMI_CTX_PRX_N0 D24 D35 G25
DMI_TX#[0] PEG_RX#[7] PCIE_CRX_GTX_N8 RSVD11
<13> DMI_CTX_PRX_N1 G24 E33 G17
DMI_TX#[1] PEG_RX#[8] PCIE_CRX_GTX_N9 RSVD12
<13> DMI_CTX_PRX_N2 F23 C33 E31 AP1
DMI_TX#[2] PEG_RX#[9] PCIE_CRX_GTX_N10 RSVD13 RSVD_NCTF_40
<13> DMI_CTX_PRX_N3 H23 D32 E30 AT2
DMI_TX#[3] PEG_RX#[10] PCIE_CRX_GTX_N11 RSVD14 RSVD_NCTF_41
B32
PEG_RX#[11] PCIE_CRX_GTX_N12
<13> DMI_CTX_PRX_P0 D25 C31 AT3
DMI_TX[0] PEG_RX#[12] PCIE_CRX_GTX_N13 RSVD_NCTF_42
<13> DMI_CTX_PRX_P1 F24 B28 AR1
DMI_TX[1] PEG_RX#[13] PCIE_CRX_GTX_N14 RSVD_NCTF_43
<13> DMI_CTX_PRX_P2 E23 B30
DMI_TX[2] PEG_RX#[14] PCIE_CRX_GTX_N15
<13> DMI_CTX_PRX_P3 G23 A31
DMI_TX[3] PEG_RX#[15]
PCIE_CRX_GTX_P[0..15] <24>
J35 PCIE_CRX_GTX_P0 AL28
PEG_RX[0] PCIE_CRX_GTX_P1 CF G0 RSVD45
H34 AM30 AL29
PEG_RX[1] PCIE_CRX_GTX_P2 CF G1 CFG[0] RSVD46
H33 AM28 AP30
PEG_RX[2] PCIE_CRX_GTX_P3 CF G2 CFG[1] RSVD47
<13> FDI_CTX_PRX_N0 E22 F35 AP31 AP32
FDI_TX#[0] PEG_RX[3] PCIE_CRX_GTX_P4 CF G3 CFG[2] RSVD48
<13> FDI_CTX_PRX_N1 D21 G33 AL32 AL27
FDI_TX#[1] PEG_RX[4] PCIE_CRX_GTX_P5 CF G4 CFG[3] RSVD49
<13> FDI_CTX_PRX_N2 D19 E34 AL30 AT31
FDI_TX#[2] PEG_RX[5] PCIE_CRX_GTX_P6 CF G5 CFG[4] RSVD50
<13> FDI_CTX_PRX_N3 D18 F32 AM31 AT32
FDI_TX#[3] PEG_RX[6] PCIE_CRX_GTX_P7 CF G6 CFG[5] RSVD51
<13> FDI_CTX_PRX_N4 G21 D34 AN29 AP33
FDI_TX#[4] PEG_RX[7] CFG[6] RSVD52

PCI EXPRESS -- GRAPHICS

E19 F33 PCIE_CRX_GTX_P8 CF G7 AM32 AR33
<13> FDI_CTX_PRX_N5 FDI_TX#[5] PEG_RX[8] CFG[7] RSVD53
F21 B33 PCIE_CRX_GTX_P9 CF G8 AK32 AT33
<13> FDI_CTX_PRX_N6 FDI_TX#[6] PEG_RX[9] CFG[8] RSVD_NCTF_54
Intel(R) FDI
G18 D31 PCIE_CRX_GTX_P10 CF G9 AK31 AT34

RESERVED
<13> FDI_CTX_PRX_N7 FDI_TX#[7] PEG_RX[10] CFG[9] RSVD_NCTF_55
A32 PCIE_CRX_GTX_P11 CF G10 AK28 AP35
PEG_RX[11] PCIE_CRX_GTX_P12 CF G11 CFG[10] RSVD_NCTF_56
C30 AJ28 AR35
PEG_RX[12] PCIE_CRX_GTX_P13 CF G12 CFG[11] RSVD_NCTF_57
<13> FDI_CTX_PRX_P0 D22 A28 AN30 AR32
FDI_TX[0] PEG_RX[13] PCIE_CRX_GTX_P14 CF G13 CFG[12] RSVD58
<13> FDI_CTX_PRX_P1 C21 B29 AN32
FDI_TX[1] PEG_RX[14] PCIE_CRX_GTX_P15 CF G14 CFG[13]
<13> FDI_CTX_PRX_P2 D20 A30 AJ32
FDI_TX[2] PEG_RX[15] CF G15 CFG[14]
<13> FDI_CTX_PRX_P3 C18 PCIE_CTX_GRX_N[0..15] <24> AJ29 E15
FDI_TX[3] PCIE_CTX_GRX_C_N0 SG@ C4 0.1U_0402_16V4Z PCIE_CTX_GRX_N0 CF G16 CFG[15] RSVD_TP_59
<13> FDI_CTX_PRX_P4 G22 L33 1 2 AJ30 F15
FDI_TX[4] PEG_TX#[0] PCIE_CTX_GRX_C_N1 SG@ C5 0.1U_0402_16V4Z PCIE_CTX_GRX_N1 CF G17 CFG[16] RSVD_TP_60
<13> FDI_CTX_PRX_P5 E20 M35 1 2 AK30 A2
C FDI_TX[5] PEG_TX#[1] PCIE_CTX_GRX_C_N2 SG@ C6 0.1U_0402_16V4Z PCIE_CTX_GRX_N2 CF G18 CFG[17] KEY C
<13> FDI_CTX_PRX_P6 F20 M33 1 2 H16 D15
FDI_TX[6] PEG_TX#[2] PCIE_CTX_GRX_C_N3 SG@ C7 0.1U_0402_16V4Z PCIE_CTX_GRX_N3 RSVD_TP_86 RSVD62
<13> FDI_CTX_PRX_P7 G19 M30 1 2 C15
FDI_TX[7] PEG_TX#[3] PCIE_CTX_GRX_C_N4 SG@ C8 0.1U_0402_16V4Z PCIE_CTX_GRX_N4 RSVD63 @ R48
L31 1 2 AJ15 1 2 0_0402_5%
PEG_TX#[4] PCIE_CTX_GRX_C_N5 SG@ C9 0.1U_0402_16V4Z PCIE_CTX_GRX_N5 RSVD64 @ R49
<13> F DI_ F S YNC0 F17 K32 1 2 AH15 1 2 0_0402_5%
FDI_FSYNC[0] PEG_TX#[5] PCIE_CTX_GRX_C_N6 SG@ C10 0.1U_0402_16V4Z PCIE_CTX_GRX_N6 RSVD65
<13> F DI_ F S YNC1 E17 M29 1 2
FDI_FSYNC[1] PEG_TX#[6] PCIE_CTX_GRX_C_N7 SG@ C11 0.1U_0402_16V4Z PCIE_CTX_GRX_N7
J31 1 2 B19
PEG_TX#[7] PCIE_CTX_GRX_C_N8 SG@ C12 0.1U_0402_16V4Z PCIE_CTX_GRX_N8 RSVD15
<13> F DI_INT C17 K29 1 2 A19
FDI_INT PEG_TX#[8] PCIE_CTX_GRX_C_N9 SG@ C13 0.1U_0402_16V4Z PCIE_CTX_GRX_N9 RSVD16
H30 1 2
PEG_TX#[9] PCIE_CTX_GRX_C_N10 SG@ C14 0.1U_0402_16V4Z PCIE_CTX_GRX_N10 @ R50
<13> F DI_ L SYNC0 F18 H29 1 2 1 2 0_0402_5% A20
FDI_LSYNC[0] PEG_TX#[10] PCIE_CTX_GRX_C_N11 SG@ C15 0.1U_0402_16V4Z PCIE_CTX_GRX_N11 @ R51 RSVD17
<13> F DI_ L SYNC1 D17 F29 1 2 1 2 0_0402_5% B20
FDI_LSYNC[1] PEG_TX#[11] PCIE_CTX_GRX_C_N12 SG@ C16 0.1U_0402_16V4Z PCIE_CTX_GRX_N12 RSVD18
E28 1 2 AA5
PEG_TX#[12] PCIE_CTX_GRX_C_N13 SG@ C17 0.1U_0402_16V4Z PCIE_CTX_GRX_N13 RSVD_TP_66
D29 1 2 U9 AA4
PEG_TX#[13] PCIE_CTX_GRX_C_N14 SG@ C18 0.1U_0402_16V4Z PCIE_CTX_GRX_N14 RSVD19 RSVD_TP_67
D27 1 2 T9 R8
PEG_TX#[14] PCIE_CTX_GRX_C_N15 SG@ C19 0.1U_0402_16V4Z PCIE_CTX_GRX_N15 RSVD20 RSVD_TP_68
C26 1 2 AD3
PEG_TX#[15] RSVD_TP_69
PCIE_CTX_GRX_P[0..15] <24> AC9 AD2
PCIE_CTX_GRX_C_P0 SG@ C20 0.1U_0402_16V4Z PCIE_CTX_GRX_P0 RSVD21 RSVD_TP_70
L34 1 2 AB9 AA2
PEG_TX[0] PCIE_CTX_GRX_C_P1 SG@ C21 0.1U_0402_16V4Z PCIE_CTX_GRX_P1 RSVD22 RSVD_TP_71
M34 1 2 AA1
PEG_TX[1] PCIE_CTX_GRX_C_P2 SG@ C22 0.1U_0402_16V4Z PCIE_CTX_GRX_P2 RSVD_TP_72
M32 1 2 R9
PEG_TX[2] PCIE_CTX_GRX_C_P3 SG@ C23 0.1U_0402_16V4Z PCIE_CTX_GRX_P3 RSVD_TP_73
L30 1 2 AG7
PEG_TX[3] PCIE_CTX_GRX_C_P4 SG@ C24 0.1U_0402_16V4Z PCIE_CTX_GRX_P4 RSVD_TP_74
M31 1 2 C1 AE3
PEG_TX[4] PCIE_CTX_GRX_C_P5 SG@ C25 0.1U_0402_16V4Z PCIE_CTX_GRX_P5 RSVD_NCTF_23 RSVD_TP_75
K31 1 2 A3
PEG_TX[5] PCIE_CTX_GRX_C_P6 SG@ C26 0.1U_0402_16V4Z PCIE_CTX_GRX_P6 RSVD_NCTF_24
M28 1 2
PEG_TX[6] PCIE_CTX_GRX_C_P7 SG@ C27 0.1U_0402_16V4Z PCIE_CTX_GRX_P7
H31 1 2 V4
PEG_TX[7] PCIE_CTX_GRX_C_P8 SG@ C28 0.1U_0402_16V4Z PCIE_CTX_GRX_P8 RSVD_TP_76
K28 1 2 V5
PEG_TX[8] PCIE_CTX_GRX_C_P9 SG@ C29 0.1U_0402_16V4Z PCIE_CTX_GRX_P9 RSVD_TP_77
G30 1 2 N2
PEG_TX[9] PCIE_CTX_GRX_C_P10 SG@ C30 0.1U_0402_16V4Z PCIE_CTX_GRX_P10 RSVD_TP_78
G29 1 2 J29 AD5
PEG_TX[10] PCIE_CTX_GRX_C_P11 SG@ C31 0.1U_0402_16V4Z PCIE_CTX_GRX_P11 RSVD26 RSVD_TP_79
F28 1 2 J28 AD7
PEG_TX[11] PCIE_CTX_GRX_C_P12 SG@ C32 0.1U_0402_16V4Z PCIE_CTX_GRX_P12 RSVD27 RSVD_TP_80
E27 1 2 W3
PEG_TX[12] PCIE_CTX_GRX_C_P13 SG@ C33 0.1U_0402_16V4Z PCIE_CTX_GRX_P13 RSVD_TP_81
D28 1 2 A34 W2
PEG_TX[13] PCIE_CTX_GRX_C_P14 SG@ C34 0.1U_0402_16V4Z PCIE_CTX_GRX_P14 RSVD_NCTF_28 RSVD_TP_82
C27 1 2 A33 N3
PEG_TX[14] PCIE_CTX_GRX_C_P15 SG@ C35 0.1U_0402_16V4Z PCIE_CTX_GRX_P15 RSVD_NCTF_29 RSVD_TP_83
C25 1 2 AE5
PEG_TX[15] RSVD_TP_84
C35 AD9
B RSVD_NCTF_30 RSVD_TP_85 B
B35
RSVD_NCTF_31
IC,A UB_CFD_rPGA,R1P0 AP34
C ONN@ VSS

IC,A UB_CFD_rPGA,R1P0
C ONN@
CRB 0.9 change to GND

CFG Straps for PROCESSOR

CF G0 @ R52 1 2 3.01K_0402_1% CF G4 @ R53 1 2 3.01K_0402_1%

PCI-Express Configuration Select C F G 4 - Display Port Presence

1: Single PEG 1: D i s abled; No Physical
C FG0 *
0: B i f urcation enabled D isplay Port *
N o t a p p l i cable for Clarksfield Processor a t t a c h e d to Embedded Display Port
A C FG4 0: E n a bled; An external A
CF G3 R54 1 2 3.01K_0402_1% D isplay Port CFG7
WW33 GPD 3.01K on CFG7 for PCIE Jitter
d e v i c e is connected to the WW41Κ don't staff
E m b e d ded Display Port
C F G 3 - P C I Express Static Lane Reversal
1: N o rmal Operation CF G7 @ R55 1 2 3.01K_0402_1%
C FG3 0 : L a n e Numbers Reversed
15 - > 0, 14 ->1, .....
Security Classification Compal Secret Data Compal Electronics, Inc.
Only temporary for early 2008/03/13 2009/05/11 Title
* Issued Date Deciphered Date
CFD samples (rPGA/BGA)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Auburndale(2/5)-DMI/PEG/FDI
Only for pre ES1 sample AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev

http://laptop-motherboard-schematic.blogspot.com/ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom C alpella DI S LA4743P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: Monday, April 13, 2009 Sheet 7 of 49
5 4 3 2 1
 5 4 3 2 1

J CP U1D
J CP U1C

<18> DDR_ B _D[0..63] W8 M _ CLK_DDR2 <18>

D SB_CK[0] D
AA6 M _ CLK_DDR0 <17> W9 M _ CLK_DDR#2 <18>
SA_CK[0] DDR_ B_D0 SB_CK#[0]
<17> DDR_ A _D[0..63] AA7 M _CLK_DDR#0 <17> B5 M3 DDR_CKE2_DIMMB <18>
SA_CK#[0] DDR_ B_D1 SB_DQ[0] SB_CKE[0]
P7 DDR_CKE0_DIMMA <17> A5
DDR_ A_D0 SA_CKE[0] DDR_ B_D2 SB_DQ[1]
A10 C3
DDR_ A_D1 SA_DQ[0] DDR_ B_D3 SB_DQ[2]
C10 B3 V7 M _ CLK_DDR3 <18>
DDR_ A_D2 SA_DQ[1] DDR_ B_D4 SB_DQ[3] SB_CK[1]
C7 E4 V6 M _ CLK_DDR#3 <18>
DDR_ A_D3 SA_DQ[2] DDR_ B_D5 SB_DQ[4] SB_CK#[1]
A7 Y6 M _ CLK_DDR1 <17> A6 M2 DDR_CKE3_DIMMB <18>
DDR_ A_D4 SA_DQ[3] SA_CK[1] DDR_ B_D6 SB_DQ[5] SB_CKE[1]
B10 Y5 M _CLK_DDR#1 <17> A4
DDR_ A_D5 SA_DQ[4] SA_CK#[1] DDR_ B_D7 SB_DQ[6]
D10 P6 DDR_CKE1_DIMMA <17> C4
DDR_ A_D6 SA_DQ[5] SA_CKE[1] DDR_ B_D8 SB_DQ[7]
E10 D1
DDR_ A_D7 SA_DQ[6] DDR_ B_D9 SB_DQ[8]
A8 D2
DDR_ A_D8 SA_DQ[7] DDR _B_D10 SB_DQ[9]
D8 F2 AB8 DDR_CS2_DIMMB# <18>
DDR_ A_D9 SA_DQ[8] DDR _B_D11 SB_DQ[10] SB_CS#[0]
F10 AE2 DDR_CS0_DIMMA# <17> F1 AD6 DDR_CS3_DIMMB# <18>
DDR _A_D10 SA_DQ[9] SA_CS#[0] DDR _B_D12 SB_DQ[11] SB_CS#[1]
E6 AE8 DDR_CS1_DIMMA# <17> C2
DDR _A_D11 SA_DQ[10] SA_CS#[1] DDR _B_D13 SB_DQ[12]
F7 F5
DDR _A_D12 SA_DQ[11] DDR _B_D14 SB_DQ[13]
E9 F3
DDR _A_D13 SA_DQ[12] DDR _B_D15 SB_DQ[14]
B7 G4 AC7 M_ODT2 <18>
DDR _A_D14 SA_DQ[13] DDR _B_D16 SB_DQ[15] SB_ODT[0]
E7 AD8 M_ODT0 <17> H6 AD1 M_ODT3 <18>
DDR _A_D15 SA_DQ[14] SA_ODT[0] DDR _B_D17 SB_DQ[16] SB_ODT[1]
C6 AF9 M_ODT1 <17> G2
DDR _A_D16 SA_DQ[15] SA_ODT[1] DDR _B_D18 SB_DQ[17]
H10 J6
DDR _A_D17 SA_DQ[16] DDR _B_D19 SB_DQ[18]
G8 J3
DDR _A_D18 SA_DQ[17] DDR _B_D20 SB_DQ[19]
K7 G1 DDR_ B _DM[0..7] <18>
DDR _A_D19 SA_DQ[18] DDR _B_D21 SB_DQ[20] DDR _B_DM0
J8 G5 D4
DDR _A_D20 SA_DQ[19] DDR _B_D22 SB_DQ[21] SB_DM[0] DDR _B_DM1
G7 J2 E1
DDR _A_D21 SA_DQ[20] DDR _B_D23 SB_DQ[22] SB_DM[1] DDR _B_DM2
G10 DDR_ A _DM[0..7] <17> J1 H3
DDR _A_D22 SA_DQ[21] DDR _A_DM0 DDR _B_D24 SB_DQ[23] SB_DM[2] DDR _B_DM3
J7 B9 J5 K1
DDR _A_D23 SA_DQ[22] SA_DM[0] DDR _A_DM1 DDR _B_D25 SB_DQ[24] SB_DM[3] DDR _B_DM4
J10 D7 K2 AH1
DDR _A_D24 SA_DQ[23] SA_DM[1] DDR _A_DM2 DDR _B_D26 SB_DQ[25] SB_DM[4] DDR _B_DM5
L7 H7 L3 AL2
DDR _A_D25 SA_DQ[24] SA_DM[2] DDR _A_DM3 DDR _B_D27 SB_DQ[26] SB_DM[5] DDR _B_DM6
M6 M7 M1 AR4
DDR _A_D26 SA_DQ[25] SA_DM[3] DDR _A_DM4 DDR _B_D28 SB_DQ[27] SB_DM[6] DDR _B_DM7
M8 AG6 K5 AT8
DDR _A_D27 SA_DQ[26] SA_DM[4] DDR _A_DM5 DDR _B_D29 SB_DQ[28] SB_DM[7]
L9 AM7 K4
DDR _A_D28 SA_DQ[27] SA_DM[5] DDR _A_DM6 DDR _B_D30 SB_DQ[29]
L6 AN10 M4
C DDR _A_D29 SA_DQ[28] SA_DM[6] DDR _A_DM7 DDR _B_D31 SB_DQ[30] C
K8 AN13 N5
DDR _A_D30 SA_DQ[29] SA_DM[7] DDR _B_D32 SB_DQ[31]
N8 AF3
DDR _A_D31 SA_DQ[30] DDR _B_D33 SB_DQ[32]
P9 AG1 DDR_ B _DQS#[0..7] <18>
DDR _A_D32 SA_DQ[31] DDR _B_D34 SB_DQ[33] DDR _B_DQS#0
AH5 AJ3 D5
DDR _A_D33 SA_DQ[32] DDR _B_D35 SB_DQ[34] SB_DQS#[0] DDR _B_DQS#1
AF5 DDR_ A_DQS#[0..7] <17> AK1 F4
DDR _A_D34 SA_DQ[33] DDR _A_DQS#0 DDR _B_D36 SB_DQ[35] SB_DQS#[1] DDR _B_DQS#2
AK6 C9 AG4 J4
DDR SYSTEM MEMORY A

DDR _A_D35 SA_DQ[34] SA_DQS#[0] DDR _A_DQS#1 DDR _B_D37 SB_DQ[36] SB_DQS#[2] DDR _B_DQS#3
AK7 F8 AG3 L4
DDR _A_D36 SA_DQ[35] SA_DQS#[1] DDR _A_DQS#2 DDR _B_D38 SB_DQ[37] SB_DQS#[3] DDR _B_DQS#4
AF6 J9 AJ4 AH2
SA_DQ[36] SA_DQS#[2] SB_DQ[38] SB_DQS#[4]

DDR SYSTEM MEMORY - B

DDR _A_D37 AG5 N9 DDR _A_DQS#3 DDR _B_D39 AH4 AL4 DDR _B_DQS#5
DDR _A_D38 SA_DQ[37] SA_DQS#[3] DDR _A_DQS#4 DDR _B_D40 SB_DQ[39] SB_DQS#[5] DDR _B_DQS#6
AJ7 AH7 AK3 AR5
DDR _A_D39 SA_DQ[38] SA_DQS#[4] DDR _A_DQS#5 DDR _B_D41 SB_DQ[40] SB_DQS#[6] DDR _B_DQS#7
AJ6 AK9 AK4 AR8
DDR _A_D40 SA_DQ[39] SA_DQS#[5] DDR _A_DQS#6 DDR _B_D42 SB_DQ[41] SB_DQS#[7]
AJ10 AP11 AM6
DDR _A_D41 SA_DQ[40] SA_DQS#[6] DDR _A_DQS#7 DDR _B_D43 SB_DQ[42]
AJ9 AT13 AN2
DDR _A_D42 SA_DQ[41] SA_DQS#[7] DDR _B_D44 SB_DQ[43]
AL10 AK5
DDR _A_D43 SA_DQ[42] DDR _B_D45 SB_DQ[44]
AK12 AK2
DDR _A_D44 SA_DQ[43] DDR _B_D46 SB_DQ[45]
AK8 AM4
DDR _A_D45 SA_DQ[44] DDR _B_D47 SB_DQ[46]
AL7 DDR_ A _DQS[0..7] <17> AM3 DDR_ B _ DQS[0..7] <18>
DDR _A_D46 SA_DQ[45] DDR _A_DQS0 DDR _B_D48 SB_DQ[47] DDR _B_DQS0
AK11 C8 AP3 C5
DDR _A_D47 SA_DQ[46] SA_DQS[0] DDR _A_DQS1 DDR _B_D49 SB_DQ[48] SB_DQS[0] DDR _B_DQS1
AL8 F9 AN5 E3
DDR _A_D48 SA_DQ[47] SA_DQS[1] DDR _A_DQS2 DDR _B_D50 SB_DQ[49] SB_DQS[1] DDR _B_DQS2
AN8 H9 AT4 H4
DDR _A_D49 SA_DQ[48] SA_DQS[2] DDR _A_DQS3 DDR _B_D51 SB_DQ[50] SB_DQS[2] DDR _B_DQS3
AM10 M9 AN6 M5
DDR _A_D50 SA_DQ[49] SA_DQS[3] DDR _A_DQS4 DDR _B_D52 SB_DQ[51] SB_DQS[3] DDR _B_DQS4
AR11 AH8 AN4 AG2
DDR _A_D51 SA_DQ[50] SA_DQS[4] DDR _A_DQS5 DDR _B_D53 SB_DQ[52] SB_DQS[4] DDR _B_DQS5
AL11 AK10 AN3 AL5
DDR _A_D52 SA_DQ[51] SA_DQS[5] DDR _A_DQS6 DDR _B_D54 SB_DQ[53] SB_DQS[5] DDR _B_DQS6
AM9 AN11 AT5 AP5
DDR _A_D53 SA_DQ[52] SA_DQS[6] DDR _A_DQS7 DDR _B_D55 SB_DQ[54] SB_DQS[6] DDR _B_DQS7
AN9 AR13 AT6 AR7
DDR _A_D54 SA_DQ[53] SA_DQS[7] DDR _B_D56 SB_DQ[55] SB_DQS[7]
AT11 AN7
DDR _A_D55 SA_DQ[54] DDR _B_D57 SB_DQ[56]
AP12 AP6
DDR _A_D56 SA_DQ[55] DDR _B_D58 SB_DQ[57]
AM12 AP8
DDR _A_D57 SA_DQ[56] DDR _B_D59 SB_DQ[58]
AN12 DDR_A_MA[0..15] <17> AT9
DDR _A_D58 SA_DQ[57] D DR_A_MA0 DDR _B_D60 SB_DQ[59]
AM13 Y3 AT7
DDR _A_D59 SA_DQ[58] SA_MA[0] D DR_A_MA1 DDR _B_D61 SB_DQ[60]
AT14 W1 AP9
DDR _A_D60 SA_DQ[59] SA_MA[1] D DR_A_MA2 DDR _B_D62 SB_DQ[61]
AT12 AA8 AR10 DDR_B_MA[0..15] <18>
B DDR _A_D61 SA_DQ[60] SA_MA[2] D DR_A_MA3 DDR _B_D63 SB_DQ[62] D DR_B_MA0 B
AL13 AA3 AT10 U5
DDR _A_D62 SA_DQ[61] SA_MA[3] D DR_A_MA4 SB_DQ[63] SB_MA[0] D DR_B_MA1
AR14 V1 V2
DDR _A_D63 SA_DQ[62] SA_MA[4] D DR_A_MA5 SB_MA[1] D DR_B_MA2
AP14 AA9 T5
SA_DQ[63] SA_MA[5] D DR_A_MA6 SB_MA[2] D DR_B_MA3
V8 V3
SA_MA[6] D DR_A_MA7 SB_MA[3] D DR_B_MA4
T1 R1
SA_MA[7] D DR_A_MA8 SB_MA[4] D DR_B_MA5
Y9 <18> DDR_B_BS0 AB1 T8
SA_MA[8] D DR_A_MA9 SB_BS[0] SB_MA[5] D DR_B_MA6
<17> DDR_A_BS0 AC3 U6 <18> DDR_B_BS1 W5 R2
SA_BS[0] SA_MA[9] DDR_A_MA10 SB_BS[1] SB_MA[6] D DR_B_MA7
<17> DDR_A_BS1 AB2 AD4 <18> DDR_B_BS2 R7 R6
SA_BS[1] SA_MA[10] DDR_A_MA11 SB_BS[2] SB_MA[7] D DR_B_MA8
<17> DDR_A_BS2 U7 T2 R4
SA_BS[2] SA_MA[11] DDR_A_MA12 SB_MA[8] D DR_B_MA9
U3 R5
SA_MA[12] DDR_A_MA13 SB_MA[9] DDR_B_MA10
AG8 <18> DDR_B_CAS# AC5 AB5
SA_MA[13] DDR_A_MA14 SB_CAS# SB_MA[10] DDR_B_MA11
T3 <18> DDR_B_RAS# Y7 P3
SA_MA[14] DDR_A_MA15 SB_RAS# SB_MA[11] DDR_B_MA12
<17> DDR_A_CAS# AE1 V9 <18> DDR_B_WE# AC6 R3
SA_CAS# SA_MA[15] SB_WE# SB_MA[12] DDR_B_MA13
<17> DDR_A_RAS# AB3 AF7
SA_RAS# SB_MA[13] DDR_B_MA14
<17> DDR_A_WE# AE9 P5
SA_WE# SB_MA[14] DDR_B_MA15
N1
SB_MA[15]

IC,A UB_CFD_rPGA,R1P0
C ONN@

IC,A UB_CFD_rPGA,R1P0
C ONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/03/13 Deciphered Date 2009/05/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(2/6)-DDR3 A/B CH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev

http://laptop-motherboard-schematic.blogspot.com/
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom C alpella DI S LA4743P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: Monday, April 13, 2009 Sheet 8 of 49
5 4 3 2 1
 5 4 3 2 1

+ V CC_CORE

J CP U1F
+VGA_CORE J CP U1G

AT21
VAXG1

22U_0805_6.3V6M

22U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M
AT19 AR22 VCC_AXG_SENSE
VAXG2 VAXG_SENSE VCC_AXG_SENSE <43>
VSS_AXG_SENSE

SENSE
LINES
AT18 AT22 VSS_AXG_SENSE <43>
+ V CCP VAXG3 VSSAXG_SENSE

C987

C988

C989

C990
48A 18A 1 1 1 1 AT16
VAXG4 15A
AR21
D VAXG5 D
AG35 AH14 AR19
VCC1 VTT0_1 VAXG6

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M
AG34 AH12 AR18
VCC2 VTT0_2 2 2 2 2 VAXG7 GFXVR_VID_0
AG33 AH11 AR16 AM22 GFXVR_VID_0 <43>
VCC3 VTT0_3 VAXG8 GFX_VID[0] GFXVR_VID_1
AG32 AH10 1 1 1 1 AP21 AP22

GRAPHICS VIDs
VCC4 VTT0_4 VAXG9 GFX_VID[1] GFXVR_VID_1 <43>

C40

C41

C42

C43
AG31 J14 AP19 AN22 GFXVR_VID_2
VCC5 VTT0_5 VAXG10 GFX_VID[2] GFXVR_VID_2 <43>
AG30 J13 AP18 AP23 GFXVR_VID_3
VCC6 VTT0_6 VAXG11 GFX_VID[3] GFXVR_VID_3 <43>
AG29 H14 AP16 AM23 GFXVR_VID_4
VCC7 VTT0_7 2 2 2 2 VAXG12 GFX_VID[4] GFXVR_VID_4 <43>

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
AG28 H12 AN21 AP24 GFXVR_VID_5
VCC8 VTT0_8 VAXG13 GFX_VID[5] GFXVR_VID_5 <43>

GRAPHICS
AG27 G14 AN19 AN24 GFXVR_VID_6
VCC9 VTT0_9 VAXG14 GFX_VID[6] GFXVR_VID_6 <43>

C991

C993

C994
AG26 G13 1 1 1 AN18
VCC10 VTT0_10 @ @ @ VAXG15
AF35 G12 AN16
VCC11 VTT0_11 VAXG16

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M
AF34 G11 AM21 AR25 GFXVR_EN
VCC12 VTT0_12 VAXG17 GFX_VR_EN GFXVR_EN <43>
AF33 F14 1 1 1 1 1 AM19 AT25 GFXVR_DPRSLPVR
VCC13 VTT0_13 2 2 2 VAXG18 GFX_DPRSLPVR GFXVR_DPRSLPVR <43>
AF32 F13 AM18 AM24 GFXVR_IMON
VCC14 VTT0_14 VAXG19 GFX_IMON GFXVR_IMON <43>

C48

C49

C50

C51

C52
AF31 F12 AM16
VCC15 VTT0_15 VAXG20
AF30 F11 AL21
VCC16 VTT0_16 2 2 @ 2 @ 2 2 VAXG21 @ R128 2
AF29 E14 AL19 1
VCC17 VTT0_17 VAXG22 1K_0402_5%
AF28 E12 AL18
VCC18 VTT0_18 + V CCP VAXG23

330U_D2_2VY_R7M

330U_D2_2VY_R7M
AF27 D14 AL16
VCC19 VTT0_19 VAXG24
AF26 D13 1 1 AK21 AJ1 +1.5V
VCC20 VTT0_20 VAXG25 VDDQ1

C995

C996

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z
1.1V RAIL POWER

AD35 D12 AK19 AF1

VCC21 VTT0_21 VAXG26 VDDQ2

- 1.5V RAILS
AD34 D11 + + AK18 AE7 1 1 1 1 1
VCC22 VTT0_22 VAXG27 VDDQ3

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

C56

C57

C58

C59

C60
AD33 C14 AK16 AE4
VCC23 VTT0_23 VAXG28 VDDQ4
AD32 C13 1 1 1 AJ21 AC1
VCC24 VTT0_24 2 2 VAXG29 VDDQ5
AD31 C12 AJ19 AB7
VCC25 VTT0_25 VAXG30 VDDQ6 2 2 2 2 2

C61

C62

C63
AD30 C11 AJ18 AB4
VCC26 VTT0_26 VAXG31 VDDQ7
AD29 B14 AJ16 Y1
VCC27 VTT0_27 2 2 2 VAXG32 VDDQ8
AD28 B12 AH21 W7
VCC28 VTT0_28 VAXG33 VDDQ9

POWER
AD27 A14 AH19 3A W4
VCC29 VTT0_29 VAXG34 VDDQ10
AD26 A13 AH18 U1
VCC30 VTT0_30 VAXG35 VDDQ11

330U_D2_2VY_R7M

22U_0805_6.3V6M

22U_0805_6.3V6M
AC35 A12 AH16 T7
VCC31 VTT0_31 VAXG36 VDDQ12
AC34 A11 T4 1
C VCC32 VTT0_32 VDDQ13 C
AC33 P1 1 1
VCC33 + V CCP VDDQ14

C64

C65

C66
AC32 N7 +
VCC34 + V CCP VDDQ15
AC31 N4
VCC35 VDDQ16

DDR3
AC30 AF10 L1
VCC36 VTT0_33 VDDQ17 2 2 2
22U_0805_6.3V6M

22U_0805_6.3V6M

AC29 AE10 J24 H1

VCC37 VTT0_34 VTT1_45 VDDQ18

22U_0805_6.3V6M

22U_0805_6.3V6M

FDI
AC28 AC10 J23
VCC38 VTT0_35 VTT1_46
CPU CORE SUPPLY

AC27 AB10 1 1 H25

VCC39 VTT0_36 VTT1_47
C67

C68

AC26 Y10 1 1
VCC40 VTT0_37

C6 9

C7 0
AA35 W10
VCC41 VTT0_38
AA34 U10 P10 + V CCP
VCC42 VTT0_39 2 2 VTT0_59

10U_0805_6.3V6M

10U_0805_6.3V6M
AA33 T10 N10
VCC43 VTT0_40 2 2 VTT0_60
AA32 J12 L10
VCC44 VTT0_41 VTT0_61
AA31 J11 K10 1 1
VCC45 VTT0_42 VTT0_62

C71

C72
AA30 J16 +VTT_43
VCC46 VTT0_43 +VTT_44 + VCCP
AA29 J15
VCC47 VTT0_44
AA28
VCC48 +VTT_44 R56 + V CCP 2 2
AA27 1 2 0_0603_5%
VCC49

1.1V
AA26 J22
VCC50 +VTT_43 R57 VTT1_63
Y35 1 2 0_0603_5% K26 J20
VCC51 VTT1_48 VTT1_64

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
Y34 J27 J18
VCC52 VTT1_49 VTT1_65

PEG & DMI

Y33 1 1 1 1 J26 H21 + V CCP
VCC53 VTT1_50 VTT1_66

22U_0805_6.3V6M

22U_0805_6.3V6M
C73

C74

C75

C76
Y32 J25 H20
VCC54 VTT1_51 VTT1_67
Y31 H27 H19
VCC55 VTT1_52 VTT1_68
Y30 G28 1 1
VCC56 2 2 2 2 VTT1_53

C77

C78
Y29 G27
VCC57 VTT1_54
Y28 G26
VCC58 VTT1_55
Y27 F26
VCC59 to power VTT1_56 2 2
Y26 E26 L26
VCC60 VTT1_57 VCCPLL1

1.8V
V35 AN33 H_PSI# <46> E25 L27
VCC61 PSI# VTT1_58 VCCPLL2
V34 0.6A M26
POWER

VCC62 VCCPLL3
V33 H_ V ID[0..6] <46>
VCC63 H_ VID0
V32 AK35 +1.8VS
VCC64 VID[0]

22U_0805_6.3V6M
1U_0603_10V4Z

1U_0603_10V4Z

2.2U_0603_6.3V4Z

4.7U_0603_6.3V6K
B H_ VID1 to power B
V31 AK33
VCC65 VID[1] H_ VID2
V30 AK34 1 1 1 1 1
VCC66 VID[2]

C79

C80

C81

C82

C83
V29 AL35 H_ VID3
VCC67 VID[3]
CPU VIDS

V28 AL33 H_ VID4

VCC68 VID[4] H_ VID5
V27 AM33
VCC69 VID[5] 2 2 2 2 2
CPU

V26 AM35 H_ VID6 IC,A UB_CFD_rPGA,R1P0

VCC70 VID[6] PM_DPRSLPVR_R R58
U35 AM34 1 2 0_0402_5% H_ DPRSLPVR <46>
C ONN@
VCC71 PROC_DPRSLPVR
U34
VCC72 to power
U33
VCC73
U32
VCC74
U31 G15 VTT_SELECT <44>
VCC75 VTT_SELECT
U30
VCC76
U29
VCC77
U28
VCC78
H_VTTVID1 = Low, 1.1V(Clarksfield)
U27
VCC79
U26
VCC80 H_VTTVID1 = High, 1.05V(Auburndale)
R35
VCC81
R34
VCC82
R33
VCC83
R32 AN35 IMVP_IMON <46>
VCC84 ISENSE
R31
VCC85 to power
R30
VCC86
R29
VCC87
AJ34 V C CSENSE_R R5 9 0_0402_5% V CCSENSE
SENSE LINES

R28 1 2 V CCSENSE <46>

VCC88 VCC_SENSE
R27 AJ35 VSSSENSE_R R6 0 1 2 0_0402_5% VSSSENSE
VSSSENSE <46>
VCC89 VSS_SENSE
R26
VCC90
P35
VCC91
P34 B15 VTT_SENSE <44>
VCC92 VTT_SENSE VSS_SENSE_VTT R203 1
P33 A15 2 0_0402_5%
VCC93 VSS_SENSE_VTT
P32
VCC94
P31
VCC95
P30
A VCC96 A
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
Near Processor
+ V CC_CORE

V CCSENSE R61 1 2 100_0402_1%

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/03/13 Deciphered Date 2009/05/11 Title
VSSSENSE R62 1 2 100_0402_1%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Auburndale(4/5)-PWR
IC,A UB_CFD_rPGA,R1P0 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev

http://laptop-motherboard-schematic.blogspot.com/
C ONN@ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom C alpella DI S LA4743P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: Monday, April 13, 2009 Sheet 9 of 49
5 4 3 2 1
 5 4 3 2 1

J CP U1H J CP U1I
+ V CC_CORE
CPU CORE
AT20 AE34
VSS1 VSS81

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M
AT17 AE33
VSS2 VSS82
AR31 AE32 K27
VSS3 VSS83 VSS161
AR28 AE31 K9 1 1 1 1 1 1 1 1 1 1 1 1
VSS4 VSS84 VSS162

C84

C85

C86

C87

C88

C89

C90

C91

C92

C93

C94

C95
AR26 AE30 K6
AR24
VSS5
VSS6
VSS85
VSS86
AE29 K3
VSS163
VSS164
Inside cavity
AR23 AE28 J32
VSS7 VSS87 VSS165 2 2 2 2 2 2 2 2 2 2 2 2
AR20 AE27 J30
D VSS8 VSS88 VSS166 D
AR17 AE26 J21
VSS9 VSS89 VSS167
AR15 AE6 J19
VSS10 VSS90 VSS168
AR12 AD10 H35
VSS11 VSS91 VSS169
AR9 AC8 H32
VSS12 VSS92 VSS170
AR6 AC4 H28
VSS13 VSS93 VSS171

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M
AR3 AC2 H26
VSS14 VSS94 VSS172
AP20 AB35 H24
VSS15 VSS95 VSS173

C100
AP17 AB34 H22
VSS16 VSS96 VSS174 1 1 1 1 1 1 1 1 1 1 1 1
between

C96

C97

C98

C99

C101

C102

C103

C104

C105

C106

C107
AP13 AB33 H18
VSS17 VSS97 VSS175
AP10 AB32 H15
AP7
VSS18
VSS19
VSS98
VSS99
AB31 H13
VSS176
VSS177 2 2 2 2 2 2 2 2 2 2 2 2
Inductor and
AP4 AB30 H11
VSS20 VSS100 VSS178
AP2
AN34
VSS21 VSS101
AB29
AB28
H8
H5
VSS179 socket
VSS22 VSS102 VSS180
AN31 AB27 H2
VSS23 VSS103 VSS181
AN23 AB26 G34
VSS24 VSS104 VSS182
AN20 AB6 G31
VSS25 VSS105 VSS183

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M
AN17 AA10 G20
VSS26 VSS106 VSS184

47P_0402_50V8J
AM29 Y8 G9 1 1 1 1
VSS27 VSS107 VSS185
AM27 Y4 G6 1 1 1 1 1 1 1 1 1
VSS28 VSS108 VSS186

C982

C114

C115

C116

C117

C118

C119

C120

C121

C108

C109

C110

C111
AM25 Y2 G3 + + + +
VSS29 VSS109 VSS187
AM20 W35 F30
VSS30 VSS110 VSS188 @
AM17 W34 F27
VSS31 VSS111 VSS189 2 2 2 2 2 2 2 2 2 2 2 2 2
AM14 W33 F25
VSS32 VSS112 VSS190
AM11 W32 F22
VSS33 VSS113 VSS191
AM8 W31 F19
VSS34 VSS114 VSS192
AM5 W30 F16
VSS35 VSS115 VSS193
AM2 W29 E35
VSS36 VSS116 VSS194
AL34 W28 E32
AL31
VSS37
VSS38 VSS VSS117
VSS118
W27 E29
VSS195
VSS196 VSS 470uF 4.5mohm
AL23 W26 E24
VSS39 VSS119 VSS197
AL20 W6 E21
C VSS40 VSS120 VSS198 C
AL17 V10 E18
VSS41 VSS121 VSS199
AL12 U8 E13
VSS42 VSS122 VSS200
AL9 U4 E11
VSS43 VSS123 VSS201
AL6 U2 E8
VSS44 VSS124 VSS202
AL3 T35 E5
VSS45 VSS125 VSS203 VSS_NCTF1_R
AK29 T34 E2 AT35
VSS46 VSS126 VSS204 VSS_NCTF1 VSS_NCTF2_R
AK27 T33 D33 AT1
VSS47 VSS127 VSS205 VSS_NCTF2 VSS_NCTF3_R
AK25 T32 D30 AR34
VSS48 VSS128 VSS206 VSS_NCTF3 VSS_NCTF4_R
AK20 T31 D26 B34
VSS49 VSS129 VSS207 VSS_NCTF4 VSS_NCTF5_R
AK17 T30 D9 B2

NCTF
VSS50 VSS130 VSS208 VSS_NCTF5 VSS_NCTF6_R
AJ31 T29 D6 B1
VSS51 VSS131 VSS209 VSS_NCTF6 VSS_NCTF7_R
AJ23 T28 D3 A35
VSS52 VSS132 VSS210 VSS_NCTF7
AJ20 T27 C34
VSS53 VSS133 VSS211
AJ17 T26 C32
VSS54 VSS134 VSS212
AJ14 T6 C29
VSS55 VSS135 VSS213
AJ11 R10 C28
VSS56 VSS136 VSS214
AJ8 P8 C24
VSS57 VSS137 VSS215
AJ5 P4 C22
VSS58 VSS138 VSS216
AJ2 P2 C20
VSS59 VSS139 VSS217
AH35 N35 C19
VSS60 VSS140 VSS218
AH34 N34 C16
VSS61 VSS141 VSS219
AH33 N33 B31
VSS62 VSS142 VSS220
AH32 N32 B25
VSS63 VSS143 VSS221
AH31 N31 B21
VSS64 VSS144 VSS222
AH30 N30 B18
VSS65 VSS145 VSS223
AH29 N29 B17
VSS66 VSS146 VSS224
AH28 N28 B13
VSS67 VSS147 VSS225
AH27 N27 B11
VSS68 VSS148 VSS226
AH26 N26 B8
VSS69 VSS149 VSS227
AH20 N6 B6
VSS70 VSS150 VSS228
AH17 M10 B4
VSS71 VSS151 VSS229
AH13 L35 A29
B VSS72 VSS152 VSS230 B
AH9 L32 A27
VSS73 VSS153 VSS231
AH6 L29 A23
VSS74 VSS154 VSS232
AH3 L8 A9
VSS75 VSS155 VSS233
AG10 L5
VSS76 VSS156
AF8 L2
VSS77 VSS157
AF4 K34
VSS78 VSS158
AF2 K33
VSS79 VSS159
AE35 K30
VSS80 VSS160

IC,A UB_CFD_rPGA,R1P0 IC,A UB_CFD_rPGA,R1P0

C ONN@ C ONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/03/13 Deciphered Date 2009/05/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Auburndale(5/5)-GND/Bypass
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev

http://laptop-motherboard-schematic.blogspot.com/
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom C alpella DI S LA4743P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: Monday, April 13, 2009 Sheet 10 of 49
5 4 3 2 1
 5 4 3 2 1

I C H _ RTCX1 + R T C V CC + 3VS

R63 1 2 10M_0402_5% I C H _ RTCX2

R65 1 2 1M_0402_5% S M _ I N T R UDER# R64 1 2 10K_0402_5% SIRQ

R66 1 2 330K_0402_5%P C H _ I N T V RMEN

3 2 .768KHZ_12.5PF_Q13MC14610002
@ R67 1 2 1K_0402_5% S B _ S PKR
INTVRMEN
H Κ In tegrated VRM enable LOW=Default
*
1

4
L Κ In tegrated VRM disable
18P_0402_50V8J

18P_0402_50V8J
HIGH=No Reboot*
1 1
OSC

OSC
C 122

C 123
D D
U1A
2 2
NC

NC
Y1

1
+RTCVCC I C H _ RTCX1 B13 D33
RTCX1 FWH0 / LAD0 L P C _AD0 <31,36,37>
C 124 C L R P1 I C H _ RTCX2 D13 B33
2

RTCX2 FWH1 / LAD1 L P C _AD1 <31,36,37>

1 U_0603_10V4Z S H O R T P ADS C32

2
2 FWH2 / LAD2 L P C _AD2 <31,36,37>
A32 L P C _AD3 <31,36,37>
R69 FWH3 / LAD3
1 2 20K_0402_1% I C H _ R T CRST# C14
RTCRST#
C34 L P C _ F RAME# <31,36,37>
R70 FWH4 / LFRAME#
1 2 20K_0402_1% I C H _ S R T CRST# D17
SRTCRST# L D R Q0#
A34

RTC

LPC
1 T13 P AD

1
S M _ I N T R UDER# LDRQ0# L D R Q1#
A16 F34 T14 P AD
C 125 C L R P2 INTRUDER# LDRQ1# / GPIO23
1 U_0603_10V4Z S H O R T P ADS P C H _ I N T V RMEN A14 AB9 SIRQ
SIRQ <37>

2
2 INTVRMEN SERIRQ

R72 1 2 33_0402_5% H D A _ B IT_CLK A30

<33> H D A _ B I T C LK_MDC HDA_BCLK
R73 1 2 33_0402_5% AK7 S A T A_RXN0_C
<33> H D A _ B I T C L K_CODEC SATA0RXN S A T A_RXN0_C <30>
R74 1 2 33_0402_5% H DA_SYNC D29 AK6 S A T A_RXP0_C
<33> HDA_ SYNC_ MDC
R75 1 2 33_0402_5% HDA_SYNC SATA0RXP
AK11 S A TA_TXN0_C C 126 1 2 0.01U_0402_50V7K S ATA_TXN0
S A TA_RXP0_C <30> HDD
<33> H D A _ S Y N C _ C O D EC SATA0TXN S ATA_TXN0 <30>
S B _ S PKR P1 AK9 S ATA_TXP0_C C 127 1 2 0.01U_0402_50V7K SATA_TXP0
<33> S B _ S PKR SPKR SATA0TXP S ATA_TXP0 <30>
1 2 H D A _ R ST# C30
<33> H D A _ R S T #_MDC HDA_RST#
R 77 1 2 33_0402_5% AH6 S A T A_RXN4_C
<33,37> H D A _ R S T # _CODEC SATA1RXN S A T A_RXN4_C <30>
R 78 33_0402_5% AH5 S A T A_RXP4_C
SATA1RXP S A TA_RXP4_C <30>
H D A _ S D IN0 G30 AH9 S A TA_TXN4_C C 130 1 2 0.01U_0402_50V7K S ATA_TXN4
<33> H D A _ S D IN0 HDA_SDIN0 SATA1TXN
AH8 S ATA_TXP4_C C 131 1 2 0.01U_0402_50V7K SATA_TXP4
S ATA_TXN4 <30> ODD
SATA1TXP S ATA_TXP4 <30>
<33> H D A _ S D IN1 H D A _ S D IN1 F30
HDA_SDIN1 AF11
SATA2RXN
E32 AF9

IHDA
HDA_SDIN2 SATA2RXP AF7
C SATA2TXN C
F32 AF6
HDA_SDIN3 SATA2TXP
AH3
R 81 SATA3RXN
<33> H D A _ S D O U T _MDC 1 2 33_0402_5% H D A _ S D OUT B29 AH1
R 82 1 2 33_0402_5% HDA_SDO SATA3RXP
<33> H D A _ S D O U T _ CODEC AF3
SATA3TXN
AF1
@ R 670 1 SATA3TXP
2 100K_0402_5%H D A _ D O C K _EN# H32

SATA
HDA_DOCK_EN# / GPIO33 S A T A_RXN2_C
AD9 S A T A_RXN2_C <35>
SATA4RXN S A T A_RXP2_C
P AD T16 J30 AD8 S A TA_RXP2_C <35>
HDA_DOCK_RST# / GPIO13 SATA4RXP AD6 S A TA_TXN2_C C 128 1 2 0.01U_0402_50V7K S ATA_TXN2
SATA4TXN
AD5 S ATA_TXP2_C C 129 1 2 0.01U_0402_50V7K SATA_TXP2
S ATA_TXN2 <35> E SATA
SATA4TXP S ATA_TXP2 <35>
P C H _ J T AG_TCK M3 AD3
JTAG_TCK SATA5RXN
AD1
P C H _ J TAG_TMS SATA5RXP
K3 AB3
JTAG_TMS SATA5TXN
AB1
P C H _ J TAG_TDI SATA5TXP
K1
JTAG_TDI

JTAG
P C H _ J TAG_TDO J2 AF16
JTAG_TDO SATAICOMPO
P C H _ J TAG_RST# J4 AF15 R89 1 2 37.4_0402_1% + 1.05VS
TRST# SATAICOMPI + 3 V ALW + 3 V ALW + 3 V ALW + 3 V ALW

+ 3VS

2
<36> S P I _ C L K_PCH S P I _ C L K_PCH R 654 1 2 15_0402_5% BA2
SPI_CLK R 85 R 87
R86 R84
R 656 1 2 10K_0402_5% S P I _ SB_CS# S P I _ SB_CS# AV3 R 91 1 2 10K_0402_1% + 3VS @ 200_0402_5% @ 200_0402_5% 20K_0402_5% @ 20K_0402_5%
<36> S P I _ SB_CS# SPI_CS0#
AY3 T3

1
SPI_CS1# SATALED# S A T A_LED# <38>
R 657 1 2 10K_0402_5% S P I _SO_R P C H _ J TAG_TDO P C H _ J TAG_TMS P C H _ J TAG_TDI P C H _ J TAG_RST#

1
<36> S P I _SI S P I_SI R 655 1 2 15_0402_5% AY1 Y9 G PIO21
B SPI_MOSI SATA0GP / GPIO21 R 685 R88 B
R 6 84 R 6 83
SPI

S P I _SO_R AV1 V1 H D D H A L T_LED# @ 100_0402_1% @ 100_0402_1% 10K_0402_1% @ 10K_0402_5%

<36> S P I _ SO_R SPI_MISO SATA1GP / GPIO19 H D D H A L T _LED# <38>

2
I B E X P EAK-M_FCBGA1071

1 2 P C H _ J T AG_TCK
HDA_SDO R90 51_0402_5%
HDA_SYNC This signal has a weak internal pull down.
This signal can't PU
This signal has a weak internal pull down. PCH JTAG Enable PCH JTAG Disable
H=>On Die PLL is supplied by 1.5V Disable iTPM=No Stuff PCH Pin RefDes
L=>On Die PLL is supplied by 1.8V * Enable iTPM=Stuff ES1 ES2 ES1 ES2
* @ B ATT1
R86 No Install 200ohm No Install No Install
PCH_JTAG_TDO
HDA_DOCK_EN# R684 No Install 100ohm No Install No Install
+ R T C V CC + 3VL B ATT1.1
ME debug mode , this signal has a weak internal PU R84 200ohm 200ohm No Install No Install
CR2032 RTC BATTERY PCH_JTAG_TMS
H=>security measures defined in the Flash D3 R683 100ohm 100ohm No Install No Install
* Descriptor will be in effect (default) 2
1 J BATT1 R85 200ohm 200ohm 20Kohm No Install
W=20mils W=20mils 3 R 94 1 2 1K_0402_5% 1 PCH_JTAG_TDI
1
L=>Flash Descriptor Security will be overridden W=20mils 2
2
R685 100ohm 100ohm 10Kohm No Install
1 D A N 2 0 2U_SC70 3
C 132 GND
4
GND
PCH_JTAG_TCK R90 51ohm 51ohm 51ohm 51ohm
2 .2U_0603_6.3V4Z
ACES_85205-02001 R87 20Kohm 20Kohm No Install No Install
A SPI_MOSI 2 Place near IBEX-M C ONN@ PCH_JTAG_RST# A
This signal has a weak internal pull down. R88 10Kohm 10Kohm No Install No Install

* Disable iTPM=No Stuff

Enable iTPM=Stuff
+ 3VS

iTPM ENABLE/DISABLE
+ 3 VS
G PIO21 R 92 2 1 10K_0402_5%
S ecurity Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/03/13 Deciphered Date 2009/05/11 Title
H D D H A L T_LED# R 93 2 1 10K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IBEX-M(1/6)-HDA/JTAG/SATA
@ R 68 1 2 1K_0402_5% S P I_SI Size D o c u m ent Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
C u s t om Ca lp e lla DI S LA4 743P 0 .1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D a te: Monday, April 13, 2009 Sheet 11 of 49
5 4 3 2 1

http://laptop-motherboard-schematic.blogspot.com/
 5 4 3 2 1

E C _ L ID_OUT# R 9 5 1 2 10K_0402_5% + 3 V ALW

S M B CLK R96 1 2 2.2K_0402_5% + 3VS

S M B D ATA R97 1 2 2.2K_0402_5% + 3VS

S M L0CLK R98 1 2 2.2K_0402_5%

+ 3VS
S M L 0DATA R99 1 2 2.2K_0402_5%
R 105 R 1 06
S M L0ALERT# R 100 1 2 10K_0402_5% 2.2K_0402_5% 2.2K_0402_5%

2
S M L1ALERT# R 101 1 2 10K_0402_5% Q 1A
D D
S M L1CLK R 103 1 2 2.2K_0402_5% S M B D ATA 6 1 S M B _DATA_S3
S M B _DATA_S3 <17,18,19,30>

5
S M L 1DATA R 104 1 2 2.2K_0402_5% Q1B 2 N7002DW-7-F_SOT363-6 XDP Ε SODIMM Ε Clock genΕ
ΕG sensor
S M B CLK 3 4 S M B _CLK_S3
S M B _CLK_S3 <17,18,19,30>
U1B 2 N7002DW-7-F_SOT363-6

<31> P C I E _RXN1 P C I E _RXN1 BG30 B9 E C _ L ID_OUT# E C _ L ID_OUT# <37>

P C I E_RXP1 PERN1 SMBALERT# / GPIO11
<31> P C I E_RXP1 BJ30
C 133 1 2 0 .1U_0402_16V4Z P C I E_C_TXN1 PERP1 S M B CLK
WWAN <31> P C IE_TXN1 BF29 H14 S M B CLK <31>
PETN1 SMBCLK
<31> P CIE_TXP1
C 134 1 2 0 .1U_0402_16V4Z P C IE_C_TXP1 BH29
PETP1 WLANΕ WWANΕ New card PCH
C8 S M B D ATA S M B D ATA <31>
P C I E _RXN2 AW30 SMBDATA
<31> P C I E _RXN2 PERN2
<31> P C I E_RXP2 P C I E_RXP2 BA30
C 135 1 2 0 .1U_0402_16V4Z P C I E_C_TXN2 PERP2 S M L0ALERT#
WLAN <31> P C IE_TXN2 BC30 J14
C 136 1 PETN2 SML0ALERT# / GPIO60 + 3VS
<31> P CIE_TXP2 2 0 .1U_0402_16V4Z P C IE_C_TXP2 BD30
PETP2 C6 S M L0CLK
P C I E _RXN3 SML0CLK + 3VS
AU30 For Intel LAN only

SMBus
<32> P C I E _RXN3 PERN3
<32> P C I E_RXP3 P C I E_RXP3 AT30 G8 S M L 0DATA
C 137 1 PERP3 SML0DATA
LAN <32> P C IE_TXN3 2 0 .1U_0402_16V4Z G L A N_C_TXN AU32
C 138 1 PETN3 + 3VS
<32> P CIE_TXP3 2 0 .1U_0402_16V4Z G L AN_C_TXP AV32
PETP3 M14 S M L1ALERT#
P C I E _RXN4 SML1ALERT# / GPIO74 R 681 R 682
<31> P C I E _RXN4 BA32
P C I E_RXP4 PERN4 S M L1CLK R 2 15 0_0402_5% 2.2K_0402_5% 2.2K_0402_5%
<31> P C I E_RXP4 BB32 E10 S M B _ EC_CK2 <37>
C 139 1 PERP4 SML1CLK / GPIO58
New Card <31> P C IE_TXN4 2 0 .1U_0402_16V4Z P C I E_C_TXN4 BD32
PETN4

2
C 140 1 2 0 .1U_0402_16V4Z P C IE_C_TXP4 BE32 G12 S M L 1DATA R 2 31 0_0402_5% S M B _ EC_DA2 <37> Q4A
<31> P CIE_TXP4 PETP4 SML1DATA / GPIO75

PCI-E*
BF33 DTS , read from EC S M B _ EC_DA2 6 1 S M B _ E C_DA2_R
PERN5 S M B _ E C _DA2_R <24>
BH33 T13

Controller

5
BG32 PERP5 CL_CLK1 Q 4B 2 N7002DW-7-F_SOT363-6
C PETN5 Nvidisa thermall sensor C
BJ32 T11
R 4 05 1 2 10K_0402_5% C L K R E Q _ W W AN#_R PETP5 CL_DATA1 S M B _ EC_CK2 3 4 S M B _ E C_CK2_R

Link
+ 3 VALW S M B _ E C _CK2_R <24>
BA34 T9
PERN6 CL_RST1# 2 N7002DW-7-F_SOT363-6
AW34
R 4 11 1 2 10K_0402_5% C L K R E Q _ WLAN# PERP6
+ 3 VS BC34 P E G _ CLKREQ# <14>
PETN6
BD34
PETP6 P E G _ C LKREQ# R 102 1
H1 2 10K_0402_5%
R 6 77 1 2 10K_0402_5% C L K R E Q_LAN# PEG_A_CLKRQ# / GPIO47
+ 3 VS AT34
PERN7
AU34
AU36 PERP7 AD43 L _ C L K_PCIE_VGA# R 604 1 2 0_0402_5%
PETN7 CLKOUT_PEG_A_N C L K _ PCIE_VGA# <24>
+ 3 VALW R 4 15 1 2 10K_0402_5% C L K R EQ_EXP#_R AV36 AD45 L _ C L K_PCIE_VGA R 605 1 2 0_0402_5% OK
PETP7 CLKOUT_PEG_A_P C L K _ P CIE_VGA <24>
BG34 AN4 C LK_EXP# < 6>
PERN8 CLKOUT_DMI_N

PEG
BJ34
PERP8 CLKOUT_DMI_P
AN2 C LK_EXP <6> OK
BG36
PETN8
BJ36
PETP8 C L K _DP#
AT1 T71 P AD
CLKOUT_DP_N / CLKOUT_BCLK1_N AT3 C L K _ DP
CLKOUT_DP_P / CLKOUT_BCLK1_P T72 P AD
R 107 1 2 0_0402_5% C L K _ P C I E _ W WAN#_R AK48
<31> C L K _ P C I E _ WWAN# CLKOUT_PCIE0N
OK WWAN R 108 1 2 0_0402_5% C L K _ P C I E _ W WAN_R AK47
<31> C L K _ P C I E _ WWAN CLKOUT_PCIE0P

From CLK BUFFER

AW24 C L K _DMI# <19>
R 80 2 100_0402_5% C L K R E Q _ W W AN#_R CLKIN_DMI_N
<31> C L K R E Q _ W W AN# 1 P9
PCIECLKRQ0# / GPIO73 CLKIN_DMI_P
BA24 C L K _DMI <19> OK

R 109 1 2 0_0402_5% C L K _ P C I E _WLAN#_R AM43 AP3

<31> C L K _ P C I E_WLAN# CLKOUT_PCIE1N CLKIN_BCLK_N C L K _ B U F_BCLK# <19>
OK WLAN R 110 1 2 0_0402_5% C L K _ P C I E _WLAN_R AM45 AP1 OK
<31> C L K _ P C I E_WLAN CLKOUT_PCIE1P CLKIN_BCLK_P C L K _ B U F_BCLK <19>

<31> C L K R E Q _ WLAN# U4 XTAL25_IN

PCIECLKRQ1# / GPIO18
F18 C L K _ B UF_DOT96# <19>
CLKIN_DOT_96N
CLKIN_DOT_96P
E18 C L K _ B UF_DOT96 <19> OK
R 111 1 2 0_0402_5% C L K _ P C IE_LAN#_R AM47 XTAL25_OUT R 113 1 2 1M_0402_5%
<32> C L K _ P CIE_LAN# CLKOUT_PCIE2N
OK LAN R 112 1 2 0_0402_5% C L K _ P C IE_LAN_R AM48
B <32> C L K _ P CIE_LAN CLKOUT_PCIE2P B
AH13 C L K _ B U F _ C KSSCD# <19>
CLKIN_SATA_N / CKSSCD_N Y2
<32> C L K R E Q_LAN# N4
PCIECLKRQ2# / GPIO20 CLKIN_SATA_P / CKSSCD_P
AH12 C L K _ B U F _ C KSSCD <19> OK
1 2
R 114 1 2 0_0402_5% C L K _ PCIE_EXP#_R AH42 P41 OK
<31> C L K _PCIE_EXP# CLKOUT_PCIE3N REFCLK14IN C L K _ 14M_PCH <19>
OK EXP R 115 1 2 0_0402_5% C L K _ PCIE_EXP_R AH41
<31> C L K _ PCIE_EXP CLKOUT_PCIE3P 2 5 M HZ_20P_1BG25000CK1A

18P_0402_50V8J
<31> C L K REQ_EXP# R 83 1 2 100_0402_5% C L K R EQ_EXP#_R A8 J42 OK
PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK C L K _ P CI_FB <14>

18P_0402_50V8J
1 1

C 141

C 142
P AD T57 AM51 AH51 XTAL25_IN
CLKOUT_PCIE4N XTAL25_IN XTAL25_OUT
P AD T58 AM53 AH53
CLKOUT_PCIE4P XTAL25_OUT 2 2
+ 3 V ALW R 756 1 2 10K_0402_5% P C I E C L KREQ4# M9 AF38 R 116 1 2 90.9_0402_1% + 1.05VS
PCIECLKRQ4# / GPIO26 XCLK_RCOMP

P AD T59 AJ50 T45

CLKOUT_PCIE5N CLKOUTFLEX0 / GPIO64
P AD T60 AJ52
CLKOUT_PCIE5P
R 757 1 2 10K_0402_5% P C I E C L KREQ5# H6 P43
Clock Flex

+ 3 V ALW PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65

P AD T61 AK53 T42

CLKOUT_PEG_B_N CLKOUTFLEX2 / GPIO66
P AD T62 AK51
CLKOUT_PEG_B_P
+ 3 V ALW R 606 1 2 10K_0402_5% P E G _ B_CLKRQ# P13 N50
PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67

I B E X PEAK-M_FCBGA1071

A A

S ecurity Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/03/13 Deciphered Date 2009/05/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IBEX-M(2/6)-PCI-E/SMBUS/CLK
Size D o c u m ent Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
C u s t om Ca lp e lla DI S LA4 743P 0 .1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D a te: Monday, April 13, 2009 Sheet 12 of 49
5 4 3 2 1

http://laptop-motherboard-schematic.blogspot.com/
 5 4 3 2 1

R 770 EDID_CLK and EDID_DATA single

end and keep 30 mil with other
1 2 I G P U _BKLT_EN
LVDS signal avoid noise
U 1C 100K_0402_5% U 1D
BA18 F D I _ CTX_PRX_N0 <22> I G P U _ BKLT_EN I G P U _BKLT_EN T48 BJ46
FDI_RXN0 F D I _ CTX_PRX_N0 <7> L_BKLTEN SDVO_TVCLKINN
<7> D M I_CTX_PRX_N0 D M I_CTX_PRX_N0 BC24 BH17 F D I _ CTX_PRX_N1 I _ E N A V DD T47 BG46
DMI0RXN FDI_RXN1 F D I _ CTX_PRX_N1 <7> <21> I _ E N A V DD L_VDD_EN SDVO_TVCLKINP
<7> D M I_CTX_PRX_N1 D M I_CTX_PRX_N1 BJ22 BD16 F D I _ CTX_PRX_N2
DMI1RXN FDI_RXN2 F D I _ CTX_PRX_N2 <7>
<7> D M I_CTX_PRX_N2 D M I_CTX_PRX_N2 AW20 BJ16 F D I _ CTX_PRX_N3 <22> D P S T _ PWM D P S T _ PWM Y48 BJ48
DMI2RXN FDI_RXN3 F D I _ CTX_PRX_N3 <7> L_BKLTCTL SDVO_STALLN
<7> D M I_CTX_PRX_N3 D M I_CTX_PRX_N3 BJ20 BA16 F D I _ CTX_PRX_N4 BG48
DMI3RXN FDI_RXN4 F D I _ CTX_PRX_N4 <7> SDVO_STALLP
BE14 F D I _ CTX_PRX_N5 AB48
FDI_RXN5 F D I _ CTX_PRX_N5 <7> <22> I _ E D I D_CLK L_DDC_CLK
<7> D M I_CTX_PRX_P0 D M I_CTX_PRX_P0 BD24 BA14 F D I _ CTX_PRX_N6 Y45 BF45
DMI0RXP FDI_RXN6 F D I _ CTX_PRX_N6 <7> <22> I _ E D I D _DATA L_DDC_DATA SDVO_INTN
<7> D M I_CTX_PRX_P1 D M I_CTX_PRX_P1 BG22 BC12 F D I _ CTX_PRX_N7 BH45
DMI1RXP FDI_RXN7 F D I _ CTX_PRX_N7 <7> SDVO_INTP
<7> D M I_CTX_PRX_P2 D M I_CTX_PRX_P2 BA20 + 3VS 1 2 AB46
DMI2RXP L_CTRL_CLK

SDVO
<7> D M I_CTX_PRX_P3 D M I_CTX_PRX_P3 BG20 BB18 F D I _CTX_PRX_P0 1 R 771 2 10K_0402_5% V48
DMI3RXP FDI_RXP0 F D I _CTX_PRX_P0 <7> L_CTRL_DATA
BF17 F D I _CTX_PRX_P1 R 772 10K_0402_5%
FDI_RXP1 F D I _CTX_PRX_P1 <7>
D D M I_CRX_PTX_N0 BE22 BC16 F D I _CTX_PRX_P2 R 7731 2 2.37K_0402_1% AP39 T51 D
<7> D M I_CRX_PTX_N0 DMI0TXN FDI_RXP2 F D I _CTX_PRX_P2 <7> LVD_IBG SDVO_CTRLCLK
D M I_CRX_PTX_N1 BF21 BG16 F D I _CTX_PRX_P3 AP41 T53
<7> D M I_CRX_PTX_N1 DMI1TXN FDI_RXP3 F D I _CTX_PRX_P3 <7> LVD_VBG SDVO_CTRLDATA
D M I_CRX_PTX_N2 BD20 AW16 F D I _CTX_PRX_P4 P AD T69
<7> D M I_CRX_PTX_N2 DMI2TXN FDI_RXP4 F D I _CTX_PRX_P4 <7>

Display Port B
D M I_CRX_PTX_N3 BE18 BD14 F D I _CTX_PRX_P5 AT43
<7> D M I_CRX_PTX_N3 DMI3TXN FDI_RXP5 F D I _CTX_PRX_P5 <7> LVD_VREFH
BB14 F D I _CTX_PRX_P6 AT42 BG44
FDI_RXP6 F D I _CTX_PRX_P6 <7> LVD_VREFL DDPB_AUXN
D M I_CRX_PTX_P0 BD22 BD12 F D I _CTX_PRX_P7 Close PCH and mini space 20mil BJ44
<7> D M I_CRX_PTX_P0 DMI0TXP FDI_RXP7 F D I _CTX_PRX_P7 <7> DDPB_AUXP
D M I_CRX_PTX_P1 BH21 AU38
<7> D M I_CRX_PTX_P1 DMI1TXP DDPB_HPD

LVDS
D M I_CRX_PTX_P2 BC20 AV53
<7> D M I_CRX_PTX_P2 DMI2TXP <22> I _ L V DS_ACLK- LVDSA_CLK#
D M I_CRX_PTX_P3 BD18 BJ14 AV51 BD42
<7> D M I_CRX_PTX_P3 DMI3TXP FDI_INT F D I _ I NT <7> <22> I _ L V DS_ACLK+ LVDSA_CLK DDPB_0N
BC42

DMI
FDI
DDPB_0P
BF13 F D I _ F S Y N C 0 <7> <22> I _ LVDS_A0- BB47 BJ42
FDI_FSYNC0 LVDSA_DATA#0 DDPB_1N

Digital Display Interface

+ 1.05VS BH25 BA52 BG42
DMI_ZCOMP <22> I _ LVDS_A1- LVDSA_DATA#1 DDPB_1P
BH13 F D I _ F S Y N C 1 <7> <22> I _ LVDS_A2- AY48 BB40
R 118 1 2 49.9_0402_1% D M I _ I R COMP BF25 FDI_FSYNC1 AV47 LVDSA_DATA#2 DDPB_2N BA40
DMI_IRCOMP LVDSA_DATA#3 DDPB_2P
BJ12 F D I _ L S Y N C0 <7> AW38
FDI_LSYNC0 DDPB_3N
4mil width and place <22> I _ L VDS_A0+ BB48
LVDSA_DATA0 DDPB_3P
BA38
within 500mil of the PCH BG14 F D I _ L S Y N C1 <7> <22> I _ L VDS_A1+ BA50
FDI_LSYNC1 AY49 LVDSA_DATA1
<22> I _ L VDS_A2+ LVDSA_DATA2
AV48 Y49
Checklist0.8 Κ MEPWROK LVDSA_DATA3 DDPC_CTRLCLK
AB49
DDPC_CTRLDATA
can be connect to

Display Port C
PWROK if iAMT disable AP48
AP47 LVDSB_CLK# BE44
LVDSB_CLK DDPC_AUXN
BD44
R 119 1 DDPC_AUXP
<6> X D P _ DBRESET# 2 0_0402_5% S Y S _ R ST# T6 J12 I C H _ P C I E _WAKE#
I C H _ P C I E _WAKE# <31,32> AY53 AV40
SYS_RESET# WAKE# LVDSB_DATA#0 DDPC_HPD
AT49
LVDSB_DATA#1
AU52 BE40
R 365 1 LVDSB_DATA#2 DDPC_0N
<19,46> V G A TE 2 0_0402_5% M6 Y1 P M _ C L K RUN# AT53 BD40
SYS_PWROK CLKRUN# / GPIO32 LVDSB_DATA#3 DDPC_0P BF41
@ R 373 1 DDPC_1N
<37> P M _ P W R OK 2 0_0402_5% System Power Management AY51 BH41
B17 AT48 LVDSB_DATA0 DDPC_1P BD38
@ R 120 2 10K_0402_5% PWROK LVDSB_DATA1 DDPC_2N
1 AU50 BC38
AT51 LVDSB_DATA2 DDPC_2P BB36
R 121 1 LVDSB_DATA3 DDPC_3N
2 0_0402_5% K5 P8 P M _ SUS_STAT#
T17 BA36
@ R 379 1 MEPWROK SUS_STAT# / GPIO61 DDPC_3P
C <37> M _ P W ROK 2 0_0402_5% C
R 122 1 2 10K_0402_5%A10 F3 S U S _ CLK I _ B LUE AA52 U50 H D M I D _ C T RLCLK
LAN_RST# SUSCLK / GPIO62 T18 <22> I _ B LUE CRT_BLUE DDPD_CTRLCLK H D M I D _ C T RLCLK <23>
I _ G R EEN AB53 U52 H D M I D _ C T RLDATA
<22> I _ G R E EN CRT_GREEN DDPD_CTRLDATA H D M I D _ C T RLDATA <23>
I_RED AD53
<22> I _ R E D CRT_RED
P M _ D R A M _ P WRGD D9 E4
<6> P M _ D R A M _ PWRGD DRAMPWROK SLP_S5# / GPIO63 S L P_S5# <37>

Display Port D
<42> R _ E C _ R SMRST# BC46
DDPD_AUXN
<20> I _ C R T _ D DC_CLK V51 BD46
R 123 1 2 P M _ R SMRST# C16 CRT_DDC_CLK DDPD_AUXP T M D S _ B_HPD#
<37> E C _ R S MRST# H7 S L P_S4# <37> <20> I _ C R T _ D D C_DATA V53 AT38 T M D S _ B_HPD# <23>
100_0402_5% RSMRST# SLP_S4# CRT_DDC_DATA DDPD_HPD
R 124 2 1 10K_0402_5% 0_0402_5% BJ40
DDPD_0N T M D S D _DATA0# <23>
+ 3 VALW R 151 1 2 10K_0402_5% M1 P12 1 R 774 2 H S Y NC Y53 BG40
SUS_PWR_DN_ACK / GPIO30 SLP_S3# S L P_S3# <37> <22> I _ C R T _ H S Y NC CRT_HSYNC DDPD_0P T M D S D _DATA0 <23>
1 2 V S YNC Y51 BJ38
<22> I _ C R T _ V S YNC CRT_VSYNC DDPD_1N T M D S D _DATA1# <23>
R 775 0_0402_5% BG38
DDPD_1P T M D S D _DATA1 <23>

CRT
<6> P M _ P W R BTN#_R P5
PWRBTN# SLP_M#
K8 Can be left NC when IAMT is DDPD_2N
BF37 T M D S D _DATA2# <23>
not support on the platfrom CRB0.9 change to 0 ohm AD48
DAC_IREF DDPD_2P
BH37 T M D S D _DATA2 <23>
R 125 1 2 0_0402_5% AB51 BE36
<37> P W R B T N _OUT# CRT_IRTN DDPD_3N T M D S D_CLK# <23>

1K_0402_0.5%
E C _ A C IN P7 N2 BD36
<37> E C _ A C IN ACPRESENT / GPIO31 TP23 DDPD_3P T M D S D _CLK <23>

R 126
I B E X PEAK-M_FCBGA1071
L O W _BAT# A6 BJ10
BATLOW# / GPIO72 PMSYNCH H _ P M _ S Y N C <6>

2
P M _RI# F14 F6 If not using integrated
RI# SLP_LAN# / GPIO29
LAN,signal may be left as NC.
D37 I B E X P EAK-M_FCBGA1071 CRB0.9 change to 1K_0402_0.5%
P M _ P W ROK 2 1 P M _ R SMRST#

C H 751H-40PT_SOD323-2

I _ B LUE 1 2
+ 3 VS R 776 150_0402_1%
I _ G R EEN 1 2
S Y S _ R ST# @ R 133 1 2 10K_0402_5% R 777 150_0402_1%
B I_RED 1 2 B
P M _ C L K RUN# R 129 1 2 8.2K_0402_5% R 778 150_0402_1%

Place the 3 resistors close to IBEX

+ 3 V ALW

L O W _BAT# R 134 1 2 8.2K_0402_5%

Check PM_SLP_LAN#
P M _RI# R 136 1 2 10K_0402_5%

I C H _ P C I E _WAKE# R 137 1 2 1K_0402_5%

E C _ A C IN R 138 2 1 8.2K_0402_5%

A A

S ecurity Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/03/13 Deciphered Date 2009/05/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IBEX-M(3/6)-DMI/GPIO/LVDS
Size D o c u m ent Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
C u s t om Ca lp e lla DI S LA4 743P 0 .1

5 http://laptop-motherboard-schematic.blogspot.com/
4 3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2
D a te: Monday, April 13, 2009
1
Sheet 13 of 49
 5 4 3 2 1

+ 3VS U 1E U 1F
GPIO8
R P3 H40 AY9 This signal has a weak internal
AD0 NV_CE#0 R 1 40 1
P C I _ D EVSEL# 1 8 N34 BD1 pull up ,can't Pull low + 3VS 2 1K_0402_1% P C H _ GPIO0 Y3 AH45 T19 P AD
P C I _ S ERR# AD1 NV_CE#1 BMBUSY# / GPIO0 CLKOUT_PCIE6N
2 7 C44 AP15 AH46 T20 P AD
P C I _ REQ0# AD2 NV_CE#2 D G P U _ E D IDSEL# CLKOUT_PCIE6P
3 6 A38 BD8 <20> D G P U _ E D IDSEL# C38
P C I _ P IRQB# AD3 NV_CE#3 TACH1 / GPIO1
4 5 C36
AD4 GPIO15 D G P U _ H P D_INT#
J34 AV9 <23> D G P U _ H P D_INT# D37
8 .2K_0804_8P4R_5% AD5 NV_DQS0 L Κ Int el ME Crypto Transport TACH2 / GPIO6
A40 BG8 AF48
AD6 NV_DQS1 * CLKOUT_PCIE7N T21 P AD

MISC
D45 Layer Security(TLS) chiper suite <37> E C _ S CI# E C _ S CI# J32 AF47 T22 P AD
R P4 AD7 TACH3 / GPIO7 CLKOUT_PCIE7P
E36 AP7 with no confidentiality
P C I _ REQ1# AD8 NV_DQ0 / NV_IO0 E C _ SMI#
1 8 H48 AP6 <37> E C _ SMI# F10
P C I _ F R AME# 2 7 E40 AD9 NV_DQ1 / NV_IO1 AT6 H Κ Int el ME Crypto Transport GPIO8
P C I _ T R DY# AD10 NV_DQ2 / NV_IO2 P C H _ GPIO12 G A TEA20
3 6 C40 AT9 Layer Security(TLS) chiper suite K9 U2 G A TEA20 <37>
P C I _ P IRQH# AD11 NV_DQ3 / NV_IO3 LAN_PHY_PWR_CTRL / GPIO12 A20GATE
4 5 M48 BB1 with confidentiality
M45 AD12 NV_DQ4 / NV_IO4 AV6 P C H _ GPIO15 T7
D 8 .2K_0804_8P4R_5% AD13 NV_DQ5 / NV_IO5 GPIO15 D
F53 BB3
AD14 NV_DQ6 / NV_IO6 it have weak internal PU 20K D G P U _ H O LD_RST#
M40 BA4 <24> D G P U _ H OLD_RST# AA2 AM3 C L K _ C P U_BCLK# <6>
AD15 NV_DQ7 / NV_IO7 SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N

NVRAM
R P5 M43 BE4 OK
P C I _ REQ3# AD16 NV_DQ8 / NV_IO8 D G P U _ P W R OK
1 8 J36 BB6 F38 AM1 C L K _ C P U_BCLK < 6>
P C I _ P I RQF# AD17 NV_DQ9 / NV_IO9 TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P
2 7 K48
AD18 NV_DQ10 / NV_IO10
BD6 Check list Rev0.8 section1.23.2 If not
P C I _ P ERR# 3 6 F40 BB7 C R _ W A K E# Y7 BG10 P C H _ P E C I_R R 144 1 2 0_0402_5%
AD19 NV_DQ11 / NV_IO11 implemented, the Braidwood interface <32> C R _ W A K E# SCLOCK / GPIO22 PECI H _ P E CI < 6>

GPIO
P C I _ LOCK# 4 5 C42 BC8
AD20 NV_DQ12 / NV_IO12 signals can be left as No Connect (NC). X M I T_OFF K B _ RST#
K46 BJ8 <31> X M I T_OFF H10 T1 K B _ RST# <37>
8 .2K_0804_8P4R_5% AD21 NV_DQ13 / NV_IO13 GPIO24 RCIN#
M51 BJ6
AD22 NV_DQ14 / NV_IO14
J52
AD23 NV_DQ15 / NV_IO15
BG6 Internal VccVRM Option AB12 GPIO27 PROCPWRGD
BE10 H _ C P U P W R G D <6>
+ 3VS

CPU
K51
R P6 AD24 N V _ ALE P C H _ GPIO28
L34 BD3 V13 BD10 H _ T H E RMTRIP#_L 1 2 54.9_0402_1% H _ T H E R MTRIP# <6>
P C I _ P IRQA# AD25 NV_ALE N V _ C LE GPIO28 THRMTRIP# R 146
1 8 F42 AY6

1
P C I _ P IRQD# 2 7 AD26 NV_CLE R 145 1 2 10K_0402_5% H _ S T P_PCI#
J40 + 3VS M11
P C I _ PIRQG# 3 6 G46 AD27 STP_PCI# / GPIO34 R 147
P C I _ P IRQC# AD28 G PIO35 56_0402_5%
4 5 F44 AU2 V6
AD29 NV_RCOMP SATACLKREQ# / GPIO35
M47
AD30

PCI
8 .2K_0804_8P4R_5% H36 AV7 <23,39,45,47> D G P U _ P W R _EN D G P U _ P W R _EN AB7 BA22

2
AD31 NV_RB# SATA2GP / GPIO36 TP1
+VCCP
R P7 J50 AY8 GPIO27 V G A _ PRSNT_L# AB13 AW22
C/BE0# NV_WR#0_RE# SATA3GP / GPIO37 TP2
P C I _ P IRQE# 1 8 G42
C/BE1# NV_WR#1_RE#
AY5 On-Die PLL Voltage Regulator
P C I _STOP# 2 7 H47 This signal has a weak internal pull up G PIO38 V3 BB22
P C I _ I R D Y# C/BE2# SLOAD / GPIO38 TP3
3 6 G34 AV11
D G P U _ SELECT# C/BE3# NV_WE#_CK0 H Κ On-D ie voltage regulator enable G PIO39
4 5 BF5 P3 AY45
P C I _ P IRQA# G38
PIRQA#
NV_WE#_CK1 * L Κ On-Di e PLL Voltage Regulator disable SDATAOUT0 / GPIO39 TP4 + 3VS
8 .2K_0804_8P4R_5% P C I _ P IRQB# H51 P C I E C L KREQ6# H3 AY46
P C I _ P IRQC# PIRQB# U S B 20_N0 PCIECLKRQ6# / GPIO45 TP5
B37 H18 U S B 20_N0 <35>
PIRQC# USBP0N R 166 1
P C I _ P IRQD# A44 J18 U S B20_P0
U S B20_P0 <35> MB P C I E C L KREQ7# F1 AV43 E C _ S CI# 2 10K_0402_5%
PIRQD# USBP0P U S B 20_N1 PCIECLKRQ7# / GPIO46 TP6
A18 U S B 20_N1 <35>
P C I _ REQ0# F51 USBP1N C18 U S B20_P1 G PIO48 AB6 AV45 D G P U _ E D IDSEL# R 167 1 2 10K_0402_5%
REQ0# USBP1P U S B20_P1 <35> MB SDATAOUT1 / GPIO48 TP7
P C I _ REQ1# A46 N20 U S B 20_N2
REQ1# / GPIO50 USBP2N U S B 20_N2 <35>
D G P U _ SELECT# B45 P20 U S B20_P2 MB USB/ESATA P C H _ T EMP_ALERT# AA4 AF13 K B _ RST# R 171 1 2 10K_0402_5%
C <22> D G P U _ S ELECT# REQ2# / GPIO52 USBP2P U S B20_P2 <35> P C H _ T EMP_ALERT# SATA5GP / GPIO49 TP8 C
P C I _ REQ3# M53 J20
REQ3# / GPIO54 USBP3N L20 G PIO57 F8 M18 D G P U _ P W R _EN R 172 1 2 10K_0402_5%
P C I _GNT0# USBP3P U S B 20_N4
DOCK GPIO57 TP9
F48 F20 U S B 20_N4 <21>
GNT0# USBP4N R 173 1
P C I _GNT1# K45 G20 U S B20_P4
U S B20_P4 <21> USB Camera N18 D G P U _ H P D_INT# 2 10K_0402_5%
D G P U _ P W M_SELECT# GNT1# / GPIO51 USBP4P U S B 20_N5 TP10
T70 P A D F36 A20 U S B 20_N5 <31>
GNT2# / GPIO53 USBP5N R 175 1
P C I _GNT3# H53 C20 U S B20_P5
U S B20_P5 <31> WLAN A4 AJ24 V G A _ PRSNT_L# 2 10K_0402_5%
GNT3# / GPIO55 USBP5P U S B 20_N6 VSS_NCTF_1 TP11
M22 A49

NCTF
USBP6N U S B 20_N6 <35> VSS_NCTF_2

RSVD
P C I _ P IRQE# B41 N22 U S B20_P6 BT A5 AK41 D G P U _ H O LD_RST# R 176 1 2 10K_0402_5%
PIRQE# / GPIO2 USBP6P U S B20_P6 <35> VSS_NCTF_3 TP12
P C I _ P I RQF# K53 B21 U S B 20_N7 A50
PIRQF# / GPIO3 USBP7N U S B 20_N7 <35> VSS_NCTF_4
R 150 P C I _ PIRQG# A36 D21 U S B20_P7 Finger print A52 AK42 G PIO38 R 178 1 2 10K_0402_5%
PIRQG# / GPIO4 USBP7P U S B20_P7 <35> VSS_NCTF_5 TP13
A C C E L _INT 2 1 P C I _ P IRQH# A48 H22 U S B 20_N8 A53
<30> A C C E L _INT PIRQH# / GPIO5 USBP8N U S B 20_N8 <31> VSS_NCTF_6
0_0402_5% J22 U S B20_P8 WWAN B2 M32 G A TEA20 R 180 1 2 10K_0402_5%
USBP8P U S B20_P8 <31> VSS_NCTF_7 TP14
USB

K6 E22 U S B 20_N9 B4
<36,37> P C I _RST# PCIRST# USBP9N U S B 20_N9 <31> VSS_NCTF_8
F22 U S B20_P9 New Card B52 N32 P C H _ T EMP_ALERT# R 181 1 2 10K_0402_5%
USBP9P U S B20_P9 <31> VSS_NCTF_9 TP15
P C I _ S ERR# E44 A22 B53
<37> P C I _ S E RR# SERR# USBP10N VSS_NCTF_10
P C I _ P ERR# E50 C22 BE1 M30 G PIO39 R 169 1 2 10K_0402_5%
PERR# USBP10P VSS_NCTF_11 TP16
G24 BE53
GNT2 USBP11N H24 BF1 VSS_NCTF_12 N30 G PIO48 R 170 1 2 10K_0402_5%
P C I _ I R D Y# USBP11P VSS_NCTF_13 TP17
A42 L24 BF53
IRDY# USBP12N VSS_NCTF_14 C R _ W A K E# R 168 1
Default-Internal pull up H44 M24 BH1 H12 2 10K_0402_5%
* P C I _ D EVSEL# F46
PAR
DEVSEL#
USBP12P
USBP13N
A24 BH2
VSS_NCTF_15
VSS_NCTF_16
TP18
Low=Configures DMI for ESI P C I _ F R AME# C46 C24 BH52 AA23 D G P U _ P W R OK R 874 1 2 10K_0402_5%
FRAME# USBP13P VSS_NCTF_17 TP19
compatible operation(for BH53
P C I _ LOCK# VSS_NCTF_18
servers only.Not for D49 BJ1 AB45
PLOCK# U S B R B I AS R 155 1 VSS_NCTF_19 NC_1
B25 2 22.6_0402_1% BJ2
mobile/desktops) P C I _STOP# USBRBIAS# VSS_NCTF_20
D41 BJ4 AB38
P C I _ T R DY# STOP# VSS_NCTF_21 NC_2
C48 D25 Within 500 BJ49
TRDY# USBRBIAS BJ5 VSS_NCTF_22 AB42 INIT3_3V
mils VSS_NCTF_23 NC_3
<37> P C I _PME# M7 BJ50
PME# U S B _ OC#0 VSS_NCTF_24
OC0# / GPIO59
N16 BJ52
VSS_NCTF_25 NC_4
AB41 This signal has weak internal
P L T_RST# D5 J16 U S B _ OC#1 R 156 2 1 0_0402_5% BJ53 PU, can't pull low
<6,31,32> P LT_RST# PLTRST# OC1# / GPIO40 B T _ OFF <35> VSS_NCTF_26
F16 U S B _ OC#2 D1 T39
B N52 OC2# / GPIO41 L16 W X M I T_OFF# D2 VSS_NCTF_27 NC_5 B
CLKOUT_PCI0 OC3# / GPIO42 W X M I T_OFF# <31> VSS_NCTF_28
R _ C L K _ PCI_FB P53 E14 U S B _ OC#4 D53
R _ C L K _ PCI_EC CLKOUT_PCI1 OC4# / GPIO43 U S B _ OC#5 VSS_NCTF_29
P46 G16 E1 P6 T48 P AD
R _ C L K _ D EBUG_PORT_0 CLKOUT_PCI2 OC5# / GPIO9 U S B _ OC#6 VSS_NCTF_30 INIT3_3V#
P51 F12 E53
R _ C L K _ D EBUG_PORT_1 CLKOUT_PCI3 OC6# / GPIO10 U S B _ OC#7 VSS_NCTF_31
P48 T15 C10
CLKOUT_PCI4 OC7# / GPIO14 TP24
I B E X PEAK-M_FCBGA1071 + 3 V ALW
I B E X PEAK-M_FCBGA1071
R 158 1 2 22_0402_5% R _ C L K _ PCI_FB
<12> C L K _ P CI_FB
R 160 1 2 22_0402_5% R _ C L K _ PCI_EC P C I _GNT0# @ R 163 1 2 1K_0402_5% Intel Anti-Theft Techonlogy E C _ SMI# R 157 1 2 10K_0402_5%
<37> C L K _ P CI_EC
R 161 1 2 22_0402_5% R _ C L K _ D EBUG_PORT_0
<36> C L K _ D E BUG_PORT_0
R 162 1 2 22_0402_5% R _ C L K _ D EBUG_PORT_1 P C I _GNT1# @ R 164 1 2 1K_0402_5% High=Endabled P C H _ GPIO15 R 159 1 2 1K_0402_5%
<31> C L K _ D E BUG_PORT_1
NV_ALE
Low=Disable(floating) P C H _ GPIO12 R 811 1 2 10K_0402_5%
Boot BIOS Strap *
NV_ALE P C I E C L KREQ6# R 812 1 2 10K_0402_5%
+ 3 V ALW PCI_GNT0# PCI_GNT1# Boot BIOS + 1.8VS Enable Intel Anti-Theft
RP8
Location Technology Κ 8.2K PU to +3VS P C I E C L KREQ7# R 813 1 2 10K_0402_5%
U S B _ OC#0 4 5 N V _ ALE @ R 1 74 1 2 1K_0402_5%
W X M I T_OFF# 3 6 0 0 LPC Disable Intel Anti-Theft P C H _ GPIO28 R 814 1 2 10K_0402_5%
U S B _ OC#1 2 7 Technology Κ floating(internal PD)
U S B _ OC#2 1 8 0 1 Reserved(NAND) DMI Termination Voltage G PIO57 R 182 1 2 10K_0402_5%
NV_CLE
10K_1206_8P4R_5% 1 0 PCI Set to Vcc when HIGH G PIO35 R 165 2 1 10K_0402_5%
NV_CLE DMI termination voltage. + 3 V S_NV D G P U _ P W R OK
RP9 1 1 SPI Set to Vss when LOW V G A _ PRSNT_L# R 911 1 2 10K_0402_5%
* weak internal PU, don't PD

2 N 7002DW-7-F_SOT363-6
U S B _ OC#6 4 5
U S B _ OC#5 3 6 Weak internal
U S B _ OC#4 2 7 + 3VS
PU,Do not pull low

3
U S B _ OC#7 1 8 R 179 1 2 0_0402_5%

2
N V _ C LE @ R 1 84 1 2 1K_0402_5% Q 29B
10K_1206_8P4R_5% + 3VS
A 1 6 5 A
<12> P E G _ CLKREQ#
P C I _GNT3# @ R 183 1 2 1K_0402_5%

4
5

@U2 Q 29A
1 P L T_RST# 2 N7002DW-7-F_SOT363-6
P

4 IN1
<6> B U F _ PLT_RST# O
A16 swap overide Strap/Top-Block 2
G
1

IN2
Swap Override jumper
S N 7 4 A H C 1 G08DCKR_SC70-5 S ecurity Classification Compal Secret Data Compal Electronics, Inc.
3

Low=A16 swap @ R 1 85 2008/03/13 2009/05/11 Title

100K_0402_5%
Issued Date Deciphered Date
override/Top-Block
PCI_GNT3# Swap Override enabled IBEX-M(4/6)-PCI/USB/RSVD
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
High=Default * Size D o c u m ent Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
C u s t om Ca lp e lla DI S LA4 743P 0 .1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D a te: Monday, April 13, 2009 Sheet 14 of 49
5 4 3 2 1

http://laptop-motherboard-schematic.blogspot.com/
 5 4 3 2 1

+ 1.05VS + V C C P _ V CCA_CLK_L + V C C P _ V C CA_CLK + 3 VS

@ R 186 @ L1 + 1.05VS L 45
1 2 1 2
U1G POWER 2 1

10U_0805_6.3V6M

10U_0805_6.3V6M

0 .1U_0402_16V4Z
1U_0402_6.3V6K

0.01U_0402_25V7K
0_0603_5% AB24 AE50 M U R A TA_BLM18AG601SN1D_0603
VCCCORE[1] VCCADAC[1]

10U_0603_6.3V6M
1U_0402_6.3V6K
10UH_LB2012T100MR_20%_0805 AB26
1 1
U 1J POWER + 1.05VS
1 1 AB28
VCCCORE[2]
VCCCORE[3] 0.069A VCCADAC[2]
AE52 1 1 1

C 143

C 144
AD26
VCCCORE[4]1.524A

1 U_0402_6.3V6K

C 1 45

C 1 46

C 1 47

C 1 48

C 1 49
CRT
AP51 V24 AD28 AF53
@ @ VCCACLK[1] VCCIO[5] V26 AF26 VCCCORE[5] VSSA_DAC[1]
2 2 0.052A VCCIO[6] 1 2 2 VCCCORE[6] 2 2 2

VCC CORE
AP53 Y24 AF28 AF51
VCCACLK[2] VCCIO[7] VCCCORE[7] VSSA_DAC[2]

C 150
Y26 AF30
VCCIO[8] VCCCORE[8]
D
DG1.1 no M3 2
AF31
VCCCORE[9] D
support and not AF23 V28 AH26
VCCLAN[1] VCCSUS3_3[1] VCCCORE[10] + 3VS
0.344A U28 AH28
Intel LAN, VCCLAN VCCSUS3_3[2] VCCCORE[11]
AF24 U26 AH30
VCCLAN[2] VCCSUS3_3[3] U24 AH31 VCCCORE[12] AH38
Source=>GND VCCSUS3_3[4] VCCCORE[13] 0.030A VCCALVDS
P28 AJ30
VCCSUS3_3[5] VCCCORE[14]
1 2 C 152 Y20 P26 AJ31 AH39
0 .1U_0402_16V4Z DCPSUSBYP VCCSUS3_3[6] N28 VCCCORE[15] VSSA_LVDS
VCCSUS3_3[7] R 7 79 1
N26 2 0_0603_5% + 1.8VS
+1.05VS VCCSUS3_3[8] + 1.05VS

0.01U_0603_16V7K

0.01U_0603_16V7K

10U_0805_6.3V6M
AD38 M28 AP43
VCCME[1] VCCSUS3_3[9] + 3 V ALW VCCTX_LVDS[1]
M26 0.059A VCCTX_LVDS[2] AP45
VCCSUS3_3[10]

C 9 98

C 9 99

C 1000
AD39 L28 AT46 1 1 1

USB

LVDS
VCCME[2] VCCSUS3_3[11] VCCTX_LVDS[3]

1U_0402_6.3V6K
1 L26 AK24 AT45
VCCSUS3_3[12] VCCIO[24] VCCTX_LVDS[4]

0 .1U_0402_16V4Z

0 .1U_0402_16V4Z
AD41 J28 + 1.05VS_APLL
VCCME[3] VCCSUS3_3[13]
C 153
J26 1 1 @ R 188 @ L3
VCCSUS3_3[14] 2 2 2

C 157

C 158
AF43 H28 1 2 1 2 BJ24 0.042A
2 VCCME[4] VCCSUS3_3[15] VCCAPLLEXP

10U_0805_6.3V6M
H26 0_0603_5% 10UH_LB2012T100MR_20%_0805 AB34
VCCSUS3_3[16] VCC3_3[2] + 3VS
AF41 0.163AVCCSUS3_3[17] G28
VCCME[5] 2 2
G26 1 AN20 AB35
VCCSUS3_3[18] VCCIO[25] VCC3_3[3]

0 .1U_0402_16V4Z
C 159
AF42 F28 AN22

HVCMOS
VCCME[6] VCCSUS3_3[19] VCCIO[26]
1.998A F26 AN23 AD35
VCCSUS3_3[20] @ VCCIO[27] VCC3_3[4]
V39 E28 AN24 1
VCCME[7] VCCSUS3_3[21] 2 VCCIO[28]

Clock and Miscellaneous

C 160
E26 AN26
VCCSUS3_3[22] VCCIO[29]
V41 C28 AN28
VCCME[8] VCCSUS3_3[23] VCCIO[30]
10U_0805_6.3V6M

10U_0805_6.3V6M

1U_0402_6.3V6K

C26 BJ26
VCCSUS3_3[24] VCCIO[31] 2
1 1 1 V42 B27 BJ28
VCCME[9] VCCSUS3_3[25] VCCIO[32]
A28 AT26
VCCSUS3_3[26] + 1.05VS VCCIO[33]
C 162

C 163

C 161

Y39 A26 AT28

VCCME[10] VCCSUS3_3[27] VCCIO[34] + 1 .8VS
AU26
2 2 2 VCCIO[35]
Y41 U23 AU28
VCCME[11] VCCSUS3_3[28] VCCIO[36]

1U_0402_6.3V6K

1U_0402_6.3V6K
AV26
VCCIO[37]
Y42 V23 + 1.05VS 1 1 AV28 AT24
VCCME[12] VCCIO[56] AW26 VCCIO[38] VCCVRM[2]
VCCIO[39]

C 164

C 165
C I C H _ V 5 R E F_SUS C
>1mA V5REF_SUS
F24 AW28
VCCIO[40] +VCCP

DMI
BA26 AT16
C 166 1 + V C C RTCEXT 2 2 VCCIO[41] VCCDMI[1]
2 V9 BA28 0.061A
DCPRTC VCCIO[42]

1 U_0402_6.3V6K
0 .1U_0402_16V4Z BB26 AU16
VCCIO[43] VCCDMI[2]
BB28 1
VCCIO[44]

C 167
0.035A >1mA K49 I C H _ V 5 R E F _ RUN BC26
V5REF VCCIO[45]

PCI E*
AU24 BC28
PCI/GPIO/LPC

+ 1.8VS VCCVRM[3] VCCIO[46]

BD26
VCCIO[47] 2

10U_0603_6.3V6M
1 U_0402_6.3V6K

1 U_0402_6.3V6K
+ 3VS
0.072A VCC3_3[8]
J38 BD28
VCCIO[48]

0 .1U_0402_16V4Z
BB51 1 1 1 BE26 AM16
+ V 1 . 0 5S_VCCA_A_DPL VCCADPLLA[1] VCCIO[49] VCCPNAND[1]
BB53 L38 BE28 AK16
VCCADPLLA[2] VCC3_3[9] VCCIO[50] VCCPNAND[2]

C 168

C 169

C 170
1 BG26 AK20
VCCIO[51] VCCPNAND[3]

C 171
+ V 1 . 0 5S_VCCA_B_DPL 0.073A M36 BG28 AK19 R 671 1 2 0_0402_5% + 1.8VS
VCC3_3[10] 2 2 2 VCCIO[52] VCCPNAND[4]

0 .1U_0402_16V4Z
+ 1.05VS
BD51
VCCADPLLB[1] 0.357A BH27
VCCIO[53] 0.156A VCCPNAND[5] AK15
BD53 N36 AK13 1
VCCADPLLB[2] VCC3_3[11] 2 VCCPNAND[6]

C 172
AN30 AM12 @ R 672 1 2 0_0402_5% + 3VS
VCCIO[54] VCCPNAND[7]

NAND / SPI
AH23 P36 AN31 AM13
VCCIO[21] VCC3_3[12] VCCIO[55] VCCPNAND[8]
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

AJ35 AM15
VCCIO[22] + 3VS VCCPNAND[9] 2
1 1 1 AH35 U35
VCCIO[23] VCC3_3[13] AN35
+ 3VS VCC3_3[1]
C 173

C 174

C 175

AF34
VCCIO[2] 3.208A C 176 1
AD13 2 0 .1U_0402_16V4Z C 682 1 2 0 .1U_0402_16V4Z
2 2 2 VCC3_3[14] + 3VS
AH34 + 1.8VS AT22 0.035A
VCCIO[3] VCCVRM[1]
AF32 + 1 . 05VS_VCCAPLL + 1 . 05VS_VCCAPLL_L + 1.05VS + 1 . 0 5 V S_VCCFDIPLL BJ18 AM8
VCCIO[4] 1 / 2BA2/2W VCCFDIPLL 6mA VCCME3_3[1]

0 .1U_0402_16V4Z
AK3 @ L4 @ R 189 AM9
VCCSATAPLL[1] VCCME3_3[2]

FDI
1 2 + V C C SST V12 0.032A VCCSATAPLL[2] AK1 1 2 1 2 + 1.05VS AM23 0.085A AP11 1
DCPSST VCCIO[1] VCCME3_3[3]
1U_0402_6.3V6K

C 178
0 .1U_0402_16V4Z 10UH_LB2012T100MR_20%_0805 0_0603_5% AP9
VCCME3_3[4]

10U_0805_6.3V6M
C 177 1
1 2
C 180

C 181
1 2 + V 1 . 1 A _ INT_VCCSUS Y22
0 .1U_0402_16V4Z DCPSUS AH22 I B E X PEAK-M_FCBGA1071
B C 179 VCCIO[9] @ 2 @ B
+ 3 VALW 2
1 / 3BA4/4W P18 AT20 + 1.8VS
+ 1 . 0 5 V S_VCCFDIPLL_L
VCCSUS3_3[29] VCCVRM[4] @ R 190 @ L5
U19 1 2 1 2 + 1 . 0 5 V S_VCCFDIPLL
SATA

VCCSUS3_3[30] + 1.05VS

10U_0805_6.3V6M
+ 1.05VS
PCI/GPIO/LPC

1 2 AH19 0_0603_5% 10UH_LB2012T100MR_20%_0805

0 .1U_0402_16V4Z VCCIO[10]
U20
C 182 VCCSUS3_3[31]
AD20 1
VCCIO[11]
1U_0402_6.3V6K

C 183
U22
VCCSUS3_3[32] AF22
VCCIO[12] 1
+ 3VS @
1 / 5BA4/4W 2
C 1 84

AD19
V15 VCCIO[13] AF20 + 1.05VS + 1.05VS_L + V 1 . 05S_VCCA_A_DPL_L
VCC3_3[5] VCCIO[14] 2 R 191 R 1 92 L6
AF19
VCCIO[15] + V 1 . 0 5S_VCCA_A_DPL
1 2 V16 AH20 1 2 1 2 1 2
VCC3_3[6] VCCIO[16]

1U_0402_6.3V6K

2 2 0U_D2_4VM_R15
0 .1U_0402_16V4Z 0_0603_5% 0_0603_5% 10UH_LB2012T100MR_20%_0805 1
C 185 Y16 AB19 2
VCC3_3[7] VCCIO[17] + 5 V ALW + 3 V ALW + 5 VS + 3VS

C 186
AB20 +
VCCIO[18]

1
C 187
+VCCP AB22
1 / 2BA2/2W VCCIO[19] AD22 + 1.05VS @ R 1 93

2
AT18 VCCIO[20] 1 2 0_0603_5%
V_CPU_IO[1]
0 .1U_0402_16V4Z

0 .1U_0402_16V4Z
4 .7U_0603_6.3V6K

AA34 + P C H _VCC1_1_20 R 194 1 2 0_0402_5% D4 R 197 D5

CPU

VCCME[13] Y34 + P C H _VCC1_1_21 R 195 1 2 0_0402_5% R 196

1 1 1

2
VCCME[14] + P C H _VCC1_1_22 R 198 0_0402_5% + V 1 . 0 5S_VCCA_B_DPL_L 100_0402_5% C H 751H-40PT_SOD323-2 100_0402_5% C H 751H-40PT_SOD323-2
AU18 Y35 1 2
V_CPU_IO[2] VCCME[15]
C 188

C 189

C 190

AA35 + P C H _VCC1_1_23 R 200 1 2 0_0402_5% R 201 L7

1
VCCME[16] + V 1 . 0 5S_VCCA_B_DPL I C H _ V 5 R E F _ RUN
1 2 1 2
2 2 2

1 U_0402_6.3V6K
0_0603_5% 10UH_LB2012T100MR_20%_0805 I C H _ V 5 R E F_SUS
+ R T C V CC

2 2 0U_B_2.5VM_R15M
RTC

A12 2mA 6mA L30 + 3 . 3 A _ 1 .5A_VCCPAZSUS + 3 V ALW 1 20 mils 20 mils

VCCRTC VCCSUSHDA
HDA

1 1 1
1U_0402_6.3V6K

C 192

C 191
+ C 194 C 1 95
1
3 n BA4/4W I B E X PEAK-M_FCBGA1071 1U_0402_6.3V4K_X5R 1U_0402_6.3V4K_X5R
0 .1U_0402_16V4Z

0 .1U_0402_16V4Z

C 1 93

A 2 2 2 2 A
1 1 2
C 196

C 197

2 2

S ecurity Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/03/13 Deciphered Date 2009/05/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IBEX-M(5/6)-PWR
Size D o c u m ent Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
C u s t om Ca lp e lla DI S LA4 743P 0 .1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D a te: Monday, April 13, 2009 Sheet 15 of 49
5 4 3 2 1

http://laptop-motherboard-schematic.blogspot.com/
 5 4 3 2 1

U1I U 1H
AY7 H49 AB16
VSS[159] VSS[259] VSS[0]
B11 H5
VSS[160] VSS[260]
B15 J24 AA19 AK30
VSS[161] VSS[261] VSS[1] VSS[80]
B19 K11 AA20 AK31
VSS[162] VSS[262] VSS[2] VSS[81]
B23 K43 AA22 AK32
VSS[163] VSS[263] VSS[3] VSS[82]
B31 K47 AM19 AK34
B35 VSS[164] VSS[264] K7 AA24 VSS[4] VSS[83] AK35
VSS[165] VSS[265] VSS[5] VSS[84]
B39 L14 AA26 AK38
B43 VSS[166] VSS[266] L18 AA28 VSS[6] VSS[85] AK43
B47 VSS[167] VSS[267] L2 AA30 VSS[7] VSS[86] AK46
D VSS[168] VSS[268] VSS[8] VSS[87] D
B7 L22 AA31 AK49
VSS[169] VSS[269] VSS[9] VSS[88]
BG12 L32 AA32 AK5
VSS[170] VSS[270] VSS[10] VSS[89]
BB12 L36 AB11 AK8
BB16 VSS[171] VSS[271] L40 AB15 VSS[11] VSS[90] AL2
VSS[172] VSS[272] VSS[12] VSS[91]
BB20 L52 AB23 AL52
VSS[173] VSS[273] VSS[13] VSS[92]
BB24 M12 AB30 AM11
BB30 VSS[174] VSS[274] M16 AB31 VSS[14] VSS[93] BB44
VSS[175] VSS[275] VSS[15] VSS[94]
BB34 M20 AB32 AD24
VSS[176] VSS[276] VSS[16] VSS[95]
BB38 N38 AB39 AM20
VSS[177] VSS[277] VSS[17] VSS[96]
BB42 M34 AB43 AM22
VSS[178] VSS[278] VSS[18] VSS[97]
BB49 M38 AB47 AM24
VSS[179] VSS[279] VSS[19] VSS[98]
BB5 M42 AB5 AM26
VSS[180] VSS[280] VSS[20] VSS[99]
BC10 M46 AB8 AM28
VSS[181] VSS[281] VSS[21] VSS[100]
BC14 M49 AC2 BA42
BC18 VSS[182] VSS[282] M5 AC52 VSS[22] VSS[101] AM30
VSS[183] VSS[283] VSS[23] VSS[102]
BC2 M8 AD11 AM31
VSS[184] VSS[284] VSS[24] VSS[103]
BC22 N24 AD12 AM32
VSS[185] VSS[285] VSS[25] VSS[104]
BC32 P11 AD16 AM34
BC36 VSS[186] VSS[286] AD15 AD23 VSS[26] VSS[105] AM35
VSS[187] VSS[287] VSS[27] VSS[106]
BC40 P22 AD30 AM38
VSS[188] VSS[288] VSS[28] VSS[107]
BC44 P30 AD31 AM39
BC52 VSS[189] VSS[289] P32 AD32 VSS[29] VSS[108] AM42
VSS[190] VSS[290] VSS[30] VSS[109]
BH9 P34 AD34 AU20
BD48 VSS[191] VSS[291] P42 AU22 VSS[31] VSS[110] AM46
VSS[192] VSS[292] VSS[32] VSS[111]
BD49 P45 AD42 AV22
VSS[193] VSS[293] VSS[33] VSS[112]
BD5 P47 AD46 AM49
VSS[194] VSS[294] VSS[34] VSS[113]
BE12 R2 AD49 AM7
VSS[195] VSS[295] VSS[35] VSS[114]
BE16 R52 AD7 AA50
VSS[196] VSS[296] VSS[36] VSS[115]
BE20 T12 AE2 BB10
BE24 VSS[197] VSS[297] T41 AE4 VSS[37] VSS[116] AN32
VSS[198] VSS[298] VSS[38] VSS[117]
BE30 T46 AF12 AN50
BE34 VSS[199] VSS[299] T49 Y13 VSS[39] VSS[118] AN52
C VSS[200] VSS[300] VSS[40] VSS[119] C
BE38 T5 AH49 AP12
BE42 VSS[201] VSS[301] T8 AU4 VSS[41] VSS[120] AP42
VSS[202] VSS[302] VSS[42] VSS[121]
BE46 U30 AF35 AP46
VSS[203] VSS[303] VSS[43] VSS[122]
BE48 U31 AP13 AP49
VSS[204] VSS[304] VSS[44] VSS[123]
BE50 U32 AN34 AP5
VSS[205] VSS[305] VSS[45] VSS[124]
BE6 U34 AF45 AP8
VSS[206] VSS[306] VSS[46] VSS[125]
BE8 P38 AF46 AR2
VSS[207] VSS[307] VSS[47] VSS[126]
BF3 V11 AF49 AR52
VSS[208] VSS[308] VSS[48] VSS[127]
BF49 P16 AF5 AT11
BF51 VSS[209] VSS[309] V19 AF8 VSS[49] VSS[128] BA12
VSS[210] VSS[310] VSS[50] VSS[129]
BG18 V20 AG2 AH48
VSS[211] VSS[311] VSS[51] VSS[130]
BG24 V22 AG52 AT32
BG4 VSS[212] VSS[312] V30 AH11 VSS[52] VSS[131] AT36
VSS[213] VSS[313] VSS[53] VSS[132]
BG50 V31 AH15 AT41
VSS[214] VSS[314] VSS[54] VSS[133]
BH11 V32 AH16 AT47
VSS[215] VSS[315] VSS[55] VSS[134]
BH15 V34 AH24 AT7
VSS[216] VSS[316] VSS[56] VSS[135]
BH19 V35 AH32 AV12
BH23 VSS[217] VSS[317] V38 AV18 VSS[57] VSS[136] AV16
VSS[218] VSS[318] VSS[58] VSS[137]
BH31 V43 AH43 AV20
BH35 VSS[219] VSS[319] V45 AH47 VSS[59] VSS[138] AV24
VSS[220] VSS[320] VSS[60] VSS[139]
BH39 V46 AH7 AV30
BH43 VSS[221] VSS[321] V47 AJ19 VSS[61] VSS[140] AV34
VSS[222] VSS[322] VSS[62] VSS[141]
BH47 V49 AJ2 AV38
VSS[223] VSS[323] VSS[63] VSS[142]
BH7 V5 AJ20 AV42
C12 VSS[224] VSS[324] V7 AJ22 VSS[64] VSS[143] AV46
VSS[225] VSS[325] VSS[65] VSS[144]
C50 V8 AJ23 AV49
VSS[226] VSS[326] VSS[66] VSS[145]
D51 W2 AJ26 AV5
E12 VSS[227] VSS[327] W52 AJ28 VSS[67] VSS[146] AV8
VSS[228] VSS[328] VSS[68] VSS[147]
E16 Y11 AJ32 AW14
E20 VSS[229] VSS[329] Y12 AJ34 VSS[69] VSS[148] AW18
VSS[230] VSS[330] VSS[70] VSS[149]
E24 Y15 AT5 AW2
E30 VSS[231] VSS[331] Y19 AJ4 VSS[71] VSS[150] BF9
B E34 VSS[232] VSS[332] Y23 AK12 VSS[72] VSS[151] AW32 B
VSS[233] VSS[333] VSS[73] VSS[152]
E38 Y28 AM41 AW36
VSS[234] VSS[334] VSS[74] VSS[153]
E42 Y30 AN19 AW40
VSS[235] VSS[335] VSS[75] VSS[154]
E46 Y31 AK26 AW52
VSS[236] VSS[336] VSS[76] VSS[155]
E48 Y32 AK22 AY11
VSS[237] VSS[337] VSS[77] VSS[156]
E6 Y38 AK23 AY43
VSS[238] VSS[338] VSS[78] VSS[157]
E8 Y43 AK28 AY47
VSS[239] VSS[339] VSS[79] VSS[158]
F49 Y46
VSS[240] VSS[340] I B E X PEAK-M_FCBGA1071
F5 P49
G10 VSS[241] VSS[341] Y5
G14 VSS[242] VSS[342] Y6
VSS[243] VSS[343]
G18 Y8
G2 VSS[244] VSS[344] P24
VSS[245] VSS[345]
G22 T43
G32 VSS[246] VSS[346] AD51
G36 VSS[247] VSS[347] AT8
VSS[248] VSS[348]
G40 AD47
VSS[249] VSS[349]
G44 Y47
VSS[250] VSS[350]
G52 AT12
AF39 VSS[251] VSS[351] AM6
H16 VSS[252] VSS[352] AT13
VSS[253] VSS[353]
H20 AM5
H30 VSS[254] VSS[354] AK45
VSS[255] VSS[355]
H34 AK39
H38 VSS[256] VSS[356] AV14
VSS[257] VSS[366]
H42
VSS[258]

I B E X PEAK-M_FCBGA1071

A A

S ecurity Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/03/13 Deciphered Date 2009/05/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IBEX-M(6/6)-GND
Size D o c u m ent Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
C u s t om Ca lp e lla DI S LA4 743P 0 .1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D a te: Monday, April 13, 2009 Sheet 16 of 49
5 4 3 2 1

http://laptop-motherboard-schematic.blogspot.com/
 5 4 3 2 1

+ V R E F _ D Q_DIMMA +1.5V + 1.5V

4 B A 2 /6W
<8> D D R _ A _D[0..63] +1.5V
+ V _ D D R _ C P U _REF
<8> D D R _ A _ DM[0..7] + V R E F _ D Q_DIMMA

1
J D I M M1 C O NN@
<8> D D R _ A _ DQS[0..7]
+ V R E F _ D Q_DIMMA 1 2 1 2 V _ D D R _ C P U _ REF R 205
VREF_DQ VSS1 D D R _ A _D4 R 884 0_0402_5% + V _ D D R _ C P U_REF0 1K_0402_1%
3 4 <8> D D R _ A _ DQS#[0..7]
VSS2 DQ4 + V _ D D R _ C P U _REF
0.1U_0402_10V6K

2 .2U_0603_6.3V4Z
D D R _ A _D0 5 6 D D R _ A _D5
DQ0 DQ5
C 1057

C 1058
1 1 D D R _ A _D1 7 8

2
DQ1 VSS3 <8> D D R _ A _MA[0..15]
9 10 D D R _ A _ DQS#0 1 2
D D R _ A _DM0 VSS4 DQS#0 D D R _ A _ DQS0 R 898 0_0402_5%
11 12
13 DM0 DQS0 14 M3 @

1
2 2 D D R _ A _D2 15 VSS5 VSS6 16 D D R _ A _D6
D D D R _ A _D3 DQ2 DQ6 D D R _ A _D7 D
17 18
DQ3 DQ7 R 206
19 20
D D R _ A _D8 VSS7 VSS8 D D R _ A _D12 1K_0402_1%
21 22
D D R _ A _D9 23 DQ8 DQ12 24 D D R _ A _D13

2
DQ9 DQ13
25 26
D D R _ A _ DQS#1 VSS9 VSS10 D D R _ A _DM1
27 28
D D R _ A _ DQS1 29 DQS#1 DM1 30 D R A M R ST#
DQS1 RESET# D R A M R ST# <6,18>
31 32
D D R _ A _D10 VSS11 VSS12 D D R _ A _D14
33 34
D D R _ A _D11 DQ10 DQ14 D D R _ A _D15
35 36
DQ11 DQ15
37 38
D D R _ A _D16 VSS13 VSS14 D D R _ A _D20
39 40
D D R _ A _D17 DQ16 DQ20 D D R _ A _D21
41 42
DQ17 DQ21
43 44
D D R _ A _ DQS#2 45 VSS15 VSS16 46 D D R _ A _DM2
D D R _ A _ DQS2 DQS#2 DM2
47 48
DQS2 VSS17 D D R _ A _D22
49 50
D D R _ A _D18 VSS18 DQ22 D D R _ A _D23
51 52
D D R _ A _D19 53 DQ18 DQ23 54
DQ19 VSS19 D D R _ A _D28
55 56
D D R _ A _D24 VSS20 DQ28 D D R _ A _D29
57 58
D D R _ A _D25 59 DQ24 DQ29 60
DQ25 VSS21 Layout Note:
61 62 D D R _ A _ DQS#3
D D R _ A _DM3 63 VSS22 DQS#3 64 D D R _ A _ DQS3 Pla ce near JP4
DM3 DQS3
65 66
D D R _ A _D26 VSS23 VSS24 D D R _ A _D30
67 68
D D R _ A _D27 DQ26 DQ30 D D R _ A _D31
69 70
DQ27 DQ31
71 72
VSS25 VSS26

+1.5V
<8> D D R _ C K E 0 _DIMMA D D R _ C K E 0 _DIMMA 73 74 D D R _ C K E 1 _DIMMA
C CKE0 CKE1 D D R _ C K E 1 _DIMMA <8> C
75 76
77 VDD1 VDD2 78 D D R _ A_MA15
NC1 A15

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0 .1U_0402_16V4Z

0 .1U_0402_16V4Z

0 .1U_0402_16V4Z

0 .1U_0402_16V4Z
<8> D D R _ A _BS2 D D R _ A _BS2 79 80 D D R _ A_MA14 1
BA2 A14
81 82 1 1 1 1 1 1 1 1 1 1 1
VDD3 VDD4

C 212
D D R _ A_MA12 83 84 D DR_A_MA11 + C 200
A12/BC# A11

C 201

C 203

C 204

C 205

C 206

C 207

C 208

C 209

C 210

C 211
D D R _ A _MA9 85 86 D D R _ A _MA7 3 3 0 U _D2_2VY_R7M
A9 A7
87 88
D D R_A_MA8 VDD5 VDD6 D D R_A_MA6 2 2 2 2 2 2 2 2 2 2 2 2
89 90
D D R _ A _MA5 A8 A6 D D R _ A _MA4
91 92
93 A5 A4 94
D D R _ A _MA3 VDD7 VDD8 D D R _ A _MA2
95 96
D D R _ A _MA1 A3 A2 D D R _ A _MA0
97 98
99 A1 A0 100
M _ C L K _DDR0 VDD9 VDD10 M _ C L K _DDR1
<8> M _ C L K _DDR0 101 102 M _ C L K _DDR1 <8>
M _ C L K _DDR#0 CK0 CK1 M _ C L K _DDR#1
<8> M _ C L K _DDR#0 103 104 M _ C L K _DDR#1 <8>
CK0# CK1#
105 106
D D R _ A_MA10 VDD11 VDD12 D D R _ A _BS1
107 108 D D R _ A _BS1 <8>
D D R _ A _BS0 109 A10/AP BA1 110 D D R _ A _ RAS#
<8> D D R _ A _BS0 BA0 RAS# D D R _ A _ RAS# <8> Layout Note:
111 112
D D R _ A _ WE# 113 VDD13 VDD14 114 D D R _ C S 0 _DIMMA# Place near JP4.203 & JP4.204
<8> D D R _ A _ WE# WE# S0# D D R _ C S 0 _DIMMA# <8>
<8> D D R _ A _ CAS# D D R _ A _ CAS# 115 116 M _ ODT0
CAS# ODT0 M _ ODT0 <8>
117 118
D D R _ A_MA13 VDD15 VDD16 M _ ODT1
119 120 M _ ODT1 <8>
D D R _ C S 1 _DIMMA# A13 ODT1 + V R E F _CA + V _ D D R _ C P U _REF
<8> D D R _ C S 1 _DIMMA# 121 122
123 S1# NC2 124 + 0.75VS
VDD17 VDD18 V _ D D R _ M C H _ REF
125 126 1 2
NCTEST VREF_CA R 877 0_0402_5%
127 128
VSS27 VSS28 0 .1U_0402_16V4Z

2.2U_0402_6.3V6M
D D R _ A _D32 129 130 D D R _ A _D36 1 1
DQ32 DQ36

10U_0805_6.3V6M
1 U_0402_6.3V6K

1 U_0402_6.3V6K

1 U_0402_6.3V6K

1 U_0402_6.3V6K
D D R _ A _D33 131 132 D D R _ A _D37
DQ33 DQ37
C 213

C 214
133 134 1 1 1 1 1
D D R _ A _ DQS#4 VSS29 VSS30 D D R _ A _DM4
135 136
DQS#4 DM4 2 2

C 215

C 216

C 217

C 218

C 202
D D R _ A _ DQS4 137 138
B 139 DQS4 VSS31 140 D D R _ A _D38 B
D D R _ A _D34 VSS32 DQ38 D D R _ A _D39 2 2 2 2 2
141 142
D D R _ A _D35 DQ34 DQ39
143 144
DQ35 VSS33 D D R _ A _D44
145 146
D D R _ A _D40 VSS34 DQ44 D D R _ A _D45
147 148
D D R _ A _D41 DQ40 DQ45
149 150
DQ41 VSS35 D D R _ A _ DQS#5
151 152
D D R _ A _DM5 VSS36 DQS#5 D D R _ A _ DQS5
153 154
DM5 DQS5
155 156
D D R _ A _D42 157 VSS37 VSS38 158 D D R _ A _D46
D D R _ A _D43 159 DQ42 DQ46 160 D D R _ A _D47
DQ43 DQ47
161 162
D D R _ A _D48 163 VSS39 VSS40 164 D D R _ A _D52
D D R _ A _D49 DQ48 DQ52 D D R _ A _D53
165 166
167 DQ49 DQ53 168
D D R _ A _ DQS#6 169 VSS41 VSS42 170 D D R _ A _DM6
D D R _ A _ DQS6 DQS#6 DM6
171 172
DQS6 VSS43 D D R _ A _D54
173 174
D D R _ A _D50 VSS44 DQ54 D D R _ A _D55
175 176
D D R _ A _D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 D D R _ A _D60
D D R _ A _D56 VSS46 DQ60 D D R _ A _D61
181 182
D D R _ A _D57 183 DQ56 DQ61 184
DQ57 VSS47 D D R _ A _ DQS#7
185 186
D D R _ A _DM7 187 VSS48 DQS#7 188 D D R _ A _ DQS7
DM7 DQS7
189 190
D D R _ A _D58 VSS49 VSS50 D D R _ A _D62
191 192
D D R _ A _D59 DQ58 DQ62 D D R _ A _D63
193 194
DQ59 DQ63
1 R 207 2 195 196
10K_0402_5% 197 VSS51 VSS52 198 P M_EXTTS#1_R
SA0 EVENT# PM_EXTTS#1_R <6,18>
199 200 S M B _DATA_S3
+ 3VS VDDSPD SDA S M B _ DATA_S3 <12,18,19,30>
2.2U_0402_6.3V6M

0 .1U_0402_16V4Z

201 202 S M B _CLK_S3

A SA1 SCL S M B _CLK_S3 <12,18,19,30> A
1 1 203 204 + 0.75VS
VTT1 VTT2
1

10K_0402_5%

1 / 7 6 B A1/86W
C 219

C 220

R 208

205 206
2 2
G1
+ 0.75VS
G2
DDR3 SO-DIMM A
REVERSE
2

S ecurity Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/03/13 Deciphered Date 2009/05/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT1
Size D o c u m ent Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
C u s t om Ca lp e lla DI S LA4 743P 0 .1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D a te: Monday, April 13, 2009 Sheet 17 of 49
5 4 3 2 1

http://laptop-motherboard-schematic.blogspot.com/
 5 4 3 2 1

+ 1.5V + 1.5V
<8> D D R _ B _ DQS#[0..7]
4 B A 2 /6W
<8> D D R _ B _ D[0..63]
+ V R E F _ D Q_DIMMB + V R E F _ D Q_DIMMB + V _ D D R _ C P U_REF
<8> D D R _ B _ DM[0..7]
J D I MM2
V _ D D R _ M C H _ REF 1 2 R 885
VREF_DQ VSS1 <8> D D R _ B _ D QS[0..7] + V _ D D R _ C P U_REF1
2.2U_0402_6.3V6M

3 4 D D R _ B _D4 1 2
VSS2 DQ4

0.1U_0402_10V6K
D D R _ B _D0 5 6 D D R _ B _D5 0_0402_5%
DQ0 DQ5 <8> D D R _ B _MA[0..15]
1 1 D D R _ B _D1 7 8
9 DQ1 VSS3 10 D D R _ B _ DQS#0 1 2
VSS4 DQS#0
C 221

C 1059

D D R _ B _DM0 11 12 D D R _ B _ DQS0 R 899 M 3@ 0_0402_5%

13 DM0 DQS0 14
2 2 D D R _ B _D2 15 VSS5 VSS6 16 D D R _ B _D6
D D D R _ B _D3 DQ2 DQ6 D D R _ B _D7 D
17 18
DQ3 DQ7
19 20
D D R _ B _D8 VSS7 VSS8 D D R _ B _D12
21 22
D D R _ B _D9 23 DQ8 DQ12 24 D D R _ B _D13
DQ9 DQ13
25 26
D D R _ B _ DQS#1 VSS9 VSS10 D D R _ B _DM1
27 28
D D R _ B _ DQS1 29 DQS#1 DM1 30 D R A M R ST#
DQS1 RESET# D R A M R ST# <6,17>
31 32
D D R _ B _D10 VSS11 VSS12 D D R _ B _D14
33 34
D D R _ B _D11 DQ10 DQ14 D D R _ B _D15
35 36
DQ11 DQ15
37 38
D D R _ B _D16 VSS13 VSS14 D D R _ B _D20
39 40
D D R _ B _D17 DQ16 DQ20 D D R _ B _D21
41 42
DQ17 DQ21
43 44
D D R _ B _ DQS#2 45 VSS15 VSS16 46 D D R _ B _DM2
D D R _ B _ DQS2 DQS#2 DM2
47 48
DQS2 VSS17 D D R _ B _D22
49 50
D D R _ B _D18 VSS18 DQ22 D D R _ B _D23
51 52
D D R _ B _D19 53 DQ18 DQ23 54
DQ19 VSS19 D D R _ B _D28
55 56
D D R _ B _D24 VSS20 DQ28 D D R _ B _D29
57 58
D D R _ B _D25 59 DQ24 DQ29 60
DQ25 VSS21 D D R _ B _ DQS#3
61 62
D D R _ B _DM3 63 VSS22 DQS#3 64 D D R _ B _ DQS3
DM3 DQS3
65 66
D D R _ B _D26 VSS23 VSS24 D D R _ B _D30
67 68
D D R _ B _D27 DQ26 DQ30 D D R _ B _D31
69 70
DQ27 DQ31
71 72
VSS25 VSS26

<8> D D R _ C K E 2 _DIMMB D D R _ C K E 2 _DIMMB 73 74 D D R _ C K E 3 _DIMMB Layout Note:

C CKE0 CKE1 D D R _ C K E 3 _DIMMB <8> C
75 76
77 VDD1 VDD2 78 D D R _ B_MA15 Pla ce near JP5
D D R _ B _BS2 NC1 A15 D D R _ B_MA14
<8> D D R _ B _BS2 79 80
BA2 A14
81 82
D D R _ B_MA12 VDD3 VDD4 DDR_B_MA11
83 84
D D R _ B _MA9 A12/BC# A11 D D R _ B _MA7
85 86
A9 A7
87 88
D DR_B_MA8 VDD5 VDD6 D DR_B_MA6
89 90
D D R _ B _MA5 A8 A6 D D R _ B _MA4 +1.5V
91 92
93 A5 A4 94
D D R _ B _MA3 VDD7 VDD8 D D R _ B _MA2
95 96
D D R _ B _MA1 A3 A2 D D R _ B _MA0
97 98
A1 A0

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0 .1U_0402_16V4Z

0 .1U_0402_16V4Z

0 .1U_0402_16V4Z

0 .1U_0402_16V4Z
99 100
M _ C L K _DDR2 VDD9 VDD10 M _ C L K _DDR3
<8> M _ C L K _DDR2 101 102 M _ C L K _DDR3 <8> 1 1 1 1 1 1 1 1 1 1 1 1
M _ C L K _DDR#2 CK0 CK1 M _ C L K _DDR#3
<8> M _ C L K _DDR#2 103 104 M _ C L K _DDR#3 <8>
CK0# CK1#

C 223

C 224

C 225

C 226

C 227

C 228

C 229

C 230

C 231

C 232

C 233

C 234
105 106
D D R _ B_MA10 VDD11 VDD12 D D R _ B _BS1
107 108 D D R _ B _BS1 <8>
D D R _ B _BS0 109 A10/AP BA1 110 D D R _ B _ RAS# 2 @ 2 @ 2 2 2 2 2 2 2 2 2 2
<8> D D R _ B _BS0 BA0 RAS# D D R _ B _ RAS# <8>
111 112
D D R _ B _ WE# 113 VDD13 VDD14 114 D D R _ C S 2 _DIMMB#
<8> D D R _ B _ WE# WE# S0# D D R _ C S 2 _DIMMB# <8>
<8> D D R _ B _ CAS# D D R _ B _ CAS# 115 116 M _ ODT2
CAS# ODT0 M _ODT2 <8>
117 118
D D R _ B_MA13 VDD15 VDD16 M _ ODT3
119 120 M _ODT3 <8>
D D R _ C S 3 _DIMMB# A13 ODT1 + V R E F _CA
<8> D D R _ C S 3 _DIMMB# 121 122
123 S1# NC2 124
VDD17 VDD18 V _ D D R _ M C H _ REF
125 126
NCTEST VREF_CA
127 128
VSS27 VSS28

0 .1U_0402_16V4Z

2 .2U_0603_6.3V4Z
D D R _ B _D32 129 130 D D R _ B _D36 Layout Note:
D D R _ B _D33 DQ32 DQ36 D D R _ B _D37
131 132 1 1
DQ33 DQ37 Place near JP5.203 & JP5.204
C 235

C 1060
133 134
D D R _ B _ DQS#4 VSS29 VSS30 D D R _ B _DM4
135 136
D D R _ B _ DQS4 137 DQS#4 DM4 138
B 139 DQS4 VSS31 140 D D R _ B _D38 2 2 B
D D R _ B _D34 VSS32 DQ38 D D R _ B _D39
141 142
D D R _ B _D35 DQ34 DQ39 +0.75VS
143 144
DQ35 VSS33 D D R _ B _D44
145 146
D D R _ B _D40 VSS34 DQ44 D D R _ B _D45
147 148
D D R _ B _D41 DQ40 DQ45
149 150
DQ41 VSS35

1 U_0402_6.3V6K

1 U_0402_6.3V6K

1 U_0402_6.3V6K

1 U_0402_6.3V6K
151 152 D D R _ B _ DQS#5
D D R _ B _DM5 VSS36 DQS#5 D D R _ B _ DQS5
153 154 1 1 1 1
DM5 DQS5
155 156
VSS37 VSS38

C 237

C 238

C 239

C 240
D D R _ B _D42 157 158 D D R _ B _D46
D D R _ B _D43 159 DQ42 DQ46 160 D D R _ B _D47
DQ43 DQ47 2 2 2 2
161 162
D D R _ B _D48 163 VSS39 VSS40 164 D D R _ B _D52
D D R _ B _D49 DQ48 DQ52 D D R _ B _D53
165 166
167 DQ49 DQ53 168
D D R _ B _ DQS#6 169 VSS41 VSS42 170 D D R _ B _DM6
D D R _ B _ DQS6 DQS#6 DM6
171 172
DQS6 VSS43 D D R _ B _D54
173 174
D D R _ B _D50 VSS44 DQ54 D D R _ B _D55
175 176
D D R _ B _D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 D D R _ B _D60
D D R _ B _D56 VSS46 DQ60 D D R _ B _D61
181 182
D D R _ B _D57 183 DQ56 DQ61 184
DQ57 VSS47 D D R _ B _ DQS#7
185 186
D D R _ B _DM7 187 VSS48 DQS#7 188 D D R _ B _ DQS7
DM7 DQS7
189 190
D D R _ B _D58 VSS49 VSS50 D D R _ B _D62
191 192
D D R _ B _D59 DQ58 DQ62 D D R _ B _D63
193 194
DQ59 DQ63
1 R 210 2 195 196
10K_0402_5% 197 VSS51 VSS52 198 P M_EXTTS#1_R
SA0 EVENT# P M_EXTTS#1_R <6,17>
199 200 S M B _DATA_S3
+ 3 VS VDDSPD SDA S M B _DATA_S3 <12,17,19,30>
2.2U_0402_6.3V6M

0 .1U_0402_16V4Z

R 211 201 202 S M B _CLK_S3

A SA1 SCL S M B _CLK_S3 <12,17,19,30> A
1 2 203 204
1 1 VTT1 VTT2 + 0.75VS
1 / 7 6 B A1/86W
DDR3 SO-DIMM B
C 241

C 242

10K_0402_5% 205 206

2 2
G1
+ 0.75VS
G2
REVERSE
C ONN@

S ecurity Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/03/13 Deciphered Date 2009/05/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT2
Size D o c u m ent Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Ca lp e lla DI S LA4 743P 0 .1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D a te: Monday, April 13, 2009 Sheet 18 of 49
5 4 3 2 1

http://laptop-motherboard-schematic.blogspot.com/
 5 4 3 2 1

+1.05VS_CK505
+1.05VS_CK505
80mA CLK_14M_PCH @ C808 1 2 10P_0402_50V8J
+3VS_CK505 +3VS_CK505
U3
250mA SMB_CLK_S3
1 32 SMB_CLK_S3 <12,17,18,30>
VDD_DOT SCL SMB_DATA_S3
2 31 SMB_DATA_S3 <12,17,18,30>
CLK_BUF_DOT96 R213 2 33_0402_5% L_CLK_BUF_DOT96 VSS_DOT SDA R EF_0/CPU_SEL R222 2
<12> CLK_BUF_DOT96 1 3 30 1 33_0402_5% CLK_14M_PCH
CLK_BUF_DOT96# R214 2 33_0402_5% L_CLK_BUF_DOT96# DOT_96 REF_0/CPU_SEL CLK_14M_PCH <12>
OK DOT96 <12> CLK_BUF_DOT96# DOT_96# 96MHz 14M OK
1 4 29
VDD_REF CLK_XTAL_IN
5 28
D 27M_CLK @ R216 2 33_0402_5% L_27M_CLK VDD_27 XTAL_IN CLK_XTAL_OUT D
<24> 27M_CLK 1 6 27
27M_SSC @ R217 2 33_0402_5% L_27M_SSC 27MHZ XTAL_OUT @ R226 1
OK 27M <24> 27M_SSC 1 7 26 2 0_0402_5%
27MHZ_SS VSS_REF R_ CK P WRGD R237 1 VGATE <13,46>
8 25 2 0_0402_5% CK P W R GD
VSS_27 CKPWRGD/PD#
9 24
CL K_DMI R221 1 33_0402_5% L _CLK_DMI VSS_SATA VDD_CPU L_CLK_BUF_BCLK R224 1
<12> CL K_DMI 2 10 23 2 33_0402_5% CLK_BUF_BCLK <12>
C LK_DMI# R223 1 33_0402_5% L_CLK_DMI# SRC_1/SATA CPU_0 L_CLK_BUF_BCLK# R225 1 2 33_0402_5%
OK DMI<12> SRC_1#/SATA# 100MHz 133MHz BCLK OK
CLK_DMI# 2 11 22 CLK_BUF_BCLK# <12>
CPU_0#
12 21
CL K _BUF_CKSSCD R219 1 33_0402_5% L _CLK_BUF_CKSSCD VSS_SRC VSS_CPU
<12> CL K _BUF_CKSSCD 2 13 20
CL K_BUF_CKSSCD# R220 1 33_0402_5% L _CLK_BUF_CKSSCD# SRC_2 CPU_1
SRC_2# 100MHz
OK CKSSCD <12> CL K_BUF_CKSSCD# 2 14 19
CPU_1#
15 18
CPU_STOP# VDD_SRC_IO VDD_CPU_IO
16 17
CPU_STOP# VDD_SRC

TGND
SLG8SP585VTR_QFN32_5X5

33
Number of Clock Outputs +3VS +3VS_CK505
R212
Output Number SLG8SP585Κ pin8 is GND (for DELLΕHP) 1 2

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
SLG8SP587Κ pin8 is 48MHz (For ABO or 030)
133MHz 2 0_0805_5% 1 1 1 1 1 1

C245

C246

C247

C248

C249

C250
SRC(100MHz_SS) 1
CLK_XTAL_OUT 2 2 2 2 2 2
SRC/SATA(100MHz) 1
CLK_XTAL_IN +3VS_CK505
REF(14.318MHz) 1 Y3
1 2 Place close to U51
+1.05VS_CK505

1
+ V CCP
DOT_CLK(96MHz) 1 2 2 14.318MHZ_16PF_7A14300083
C C259 C260 R607 R218 C
27MHz 1 18P_0402_50V8J 18P_0402_50V8J 10K_0402_5% 1 2

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
Vendor suggests 22pF 0_0805_5% Routing the trace at least 10mil
1 1
27MHz_SS 1 1 1 1

C252

C253

C254
CK P W R GD

1
D 2 2 2
PIN 30 CPU_0 CPU_1 CLK_EN# 2
<46> CLK_EN# G
+3VS_CK505 S Q30

3
0(default) 133MHz 133MHz 2N7002_SOT23-3

CPU_STOP# R234 1 2 10K_0402_5%

1 100MHz 100MHz

CPU_SEL During CK_PEWGD Latch Pin1

+3VS
@
R244 1 2 10K_0402_5% R EF_0/CPU_SEL

R247 1 2 10K_0402_5%

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock Generator CK505
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C alpella DI S LA 4743P 0.1

5
http://laptop-motherboard-schematic.blogspot.com/
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3 2
Da te: Monday, April 13, 2009

1
Sheet 19 of 49
 A B C D E

BLUE
GR EEN
R ED
Place close to
D6 D7 D8 JCRT1

1
1 +5VS + RCRT_VCC + CRT VDD 1

DAN217T146_SC59-3

DAN217T146_SC59-3

DAN217T146_SC59-3
D9 F1
2 1 1 2 W=40mils
CRT Connector RB491D_SC59-3 1 .1A_6VDC_FUSE
1

3
+3VS
0.1U_0402_16V4Z
C266 2
J CRT1
6
11
R ED 1
7
12
GR EEN 2
8
13 +3VS
BLUE 3
9

2
14 UMA@
+5VS +5VS 4 16 R901
10 17 10K_0402_5%
C267 C268 15
0.1U_0402_16V4Z 0.1U_0402_16V4Z 5

1
1 2 1 2 DGP U_EDIDSEL# DGP U_EDIDSEL#
SUYIN_070546FR015S263ZR
R815 2 1 10K_0402_5% C ONN@ +3VS

+ CRTVDD + CRTVDD
5
1

U5

1
SN74AHCT1G125GW_SOT353-5
P
OE#

1
2 CRT _ HS YNC HS Y N C_G_A R269 1 2 0_0603_5% D_ HS Y NC R272 R273 2
<22> CRT _ HSYNC 2 4
A Y R270 R271 4.7K_0402_5% 4.7K_0402_5%
G

5
1

4.7K_0402_5% 4.7K_0402_5%

2
P
OE#
3

2
CRT _ VSYNC 2 4 V S YNC_G_A R274 1 2 0_0603_5% D_ V S YNC
<22> CRT _VSYNC

2
A Y D_ DD CDATA I_ C RT_DDC_DATA
6 1 I_ CRT_DDC_DATA <13>
G

U6 1 1
SN74AHCT1G125GW_SOT353-5 @ C269 @ C270
3

Q2A

5
5P_0402_50V8C 5P_0402_50V8C
2N7002DW-7-F_SOT363-6
2 2 D_ DDC CLK I_ CRT _DDC_CLK
3 4 I_ CRT_DDC_CLK <13>

Q2B
2N7002DW-7-F_SOT363-6
+3VS_NV

DGP U_EDIDSEL R900 1 2 0_0402_5% E D IDSEL

1
SG@ S G@ S G@
R878 R879
4.7K_0402_5% 4.7K_0402_5%

2
D_ DD CDATA 6 1 D_ CRT_DDC_DATA <24>
S G@
Q11A
2N7002DW-7-F_SOT363-6
3 3
E D IDSEL
E DIDSEL <22>

5
D_ DDC CLK 3 4 D_ CRT _DDC_CLK <24>
S G@
CRT Termination/EMI Filter Q11B
2N7002DW-7-F_SOT363-6

C_ R ED L8 1 2 HLC0603CSCCR11JT_0603 R ED
<22> M _RED
+3VS
C_ GRN L9 1 2 HLC0603CSCCR11JT_0603 GR EEN
<22> M _GREEN

2
SG@
C_ BLU L10 1 2 HLC0603CSCCR11JT_0603 BLUE R902
<22> M_BLUE
10K_0402_5%
22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J
1

1
150_0402_1%

150_0402_1%

150_0402_1%

1 1 1 1 1 1

1
C271

C272

C273

C274

C275

C276

DGP U_EDIDSEL
R275

R276

R277

3
@ @ @ SG@

1
2 2 2 2 2 2 Q12B
2

2N7002DW-7-F_SOT363-6 2 Q12A
DGP U_EDIDSEL# 5 2N7002DW-7-F_SOT363-6
<14> DGPU_EDIDSEL#

6
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev

http://laptop-motherboard-schematic.blogspot.com/ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C alpella DI S LA 4743P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: Monday, April 13, 2009 Sheet 20 of 49
A B C D E
 5 4 3 2 1

+3VS + L CDVDD INV PWR_B+

D
LVDS CONN & USB Camera + Dig Mic D
680P_0402_50V7K

680P_0402_50V7K

680P_0402_50V7K
1 02/20 Change to 0805 size
1

1
C277

C278

C279
+ L CDVDD +3VS
+ L CDVDD + L CDVDD +5VALW Q13
SI2301BDS-T1-E3_SOT23-3
2

2
2

1
J LVDS1 1 3

S
D
1 2 LVDS_A2- 1
1 2 LVDS_A2- <22>
3 4 LVDS_A2+ 1 1 R278 R279
3 4 LVDS_A2+ <22>
5 6 LVDS_A1- C281 C282 470_0805_5% 1M_0402_5% C280 1

G
LVDS_A1- <22>

2
5 6 LVDS_A1+ 4.7U_0805_10V4Z
7 8 LVDS_A1+ <22>

6 2

2
7 8 LVDS_A0- 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 C283
9 10 LVDS_A0- <22>
9 10 LVDS_A0+ 2 2 4.7U_0805_10V4Z
11 12 LVDS_A0+ <22>
USB20_P4 11 12 LVDS_ACLK- 2
<14> USB20_P4 13 14 LVDS_ACLK- <22>
USB20_N4 13 14 LVDS_ACLK+ R280
<14> USB20_N4 15 16 LVDS_ACLK+ <22>
15 16
17 18 2 2 1
+3VS 17 18
19 20
19 20 2N7002DW-7-F_SOT363-6 100K_0402_5%
21 22

1
21 22 DM IC_DAT C284
23 24 DM IC_DAT <33> Q3A
23 24 DM I C_CLK
25 26 DM IC_CLK <33>
25 26 +3V_LOGO R281 0.047U_0402_16V7K
27 28 1 2 +5VS
27 28

2N7002DW-7-F_SOT363-6
29 30 LVDS_INV_PWM 100_0805_5% 02/13 Reserve
29 30 LVDS_INV_PWM <22>

3
31 32 BKOFF# BKOFF# <37> Limited Current < 1A 01/03 Change to 0.047u to meet T1 timing
31 32
33 34
33 34

Q3B
35 36 +USB_CAM BKOFF#
35 36 L V DS_EDID_CLK I_ E NAVDD
37 38 L V DS_EDID_CLK <22> <13> I_ E NAVDD 5
37 38 LVDS_EDID_DATA
39 40
39 40

1
41 42 LVDS_EDID_DATA <22>

4
GND GND @ R282 R283
ACES_88242-4001 10K_0402_5% 10K_0402_5%
C ONN@
C C

2
1
C286

1
680P_0402_50V7K D S G@
2 Q33
<24> D_ E NAVDD 2
G 2N7002_SOT23-3

2
SG@ S

3
R880
EMI request. 2.2K_0402_5%

1
+3VS Ε26
Must close JLVDS1pin 24Ε
DM I C_CLK

DM IC_DAT
2

B+ INVPWR_B+
R284 R285 1 1 @
2.2K_0402_5% 2.2K_0402_5% @ C287 @ C288 L11 1 2 0_0805_5%
220P_0402_25V8J 220P_0402_25V8J
1

L V DS_EDID_CLK 2 2 L12 1 2
LVDS_EDID_DATA FBMA-L11-201209-221LMA30T_0805

0308_Reserve L10 and install L11.

B B

USB Camera +USB_CAM

+5VS
U7

1
1 5 R286
IN OUT

47P_0402_50V8J
215K_0603_1%

10U_0805_6.3V6M
2
R288 GND
1 1

C289

C981
0_0402_5% 3 4
SHDN BYP
1

1
C290 G916-390T1UF_SOT23-5 @

1
10U_0805_6.3V6M R287 2 2
100K_0402_1%
2

2
+USB_CAM is +3.9VS, R286:215K; R287:100Kohm
A
+USB_CAM=1.25(1+R1091/R1093) A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev

http://laptop-motherboard-schematic.blogspot.com/ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C alpella DI S LA 4743P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: Monday, April 13, 2009 Sheet 21 of 49
5 4 3 2 1
 5 4 3 2 1

LVDS Switch + 3VS LVDS I2C switch Backlight Enable

U35
+ 3 VS

0 .1U_0402_16V4Z

4 .7U_0805_10V4Z
4
VCC
10 1
D _ L VDS_A0+ VCC
<25> D _ L VDS_A0+ 48 18
0B1 VCC

S G @ C 1004

S G @ C 1005
<25> D _ L VDS_A0- D _ L VDS_A0- 47 27
D _ L VDS_A1+ 1B1 VCC
<25> D _ L VDS_A1+ 43 38

2
D _ L VDS_A1- 42 2B1 VCC 50 2 E D I D S EL SG@
<25> D _ L VDS_A1- 3B1 VCC E D I D SEL <20>

2
<25> D _ L VDS_A2+ D _ L VDS_A2+ 37 56 SG@ R 8 82
D _ L VDS_A2- 36 4B1 VCC R 883
<25> D _ L VDS_A2- 4.7K_0402_5%
D _ L V D S_ACLK+ 32 5B1 2 L V DS_A0+ 4.7K_0402_5%
D
<25> D _ L V DS_ACLK+ 6B1 A0 L V DS_A0+ <21> D
<25> D _ L V D S_ACLK- D _ L V DS_ACLK- 31 3 L V DS_A0- E N B KL

3 1
L V DS_A0- <21> ENBKL <37>

2
7B1 A1 L V DS_A1+
22 7

1
8B1 A2 L V DS_A1+ <21>
23 8 L V DS_A1-
L V DS_A1- <21>

6
9B1 A3 11 L V DS_A2+ L V D S _ E D ID_DATA SG@
L V DS_A2+ <21> <24> D _ E D I D _DATA 1 6 L V D S _ E D ID_DATA <21>
A4 L V DS_A2- Q 35A
12 L V DS_A2- <21>
A5 L V D S _ACLK+ S G @ Q 34A 2 N 7002DW-7-F_SOT363-6 SG@
14 L V D S _ACLK+ <21> 5
A6 L V D S_ACLK- R 919
15 L V D S_ACLK- <21> <13> I _ E D I D_DATA 1 2 0_0402_5% 2 N7002DW-7-F_SOT363-6 <13> I G P U _BKLT_EN 2 Q 37B
A7

3
<13> I _ L VDS_A0+ I _ LVDS_A0+ 46 19 2 N7002DW-7-F_SOT363-6

4
I _ LVDS_A0- 0B2 A8
<13> I _ LVDS_A0- 45 20

1
5
I _ LVDS_A1+ 1B2 A9 R 790
<13> I _ L VDS_A1+ 41
I _ LVDS_A1- 2B2 D G P U _ SELECT#
<13> I _ LVDS_A1- 40 17 1 2 D G P U _ SELECT# <14> <24> D G P U _ BKL_EN 5
I _ LVDS_A2+ 3B2 SEL 0_0402_5% L V D S _ E D ID_CLK S G@
<13> I _ L VDS_A2+ 35 <24> D _ E D I D _CLK 4 3 L V D S _ E DID_CLK <21>
4B2

2
<13> I _ LVDS_A2- I _ LVDS_A2- 34 1 SG@ SG@ Q 35B

4
I _ L V DS_ACLK+ 5B2 GND S G @ Q 34B R 886 2 N 7002DW-7-F_SOT363-6
<13> I _ L V DS_ACLK+ 30 6
I _ L VDS_ACLK- 29 6B2 GND 9 R 920 1 2 0_0402_5% 2 N7002DW-7-F_SOT363-6 10K_0402_5%
<13> I _ L VDS_ACLK- 7B2 GND <13> I _ E D I D_CLK
25 13
8B2 GND
26 16

1
9B2 GND
21
GND 24 I G P U _BKLT_EN 1 2 UMA@ E N B KL
GND R 7 99 0_0402_5%
28
GND
52 33
5 NC GND 39
NC GND
54 44
51 NC GND 49
NC GND
53
GND
57 55
Thermal_GND
T S 3 D V 5 2 0ERHUR_QFN56_11X5~D
GND
UMA ONLY (LVDS)
S G@
I _ LVDS_A0- R P 36 4 1 L V DS_A0-
I _ LVDS_A0+ 3 2 L V DS_A0+
U M A @ 0_0404_4P2R_5%
C
+ 3VS
LVDS PWM switch I _ LVDS_A1-
I _ LVDS_A1+
R P 37 4
3
1
2
L V DS_A1-
L V DS_A1+
C

U M A @ 0_0404_4P2R_5%
I _ LVDS_A2+ R P 38 3 2 L V DS_A2+
I _ LVDS_A2- 4 1 L V DS_A2-

2
U M A @ 0_0404_4P2R_5%
S G@ @ R 890 2 1 0_0402_5% I _ L VDS_ACLK- R P 39 4 1 L V D S_ACLK-
I N V _ P WM <37>

2
SG@ R 8 89 I _ L V DS_ACLK+ 3 2 L V D S _ACLK+
R 891 4.7K_0402_5% U M A @ 0_0404_4P2R_5%
4.7K_0402_5%

1
L V D S _ I NV_PWM <21>

6
S G@
Q 37A

6
SG@ 2 N 7002DW-7-F_SOT363-6
Q 36A 2
2 N7002DW-7-F_SOT363-6
<13> D P S T _ PWM 2

1
3
1
U MA@
<24> D _ I N V _ PWM 5 D P S T _ PWM R 892 2 1 0_0402_5% L V D S _ I NV_PWM

SG@
CRT Switch

4
Q 36B
2 N7002DW-7-F_SOT363-6
+ 3 VS
0 .1U_0402_16V4Z

0 .1U_0402_16V4Z

0 .1U_0402_16V4Z

0 .1U_0402_16V4Z

B B
1 SG@ 1 SG@ 1 SG@ 1 SG@
C 1011 C 1012 C 1013 C 1014

2 2 2 2

U 43
1
+ 3VS
4
9
VDD
VDD
VDD
SEL
12 D G P U _ SELECT#
UMA ONLY (CRT)
19 2 M_ RED
VDD YA M_ RED <20>
5 M _ G R EEN I_RED R 893 2 UMA@ 1 0_0402_5% M_ RED
YB M _ G R EEN <20>
24 6 M _ B LUE I _ G R EEN R 894 2 UMA@ 1 0_0402_5% M _ G R EEN
<24> D _RED A0 YC M _ B LUE <20>
22 I _ B LUE R 895 2 UMA@ 1 0_0402_5% M _ B LUE
<24> D _ G R E EN B0
18 8 C RT_ HSYNC I _ C R T _ H S Y NC R 896 2 UMA@ 1 0_0402_5% C RT_ HSYNC
<24> D _ B L UE C0 YD C R T _ H S Y N C <20>
17 11 CRT_ VSYNC I _ C R T _ V S YNC R 897 2 UMA@ 1 0_0402_5% CRT_ VSYNC
<24> D_ CRT_ HSYNC D0 YE C R T _ V S Y N C <20>
<24> D _ C R T _ V S Y NC 14
E0

<13> I_RED 23 3
21 A1 GND 7
<13> I _ G R EEN B1 GND
<13> I _ B LUE 16 10
15 C1 GND 20
<13> I _ C R T _ H S Y NC D1 GND
<13> I _ C R T _ V S YNC 13
E1
P I3V512QE_QSOP24
SG@

A A

S ecurity Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS Switch
Size D o c u m ent Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
C u s t om Ca lp e lla DI S LA4 743P 0 .1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D a te: Monday, April 13, 2009 Sheet 22 of 49
5 4 3 2 1

http://laptop-motherboard-schematic.blogspot.com/
 5 4 3 2 1

Parade Parade +3VS_NV

ST 8101T 8171 UMA@
R833 X X X R832
+3VS 1 2 +3VS_LS
+3VS_NV +3VS_LS +3VS_LS

10U_0805_6.3V6M
0.01U_0402_16V7K

0.1U_0402_10V6K

0.1U_0402_10V6K
R837 0 ohm 0 ohm 4.7K ohm

UMA@

UMA@

UMA@

UMA@
0_0603_5%
@ R571 @ R572
R836 X 4.7K ohm X 2.2K_0402_5% S G@
<13> TMDSD_DATA2# TMDSD_DATA1 <13> 2 1 1 1
2.2K_0402_5% <13> TMDSD_DATA2 TMDSD_DATA1# <13>

C1048

C1049

C1050

C1051
Q5A
R840 4.7K ohm X 4.7K ohm

2
2N7002DW-7-F_SOT363-6
<13> TMDSD_CLK# TMDSD_DATA0 <13>

1
1 2 2 2
R838 X X 4.7K ohm HD MIDAT
<13> TMDSD_CLK TMDSD_DATA0# <13>
<25> HDMIDAT_VGA 1 6
R842 X X X SG@ +3VS_LS

5
D Q5B @ R575 1 2 0_0402_5% D
R849 3.9K ohm 499 ohm 499 ohm 2N7002DW-7-F_SOT363-6 UMA@

48

47

46

45

44

43

42

41

40

39

38

37
1
HDM ICLK @ R833 U47
R850 0 ohm X X <25> HDMICLK_VGA
4 3
+3VS_LS 4.7K_0402_5%

GND

GND
IN_D4-

VCC3V

VCC3V
IN_D3-

IN_D2-

IN_D1-
IN_D4+

IN_D3+

IN_D2+

IN_D1+
@ R834 2 1 4.7K_0402_5% +3VS_LS
C1052 X X 2.2uF @ R576 1 +3VS_LS
2 0_0402_5% UMA@

1
R837 @ R835 2 1 4.7K_0402_5% +3VS_LS
R853 0 ohm 0 ohm X

2
@ R836 1 2 1 36
GND GND

1
4.7K_0402_5% 0_0402_5% UMA@
R855 X X 4.7K ohm @ R838 UMA@ R839 2
+3VS_LS 2 35 1 0_0402_5%
4.7K_0402_5% R840 VCC3V FUNCTION4 UMA@
R857 X X 4.7K ohm

2
1 2 3 P C0 34 R841 2 1 0_0402_5%
+3VS_LS @ R842 4.7K_0402_5% FUNCTION1 FUNCTION3
R858 0 ohm 0 ohm X

2
1 2 4 P C1 33 UMA@ R843 2 1 0_0402_5% +3VS_LS
0_0402_5% FUCNTION2 VCC3V @ R844 0_0402_5%
R851 X X 4.7K ohm UMA@ R845
2 1
4.7K_0402_5%
5 32 2 1 +3VS_LS
GND DDC_EN

1
UMA@ UMA@ UMA@ @ R846 0_0402_5%
R854 0 ohm 0 ohm X R847 R848 R849 2
2 1
1 4.3K_0402_1%6 31
2.2K_0402_5% 2.2K_0402_5% ANALOG1(REXT) GND
R843 0 ohm 0 ohm X TMDS_B_HPD H DMI_DETECT
7 30
HPD_SOURCE HPD_SINK
R844 X X 4.7K ohm

2
8 29 HD MIDAT +3VS_LS
<13> HDM ID_CTRLDATA SDA_SOURCE SDA_SINK
R839 0 ohm X 4.7K ohm EQUALIZATION SETTING:
9 28 HDM ICLK
[PC1,PC0]=00,8dB <13> HDM ID_CTRLCLK SCL_SOURCE SCL_SINK

1
UMA@
R834 X X X [PC1,PC0]=01,4dB (Recommanded) R850 1 2 0_0402_5% 10 27 @ R851 2 14.7K_0402_5% +3VS_LS R852
[PC1,PC0]=10,12dB UMA@ ANALOG2 GND 10K_0402_5%
R841 0 ohm X X R853 1
[PC1,PC0]=11,0dB 1 2 +3VS_LS 2 0_0402_5% 11 26 +3VS_LS R854 1 2 0_0402_5% UMA@
@C1052 VCC3V VCC3V UMA@
R835 X X 4.7K ohm

2
2.2U_0603_6.3V4Z @ R855 1 2 4.7K_0402_5% 12 25 R856 2 1 0_0402_5%
GND OE* UMA@

OUT_D4+

OUT_D3+

OUT_D2+

OUT_D1+
C667 0.1uF 1uF 1uF

OUT_D4-

OUT_D3-

OUT_D2-

OUT_D1-

6
49

VCC3V

VCC3V
C thm_pad C
R862 V X X

GND

GND
+3VS_LS @ R857 1 2 4.7K_0402_5%
UMA@ H DMI_DETECT 2
R867 V X X @ R859 1 2 0_0402_5% R858 1 2 0_0402_5% S IC STHDLS101TQTR QFN 48P HDMI SHIFTER

13

14

15

16

17

18

19

20

21

22

23

24
S G@ Q19A

1
S G@ L28 2N7002DW-7-F_SOT363-6
C375 2 1 0.1U_0402_16V4Z HDM ICLK- 1 2 HDM I_R_CLK-
<25> HDM I_C_CLK- 1 2
S G@ WCM-2012-900T_0805 HDMI_TX_0- +3VS_LS
C376 2 1 0.1U_0402_16V4Z HDM ICLK+ 4 3 HDM I_R_CLK+ @C1053 @ R860 @ R861 @C1054
<25> HDM I_C_CLK+ 4 3 HDM ICLK+ 1 2 1 2 HDMI_TX_0+

1
68_0402_5% 68_0402_5% UMA@
@ R866 1 2 HDM ICLK- 0.5P_0402_50V8B +3VS_LS +3VS_LS 0.5P_0402_50V8B R862
0_0402_5% 20K_0402_5%
HDMI_TX_1- UMA@
@ R868 1 2 0_0402_5% @C1055 @ R863 @ R864 @C1056 R865

2
HDMI_TX_2+ 1 2 1 2 HDMI_TX_1+ 2 1 TMDS_B_HPD
<13> TMDS_B_HPD#
S G@ L29 68_0402_5% 68_0402_5%

1
<25> HDMI_C_TX0- C377 2 1 0.1U_0402_16V4Z HDMI_TX_0- 1 2 HDMI_R_TX0- HDMI_TX_2- 0.5P_0402_50V8B 0.5P_0402_50V8B 0_0402_5%
1 2 UMA@
S G@ WCM-2012-900T_0805 R867
<25> HDMI_C_TX0+ C378 2 1 0.1U_0402_16V4Z HDMI_TX_0+ 4 3 HDMI_R_TX0+ 7.5K_0402_1%
4 3

2
@ R869 1 2
0_0402_5%

@ R870 1 2 0_0402_5%
+5VS + 5VS_HDMI
S G@ L30

22N_0402_16V7K
<25> HDMI_C_TX1- C379 2 1 0.1U_0402_16V4Z HDMI_TX_1- 1 2 HDMI_R_TX1-
1 2
B S G@ WCM-2012-900T_0805 B
1
<25> HDMI_C_TX1+ C380 2 1 0.1U_0402_16V4Z HDMI_TX_1+ 4 3 HDMI_R_TX1+
4 3

C665
@ R871 D34 @ 2
1 2
0_0402_5% +3VS
HDMI Connector RB411DT146_SOT23-3

1
@ R872 1 2 0_0402_5%
5

+5VS_HDMI

0.1U_0402_16V4Z
22N_0402_16V7K
S G@ L31 2 H DMI_DETECT
P

C382 2 B
<25> HDMI_C_TX2- 1 0.1U_0402_16V4Z HDMI_TX_2- 1 2 HDMI_R_TX2- <24> HDMI_DET 4 1 1
1 2 Y DGP U _PWR_EN
1 DGP U_PWR_EN <14,39,45,47>
A
1

1.5K_0402_5%

1.5K_0402_5%

C666

C667
S G@ WCM-2012-900T_0805 S G@

2
<25> HDMI_C_TX2+ C381 2 1 0.1U_0402_16V4Z HDMI_TX_2+ 4 3 HDMI_R_TX2+ R924 U51
3

4 3 10K_0402_5% NC7SZ08P5X_NL_SC70-5 @ 2 2

R577

R578
S G@
@ R873 1 2
2

0_0402_5%

1
HDM ICLK- J HDMI1
HDM ICLK+ 18
HDMI_TX_0- HD MIDAT +5V
16 13
HDMI_TX_0+ R579 HDM ICLK SDA CEC
15 14
HDMI_TX_1- H DMI_DETECT L32 SCL Reserved
1 2 1 2 FBML10160808121LMT_0603 19
HDMI_TX_1+ 10K_0402_1% HP_DET
2

1
HDMI_TX_2- HDM I_R_CLK- GND
1 12 5
HDMI_TX_2+ HDM I_R_CLK+ CK- GND
10 8
CK+ GND
5

D35 R580 HDMI_R_TX0- 9 11

SKS10-04AT_TSMA 100K_0402_1% C668 HDMI_R_TX0+ D0- GND
7 20
330P_0402_50V7K 2 HDMI_R_TX1- D0+ GND
<14> DGP U_HPD_INT# 3 4 6 21

2
D1- GND
1

HDMI_R_TX1+ 4 22
SG@ S G@ SG@ S G@ S G@ SG@ S G@ SG@ HDMI_R_TX2- D1+ GND
Q19B 3 23
A R733 R734 R735 R736 R737 R738 R739 R740 HDMI_R_TX2+ D2- GND A
1 17
499_0402_1% 2N7002DW-7-F_SOT363-6 D2+ DDC/CEC_GND
S G@
2

SUYIN_100042MR019S153ZL
499_0402_1% 499_0402_1% 499_0402_1% 499_0402_1% C ONN@
499_0402_1% 499_0402_1% 499_0402_1%

Security Classification Compal Secret Data Compal Electronics, Inc.

1

D
Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title
2 S G@ Q31
+3VS_NV
G 2N7002_SOT23-3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI LS & Conn.
S AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
3

http://laptop-motherboard-schematic.blogspot.com/ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom C alpella DI S LA4743P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: Monday, April 13, 2009 Sheet 23 of 49
5 4 3 2 1
 1 2 3 4 5

U8A
P a rt 1 of 5
<7> P C IE_CTX_GRX_P15 AE12 N1
PEX_RX0 GPIO0
<7> P C IE_CTX_GRX_N15 AF12 G1 H D M I _ DET <23>
PEX_RX0_N GPIO1
<7> P C IE_CTX_GRX_P14 AG12 C1 D _ I N V _ PWM <22>
PEX_RX1 GPIO2
<7> P C IE_CTX_GRX_N14 AG13 M2 D _ E N A V D D <21>
PEX_RX1_N GPIO3
<7> P C IE_CTX_GRX_P13 AF13 M3 D G P U _ B KL_EN <22>
AE13 PEX_RX2 GPIO4 K3
<7> P C IE_CTX_GRX_N13 PEX_RX2_N GPIO5 G P U _ VID0 <47>
<7> P C IE_CTX_GRX_P12 AE15 K2 G P U _ VID1 <47>
AF15 PEX_RX3 GPIO6 J2
<7> P C IE_CTX_GRX_N12 PEX_RX3_N GPIO7 G P U _ VID2
<7> P C IE_CTX_GRX_P11 AG15 C2 THERMAL ALERT S G @ R 327 1 2 0_0402_5% T H E R M#_VGA

GPIO
PEX_RX4 GPIO8 S G @ R 328 1
<7> P C IE_CTX_GRX_N11 AG16 M1 S IN N_GPIO9 2 0_0402_5% T H E R M _SCI#
PEX_RX4_N GPIO9
A <7> P C IE_CTX_GRX_P10 AF16 D2 A
PEX_RX5 GPIO10 Close to GPU
<7> P C IE_CTX_GRX_N10 AE16 D1
AE18 PEX_RX5_N GPIO11 J3
<7> P C IE_CTX_GRX_P9 PEX_RX6 GPIO12
<7> P C I E_CTX_GRX_N9 AF18 J1 D _RED S G @ R 297 1 2 150_0402_1%
PEX_RX6_N GPIO13
<7> P C IE_CTX_GRX_P8 AG18 K1
PEX_RX7 GPIO14 D _ G R E EN S G @ R 296 1
<7> P C I E_CTX_GRX_N8 AG19 F3 2 150_0402_1%
PEX_RX7_N GPIO15
<7> P C IE_CTX_GRX_P7 AF19 G3
PEX_RX8 GPIO16 D _ B L UE S G @ R 295 1
<7> P C I E_CTX_GRX_N7 AE19 G2 2 150_0402_1%
PEX_RX8_N GPIO17
<7> P C IE_CTX_GRX_P6 AE21 F1
PEX_RX9 GPIO18
<7> P C I E_CTX_GRX_N6 AF21 F2
PEX_RX9_N GPIO19
<7> P C IE_CTX_GRX_P5 AG21
PEX_RX10
<7> P C I E_CTX_GRX_N5 AG22 AD2 D _ C R T _ H S Y N C <22>
PEX_RX10_N DACA_HSYNC
<7> P C IE_CTX_GRX_P4 AF22 AD1 D _ C R T _ V S Y N C <22>
AE22 PEX_RX11 DACA_VSYNC + 3 V S_NV

DACA
<7> P C I E_CTX_GRX_N4 PEX_RX11_N
<7> P C IE_CTX_GRX_P3 AE24 AE2 D _RED
PEX_RX12 DACA_RED D _ R E D <22>
<7> P C I E_CTX_GRX_N3 AF24 AD3 D _ B L UE
PEX_RX12_N DACA_BLUE D _ B L UE <22>
<7> P C IE_CTX_GRX_P2 AG24 AE3 D _ G R E EN I 2 C B _SCL S G @ R 319 1 2 2.2K_0402_5%
PEX_RX13 DACA_GREEN D _ G R E E N <22>
<7> P C I E_CTX_GRX_N2 AF25 I 2 C B _SDA S G @ R 320 1 2 2.2K_0402_5%
PEX_RX13_N D A CA_VREF S G @ C 358 1
<7> P C IE_CTX_GRX_P1 AG25 AF1 2 0 .1U_0402_16V4Z
PEX_RX14 DACA_VREF

PCI EXPRESS
<7> P C I E_CTX_GRX_N1 AG26 AE1 D A C A _ R S EF S G @ R 294 1 2 124_0402_1% H D C P _ S CL S G @ R 686 1 2 2.2K_0402_5%
PEX_RX14_N DACA_RSET H D C P _ S D A S G @ R 687 1
<7> P C IE_CTX_GRX_P0 AF27 2 2.2K_0402_5%
PEX_RX15
<7> P C I E_CTX_GRX_N0 AE27 U6
PEX_RX15_N DACB_HSYNC U4
SG@ C 776 0 .1U_0402_16V4Z PCIE_CRX_GTX_G_P15 DACB_VSYNC G P U _ VID0 @ R 595 1
1 2 AD10 2 10K_0402_5%

DACB
<7> P C IE_CRX_GTX_P15 PEX_TX0
SG@ C 777 1 2 0 .1U_0402_16V4Z PCIE_CRX_GTX_G_N15 AD11 T5 G P U _ VID1 @ R 187 1 2 10K_0402_5%
<7> P C IE_CRX_GTX_N15 PEX_TX0_N DACB_RED
SG@ C 778 1 2 0 .1U_0402_16V4Z P C IE_CRX_GTX_G_P14 AD12 R4
<7> P C IE_CRX_GTX_P14 PEX_TX1 DACB_BLUE
SG@ C 779 1 2 0 .1U_0402_16V4Z P C IE_CRX_GTX_G_N14 AC12 T4
<7> P C IE_CRX_GTX_N14 PEX_TX1_N DACB_GREEN
SG@ C 780 1 2 0 .1U_0402_16V4Z P C IE_CRX_GTX_G_P13 AB11 D _ E D I D _CLK S G @ R 808 1 2 2.2K_0402_5%
<7> P C IE_CRX_GTX_P13 PEX_TX2
SG@ C 781 1 2 0 .1U_0402_16V4Z P C IE_CRX_GTX_G_N13 AB12 R6 D _ E D I D _DATAS G @ R 809 1 2 2.2K_0402_5%
<7> P C IE_CRX_GTX_N13 PEX_TX2_N DACB_VREF
SG@ C 782 1 2 0 .1U_0402_16V4Z P C IE_CRX_GTX_G_P12 AD13 V6
<7> P C IE_CRX_GTX_P12 PEX_TX3 DACB_RSET
SG@ C 783 1 2 0 .1U_0402_16V4Z P C IE_CRX_GTX_G_N12 AD14
<7> P C IE_CRX_GTX_N12 PEX_TX3_N
SG@ C 784 1 2 0 .1U_0402_16V4Z P C IE_CRX_GTX_G_P11 AD15
<7> P C IE_CRX_GTX_P11 PEX_TX4
SG@ C 785 1 2 0 .1U_0402_16V4Z P C IE_CRX_GTX_G_N11 AC15
<7> P C IE_CRX_GTX_N11 PEX_TX4_N
SG@ C 786 1 2 0 .1U_0402_16V4Z P C IE_CRX_GTX_G_P10 AB14 AF3 J T A G_TCK T64 T P C12
<7> P C IE_CRX_GTX_P10 PEX_TX5 JTAG_TCK
SG@ C 787 1 2 0 .1U_0402_16V4Z P C IE_CRX_GTX_G_N10 AB15 AG4 J T A G_TDI T65 T P C12
B <7> P C IE_CRX_GTX_N10 PEX_TX5_N JTAG_TDI B
SG@ C 788 1 2 0 .1U_0402_16V4Z P C IE_CRX_GTX_G_P9 AC16 AE4 J T A G_TDO

TEST
<7> P C IE_CRX_GTX_P9 PEX_TX6 JTAG_TDO T66 T P C12
SG@ C 789 1 2 0 .1U_0402_16V4Z P C I E_CRX_GTX_G_N9 AD16 AF4 J T AG_TMS T67 T P C12
<7> P C I E_CRX_GTX_N9 PEX_TX6_N JTAG_TMS
SG@ C 790 1 2 0 .1U_0402_16V4Z PCIE_CRX_GTX_G_P8 AD17 AG3 J T A G_TRST@ R 903 1 2 10K_0402_5%
<7> P C IE_CRX_GTX_P8 PEX_TX7 JTAG_TRST_N
SG@ C 791 1 2 0 .1U_0402_16V4Z PCIE_CRX_GTX_G_N8 AD18
<7> P C I E_CRX_GTX_N8 PEX_TX7_N
SG@ C 792 1 2 0 .1U_0402_16V4Z PCIE_CRX_GTX_G_P7 AC18 AD25 S G @ R 688 1 2 10K_0402_5%
<7> P C IE_CRX_GTX_P7 PEX_TX8 TESTMODE
SG@ C 793 1 2 0 .1U_0402_16V4Z PCIE_CRX_GTX_G_N7 AB18
<7> P C I E_CRX_GTX_N7 PEX_TX8_N
SG@ C 794 1 2 0 .1U_0402_16V4Z PCIE_CRX_GTX_G_P6 AB19
<7> P C IE_CRX_GTX_P6 PEX_TX9
SG@ C 795 1 2 0 .1U_0402_16V4Z PCIE_CRX_GTX_G_N6 AB20
<7> P C I E_CRX_GTX_N6 PEX_TX9_N
SG@ C 796 1 2 0 .1U_0402_16V4Z PCIE_CRX_GTX_G_P5 AD19 R1
<7> P C IE_CRX_GTX_P5 PEX_TX10 I2CA_SCL D _ C R T _ D D C_CLK <20>
SG@ C 797 1 2 0 .1U_0402_16V4Z PCIE_CRX_GTX_G_N5 AD20 T3
<7> P C I E_CRX_GTX_N5
SG@ C 798 1 2 0 .1U_0402_16V4Z PCIE_CRX_GTX_G_P4 AD21
PEX_TX10_N I2CA_SDA D _ C R T _ D D C_DATA <20> CRT
<7> P C IE_CRX_GTX_P4 PEX_TX11
SG@ C 799 1 2 0 .1U_0402_16V4Z PCIE_CRX_GTX_G_N4 AC21 R2 I 2 C B _SCL
<7> P C I E_CRX_GTX_N4 PEX_TX11_N I2CB_SCL
SG@ C 800 1 2 0 .1U_0402_16V4Z PCIE_CRX_GTX_G_P3 AB21 R3 I 2 C B _SDA GPIO I/O ACTIVE USAGE
<7> P C IE_CRX_GTX_P3 PEX_TX12 I2CB_SDA
SG@ C 801 1 2 0 .1U_0402_16V4Z PCIE_CRX_GTX_G_N3 AB22
<7> P C I E_CRX_GTX_N3 PEX_TX12_N
SG@ C 802 1 2 0 .1U_0402_16V4Z PCIE_CRX_GTX_G_P2 AC22 A2 D _EDID_CLK
<7> P C IE_CRX_GTX_P2 D _ E D I D _CLK <22>
I2C
SG@ C 803 0 .1U_0402_16V4Z PCIE_CRX_GTX_G_N2 PEX_TX13 I2CC_SCL D _EDID_DATA
1 2 AD22 B1 GPIO0 IN N/A HPD-C (used for IFPC)
<7> P C I E_CRX_GTX_N2
SG@ C 804 1 2 0 .1U_0402_16V4Z PCIE_CRX_GTX_G_P1 AD23
PEX_TX13_N I2CC_SDA D _ E D I D _DATA <22> LVDS
<7> P C IE_CRX_GTX_P1 PEX_TX14
SG@ C 805 1 2 0 .1U_0402_16V4Z PCIE_CRX_GTX_G_N1 AD24 A3 H DCP_SCL
<7> P C I E_CRX_GTX_N1 PEX_TX14_N I2CH_SCL H D C P _ S CL <25>
SG@ C 806 1 2 0 .1U_0402_16V4Z PCIE_CRX_GTX_G_P0 AE25 A4 HD CP_SDA GPIO1 IN N/A 2nd DVI Hot-plug
<7> P C IE_CRX_GTX_P0
SG@ C 807 1 2 0 .1U_0402_16V4Z PCIE_CRX_GTX_G_N0 AE26
PEX_TX15 I2CH_SDA H D C P _ S D A <25> HDCP
<7> P C I E_CRX_GTX_N0 PEX_TX15_N T1 V G A _SM_CLK 0_0402_5% 1 2 R 325 @ D _ E D I D _CLK
I2CS_SCL 0_0402_5% 1
<12> C L K _ P CIE_VGA C LK_PCIE_VGA AB10 T2 V G A _ SM_DA 2 R 326 @ D _ E D I D _DATA GPIO2 OUT H P anel Back-Light PWM
C LK_PCIE_VGA# PEX_REFCLK I2CS_SDA
<12> C L K _ P CIE_VGA# AC10
PEX_REFCLK_N @ R 690 2 1 10K_0402_5%
R 6 89 1 @ 2 200_0402_1% AF10 GPIO3 OUT H P anel Pow er Enable
AE10 PEX_TSTCLK_OUT D11 2 7 M_SSC
PEX_TSTCLK_OUT_N XTAL_SSIN 2 7 M _SSC <19>
S G @ R 6 91 1 2 2.49K_0402_1% AG10 E9 @ R 692 1 2 10K_0402_5% GPIO4 OUT H Panel Back-Light Enable
PEX_TERMP XTAL_OUTBUFF
S G @ R 6 93 1 2 0_0402_5% P EX_RST# AD9 E10 X TALOUT
CLK

<14> D G P U _ H O LD_RST# PEX_RST_N XTAL_OUT

S G @ R 6 94 1
GPIO5 OUT N/A NVVDD VID0
+ 3 VS_NV 2 10K_0402_5% AE9 D10 X TALIN @ R 695 2 1 0_0402_5% 2 7 M_CLK <19>
PEX_CLKREQ_N XTAL_IN V G A _SM_CLK S G @ R 315 2 1 0_0402_5% S M B _ E C_CK2_R <12>
V G A _ SM_DA S G @ R 316 2 1 0_0402_5% GPIO6 OUT N/A NVVDD VID1
S M B _ E C _DA2_R <12>
C N10M-GLM-S-A1_BGA533 C
SG@
+ 3 VS_NV
GPIO7 OUT N/A NVVDD VID2
S G @ Y7 SG@
2 7MHZ_18PF_X3S027000FI1H-X T H E R M _SCI# 10K_0402_5% 1 2 R 696
<37> T H E R M _SCI#
SG@ GPIO8 IN L OVERT
X TALIN 1 3 X TALOUT T H E R M#_VGA 10K_0402_5% 2 1 R 314
2 4

SG@
1 1
SG@
GPIO9 OUT L T hermal Alert
C 810 C 8 11
20P_0402_50V8 20P_0402_50V8
2 2 GPIO10 OUT N/A MEM_VREF

GPIO11 OUT L SLI SYNCO

GPIO12 IN N/A AC Detect

GPIO13 OUT L MEM_VID

GPIO14 OUT H PS Control

GPIO15 IN N/A HPD-E (used for IFPE)

GPIO16 OUT N/A FAN PWM Control

GPIO17 N/A
D D
GPIO18 N/A

GPIO19 IN N/A HPD-D (used for IFPD)

S ecurity Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/09/15 Deciphered Date 2009/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PEG Interface
Size D o c u m ent Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0 .1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Calpella DIS LA4743P
1 http://laptop-motherboard-schematic.blogspot.com/
2 3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4
D a te: Monday, April 13, 2009
5
Sheet 24 of 49
 1 2 3 4 5

LVDS Interface
U 8C
P a rt 3 of 5
<22> D _ L V D S_ACLK+ AC4 C15
IFPA_TXC NC
AD4 D15

NC
<22> D _ L V D S_ACLK- IFPA_TXC_N NC
<22> D _ L VDS_A0+ V5 J5
V4 IFPA_TXD0 NC
<22> D _ L VDS_A0- IFPA_TXD0_N
<22> D _ L VDS_A1+ AA5
AA4 IFPA_TXD1
<22> D _ L VDS_A1- IFPA_TXD1_N
<22> D _ L VDS_A2+ W4
IFPA_TXD2
<22> D _ L VDS_A2- Y4 T6
IFPA_TXD2_N RFU_1
A AB4 W6 A

RFU
IFPA_TXD3 RFU_2
AB5 Y6
IFPA_TXD3_N RFU_3 AA6
RFU_4
N3
RFU_5
AB3
AB2 IFPB_TXC
IFPB_TXC_N
W1
IFPB_TXD4 S T R AP0
V1 C7
IFPB_TXD4_N STRAP0
W3

LVDS / TMDS
STRAP
IFPB_TXD5 S T R AP1
W2 B9
IFPB_TXD5_N STRAP1
AA2
IFPB_TXD6 S T R AP2
AA3 A9
IFPB_TXD6_N STRAP2
AB1
AA1 IFPB_TXD7
IFPB_TXD7_N

<23> H D M I C LK_VGA
G4 N5
G5 IFPC_AUX_I2CW_SCL BUFRST_N
<23> H D M I D AT_VGA H D MI_C_TX2+ IFPC_AUX_I2CW_SDA_N
<23> H D MI_C_TX2+ P4
H D MI_C_TX2- IFPC_L0
N4

GENERAL
<23> H D MI_C_TX2- IFPC_L0_N
H D MI_C_TX1+ M5 D8 VG A_THERMDC
<23> H D MI_C_TX1+ IFPC_L1 THERMDN
H D MI_C_TX1- M4
<23> H D MI_C_TX1- IFPC_L1_N
H D MI_C_TX0+ L4 D9 VG A_THERMDA
<23> H D MI_C_TX0+ IFPC_L2 THERMDP
H D MI_C_TX0- K4
<23> H D MI_C_TX0- IFPC_L2_N
H D M I _ C_CLK+ H4
<23> H D M I _ C_CLK+ IFPC_L3
H D M I _ C_CLK- J4
<23> H D M I _ C_CLK- IFPC_L3_N
N2
CEC S G@
D3 F9 S P D I F _ IN R 6 69 1 2 36K_0402_1%
D4
IFPD_AUX_I2CX_SCL SPDIF SPDIF
F5 IFPD_AUX_I2CX_SDA_N
IFPD_L0 SG@
F4
E4 IFPD_L0_N B10 R O M _ CS# R 301 1 2 10K_0402_5%
IFPD_L1 ROM_CS_N + 3 V S_NV
D5

SERIAL
IFPD_L1_N R O M _ SCLK
C3 C9
B IFPD_L2 ROM_SCLK B
C4
IFPD_L2_N R O M _SI
B3 A10
IFPD_L3 ROM_SI
B4
IFPD_L3_N R O M _SO
C10
ROM_SO
F7
IFPE_AUX_I2CY_SCL
G6
IFPE_AUX_I2CY_SDA_N
D6
C6 IFPE_L0 AB6 IFPAB_RSET R 290 1 @ 2 1K_0402_1%
IFPE_L0_N IFPAB_RSET SG@
A6
IFPE_L1 IFPC_RSET R 302 2 1K_0402_1%
A7 R5 1
IFPE_L1_N IFPC_RSET SG@
B6
IFPE_L2 I F P D _ R SET R 697
B7 M6 1 2 1K_0402_1%
E6 IFPE_L2_N IFPD_RSET SG@
IFPE_L3 I F P E _ RSET R 698
E7 F8 1 2 1K_0402_1%
IFPE_L3_N IFPE_RSET

N10M-GLM-S-A1_BGA533
S G@

Straps
C MULTI LEVEL STRAPS FB HW Strap for DDR3: (RAM_CFG @ROM_SI) C
HDCP ROM + 3 VS_NV S T R AP0
- Hynix 64Mx16: 0000 (R344 pull-down 15K)
- Samsung 64Mx16: 0001 (R344 pull-down 20K)
S T R AP1
1 S T R AP2
SG@ R O M _SI
C 388 R O M _SO
0 .1U_0402_16V4Z R O M _ SCLK
2 + 3 VS_NV

U10 S G@
1 8 @ 1 R 329 2 1 R 3 30 2
A0 VCC 4.99K_0402_1% 45.3K_0402_1%
2 7
3 A1 WP 6 H DCP_SCL
A2 SCL H D C P _ S CL <24>
4 5 HD CP_SDA S G @ 1 R 339 2 @ 1 R 3 40 2
GND SDA H D C P _ S D A <24>
35K_0402_1% 4.99K_0402_1%
A T 2 4 C 1 6BN-SHBY-B
SG@ H D C P _ S CL S G @ 1 R 342 2 @ 1 R 3 43 2
24.9K_0402_1% 4.99K_0402_1%

1
R 313 @ S G @ 1 R 344 2 @ 1 R 3 45 2
10K_0402_5% 15K_0402_1% 4.99K_0402_1%

S G @ 1 R 346 2 @ 1 R 3 47 2

2
4.99K_0402_1% 4.99K_0402_1%

@ 1 R 348 2 S G @ 1 R 3 49 2
4.99K_0402_1% 4.99K_0402_1%

D D

S ecurity Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/09/15 Deciphered Date 2009/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N10M(2)_ LVDS&DP&HDCP
Size D o c u m ent Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
C u s t om Ca lp e lla DI S LA4 743P 0 .1

1 http://laptop-motherboard-schematic.blogspot.com/
2 3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4
D a te: Monday, April 13, 2009
5
Sheet 25 of 49
 1 2 3 4 5

32~63 ODT 0~31 ODT 32~63 CKE 0~31 CKE

A A
+ V D D _MEM + V D D _MEM + V D D _MEM + V D D _MEM

2
@ R 746 @ R 750 @ R 745 @ R 7 49
100_0402_5% 100_0402_5% 100_0402_5% 100_0402_5%

1
C M D A28 C M D A30 C M D A18
CMDA7

1
U8B SG@ SG@ S G@ SG@
P a rt 2 of 5 R 7 48 R 752 R 7 47 R 751
<28> M D A[15..0] C M D A [30..0] <28,29>
MDA0 D22 F26 CMDA0 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
MDA1 FBA_D0 FBA_CMD0 CMDA1
E24 J24
MDA2 E22 FBA_D1 FBA_CMD1 F25 CMDA2

2
MDA3 FBA_D2 FBA_CMD2 CMDA3
D24 M23
MDA4 FBA_D3 FBA_CMD3 CMDA4
D26 N27
MDA5 D27 FBA_D4 FBA_CMD4 M27 CMDA5
MDA6 FBA_D5 FBA_CMD5 CMDA6
C27 K26
MDA7 B27 FBA_D6 FBA_CMD6 J25 CMDA7
MDA8 FBA_D7 FBA_CMD7 CMDA8
A21 J27
MDA9 FBA_D8 FBA_CMD8 CMDA9
B21 G23
M D A10 FBA_D9 FBA_CMD9 C M D A10
C21 G26
M D A11 FBA_D10 FBA_CMD10 C M D A11
C19 J23
M D A12 FBA_D11 FBA_CMD11 C M D A12
C18 M25
M D A13 D18 FBA_D12 FBA_CMD12 K27 C M D A13
M D A14 FBA_D13 FBA_CMD13 C M D A14
B18 G25
M D A15 C16 FBA_D14 FBA_CMD14 L24 C M D A15
<28> M D A[31..16] FBA_D15 FBA_CMD15
M D A16 E21 K23 C M D A16
MEMORY INTERFACE

M D A17 F21 FBA_D16 FBA_CMD16 K24 C M D A17

M D A18 FBA_D17 FBA_CMD17 C M D A18
D20 G22
M D A19 FBA_D18 FBA_CMD18 C M D A19
F20 K25
B
M D A20 FBA_D19 FBA_CMD19 C M D A20
B
D17 H22
M D A21 FBA_D20 FBA_CMD20 C M D A21
F18 M26
M D A22 FBA_D21 FBA_CMD21 C M D A22
D16 H24
M D A23 FBA_D22 FBA_CMD22 C M D A23
E16 F27
M D A24 FBA_D23 FBA_CMD23 C M D A24
A22 J26
M D A25 C24 FBA_D24 FBA_CMD24 G24 C M D A25
M D A26 FBA_D25 FBA_CMD25 C M D A26
D21 G27
M D A27 FBA_D26 FBA_CMD26 C M D A27
B22 M24
M D A28 C22 FBA_D27 FBA_CMD27 K22 C M D A28
M D A29 FBA_D28 FBA_CMD28 C M D A29
A25 J22
M D A30 FBA_D29 FBA_CMD29 C M D A30
<29> M D A[47..32] B25 L22
M D A31 FBA_D30 FBA_CMD30
A26 D Q M A [3..0] <28>
M D A32 FBA_D31 D Q M A0
U24 C26
M D A33 V24 FBA_D32 FBA_DQM0 B19 D Q M A1
M D A34 FBA_D33 FBA_DQM1 D Q M A2
V23 D19
M D A35 R24 FBA_D34 FBA_DQM2 D23 D Q M A3
FBA_D35 FBA_DQM3 D Q M A [7..4] <29>
M D A36 T23 T24 D Q M A4
M D A37 R23 FBA_D36 FBA_DQM4 AA23 D Q M A5
M D A38 FBA_D37 FBA_DQM5 D Q M A6
P24 AB27
M D A39 FBA_D38 FBA_DQM6 D Q M A7
P22 T26
M D A40 AC24 FBA_D39 FBA_DQM7
FBA_D40 D Q S A #[3..0] <28>
M D A41 AB23 D25 D Q S A#0
M D A42 FBA_D41 FBA_DQS_RN0 D Q S A#1
AB24 A18
M D A43 W24 FBA_D42 FBA_DQS_RN1 E18 D Q S A#2
M D A44 FBA_D43 FBA_DQS_RN2 D Q S A#3
AA22 B24 D Q S A #[7..4] <29>
M D A45 W23 FBA_D44 FBA_DQS_RN3 R22 D Q S A#4
M D A46 FBA_D45 FBA_DQS_RN4 D Q S A#5
W22 Y24
M D A47 V22 FBA_D46 FBA_DQS_RN5 AA27 D Q S A#6
<29> M D A[63..48] FBA_D47 FBA_DQS_RN6
M D A48 AA25 R27 D Q S A#7
M D A49 FBA_D48 FBA_DQS_RN7
W27 D Q S A [3..0] <28>
M D A50 FBA_D49 D Q S A0
W26 C25
M D A51 FBA_D50 FBA_DQS_WP0 D Q S A1
W25 A19
M D A52 FBA_D51 FBA_DQS_WP1 D Q S A2
AB25 E19
M D A53 FBA_D52 FBA_DQS_WP2 D Q S A3
AB26 A24 D Q S A [7..4] <29>
M D A54 FBA_D53 FBA_DQS_WP3 D Q S A4
C AD26 T22 C
M D A55 FBA_D54 FBA_DQS_WP4 D Q S A5
AD27 AA24
M D A56 FBA_D55 FBA_DQS_WP5 D Q S A6
V25 AA26
M D A57 R25 FBA_D56 FBA_DQS_WP6 T27 D Q S A7
M D A58 V26 FBA_D57 FBA_DQS_WP7
M D A59 FBA_D58 FB_ VREF
V27
FBA_D59 FB_VREF
A16 W=15mils
M D A60 R26
M D A61 FBA_D60
T25 F24 C L KA0 <28>
M D A62 N25 FBA_D61 FBA_CLK0 F23
FBA_D62 FBA_CLK0_N C L KA0# <28>
M D A63 N26
FBA_D63
N24 C L KA1 <29>
FBA_CLK1
N23 C L KA1# <29>
FBA_CLK1_N
M22 ODT
FBA_DEBUG + V D D _MEM
SG@
N10M-GLM-S-A1_BGA533 ODT R12 1 2 10K_0402_5%
+ V D D _MEM SG@
1

@ R 699 Rt
1K_0402_1%
2

FB_ VREF
0 .1U_0402_16V4Z
1

1
C 813
@ R 701 Rb
1K_0402_1% @
2
2

D D
Close to U8

S ecurity Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/09/15 Deciphered Date 2009/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N10M(3)_VGA RAM Interface
Size D o c u m ent Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
C u s t om Ca lp e lla DI S LA4 743P 0 .1

1 http://laptop-motherboard-schematic.blogspot.com/
2 3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4
D a te: Monday, April 13, 2009
5
Sheet 26 of 49
 1 2 3 4 5

VGA Pow er sequence: +.3VS->+NVVDD->+VDD_MEM U 8E

+NVVDD U 8D + V D D _MEM B2 P a rt 5 of 5 U2
P a rt 4 of 5 GND GND
11.44A B5 U5
GND GND
J9 A13 B8 U11
VDD FBVDDQ GND GND

0 .1U_0402_16V4Z

0 .1U_0402_16V4Z

0 .1U_0402_16V4Z

0 .1U_0402_16V4Z

0 .1U_0402_16V4Z

0 .1U_0402_16V4Z

0 .1U_0402_16V4Z

0 .1U_0402_16V4Z

0.047U_0402_16V7K

0.047U_0402_16V7K

0.047U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

4.7U_0603_6.3V6K
J10 B13 B11 U12
VDD FBVDDQ GND GND
J12 C13 B14 U13
VDD FBVDDQ GND GND

C 814

C 815

C 816

C 817

C 818

C 819

C 820

C 821

C 822

C 823

C 824

C 826

C 827

C 828

C 829
1 1 1 1 1 1 1 1 J13 D13 1 1 1 1 B17 U14
VDD FBVDDQ GND GND
L9 D14 B20 U15
VDD FBVDDQ GND GND
M9 E13 B23 U16
M11 VDD FBVDDQ F13 B26 GND GND U17
2 2 2 2 2 2 2 2 VDD FBVDDQ 2 2 2 2 GND GND
M17 F14 E2 U23
N9 VDD FBVDDQ F15 E5 GND GND U26
SG@ SG@ SG@ SG@ S G@ SG@ SG@ SG@ N11 VDD FBVDDQ F16 E8 GND GND V9
VDD FBVDDQ S G@ SG@ SG@ SG@ SG@ S G@ SG@ GND GND
N12 F17 E11 V19
VDD FBVDDQ GND GND
A N13 F19 E17 W11 A
VDD FBVDDQ GND GND
N14
VDD 3.4A FBVDDQ
F22 E20
GND GND
W14
N15 H23 E23 W17
VDD FBVDDQ GND GND
N16 H26 E26 Y2
VDD FBVDDQ GND GND
N17 J15 H2 Y5

GND
N19 VDD FBVDDQ J16 H5 GND GND Y23
VDD FBVDDQ GND GND

0.022U_0402_16V7K

0.022U_0402_16V7K

0.022U_0402_16V7K

0.022U_0402_16V7K

0.022U_0402_16V7K

0.022U_0402_16V7K

0.022U_0402_16V7K

0.022U_0402_16V7K
P11 J18 J11 Y26
VDD FBVDDQ GND GND
0.022u X 9 P12
VDD FBVDDQ
J19 J14
GND GND
AC2

C 831

C 832

C 833

C 834

C 835

C 836

C 837

C 838
0.01u X 3 1 1 1 1 1 1 1 1 P13
VDD FBVDDQ
L19 J17
GND GND
AC5
0.1u X 8 P14 L23 K9 AC6
VDD FBVDDQ GND GND
4.7u X 1 P15
VDD FBVDDQ
L26 K19
GND GND
AC8
1u(0402) X 1 P16 M19 L2 AC11
2 2 2 2 2 2 2 2 VDD FBVDDQ GND GND
1u(0603) X 1 P17
VDD FBVDDQ
N22 L5
GND GND
AC14
10u(0805) X 3 R9
VDD FBVDDQ
U22 L11
GND GND
AC17
R11 Y22 + P C IE L12 AC20

POWER
SG@ SG@ SG@ SG@ S G@ SG@ SG@ SG@ VDD FBVDDQ GND GND
R12 L13 AC23
VDD GND GND
R13 AG6 L14 AC26
VDD PEX_IOVDDQ GND GND

0 .1U_0402_16V4Z

0 .1U_0402_16V4Z

1 U_0603_10V4Z

1 U_0603_10V4Z

4.7U_0603_6.3V6K

10U_0805_6.3V6M
R14 AF6 L15 AF2
VDD PEX_IOVDDQ GND GND
R15 AE6 L16 AF5
VDD PEX_IOVDDQ GND GND

C 8 39

C 8 40

C 8 41

C 8 42

C 8 43

C 8 44
R16 AD6 1 1 1 1 1 1 L17 AF8
R17 VDD PEX_IOVDDQ AC13 M12 GND GND AF11
VDD PEX_IOVDDQ GND GND

10U_0805_6.3V6M

4.7U_0603_6.3V6K

1 U_0402_6.3V4Z

1 U_0402_6.3V4Z
T9 AC7 M13 AF14
T11 VDD PEX_IOVDDQ AB17 M14 GND GND AF17
VDD 1.8A PEX_IOVDDQ 2 2 2 2 2 2 GND GND
C 847

C 848

C 849

C 850
1 1 1 1 T17 AB16 M15 AF20
VDD PEX_IOVDDQ GND GND
U9 AB13 M16 AF23
VDD PEX_IOVDDQ S G@ SG@ SG@ SG@ SG@ S G@ GND GND
U19 AB9 P2 AF26
VDD PEX_IOVDDQ GND GND
W9 AB8 P5 T16
2 2 2 2 VDD PEX_IOVDDQ + P C IE GND GND
W10 AB7 P9 T15
W12 VDD PEX_IOVDDQ Layout Note:Please P19 GND GND T14
SG@ S G@ SG@ SG@ VDD colse to Ball.
600 mA GND GND
W13 AG7 P23 F6
VDD PEX_IOVDD GND GND

0 .1U_0402_16V4Z

0 .1U_0402_16V4Z

1 U_0603_10V4Z

1 U_0603_10V4Z

4.7U_0603_6.3V6K

10U_0805_6.3V6M
W18 AF7 P26
VDD PEX_IOVDD GND

C 852

C 853

C 854

C 855

C 856

C 857
+ 3 VS_NV W19 AE7 T12 A15 S G @ R 742 1 2 40.2_0402_1%
VDD PEX_IOVDD 1 1 1 1 1 1 GND FB_CAL_PU_GND
AD8 T13
SG@ PEX_IOVDD GND
150mA AD7 B16 S G @ R 743 1 2 60.4_0402_1%
R 703 1 PEX_IOVDD FB_CAL_TERM_GND
2 0_0603_5% V D D 33 A12 AC9 S G@
B VDD33 PEX_IOVDD 2 2 2 2 2 2 B
1 U_0402_6.3V4Z

0 .1U_0402_16V4Z

0 .1U_0402_16V4Z
B12 0_0402_5% 1 2 R 7 04 W16 F11 S G @ R 705 1 2 40.2K_0402_1%
VDD33 GND_SENSE MULTI_STRAP_REF1_GND
1 U_0603_10V4Z

C12 AF9 P E X _ PLLDVDD S G@

VDD33 PEX_PLLVDD
C 858

C 859

C 860

C 861

1 1 1 1 D12 0_0402_5% 1 2 R 7 06 E14 F10 S G @ R 707 1 2 40.2K_0402_1%

VDD33 G P U _ P LLVDD S G@ SG@ SG@ SG@ SG@ S G@ GND_SENSE MULTI_STRAP_REF0_GND
E12 K6
VDD33 VID_PLLVDD
F12
VDD33 L6 S P _ P LLVDD N10M-GLM-S-A1_BGA533
2 2 2 2 SP_PLLVDD
SG@
P E X _SVDD_3V3 AG9 K5
SG@ SG@ S G@ SG@ PEX_SVDD_3V3 PLLVDD
R19 F B _ P L L AVDD + 3 V S_NV
IF P A_IOVDD FB_PLLAVDD SG@
V3
IFPA_IOVDD R 708 1
150mA AC19 P E X _SVDD_3V3 2 0_0402_5%
I F P B _ I OVDD FB_PLLAVDD
V2
IFPB_IOVDD

0 .1U_0402_16V4Z
150mA T19
FB_DLLAVDD

C 8 62
IF P C_IOVDD J6 1
SG@ IFPC_IOVDD
R71 1 2 10K_0402_5% I F P D E _ I O VDD H6 AG2 DACA_VDD
IFPDE_IOVDD DACA_VDD
120mA DACB_VDD W5 D A C B _ V D D S G @ R 7 09 1 2 10K_0402_5% SG@ 2
I FPAB_PLLVDD AD5
IFPAB_PLLVDD
IF PC_PLLVDD P6 B15 S G @ R 7 10 1 2 40.2_0402_1% + V D D _MEM
SG@ IFPC_PLLVDD FB_CAL_PD_VDDQ
R76 1 2 10K_0402_5% I F P D _ P L LVDD N6 W15 S G @ R 7 44 1 2 0_0402_5%
SG@ IFPD_PLLVDD VDD_SENSE
R79 1 2 10K_0402_5% I F P E _ P LLVDD D7 E15 S G @ R 7 11 1 2 0_0402_5% + N V V D D _ S ENSE to Pow er
IFPE_PLLVDD VDD_SENSE

N10M-GLM-S-A1_BGA533 SG@ + P C IE
10mA L33
SG@
F B _ P L L AVDD 1 2
B LM18PG181SN1D_0603

4.7U_0603_6.3V6K

1 U_0402_6.3V4Z
C 866

C 867
1 1
C + P C IE SG@ C
L34 85mA
1 2 I FPAB_PLLVDD
B L M18PG181SN1D_0603 I F P B _ I OVDD 2 2 Layout Note:Please
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1U_0603_10V6K

4700P_0402_25V7K

0.1U_0402_10V6K

0.1U_0402_10V6K

@ @ @ + 1 .8VS_NV SG@ colse to BGA.

C 8 68

C 8 69

C 8 70

C 8 71

C 9 52

C 9 59

1 1 1 1 1 1 L44 100mA
1 2 IF P A_IOVDD SG@ SG@
B L M18PG181SN1D_0603
1U_0603_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

SG@ 2 2 2 2 2 2
4.7U_0603_6.3V6K

S G@ + P C IE S G@ + P C IE
C 8 76

C 8 77

C 8 78

C 8 91

1 1 1 1 L 46 135mA L 37
S P _ P LLVDD 1 2 G P U _ P LLVDD 1 2
SG@ S G@ B LM18PG181SN1D_0603 B LM18PG181SN1D_0603

C 1061

4.7U_0603_6.3V6K

C 960

1 U_0402_6.3V4Z

4.7U_0603_6.3V6K

1 U_0402_6.3V4Z

0 .1U_0402_16V4Z

0 .1U_0402_16V4Z
2 2 2 2

C 879

C 880

C 881

C 882
1 1 1 1 1 1
SG@ SG@ SG@ SG@
+ 3 VS_NV S G@
L 38 2 2 2 2 2 2
70mA IF PC_PLLVDD
100mA
1 2
B L M18PG181SN1D_0603 SG@ SG@
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1U_0603_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

S G@ SG@ SG@ SG@

C 883

C 884

C 885

C 886

C 961

C 962

1 1 1 1 1 1

+ P C IE SG@ SG@ + P C IE
SG@ 2 2 2 2 2 2 L42 150mA 110mA L40
1 2 IF P C_IOVDD PEX_PLLDVDD 1 2
B LM18PG181SN1D_0603 1 0 N H_MLG1608B10NJT_5%
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1U_0603_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0 .1U_0402_16V4Z

1 U_0402_6.3V4Z

4.7U_0603_6.3V6M

1 U_0402_6.3V4Z

1 U_0402_6.3V4Z

1 U_0402_6.3V4Z

1 U_0402_6.3V4Z
SG@ S G@ SG@ SG@ SG@
C 9 02

C 9 03

C 9 04

C 9 05

C 9 63

C 8 94

C 8 95

C 8 96

C 8 97

C 8 93

C 9 64

C 8 98
1 1 1 1 1 1 1 1 1 1 1 1

+ 3 VS_NV SG@ SG@ 2 2 2 2 2 2 2 2 2 2 2 2

D D
L41 120mA Layout Note:Please
1 2 DACA_VDD colse to Ball.
B LM18PG181SN1D_0603 SG@ SG@ SG@ SG@ S G@ SG@ SG@ SG@ S G@ SG@ SG@
4.7U_0603_6.3V6K

1 U_0402_6.3V4Z

4700P_0402_25V7K

0.1U_0402_10V6K

0.1U_0402_10V6K
C 958

C 899

C 900

C 901

C 887

1 1 1 1 1 1 Layout Note:Please
C 888
colse to BGA.
470P_0402_50V8J
2 2 2 2 2 2 SG@
S ecurity Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/09/15 Deciphered Date 2009/12/31 Title
SG@ S G@ SG@ SG@ SG@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N10M(4)_Power/GND
Size D o c u m ent Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
C u s t om Ca lp e lla DI S LA4 743P 0 .1

1 http://laptop-motherboard-schematic.blogspot.com/ 2 3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4
D a te: Monday, April 13, 2009
5
Sheet 27 of 49
 1 2 3 4 5

VRAM DDR3 chips (512MB) Hynix : H5TQ1G63BFR-12C-->SA000032400 DATA Bus

Sam sung : K4W1G1646E-HC12-->SA000035700 Address 0..31 32..63
64Mx16 DDR3 700MHz*4==>512MB
CMD0 A4
Low 32 bit FB U 11 U12
CMD1 RAS# RAS#
CMD2 A5
M E M _ V REF0 M9 E4 M D A21 M E M _ V REF1 M9 E4 MDA5
VREFCA DQL0 M D A18 VREFCA DQL0 MDA1
D Q S A [7..0]
H2
VREFDQ DQL1
F8 H2
VREFDQ DQL1
F8 CMD3 BA1 BA1
<26,29> D Q S A[7..0] F3 M D A23 F3 MDA6
DQL2 DQL2
C M D A19 N4
A0 DQL3
F9 M D A16 C M D A19 N4
A0 DQL3
F9 MDA2 CMD4 A2
A D Q S A#[7..0] C M D A25 P8 H4 M D A20 C M D A25 P8 H4 MDA4 A
<26,29> D Q S A#[7..0] A1 DQL4 A1 DQL4
C M D A22 P4
A2 DQL5
H9 M D A19 C M D A22 P4
A2 DQL5
H9 MDA0 CMD5 A4
D Q M A[7..0] C M D A24 N3 G3 M D A22 C M D A24 N3 G3 MDA7
<26,29> D Q M A[7..0] A3 DQL6 A3 DQL6
CMDA0 P9 H8 M D A17 CMDA0 P9 H8 MDA3 CMD6 A3
M D A [63..0] CMDA2 A4 DQL7 CMDA2 A4 DQL7
<26,29> M D A[63..0] P3 P3
C M D A21 A5 C M D A21 A5
R9
A6
R9
A6 CMD7 CKE
C M D A [30..0] C M D A16 R3 D8 MDA8 C M D A16 R3 D8 M D A26
<26,29> C M D A [30..0] A7 DQU0 A7 DQU0
C M D A23 T9 C4 M D A14 C M D A23 T9 C4 M D A30 CMD8 CS#
C M D A20 A8 DQU1 M D A10 C M D A20 A8 DQU1 M D A28
R4 C9 R4 C9
A9 DQU2 A9 DQU2
C M D A17 L8
A10/AP DQU3
C3 M D A12 C M D A17 L8
A10/AP DQU3
C3 M D A29 CMD9 A11 A11
CMDA9 R8 A8 M D A11 CMDA9 R8 A8 M D A27
A11 DQU4 A11 DQU4
C M D A14 N8
A12 DQU5
A3 M D A13 C M D A14 N8
A12 DQU5
A3 M D A25 CMD10 CAS# CAS#
C M D A26 T4 B9 MDA9 C M D A26 T4 B9 M D A24
A13 DQU6 M D A15 A13 DQU6 M D A31
T8
A14 DQU7
A4 T8
A14 DQU7
A4 CMD11 WE# WE#
M8 M8
A15/BA3 + V D D _MEM A15/BA3 + V D D _MEM
CMD12 BA0 BA0
C M D A12 M3 B3 C M D A12 M3 B3 CMD13 A5
CMDA3 BA0 VDD CMDA3 BA0 VDD
N9 D10 N9 D10
BA1 VDD BA1 VDD
C M D A27 M4
BA2 VDD
G8 C M D A27 M4
BA2 VDD
G8 CMD14 A12 A12
K3 K3
VDD VDD
VDD
K9
VDD
K9 CMD15 RST RST
N2 N2
C L KA0 VDD C L KA0 VDD
J8
CK VDD
N10 J8
CK VDD
N10 CMD16 A7 A7
C L KA0# K8 R2 C L KA0# K8 R2
C M D A18 CK VDD C M D A18 CK VDD
K10
CKE/CKE0 VDD
R10
+ V D D _MEM
K10
CKE/CKE0 VDD
R10
+ V D D _MEM
CMD17 A10 A10
CMD18 CKE
C M D A30 K2 A2 C M D A30 K2 A2
ODT/ODT0 VDDQ ODT/ODT0 VDDQ
C M D A29 L3
CS VDDQ
A9 C M D A29 L3
CS VDDQ
A9 CMD19 A0 A0
CMDA1 J4 C2 CMDA1 J4 C2
RAS VDDQ RAS VDDQ
C M D A10 K4
CAS VDDQ
C10 C M D A10 K4
CAS VDDQ
C10 CMD20 A9 A9
C M D A11 L4 D3 C M D A11 L4 D3
WE 310mA VDDQ WE 310mA VDDQ
VDDQ
E10
VDDQ
E10 CMD21 A6 A6
F2 F2
B
D Q S A2 VDDQ D Q S A0 VDDQ B
F4
DQSL VDDQ
H3 F4
DQSL VDDQ
H3 CMD22 A2
D Q S A1 C8 H10 D Q S A3 C8 H10
DQSU VDDQ DQSU VDDQ
CMD23 A8 A8
D Q M A2 E8
DML VSS
A10 D Q M A0 E8
DML VSS
A10 CMD24 A3
D Q M A1 D4 B4 D Q M A3 D4 B4
DMU VSS DMU VSS
VSS
E2
VSS
E2 CMD25 A1 A1
G9 G9
D Q S A#2 VSS D Q S A#0 VSS
G4
DQSL VSS
J3 G4
DQSL VSS
J3 CMD26 A13 A13
D Q S A#1 B8 J9 D Q S A#3 B8 J9
DQSU VSS DQSU VSS
VSS
M2
VSS
M2 CMD27 BA2 BA2
M10 M10
VSS VSS
VSS
P2
VSS
P2 CMD28 ODT
<26,29> C M D A 15 C M D A15 T3 P10 C M D A15 T3 P10
RESET VSS RESET VSS
VSS
T2
VSS
T2 CMD29 CS#
ZQ 0 L9 T10 ZQ 1 L9 T10
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
CMD30
1

1
10K_0402_5%

243_0402_1%

243_0402_1%
J2 B2 J2 B2 LOW HIGH
NC/ODT1 VSSQ NC/ODT1 VSSQ
R 7 14

R 7 15

R 7 16
L2 B10 L2 B10
J10 NC/CS1 VSSQ D2 J10 NC/CS1 VSSQ D2
NC/CE1 VSSQ NC/CE1 VSSQ
L10 D9 L10 D9
NCZQ1 VSSQ NCZQ1 VSSQ
E3 E3
2

2
A1 VSSQ E9 A1 VSSQ E9
SG@ SG@ NC VSSQ S G@ NC VSSQ
A11 F10 A11 F10
T1 NC VSSQ G2 T1 NC VSSQ G2
NC VSSQ NC VSSQ
T11 G10 T11 G10
NC VSSQ NC VSSQ
100-BALL 100-BALL
S D R A M D DR3 S D R A M D DR3
K 4 B 1 G 1646D-HCF8_FBGA100 K 4 B 1 G 1 646D-HCF8_FBGA100
VRAM@ VRAM@
+ V D D _MEM

C C

1
+ V D D _MEM C L KA0 SG@
<26> C L K A0
R 717
1

SG@ 1K_0402_1%
1

SG@ R 718
R 7 19 121_0402_1%

2
1K_0402_1%
M E M _ V REF1
2
2

1
1 2 SG@ 1 SG@
M E M _ V REF0 0.01U_0402_16V7K C 906 R 720 C 907
SG@ 1K_0402_1% 0.01U_0402_16V7K
1

SG@ 1 S G@ SG@
R 7 21 C 9 08 R 722 2

2
1K_0402_1% 0.01U_0402_16V7K 121_0402_1%

2
2

C L KA0#
<26> C L KA0#

+ V D D _MEM
DDR3 BGA MEMORY
+ V D D _MEM
DDR3 BGA MEMORY
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

C 909

C 910

C 911

C 912

C 913

C 914

C 915

C 916

C 917

C 918
1 1 1 1 1 1 1 1 1 1
C 919

C 920

C 921

C 922

C 923

C 924

C 925

C 926

C 927

C 928

1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2
D 2 2 2 2 2 2 2 2 2 2 D
S G@ SG@ SG@ SG@ SG@ S G@ SG@ SG@ SG@ SG@

SG@ S G@ SG@ SG@ SG@ SG@ S G@ SG@ SG@ SG@

S ecurity Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/09/15 Deciphered Date 2009/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM DDR3
Size D o c u m ent Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4901P
1 http://laptop-motherboard-schematic.blogspot.com/ 2 3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4
D a te: Monday, April 13, 2009
5
Sheet 28 of 49
 1 2 3 4 5

VRAM DDR3 chips (512MB) <26,28> D Q S A[7..0]

D Q S A [7..0]

D Q S A#[7..0]
64Mx16 DDR3 700MHz*4==>512MB <26,28> D Q S A#[7..0]
D Q M A[7..0]
<26,28> D Q M A[7..0]
High 32 bit FB <26,28> M D A [63..0]
M D A [63..0]

U 13 C M D A [30..0] U 14
<26,28> C M D A [30..0]
M E M _ V REF2 M9 E4 M D A39 M E M _ V REF3 M9 E4 M D A41
H2 VREFCA DQL0 F8 M D A36 H2 VREFCA DQL0 F8 M D A46
VREFDQ DQL1 F3 M D A37 VREFDQ DQL1 F3 M D A40
C M D A19 DQL2 M D A34 C M D A19 DQL2 M D A45
N4 F9 N4 F9
C M D A25 A0 DQL3 M D A38 C M D A25 A0 DQL3 M D A42
A P8 H4 P8 H4 A
CMDA4 A1 DQL4 M D A33 CMDA4 A1 DQL4 M D A47
P4 H9 P4 H9
CMDA6 N3 A2 DQL5 G3 M D A35 CMDA6 N3 A2 DQL5 G3 M D A44
CMDA5 A3 DQL6 M D A32 CMDA5 A3 DQL6 M D A43
P9 H8 P9 H8
C M D A13 A4 DQL7 C M D A13 A4 DQL7
P3 P3
C M D A21 R9 A5 C M D A21 R9 A5
C M D A16 A6 M D A61 C M D A16 A6 M D A48
R3 D8 R3 D8
C M D A23 A7 DQU0 M D A60 C M D A23 A7 DQU0 M D A53
T9 C4 T9 C4
C M D A20 A8 DQU1 M D A59 C M D A20 A8 DQU1 M D A50
R4 C9 R4 C9
C M D A17 A9 DQU2 M D A62 C M D A17 A9 DQU2 M D A52
L8 C3 L8 C3
CMDA9 A10/AP DQU3 M D A58 CMDA9 A10/AP DQU3 M D A51
R8 A8 R8 A8
C M D A14 A11 DQU4 M D A63 C M D A14 A11 DQU4 M D A54
N8 A3 N8 A3
C M D A26 A12 DQU5 M D A57 C M D A26 A12 DQU5 M D A49
T4 B9 T4 B9
T8 A13 DQU6 A4 M D A56 T8 A13 DQU6 A4 M D A55
A14 DQU7 A14 DQU7
M8 M8
A15/BA3 + V D D _MEM A15/BA3 + V D D _MEM

C M D A12 M3 B3 C M D A12 M3 B3
CMDA3 BA0 VDD CMDA3 BA0 VDD
N9 D10 N9 D10
C M D A27 BA1 VDD C M D A27 BA1 VDD
M4 G8 M4 G8
BA2 VDD K3 BA2 VDD K3
VDD VDD
K9 K9
VDD N2 VDD N2
C L KA1 VDD C L KA1 VDD
J8 N10 J8 N10
C L KA1# CK VDD C L KA1# CK VDD
K8 R2 K8 R2
CMDA7 CK VDD CMDA7 CK VDD
<26> C M D A7 K10 R10 K10 R10
CKE/CKE0 VDD + V D D _MEM CKE/CKE0 VDD + V D D _MEM

<26> C M D A28 C M D A28 K2 A2 C M D A28 K2 A2

CMDA8 ODT/ODT0 VDDQ CMDA8 ODT/ODT0 VDDQ
L3 A9 L3 A9
CMDA1 J4 CS VDDQ C2 CMDA1 J4 CS VDDQ C2
C M D A10 RAS VDDQ C M D A10 RAS VDDQ
K4 C10 K4 C10
C M D A11 L4 CAS VDDQ D3 C M D A11 L4 CAS VDDQ D3
WE 310mA VDDQ WE 310mA VDDQ
E10 E10
VDDQ VDDQ
F2 F2
B
D Q S A4 VDDQ D Q S A5 VDDQ B
F4 H3 F4 H3
D Q S A7 DQSL VDDQ D Q S A6 DQSL VDDQ
C8 H10 C8 H10
DQSU VDDQ DQSU VDDQ

D Q M A4 E8 A10 D Q M A5 E8 A10
D Q M A7 D4 DML VSS B4 D Q M A6 D4 DML VSS B4
DMU VSS DMU VSS
E2 E2
VSS VSS
G9 G9
D Q S A#4 G4 VSS J3 D Q S A#5 G4 VSS J3
D Q S A#7 DQSL VSS D Q S A#6 DQSL VSS
B8 J9 B8 J9
DQSU VSS DQSU VSS
M2 M2
VSS VSS
M10 M10
VSS VSS
P2 P2
C M D A15 T3 VSS P10 C M D A15 T3 VSS P10
RESET VSS RESET VSS
T2 T2
ZQ 2 L9 VSS T10 ZQ 3 L9 VSS T10
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
J2 B2 J2 B2
R 7 25 NC/ODT1 VSSQ R 726 NC/ODT1 VSSQ
L2 B10 L2 B10
243_0402_1% J10 NC/CS1 VSSQ D2 243_0402_1% J10 NC/CS1 VSSQ D2
NC/CE1 VSSQ NC/CE1 VSSQ
L10 D9 L10 D9
2

2
NCZQ1 VSSQ NCZQ1 VSSQ
E3 E3
A1 VSSQ E9 A1 VSSQ E9
SG@ NC VSSQ S G@ NC VSSQ
A11 F10 A11 F10
T1 NC VSSQ G2 T1 NC VSSQ G2
NC VSSQ NC VSSQ
T11 G10 T11 G10
NC VSSQ NC VSSQ
100-BALL 100-BALL
S D R A M D DR3 S D R A M D DR3 + V D D _MEM
K 4 B 1 G 1646D-HCF8_FBGA100 C L KA1 K 4 B 1 G 1646D-HCF8_FBGA100
<26> C L K A1
VRAM@ VRAM@

1
+ V D D _MEM SG@ SG@
R 727 R 728
C 121_0402_1% 1K_0402_1% C
1

S G@
R 729

2
1K_0402_1% S G@
C 9 29 1 2 0.01U_0402_16V7K M E M _ V REF3
2

1
SG@ 1 SG@

1
M E M _ V REF2 SG@ R 730 C 930
R 731 1K_0402_1% 0.01U_0402_16V7K
1

S G@ 1 SG@ 121_0402_1%
R 732 C 931 2

2
1K_0402_1% 0.01U_0402_16V7K

2
C L KA1#
2 <26> C L K A1#
2

+ V D D _MEM
DDR3 BGA MEMORY + V D D _MEM
DDR3 BGA MEMORY
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
C 9 32

C 9 33

C 9 34

C 9 35

C 9 36

C 9 37

C 9 38

C 9 39

C 9 40

C 9 41

C 9 42

C 9 43

C 9 44

C 9 45

C 9 46

C 9 47

C 9 48

C 9 49

C 9 50

C 9 51
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

SG@ S G@ SG@ SG@ SG@ SG@ S G@ SG@ SG@ SG@ SG@ SG@ S G@ SG@ SG@ SG@ SG@ S G@ SG@ SG@

D D

S ecurity Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/09/15 Deciphered Date 2009/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM DDR3
Size D o c u m ent Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cartier DIS
1 http://laptop-motherboard-schematic.blogspot.com/ 2 3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4
D a te: Monday, April 13, 2009
5
Sheet 29 of 49
 5 4 3 2 1

D D

HDD Connector
J H DD

1 +3VS_ACL
GND
A+
A-
2
3
SATA_TXP0
SATA_TXN0
SATA_TXP0 <11>
SATA_TXN0 <11>
ACCELEROMETER (ST)

10U_0805_6.3V6M
0.1U_0402_16V4Z
4
GND SATA_RXN0 C466 2
5 1 0.01U_0402_16V7K SATA_RXN0_C
SATA_RXN0_C <11>
B- SATA_RXP0 C467 2
6 1 0.01U_0402_16V7K SATA_RXP0_C
SATA_RXP0_C <11> 1 1
B+ +3VS +3VS_ACL +3VS_ACL_IO

C468

C469
7
GND
Near CONN side. D10 R364
0_0603_5% 2 2
8
V33 +3VS
9 2 1 1 2
V33
10
V33 CH751H-40PT_SOD323-2
11
GND
12 Pleace near HDD CONN (JP3)
GND +5VS
13
GND
14
V5 +5VS
15
V5

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
16
V5
17 1 1 1 1
GND

C462

C463

C464

C465
C C
18
Reserved SMB_CLK_S3
19 SMB_CLK_S3 <12,17,18,19>
GND
20
V12 2 2 2 2

14
24 21 0011101b
GND V12 U15
23 22 VDDIO absolute man
GND V12

SCL / SPC
OCTEK_SAT-22EH1G_RV
rating is VDD+0.1
C ONN@
+3VS_ACL_IO 1 13 SMB_DATA_S3
Vdd_IO SDA / SDI / SDO SMB_DATA_S3 <12,17,18,19>
R366 2 12 R367
0_0402_5% GND SDO 0_0402_5%
1 2 3 11 1 2
Reserved Reserved
4 10
GND GND

CD-ROM Connector 5
GND INT 2
9

+3VS_ACL 6 8 A CCEL_INT <14>

Vdd INT 1

J O DD

CS
13 LIS302DLTR_LGA14_3x5

7
GND SATA_TXP4
12 SATA_TXP4 <11>
A+ SATA_TXN4
11 SATA_TXN4 <11>
A- R368 2
10 1
GND SATA_RXN4 C473 2
9 1 0.01U_0402_16V7K SATA_RXN4_C
SATA_RXN4_C <11>
10K_0402_5%
B- SATA_RXP4 C474 2
8 1 0.01U_0402_16V7K SATA_RXP4_C
SATA_RXP4_C <11> M ust be placed in the center of the system.
B B+ B
7 Placea caps. near ODD CONN.
GND +5VS
Near CONN side. 02/12 Change SM bus to VS
6
DP
5
V5
0.1U_0402_16V4Z

1U_0603_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z

4 +5VS
V5
3 1 1 1 1
MD
C475

C476

C477

C478

2
GND
1
GND
2 2 2 2 Z ZZ1
SUYIN_127382FR013GX09ZR
C ONN@

PCB-MB

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & CDROM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev

http://laptop-motherboard-schematic.blogspot.com/ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom C alpella DI S LA4743P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: Monday, April 13, 2009 Sheet 30 of 49
5 4 3 2 1
 A B C D E

+3VALW + 3VS_WWAN
Mini Card Solt--WLAN/WWAN @ C977 1 2 47P_0402_50V8J
+3VALW +1.5VS_WLAN J M INIA

0.1U_0402_16V4Z
0.01U_0402_16V7K 4.7U_0805_10V4Z R388 IC H_PCIE_WAKE# A1 A2 +3VS_WLAN
C H_DATA WAKE# +3.3Vaux
2 1 +1.5VS <35> CH_DATA A3 GND
COEX1

0.1U_0402_16V4Z

4.7U_0805_10V4Z
0.01U_0402_16V7K
1 CH_ CLK A5 A6 +1.5VS_WLAN
<35> CH_ CLK COEX2 +1.5V

C509
0.1U_0402_16V4Z 1 1 1 1 1 1 1 0_0805_5% <12> CL KREQ_WLAN# A7 A8 LPC_FRAME# <11,36,37>
CLKREQ# UIM_PWR

C512

C513

C514
C515 C516 C517 C518 A9 A10
GND UIM_DATA L PC_AD3 <11,36,37>
CL K_PCIE_MCARD2# A11 A12
2 <12> CLK_PCIE_WLAN# REFCLK- UIM_CLK L PC_AD2 <11,36,37>
CL K_PCIE_MCARD2 A13 A14
2 2 2 2 2 2 2 <12> CLK_PCIE_WLAN REFCLK+ UIM_RESET L PC_AD1 <11,36,37>
A15 A16 L PC_AD0 <11,36,37>
PLT_RST# GND UIM_VPP
A17 GND
1 0.1U_0402_16V4Z Reserved XMIT_OFF# D13 1
<14> CLK_DEBUG_PORT_1 A19 A20 2 1 XMIT_OFF <14>
Reserved W_DISABLE# PLT_RST# CH751H-40_SC76
A21 A22
R399 1 GND PERST#
<12> P CIE_RXN2 2 0_0402_5% P CIE_C_RXN2 A23 A24 @ R400 1 2 0_0805_5% +3VALW
R401 1 PERn0 +3.3Vaux
<12> PCIE_RXP2 2 0_0402_5% PCIE_C_RXP2 A25 GND R402 1 2 0_0805_5% +3VS_WLAN
PERp0
A27 A28 +1.5VS_WLAN
+ 3VS_WWAN +3VS_WLAN GND +1.5V SMBCLK
A29 A30
R389 PCIE_TXN2 GND SMB_CLK SMBDATA
<12> PCIE_TXN2 A31 A32
@ R409 PCIE_TXP2 PETn0 SMB_DATA
2 1 +3VS <12> PCIE_TXP2 A33 GND
PETp0

0.1U_0402_16V4Z

4.7U_0805_10V4Z
1 2 A35 A36 USB20_N5 <14>
0_0603_5% 0_0805_5% GND USB_D-
1 1 A37 A38 USB20_P5 <14>
+3VS GND USB_D+

C510

C511
A39 GND
R410 +3.3Vaux
+3VS_WLAN A41 A42
+3.3Vaux LED_WWAN#
S

3 1 1 2 A43 A44
D

+3VALW 2 2 GND LED_WLAN# W L_LED# <38>

0_1206_5% A45 A46
@ Q16 Reserved LED_WPAN#
A47 A48 +1.5VS_WLAN
SI2301BDS_SOT23 Reserved +1.5V
A49
G

GND
2

Reserved
<37> W W A N_POWER_OFF A51 A52 +3VS_WLAN
Reserved +3.3Vaux
2
A53 A54
GND GND @ C978
QUASA_CA0416-092N21 47P_0402_50V8J
C ONN@ 1
@ C979 1 2 47P_0402_50V8J
J M INIB
IC H_PCIE_WAKE# B1 B2 +3VS_WWAN
C H_DATA WAKE# +3.3Vaux
B3 B4
CH_ CLK COEX1 GND
B5 B6 +1.5VS_WLAN
COEX1 +1.5V UIM _ PWR_R
<12> CL K REQ_WWAN# B7 B8
CLKREQ# UIM_PWR U IM_DATA_R
B10
GND UIM_DATA UI M_CLK_R
<12> CL K_PCIE_WWAN# B11 B12
REFCLK- UIM_CLK U IM_RST_R
B13 B14
2 SIM card Connector UIM _PWR
@ R406
<12> CL K _PCIE_WWAN
B17
REFCLK+
GND
Reserved
UIM_RESET
UIM_VPP
GND
B16
B18
UIM_VPP_R
2
1 2 UIM_DATA B19 B20 M_WXMIT_OFF# D12 2 1 WXMIT_OFF# <14>
47K_0402_5% 0_0402_5% Reserved W_DISABLE# PLT_RST# CH751H-40_SC76
For PR GND PERST#
B22
J SIM <12> PCIE_RXN1 R395 1 2 P CIE_C_RXN1 B23 B24 @ R396 1 2 0_0805_5% +3VALW
UIM _PWR PERn0 +3.3Vaux
6 8 <12> PCIE_RXP1 1 2 PCIE_C_RXP1 B25 B26 R398 1 2 0_0805_5% + 3VS_WWAN
UIM_DATA 6 G2 UI M_CLK WL_LED# W W _ LED#_R R397 0_0402_5% PERp0 GND
5 7 1 2 B28 +1.5VS_WLAN
UI M_CLK 5 G1 P R@ R758 0_0402_5% GND +1.5V SMBCLK
4 1 B30
U IM_RST 4 C519 @ PCIE_TXN1 GND SMB_CLK SMBDATA
3 <12> PCIE_TXN1 B31 B32
UIM_VPP 3 18P_0402_50V8J XMIT_OFF# 1 M_WXMIT_OFF# PCIE_TXP1 PETn0 SMB_DATA
2 2 B33 B34
2 P R@ R759 0_0402_5% <12> PCIE_TXP1 PETp0 GND
1 B36 USB20_N8 <14>
1 2 R403 0_0603_5% GND USB_D-
B37 B38 USB20_P8 <14>
ACES_87212-06G0 UIM _ PWR_R LPC_FRAME# P R@ GND USB_D+
1 2 +3VS_WWAN 1 2 B39 B40
C ONN@ U IM_DATA_R R760 0_0402_5% LPC_AD3 P R@ +3.3Vaux GND
1 2 1 2 B41 B42 W W _LED# <38>
UI M_CLK_R R761 0_0402_5% LPC_AD2 P R@ R404 0_0603_5% +3.3Vaux LED_WWAN# W W _ LED#_R
1 2 B43 B44
U IM_RST_R R762 0_0402_5% LPC_AD1 P R@ GND LED_WLAN#
1 2 B45 B46
UIM_VPP_R R763 0_0402_5% LPC_AD0 P R@ Reserved LED_WPAN#
1 2 B47 B48 +1.5VS_WLAN
R764 0_0402_5% Reserved +1.5V
B49 B50
Reserved GND
B51 B52 +3VS_WWAN
UIM _ PWR_R UIM _PWR PA@ Reserved +3.3Vaux
1 2 1
U IM_DATA_R R765 1 2 0_0402_5% UIM_DATA PA@
UI M_CLK_R R766 1 2 0_0402_5% UI M_CLK PA@ C980
U IM_RST_R R767 1 2 0_0402_5% U IM_RST PA@ QUASA_CA0416-092N21 47P_0402_50V8J
UIM_VPP_R R768 0_0402_5% UIM_VPP PA@ C ONN@ 2 @
1 2
R769 0_0402_5%

JEXP Near to Express Card slot.

3 New Card 1
GND
+3VS_PEC 3

<14> USB20_N9 2
USB_D-
3
Express Card Power Switch <14> USB20_P9
EXP_CPPE# 4
USB_D+
+1.5VS CPUSB#
5 1 1
C520 RSV
6
RSV
1 2 0.1U_0402_16V4Z U19 <12> SMBCLK SMBCLK 7 C521 C522
SMBDATA SMB_CLK 0.1U_0402_16V4Z 4.7U_0805_10V4Z
12 11 +1.5VS_PEC <12> SMBDATA 8
+3VS 1.5Vin 1.5Vout SMB_DATA 2 2
14 13 +1.5VS_PEC 9
1.5Vin 1.5Vout +1.5V
10
R413 1 0_0402_5% PCIE_PME#_R +1.5V
<13,32> ICH_PCIE_WAKE# 2 11
C523 1 WAKE#
2 0.1U_0402_16V4Z 2 3 +3VS_PEC +3V_PEC 12
3.3Vin 3.3Vout PERST# +3.3VAUX +1.5VS_PEC
4 5 13
C524 1 3.3Vin 3.3Vout PERST#
2 0.1U_0402_16V4Z +3VS_PEC 14
+3.3V
+3VALW 17 15 +3V_PEC 15
AUX_IN AUX_OUT +3.3V
<12> CLKREQ_EXP# 16 1 1
PLT_RST# EXP_CPPE# CLKREQ#
<6,14,32> PLT_RST# 6 19 17
SYSRST# OC# CPPE# C525 C526
<12> CLK_PCIE_EXP# 18
S Y SON PERST# REFCLK- 0.1U_0402_16V4Z 4.7U_0805_10V4Z
<37,38,39,48> S Y S ON 20 8 <12> CLK_PCIE_EXP 19
SHDN# PERST# REFCLK+ 2 2
20
SUSP# GND
<37,39,41,44,45> SUSP# 1 16 <12> PCIE_RXN4 21
STBY# NC PERn0
<12> PCIE_RXP4 22
@ R414 1 PERp0
+3VALW 2 100K_0402_5% 10 7 23
CPPE# GND GND
<12> PCIE_TXN4 24
EXP_CPPE# PETn0
9 <12> PCIE_TXP4 25
CPUSB# PETp0
1 26
GND +3V_PEC
18
RCLKEN @ C527 27
330P_0402_50V7K GND
R5538D001-TR-F_QFN20_4X4~D 28
2 GND
SANTA_130801-5_RT
internal pull high to 3.3Vaux-in C ONN@ C528
1 1
C529
4 0.1U_0402_16V4Z 4.7U_0805_10V4Z 4
EC need setting at Hi-Z & output Low
2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WLAN, WWAN, New Card
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev

http://laptop-motherboard-schematic.blogspot.com/ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C alpella DI S LA 4743P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: Monday, April 13, 2009 Sheet 31 of 49
A B C D E
 5 4 3 2 1

+ D V D D12 + V D D33

1
L2
2 1
R 817
2
LAN Conn.
+ DVDD + 3 V_LAN
J R J 45
0_0805_5% R 369 + 3 V_LAN 13
4 . 7 U H_1008HC-472EJFS-A_5%_1008 Yellow LED+

0 .1U_0402_16V4Z

0 .1U_0402_16V4Z

0 .1U_0402_16V4Z

0 .1U_0402_16V4Z

0 .1U_0402_16V4Z

10U_0805_6.3V6M

0 .1U_0402_16V4Z

0 .1U_0402_16V4Z

0 .1U_0402_16V4Z

0 .1U_0402_16V4Z

0 .1U_0402_16V4Z
1 2 2 2 2 2 1 2 2 2 2 2 300_0402_5%

10U_0805_6.3V6M
L A N _ACT# 2 1 L A N L ED_ACT# 14
Yellow LED-

C 1018

C 1019

C 1020

C 1021

C 1022

C 1023

C 1025

C 1026

C 1027

C 1028

C 1029

C 1030
1 16
C 480 R J 4 5_MIDI3- SHLD1
8
2 1 1 1 1 1 2 1 1 1 1 1 0 .1U_0402_16V4Z PR4- 9
R J 4 5_MIDI3+ DETECT PIN1
7
2 PR4+
R J 4 5_MIDI1- 6
D PR2- D
R J 4 5_MIDI2- 5
PR3-
R J 4 5_MIDI2+ 4
PR3+
U46 R J 4 5_MIDI1+ 3
PR2+
R J 4 5_MIDI0- 2
R 819 2 PR1-
1 12K_0402_1% 1 64 L A N _MDI3- 10
REXT NC L A N _MDI3+ R J 4 5_MIDI0+ DETCET PIN2
2 + V D D33 63 2 1
LAN_X1 VDDX33 NC C 482 PR1+
3 62 + D V D D12 15
LAN_X2 XIN NC L A N _MDI2- 0 .1U_0402_16V4Z SHLD1
4 61 + 3 V_LAN 11
XOUT NC L A N _MDI2+ Green LED+
5 60
GND NC L A N _LINK# 1 L A N L E D_LINK#
Close to Pin8. + DVDD 6
LX AVDD33
59 + V D D33 2 1 12
Green LED-
+ D V D D12 7 58
FB12 GND L A N _MDI1- R 3 71 FOX_JM36113-P1122-7F
+ V D D33 8 57
VDDREG VIN_2
10U_0805_6.3V6M

<12> C L K _ P CIE_LAN# 9 56 L A N _MDI1+ 300_0402_5% C ONN@

CLKN VIP_2
0 .1U_0402_16V4Z

1 1 <12> C L K _ P CIE_LAN 10 55 + D V D D12

CLKP AVDD12
C 1035

+ V D D33 11 54 L A N _MDI0- LANGND

AVDDH VIN_1
C 1034

12 53 L A N _MDI0+ 1 1
2 2
<12> P C IE_TXP3
<12> P C IE_TXN3 13
14
RXP
RXN JMC261 VIP_1
GND
52
51 + D V D D12
C 483 C 484

C 481 2 GND VDD

<12> P C I E_RXN3 1 0.1U_0402_16V7K P C IE_PTX_IRX_N3 15 (LQFP 64) 50 L A N _LINK# 0 .1U_0402_16V4Z 4 .7U_0805_10V4Z
C 479 0.1U_0402_16V7K P CIE_PTX_IRX_P3 TXN LED1 L A N _ACT# 2 2
<12> P C I E_RXP3 2 1 16 49
TXP LED0 M D IO0
+ D V D D12 17 48
AVDDX MDIO0 M D IO1
18 47
<6,14,31> P L T_RST#
<13,31> I C H _ P C I E _WAKE# 19
RSTN
WAKEN
MDIO1
MDIO2
46 M D IO2 10/100 and Giga Transformer Co lay
M PD 20 45 + V D D33
C L K R E Q_LAN# MPD VDDIO M D IO3
<12> C L K R E Q_LAN# 21 44
22 CREQN MDIO3 43 M D IO4
D 4 1 C H 751H-40PT_SOD323-2 SMB_SCL/LED2 MDIO4 R 333 1
<14> C R _ W A K E# 1 2 C R _ C D 1 N 23 42 M D IO5 2 22_0402_5% M D I O5_R
CR_CD0N 24 CR_CD1N MDIO5 41
C CR_CD0N GND M D IO6 U17 C
+ V C C _4IN1 25 40
26 VCC3O MDIO6 39 M D IO7
+ D V D D12 VDD MDIO7
0 .1U_0402_16V4Z

2 + V D D33 27 38 + V D D33 C 1042 1 2 0 .1U_0402_16V4Z 1 24 C 1041 2 1 1000P_0402_50V7K R 8 22 1 2 75_0402_1%

VDDIO VDDIO M D IO8 L A N _MDI0+ TCT1 MCT1 R J 4 5_MIDI0+
28 37 2 23
TESTN MDIO8 TD1+ MX1+
C 1040

C R _ L ED# 29 36 M D IO9 L A N _MDI0- 3 22 R J 4 5_MIDI0-

M D IO14 SMB_SDA/CR_LEDN MDIO9 M D IO10 TD1- MX1-
30 35
1 M D IO13 MDIO14 MDIO10 M D IO11 C 1039
31 34 4 21 2 1 1000P_0402_50V7K R 8 21 1 2 75_0402_1%
MDIO13 MDIO11 M D IO12 L A N _MDI1+ TCT2 MCT2 R J 4 5_MIDI1+
32 33 5 20
GND MDIO12 L A N _MDI1- TD2+ MX2+ R J 4 5_MIDI1-
6 19
LAN_X1 LAN_X2 TD2- MX2-

R J 4 5 _ GND
7 18 C 1085 2 1 1000P_0402_50V7K R 9 23 1 2 75_0402_1%
TCT3 MCT3
2 5 MHZ_16PF_X3S025000FG1H-HX

1 1 L A N _MDI2+ 8 17 R J 4 5_MIDI2+ 8 111DL@

C 1043 C 1044 L A N _MDI2- 9 TD3+ MX3+ 16 R J 4 5_MIDI2-
TD3- MX3-
1

27P_0402_50V8J 27P_0402_50V8J
10 15 C 1083 2 1 1000P_0402_50V7K R 9 22 1 2 75_0402_1%
IN

NC OUT

2 2 J M C261-LGBZ0A_LQFP64_7X7 L A N _MDI3+ TCT4 MCT4 R J 4 5_MIDI3+ 8 111DL@

11 14
TD4+ MX4+
Y4

L A N _MDI3- 12 13 R J 4 5_MIDI3- 1
TD4- MX4-
NC

C 1045
1000P_1206_2KV7K
2

JMC251 Κ SA000039X 00 S U P E R W O R L D_SWG150401 2

JMC261 Κ SA000037N 00 1.For Giga LAN (RTL8111DL):

Mail source: LANKom: LG-2446S-1 (P/N: SP050005L00)
2nd Source: MHPC: NS892406 (P/N: SP050005900)

2.For 10/100M (RTL 8103EL):

Main Source: MHPC NS892404 (P/N: SP050003P00)
D3E support
B
Card Reader Connector B
JREAD1 @ R 925 2 1 0_0402_5% + V D D33
+ V C C _4IN1 3 21 + V C C _4IN1 P L T_RST# R 9 26 1 2 0_0402_5% M PD @ R 927 2 1 0_0402_5% + 3VS
XD-VCC SD-VCC
28
MS-VCC
10U_0805_6.3V6M

0 .1U_0402_16V4Z
M D IO0 32 2
M D IO1 XD-D0 M D I O5_R
10 7 IN 1 CONN 20 1
XD-D1 SD_CLK
C 1062

C 1086
M D IO2 9 14 M D IO0
M D IO3 XD-D2 SD-DAT0 M D IO1
8 12
M D IO8 XD-D3 SD-DAT1 M D IO2 1
7 30
M D IO9 6 XD-D4 SD-DAT2 29 M D IO3 2 @
M D IO10 5 XD-D5 SD-DAT3 27 M D IO8
M D IO11 XD-D6 SD-DAT4 M D IO9
4 23
XD-D7 SD-DAT5 18 M D IO10 + V DD33
M D IO4 SD-DAT6 M D IO11
34 16
M D IO6 33 XD-WE SD-DAT7 25 M D IO4
M D IO14 35 XD-WP SD-CMD 1 CR_CD0N
X D _ CD XD-ALE SD-CD-SW
40
M D IO13 XD-CD M D IO6
39 2
M D IO12 XD-R/B SD-WP-SW
38

1
M D I O5_R 37 XD-RE D40
M D IO7 XD-CE M D I O5_R @ R 823 1
36 26 2 0_0805_5% R 825 R 826 + 5VS R 8 28 1 2 1.2K_0402_5% 2 1 C R _ L ED#
XD-CLE MS-SCLK M D IO0 + 3 V ALW 4.7K_0402_5% 4.7K_0402_5%
17
11 MS-DATA0 15 M D IO1 H T - 1 1 0TW_WHITE
7IN1 GND MS-DATA1 M D IO2
31 19 W hite

2
7IN1 GND MS-DATA2 24 M D IO3
MS-DATA3 40 mils
+ V C C _4IN1

S
22 CR_CD1N 3 1 D 39

D
MS-INS + 3 V_LAN
0 .1U_0402_16V4Z
100K_0402_5%

13 M D IO4 CR_CD1N 2
2

MS-BS X D _ CD
41 2 1
7IN1 GND
R 824

C 485

CR_CD0N
G
42 3

2
7IN1 GND Q 15 1
T A I T W _ R 0 1 5 - B 1 0 - LM @ @ SI2301BDS-T1-E3_SOT23-3 D A N 2 02U_SC70 R 829 1 2 10K_0402_5% M D IO4
CONN@ 1 C 1047
1

A R 382 1 2 0_0402_5% 270P_0402_25V7 R 830 1 2 10K_0402_5% M D IO6 A

<37> L A N _ P O W E R _OFF 2
R 831 1 2 1K_0402_5% M D IO13

S ecurity Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB CardReader&CONN
Size D o c u m ent Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
C u s t om Ca lp e lla DI S LA4 743P 0 .1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D a te: Monday, April 13, 2009 Sheet 32 of 49
5 4 3 2 1

http://laptop-motherboard-schematic.blogspot.com/
 A B C D E

R430 R431
+VREFOUT_EXTMIC 2 1 C545 1 2 + V REFOUT_INTMIC 2 1 C546 1 2
+3VS R437 + 3VS_DVDD 0_0402_5% 1K_0402_5%

1
BLM18BD601SN1D_0603 + A V DD_CODEC +5VS 1U_0603_10V4Z 1U_0603_10V4Z
2 1

0.1U_0402_16V4Z
R904 2 1 0_0805_5% R432 R433 R434 R435

1U_0402_6.3V6K
1 1 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5%
+3VS +3VS_HDA

2
C976

C553

0.1U_0402_16V4Z

1U_0402_6.3V6K
MIC_EXT_R M IC_ IN_R
R907 1 2 0_0603_5% 1 1
2 2

C1063

C1064
0.1U_0402_16V4Z

1 MIC_EXT_L M I C_IN_L 1
U22
1

0.1U_0402_16V4Z

10U_0805_10V4Z
1U_0402_6.3V6K
2 2
C551

C1065 2 1 10U_0805_10V4Z
1 27 1 1 1
DVDD_CORE AVDD

C1066

C1067

C1068
38
2 AVDD + A V DD_CODEC
9
DVDD
39
@ C554 @ R441 PVDD 2 2 2 R438
3 45 1 2 2.5K_0402_1%
DVDD_IO PVDD R439
2 1 2 1 1 2 39.2K_0402_1% HP_DET# <34>
33P_0402_50V8K 47_0402_5% 13 SENSEA R440 1 2 20K_0402_1% EXTMIC_DET# <34>
HDA _BITCLK_CODEC SENSE_A R442 2
<11> HDA _BITCLK_CODEC 6 14 1 100K_0402_5% + A V DD_CODEC
R444 HDA_BITCLK SENSE_B @ C555 1000P_0402_50V7K C556
1 2 1 2 1000P_0402_50V7K
1 2 HDA _ S DI N0_CODEC 8
<11> HDA _ SDIN0 HDA_SDI
33_0402_5% 28
HDA _ S DOUT_CODEC HP0_PORT_A_L
<11> HDA _ S DOUT_CODEC 5 29
HDA_SDO HP0_PORT_A_R + V REFOUT_INTMIC
23
HDA _ S Y NC _CODEC VREFOUT_A_or_F
<11> HDA _ S Y NC_CODEC 10
HDA_SYNC HP_OUTL
31 HP_OUTL <34>
HDA _RST#_CODEC HP1_PORT_B_L HP _OUTR
<11,37> HDA _RST#_CODEC 11 32 HP _ OUTR <34> HP Jack
HDA_RST# HP1_PORT_B_R
19 MIC_EXTL C557 1 2 2.2U_0603_6.3V4Z MIC_EXT_L
PORT_C_L MIC_EXT_L <34>
20 MIC_EXTR C558 1 2 2.2U_0603_6.3V4Z MIC_EXT_R Ext MIC
PORT_C_R MIC_EXT_R <34>
24
R679 1 VREFOUT_C
<21> DM IC_CLK 2 33_0402_5% 2 +VREFOUT_EXTMIC
R446 1 DMIC_CLK/GPIO1
<21> DMIC_DAT 2 0_0603_5% 4 40 SPKL+
SPKL+ <34>
DMIC0/GPIO2 SPKR_PORT_D_L+ SPKL-
41 SPKL- <34>
@ R910 1 SPKR_PORT_D_L-
<37> E A P D_CODEC 2 0_0402_5% 46 Internal SPKR
DMIC1/GPIO0/SPDIF_OUT_1 SPKR- + A V DD_CODEC
43 SPKR- <34>
SPKR_PORT_D_R- SPKR+
48 44 SPKR+ <34>
SPDIF_OUT_0 SPKR_PORT_D_R+

2
+3VS R908 1 2 10K_0402_5% 47 15
EAPD PORT_E_L R909
16
2 EC_MUTE# PORT_E_R 10K_0402_5% 2
<37> EC_MUTE#
17 M IC _INL C559 1 2 2.2U_0603_6.3V4Z M I C_IN_L
PORT_F_L M IC_IN_L <34>
2 35 18 M IC_ I NR C560 1 2 2.2U_0603_6.3V4Z M IC_ IN_R Int MIC
M IC_ IN_R <34>

1
CAP- PORT_F_R
C1069 12 M ONO_ INR C561 2 1 0.1U_0402_16V4Z M ON O_IN R447 2 1 47K_0402_5% C1070 1 2 0.1U_0402_16V4Z
4.7U_0603_6.3V6M PC_BEEP
36
1 CAP+
25

1
MONO_OUT @ R448 2 D
1 47K_0402_5% EC_BEEP <37>

0.1U_0402_16V4Z
7 2 SB_SPKR
DVSS SB_SPKR <11>

10K_0402_5%
2 Q38 G

2
33 22 2N7002_SOT23-3 S

3
AVSS CAP2

C562

R449
30
AVSS
26 21
AVSS VREFFILT 1
42 34

1
PVSS V-

10U_0805_10V4Z

10U_0805_10V4Z

1U_0603_10V6K
49 37
DAP VREG
2 1 2

2
4.7U_0603_6.3V6M

C563

C564
92HD81B1X5NLGXB1X8_QFN48_7X7~D

C1071

C1072

1
1 2 1

3 3

MDC 1.5 Conn. @ C983 1 2 1000P_0402_50V7K

@ C984 1 2 1000P_0402_50V7K
JP8 +3VS
@ C985 1 2 1000P_0402_50V7K
1 2 R450 1 2 0_0603_5% +3VS
HDA _ SDOUT_MDC GND1 RES0 @ C986 1
<11> HDA _ SDOUT_MDC 3 4 2 1000P_0402_50V7K
IAC_SDATA_OUT RES1

0.1U_0402_16V4Z
1000P_0402_50V7K
5 6 +3VS
HDA _ S Y NC_MDC GND2 3.3V R754 1
<11> HDA _ S Y NC_MDC 7 8 1 1 2 0_0603_5%
R452 1 IAC_SYNC GND3
<11> HDA _ SDIN1 2 33_0402_5% HDA _ S DIN1_MDC 9 10
IAC_SDATA_IN GND4

C565

C566
<11> HDA_RST#_MDC 11 12 HDA_BITCLK_MDC <11> @ R132 1 2 0_0603_5%
IAC_RESET# IAC_BITCLK
@ R453 2 @ C568 1 2 2 @ R135 1
1 2 2 0_0603_5%
GND
GND
GND
GND
GND
GND

10_0402_5% 10P_0402_25V8K @ R139 1 2 0_0603_5% GNDA <34>

H9 H10
HOLEA HOLEA ACES_88018-124G
13
14
15
16
17
18

Connector for MDC Rev1.5

1

C ONN@ GND GNDA

MDC Standoff

4 4

Security Classification Compal Secret Data

Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title
Codec_IDT9271B7
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev

http://laptop-motherboard-schematic.blogspot.com/ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom Calpella DIS LA4743P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: Monday, April 13, 2009 Sheet 33 of 49
A B C D E
 A B C D E

1
SPEAKER
D17
JSPK1 PSOT24C_SOT23-3
<33> SPKR- SPKR- R454 1 2 0_0603_5% SPK_R- 1
SPKR+ R455 0_0603_5% SPK_R+ 1
<33> SPKR+ 1 2 2

3
SPKL- R456 0_0603_5% SPK_L- 2
<33> SPKL- 1 2 3 <33> M IC_IN_L
SPKL+ R457 0_0603_5% SPK_L+ 3
1 2 4
<33> SPKL+ 4 INTMIC IN

1
330P_0402_50V7K

330P_0402_50V7K

330P_0402_50V7K
1 1

330P_0402_50V7K
1 1 1 5
GND1 R469
1 6
GND2

C570

C571

C572
0_0402_5%

C569
E&T_3806-F04N-02R C ONN@

2
2 2 2 C ONN@ JP10
2
<33> M IC_ IN_R 1
1
2
2

3
3
GND
4
D15 D16 GND
PSOT24C_SOT23-3 PSOT24C_SOT23-3 ACES_88231-02001

1
Audio connector
J A UDIO
1
MIC_EXT_R 1
<33> MIC_EXT_R 2
MIC_EXT_L 2
<33> MIC_EXT_L 3
3
4
2 HP_OUTL 4 2
Add JSPK2 for PA <33> HP_OUTL 5
5
<33> HP _OUTR HP _OUTR 6
6
7
C ONN@ EXTMIC_DET# 7
<33> EXTMIC_DET# 8
JSPK2 HP_DET# 8
<33> HP_DET# 9
SPK_L- 9
1 10
SPK_L+ 1 10
2
2
3
GND
4 11
GND GND1
12
ACES_88231-02001 GND2
ACES_87213-1000G
C ONN@

Consumer IR
+5VL

1
R476
100_0805_5%
3 I R1 3
1

2
Vout
2
VCC
CIR_ IN 3
<37> CIR_ IN GND
4
GND
IRM-V536/TR1_3P
C597
4.7U_0805_10V4Z

4 4

Security Classification Compal Secret Data

Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title
AM P & Audio Jack
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev

http://laptop-motherboard-schematic.blogspot.com/ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom Calpella DIS LA4743P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: Monday, April 13, 2009 Sheet 34 of 49
A B C D E
 5 4 3 2 1

Right side USB Power Switch Right side ESATA/USB combination Connector
+5VALW

+ USB_VCCC
U2 4 + US B_VCCC
1 8 W=100mils JESATA
GND OUT USB
2 7 1
IN OUT VBUS

150U_B_6.3VM_R40M
4.7U_0805_10V4Z

0.1U_0402_16V4Z

1000P_0402_50V7K
D 3 6 R479 1 2 0_0402_5% U SB20_N2_R 2 D
USB_EN# IN OUT <14> USB20_N2 R480 1 D-
1 4 5 1 1 1 2 0_0402_5% USB20_P2_R 3
EN# OC# <14> USB20_P2 D+

C598

C600

C601
4
C599 TPS2061IDGNR_MSOP8 + GND
5
2 2 2 SATA_TXP2 GND
<11> SATA_TXP2 6
2 SATA_TXN2 A+ ESATA
<11> SATA_TXN2 7
A-
8
C602 2 GND
<11> SATA_RXN2_C 1 0.01U_0402_16V7KSATA_RXN2 9
B-
<11> SATA_RXP2_C
C603 2 1 0.01U_0402_16V7KSATA_RXP2 10
B+
11
R481 GND
1 2 10K_0402_5% +5VALW
12
GND
13
GND
14
GND
15
GND
TYCO_1759576-1
C ONN@

D20 D21
+5VALW 4 2 USB20_P2 +5VALW 4 2 SATA_TXP2
VIN IO1 VIN IO1

Finger printer USB20_N2 3

IO2 GND
1

PRTR5V0U2X_SOT143-4
SATA_TXN2 3
IO2 GND
1

PRTR5V0U2X_SOT143-4

1 0 / 0 8 ESD request
+3VS

C C
2

R483 C ONN@
0_0603_5% JFPR
R484 1 2 0_0402_5% U SB20_N7_R 1
<14> USB20_N7 1
R485 1 2 0_0402_5% USB20_P7_R 2
<14> USB20_P7
1

+3VS_FP 2
3

1
C604
4
5
3
4
GND
BT Connector Need change to New version
6
0.1U_0402_16V4Z GND JBT
P-TWO_161011-04021 9 1 +3VAUX_BT
2 D22 GND 1
2
USB20_P7_R 2 USB20_P6_R R487
+5VALW 4 2 3 2 1 0_0402_5% USB20_P6 <14>
VIN IO1 3 U SB20_N6_R R488
4 2 1 0_0402_5% USB20_N6 <14>
U SB20_N7_R 4
3 1 5 BT_LED <38>
IO2 GND 5 @ R489 1 1K_0402_5%
6 2 CH_DATA <31>
PRTR5V0U2X_SOT143-4 6 @ R490 1 1K_0402_5%
7 2 CH_ CLK <31>
7
10 8
GND 8
ACES_87213-0800G
D2 3
C ONN@
+5VALW 4 2 USB20_P6_R
VIN IO1
U SB20_N6_R 3 1
IO2 GND
PRTR5V0U2X_SOT143-4

1 0 / 0 8 ESD request

B
USB cable connector for Left side R491
Q20 SI2301BDS_SOT23
+3VAUX_BT

B
0.1U_0402_16V4Z

S
J USB 1 2 3 1

D
+3VS

1U_0603_10V4Z
+5VALW 1 1
1 0_0603_5%
2
2

1
C605

G
3 1 1 1

2
USB_EN# 3 C606 C607 C608
<37> USB_EN# 4
4 2 R493
5
<14> USB20_N0 5 100K_0402_5%
6
<14> USB20_P0 6 2 2 2
7

2
7
<14> USB20_N1 8
8 0.01U_0402_16V7K 4.7U_0805_10V4Z
<14> USB20_P1 9
9
10
10
R494 1 2 10K_0402_5% C609 1 2 0.1U_0402_16V4Z
<14> BT_OFF
11
GND1
12
GND2
ACES_87213-1000G
C ONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB, BT, eSATA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev

http://laptop-motherboard-schematic.blogspot.com/ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C alpella DI S LA 4743P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: Monday, April 13, 2009 Sheet 35 of 49
5 4 3 2 1
 5 4 3 2 1

SPI ROM => 1M (EC code)

D D

+3VL &U25
U25
20mils 8 4
VCC VSS
1
C610
0.1U_0402_16V4Z
3

7
W
MX25L8005M2C-15G SOP 8P
LPC Debug Port
2 HOLD 45@
1 2 SPI_FSEL# 1
<37> FSEL# S
R495 10_0402_5% Change from +3VL to +3VS. 6/9
1 2 S PI_CLK_R 6
<37> SPI_CLK C
R496 10_0402_5% Removed +3VS. 6/13
<37> F W R# 1 2 S P I_FWR# 5 2 SPI_SO 1 2 F RD# F RD# <37>
R497 10_0402_5% D Q R498 0_0402_5%
W IESON G6179 8P SPI
B+
SP07000F500 S SOCKET WIESON G6179-100000 8P SPIFLASH
WIESO_G6179-100000_8P JP15
1
Ground
SA00000XT00Κ S IC FL 8M MX25L8005M2C-15G SOP 8P (MXIC) <14> CLK_DEBUG_PORT_0 2
LPC_PCI_CLK
R233 C391 3
Ground
SA00001AW00Κ S IC FL 16M MX25L1605AM2C-15G SOP 8P SPI (MXIC) S PI_CLK_R 1 2 1 2 <11,31,37> LPC_FRAME# 4
LPC_FRAME#
5
+V3S
SA000021A00Κ S IC FL 32M MX25L3205DM2I-12G SOP 8P (MXIC) 10_0402_5% <14,37> P CI_RST# 6
LPC_RESET#
6P_0402_50V8D 7
+V3S
SA000031Q00Κ S IC FL 32M AT25DF321-SU SOIC 8P (ATMEL) <11,31,37> L PC_AD0 8
LPC_AD0
<11,31,37> L PC_AD1 9
LPC_AD1
0919 EMI request <11,31,37> L PC_AD2 10
LPC_AD2
<11,31,37> L PC_AD3 11
C LPC_AD3 C
12
ON/ OFFBTNLED# VCC_3VA
13
PWR_LED#
14
CAPS_LED#
15
SPI ROM on PCH => 4M (ME code + System BIOS) V CC1 P WRGD
SPI_CLK_JP18
16
NUM_LED#
VCC1_PWRGD
Connect pin3 & 23 SPI_CS#_JP18
17
SPI_CLK
18
+3VS together and pin 24 SPI_SI_JP18 SPI_CS#
19
SPI_SO_JP18 SPI_SI
20
+3VS &U31 to GND in 6/29. SPI_HOLD#_0 21
SPI_SO
SPI_HOLD#
22
Reserved
1 23
Reserved
24
R658 1 +3VS Reserved
2 SPI_WP# C773
3.3K_0402_5% 0.1U_0402_16V4Z
2 ACES_87216-2404_24P
32M AT25DF321-SU SOIC 8P
R659 1 2S PI_HOLD# U31 45@ C ONN@
2

3.3K_0402_5% 8 4
@ R660 VCC VSS
1K_0402_5% SPI_WP# 3
W
S PI_HOLD# 7
1

R661 HOLD SPI_CLK SPI_CLK_JP18

1 2
SPI_SB_CS# 1 2 1 R501 0_0402_5%
<11> SPI_SB_CS# S DE B UG@
S PI_CLK_PCH 15_0402_5% 6 FSEL# 1 2 SPI_CS#_JP18
<11> S PI_CLK_PCH C R662 R502 0_0402_5%
SPI_SI 5 2 SPI_SO_L 1 2 SPI_SO_R SPI_SO_R <11> DE B UG@
<11> SPI_SI D Q +3VALW F W R# 1 2 SPI_SI_JP18
W IESON G6179 8P SPI 15_0402_5% R503 0_0402_5%
DE B UG@
R504 1 2 HOL D# 1 2 SPI_HOLD#_0
B 3.3K_0402_5% R505 0_0402_5% B
DE B UG@
F RD# 1 2 SPI_SO_JP18
R506 0_0402_5%
DE B UG@
ON /OFFBTN_LED# 1 2 ON/ OFFBTNLED#
<37,38> ON/OFFBTN_LED# R507 0_0402_5%
DE B UG@
V CC1 _ PWRGD 1 2 V CC1 P WRGD
<37> V CC1 _PWRGD R508 0_0402_5%
DE B UG@

11/07 Add 0 Ohm for debug port

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS ROM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev

http://laptop-motherboard-schematic.blogspot.com/ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C alpella DI S LA 4743P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: Monday, April 13, 2009 Sheet 36 of 49
5 4 3 2 1
 C612
+3VL_EC
BATT_OVP 2 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K
1 1 1 1 1 100P_0402_50V8J

C613 C614 C615 C616 C617 +3VL +3VL_EC + EC_AVCC

2 2 2 2 2 R511
0.1U_0402_16V4Z 1000P_0402_50V7K 1 2
0_0805_5%
For EMI

111
125
+3VL +3VALW

22
33
96

67
9
U27 KSO15 @ C618 1 2 100P_0402_50V8J
SMB_EC_DA1 R512 1 2 4.7K_0402_5%

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
SMB_EC_CK1 R513 1 2 4.7K_0402_5% KSO10 @ C619 1 2 100P_0402_50V8J
SMB_EC_DA2 R514 1 2 4.7K_0402_5%
SMB_EC_CK2 R515 1 2 4.7K_0402_5% KSO11 @ C620 1 2 100P_0402_50V8J
GATEA20 1 21 I NV_PWM
<14> GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INV_PWM <22>
KB_RST# 2 23 KSO14 @ C621 1 2 100P_0402_50V8J
<14> KB_RST# S I RQ KBRST#/GPIO01 BEEP#/PWM2/GPIO10 EC_BEEP
<11> S IRQ 3 26 EC_BEEP <33>
LPC_FRAME# SERIRQ# FANPWM1/GPIO12 A C OFF KSO13 @ C622 1
<11,31,36> LPC_FRAME# 4 27 A COFF <41> 2 100P_0402_50V8J
@ C623 @ R516 LPC_AD3 LFRAME# ACOFF/FANPWM2/GPIO13 0.01U_0402_16V7K
<11,31,36> L PC_AD3 5
LPC_AD2 LAD3 C624 E CA G ND KSO12 @ C625 1
1 2 1 2 <11,31,36> L PC_AD2 7 PWM Output 1 2 2 100P_0402_50V8J
33_0402_5% LPC_AD1 LAD2 BATT_TEMP
<11,31,36> L PC_AD1 8 63 BATT_TEMP <40>
15P_0402_50V8J LPC_AD0 LAD1 BATT_TEMP/AD0/GPIO38 BATT_OVP KSO3 @ C626 1 2 100P_0402_50V8J
LAD0 LPC & MISC
<11,31,36> L PC_AD0 10 64 BATT_OVP <40>
BATT_OVP/AD1/GPIO39 A DP_I
65 A DP_I <41>
CL K_PCI_EC ADP_I/AD2/GPIO3A A D P_ID KSO6 @ C627 1
<14> CLK_PCI_EC 12 AD Input 66 A DP _ID <40> 2 100P_0402_50V8J
PCI_RST# PCICLK AD3/GPIO3B TP_BTN#
<14,36> P CI_RST# 13 75 TP_BTN# <38>
ECRST# PCIRST#/GPIO05 AD4/GPIO42 KSO8 @ C628 1
+3VL 1 2 37 76 2 100P_0402_50V8J
R517 47K_0402_5% ECRST# SELIO2#/AD5/GPIO43
<14> E C_SCI# 20
SCI#/GPIO0E KSO7 @ C629 1
<11,33> HDA _RST#_CODEC 1 2 38 2 100P_0402_50V8J
R518 CLKRUN#/GPIO1D FAB_SET
68 FAN_SET <6>
DAC_BRIG/DA0/GPIO3C
1

2 1 J4 0_0402_5% 70 V CTRL KSO4 @ C631 1 2 100P_0402_50V8J

EN_DFAN1/DA1/GPIO3D V CTRL <41>
C630 0.1U_0402_16V4Z DA Output 71 IRE F
J OPEN KSI0 IREF/DA2/GPIO3E AC_SET IRE F <41> KSO2 @ C632 1
55 72 2 100P_0402_50V8J
2

KSI1 KSI0/GPIO30 DA3/GPIO3F AC_SET <41>

56
KSI2 KSI1/GPIO31 +5V_TP KSI0 @ C633 1
57 2 100P_0402_50V8J
KSI3 KSI2/GPIO32 EC_MUTE#
58 83 EC_MUTE# <33>
KSI4 KSI3/GPIO33 PSCLK1/GPIO4A USB_EN# R519 1
59 84 USB_EN# <35> 2 10K_0402_5% KSO1 @ C634 1 2 100P_0402_50V8J
KSI5 KSI4/GPIO34 PSDAT1/GPIO4B I2 C_INT R520 1
60 85 I2 C_INT <38> 2 10K_0402_5%
KSI6 KSI5/GPIO35 PSCLK2/GPIO4C KSO5 @ C635 1
61 P S2 Interface 86 2 100P_0402_50V8J
S Y SON SUSP# PCI_RST# +3VL +3VS KSI7 KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK
62 87
KSO0 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_DATA TP_CLK <38> KSI3 @ C636 1
39 88 2 100P_0402_50V8J
KSO1 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA <38>
40
KSO1/GPIO21
2

KSO2 41 KSI2 @ C637 1 2 100P_0402_50V8J

KSO2/GPIO22
1

R521 R522 R523 KSO3 42 97 R524 1 2 0_0402_5%

KSO3/GPIO23 SDICS#/GPXOA00 A C_LED# <40>
1

8.2K_0402_5% 8.2K_0402_5% 100K_0402_5% KSO4 43 98 KSO0 @ C638 1 2 100P_0402_50V8J

R526 R525 KSO5 KSO4/GPIO24 SDICLK/GPXOA01
KSO5/GPIO25 Int. K/B
44 99 11/09 don't stuff when use C0
10K_0402_5% 10K_0402_5% KSO6 SDIDO/GPXOA02 KSI5 @ C639 1
45 109 2 100P_0402_50V8J
KSO6/GPIO26 Matrix
1

KSO7 SDIDI/GPXID0
46 SPI Device Interface
2

KSO8 KSO7/GPIO27 KSI4 @ C640 1

47 2 100P_0402_50V8J
2

KSO9 KSO8/GPIO28 F RD#

48 119 F RD# <36>
KSO10 KSO9/GPIO29 SPIDI/RD# R527 33_0402_5% F W R# KSO9 @ C641 1
49 120 1 2 F W R# <36> 2 100P_0402_50V8J
L I D_SW# TP_BTN# KSO11 KSO10/GPIO2A SPIDO/WR# R528 33_0402_5% SPI_CLK
50
KSO11/GPIO2B S PI Flash ROM SPICLK/GPIO58 126 1 2 SPI_CLK <36>
01/03 Change to +3VS KSO12 51 128 R529 1 2 33_0402_5% FSEL# KSI6 @ C642 1 2 100P_0402_50V8J
KSO12/GPIO2C SPICS# FSEL# <36>
KSO13 52
KSO14 KSO13/GPIO2D R530
53 1 2 10K_0402_5% +5VL KSI7 @ C643 1 2 100P_0402_50V8J
+3VL +3VALW KSO15 KSO14/GPIO2E CIR_ IN
54 73 C IR_ IN <34>
KSO15/GPIO2F CIR_RX/GPIO40 V CC1 _ PWRGD KSI1 @ C644 1
81 74 V CC1 _ PWRGD <36> 2 100P_0402_50V8J
KSO16/GPIO48 CIR_RLC_TX/GPIO41 F S TCHG
82 89 F S TCHG <41>
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 STD_ADP
90 STD_ADP <41>
2

BATT_CHGI_LED#/GPIO52 CAPS_LED#
91 CAPS_LED# <38>
@ R531 R532 SMB_EC_CK1 CAPS_LED#/GPIO53 BAT_LED#
77 GPIO BATT_LOW_LED#/GPIO54 92
10K_0402_5% 10K_0402_5%<38,40> SMB_EC_CK1
SMB_EC_DA1 78
SCL1/GPIO44
93 ON /OFFBTN_LED#
BAT_LED# <38>
<38,40> SMB_EC_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 ON/OFFBTN_LED# <36,38>
11/15 Delete PCI_PME# SMB_EC_CK2 79 S M Bus 95 S Y SON
<12> SMB_EC_CK2 SCL2/GPIO46 SYSON/GPIO56 S Y S ON <31,38,39,48>
SMB_EC_DA2 80 121 V R _ON ENBKL 2 1
<12> SMB_EC_DA2 V R_ ON <46>
1

SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 A C_ IN R741 10K_0402_5%

127
@ R533 1 EC_PME# AC_IN/GPIO59
<14> PCI_PME# 2 2 1
0_0402_5% R534 10K_0402_5%
SLP_S3# 6 100 EC_RSMRST#
<13> SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# <13>
EC_PME# SLP_S5# 14 101 R535 1 2
<13> SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 E C_LID_OUT# <12>
EC_SMI# 15 102 E C _ON 0_0402_5%
<14> EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 E C_ ON <42> R536
L I D_SW# 16 103 WL_BLUE_LED#
<38> L ID_SW# LID_SW#/GPIO0A EC_SWI#/GPXO06 WL_BLUE_LED# <38>
ESB_CLK_R 17 104 P M_PWROK_R 1 2
ESB_DAT_R 18
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C GPO
ICH_PWROK/GPXO06
BKOFF#/GPXO08
105 BKOFF#
B KOFF# <21>
PM_PWROK <13> 13" INT_KBD
EC_PME# 19 GPIO 106 M _PWROK 100_0402_5%
<13> E C_ ACIN
E C_ ACIN
FAN_SPEED
25
EC_PME#/GPIO0D
EC_THERM#/GPIO11
WL_OFF#/GPXO09
GPXO10
107 TP_LED# M _PWROK <13>
TP_LED# <38> PV PWROK sequence issue CONN.( TYPE "D"
<6> FAN_SPEED 28 108
FAN_SPEED1/FANFB1/GPIO14 GPXO11
1
<31> W W A N_ POWER_OFF
2 UTX
W W A N_ POWER_OFF 29
30
FANFB2/GPIO15 KB)
+3VL EC_TX/GPIO16
R538 4.7K_0402_5% L A N _POWER_OFF_R 31 110 SLP_S4#
EC_RX/GPIO17 PM_SLP_S4#/GPXID1 SLP_S4# <13>
ON/ OFFBTN# 32 112 ENBKL
<38> ON/OFFBTN# ON_OFF/GPIO18 ENBKL/GPXID2 ENBKL <22>
EC_PME# PCI_RST# DI M_LED 34 114 E A P D_CODEC
<39> DIM_LED PWR_LED#/GPIO19 GPXID3 E A P D_CODEC <33>
36 GPI 115 T HERM_SCI# JKB1
NUMLED#/GPIO1A GPXID4 T HERM_SCI# <24>
1 1 116 SUSP# 1 KSO15
C647 GPXID5 PWRBTN_OUT# SUSP# <31,39,41,44,45> 1 KSO10
117 PWRBTN_OUT# <13> 2
C645 C646 15P_0402_50V8J GPXID6 NM I_DBG# +3VL 2 KSO11
118 3
0.1U_0402_16V4Z 0.1U_0402_16V4Z C RY 2 GPXID7 D24 3 KSO14
1 2 122 4
2 2 XCLK1 +3VL A D P_ID 4 KSO13
123 124 2 1 5
XCLK0 V18R 5 KSO12
Y6 1 6
AGND

6
1

CH751H-40PT_SOD323-2 7 KSO3
GND
GND
GND
GND
GND

1
@ C648 R540 7 KSO6
3 4 8
NC OSC R539 4.7U_0603_6.3V6K 10K_0402_5% 8 KSO8
9
20M_0402_5% KB926QFB0_LQFP128_14X14 2 9 KSO7
2 1 10
11
24
35
94
113

69

NC OSC 10 KSO4
03/13 PV2 Add EMI solution 11
2

D2 5 11 KSO2
For C 12

2
32.768KHZ_12.5PF_Q13MC14610002 NM I_DBG# 12
1 2 P C I_SERR# P CI_SERR# <14> 13 KSI0
C RY 1 Revision 13 KSO1
1 2 14
+3VL_EC +3VL CH751H-40PT_SOD323-2 14 KSO5
15
C649 15 KSI3
16
E CA G ND

15P_0402_50V8J 16 KSI2
17
1

1
R541 17 KSO0
18
EC DEBUG port + E C_AVCC L26 150K_0402_5% 18
19
19 KSI5
0_0603_5% 20 KSI4
UTX @ R542 2 20 KSO9
1 21
0_0805_5% L27 D26 21 KSI6
22
2

2
R543 A C_ IN A CIN 22 KSI7
1 2 1 2 2 1 A CIN <41> 23
L A N _POWER_OFF_R C650 0.1U_0402_16V4Z 0_0603_5% 23 KSI1
<32> L A N_POWER_OFF 1 2 24
CH751H-40PT_SOD323-2 24
25
0_0402_5% G1
1 2 26
+3VL +3VL C651 100P_0402_50V8J G2
ACES_85202-24051
C ONN@
1

1
R545
R544 4.7K_0402_5% C652 @
4.7K_0402_5%
2
10P_0402_50V8J
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title
2

R546 1 2 0_0402_5% ESB_CLK_R

<38> ESB_CLK
<38> ESB_DAT
R547 1 2 0_0402_5% ESB_DAT_R
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC KB926/KB Conn.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C alpella DI S LA 4743P 0.1

http://laptop-motherboard-schematic.blogspot.com/ MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: Monday, April 13, 2009 Sheet 37 of 49
 A B C D E

1 1

System LED Conn Power Button

J L ED Caps-Lock Conn for debug only
+5VALW
+5VS
1
2
1 GND
2
9

J CAP
+5VS T/P Board (Inculde T/P_ON/OFF)
JTPSW
+3VS 3
3 SW2
<37> BAT_LED# 4 1 1 +5VS
4 1 ON/ OFFBTN# 1 TP_LED#
White <11> SATA_LED# 5 2 CAPS_LED# <37> 1 3 2 TP_LED# <37>
5 2 2 TP_BTN#
AMBER <11> HDDHALT_LED# ON /OFFBTN_LED#
6
6 3
3
3
3 TP_BTN# <37>
7 4 2 4 4
7 4 4
8 10 5 5
8 GND GND GND
6 6

6
5
ACES_87213-0800G GND GND
C ONN@ P-TWO_161011-04021 SMT1-05_4P P-TWO_161011-04021
CONN@ C ONN@

TP_DATA
Capacitor Sensor Conn +5VS +3VL @ R570 @ C662
T/P Board Conn
TP_CLK

2
ESB_DAT 2 1 2 1
2 D32 2
33_0402_5% 15P_0402_50V8J PSOT24C_SOT23-3

1
Cy p r ess@ @ R564 @ C660
R597 1 2 0_0402_5% R557 ESB_CLK 2 1 2 1 +5VALW +5V_TP
<37,40> SMB_EC_CK1
R598 1 2 0_0402_5% 0_0805_5% R558 1 2 0_0603_5%
<37,40> SMB_EC_DA1

1
Cy p r ess@ 2 33_0402_5% 15P_0402_50V8J +5V_TP

S
3 1

D
J CSB 1
1 Q23 @ C654
1

1
2 SI2301BDS-T1-E3_SOT23-3 0.1U_0402_16V4Z

G
2
ON /OFFBTN_LED# 2 @ R560
<36,37> ON/OFFBTN_LED# 3
E NE@ R561 1 3 2
<37> ESB_CLK 2 FBMA-11-100505-801T 0402 4 10K_0402_5% JTP
E NE@ R562 1 4
<37> ESB_DAT 2 FBMA-11-100505-801T 0402 5 1
5 1 TP_CLK
<37> I2 C_INT 6 2 TP_CLK <37>

2
R596 6 2
+5VALW 1 2 1.8K_0402_5% 7 3 TP_DATA TP_DATA <37>
7 3
<37> L ID_SW# 8 4
R563 8 4
<37> ON/OFFBTN# 1 2 1K_0402_5% 9 5
9 GND
10 6
10 GND

1
11 D
GND 1 1
12 S Y SON 2 @ Q24 P-TWO_161011-04021
GND <31,37,39,48> S Y SON
1 1 G 2N7002_SOT23-3 C ONN@ @ C658 @ C659
P-TWO_161021-10021 S 100P_0402_50V8J 100P_0402_50V8J

3
2 2
@

C772 C ONN@
15P_0402_50V8J C661
2 2 4.7U_0603_6.3V6K

3 Mini card LED +3VS

3

Keyboard backlight Conn

1
R565
10K_0402_5%

2
R566 JKBL WL_BLUE_LED# <37>
+5VS_LED 1 2 1 Q25
1 2N7002_SOT23-3
2
2

1
0_0805_5% D
3
3
4 <35> BT_LED 2
4
5 G
GND

1
6 S

3
GND R567
P-TWO_161011-04021 100K_0402_5%
C ONN@

2
D33

<31> W L_LED# 2
1 W L_LED
<31> W W _LED# 3

PSOT24C_SOT23-3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KBD, ON/OFF, SW, CIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev

http://laptop-motherboard-schematic.blogspot.com/ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C alpella DI S LA 4743P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: Monday, April 13, 2009 Sheet 38 of 49
A B C D E
 5 4 3 2 1

+5VALW to +5VS Transfer +3VALW to +3VS Transfer +1.5V to +1.5VS Transfer

+5VALW SI7326DN-T1-E3_PAK1212-8 +5VS +3VALW +3VS
U2 8 B+ SI7326DN-T1-E3_PAK1212-8 +1.5V +1.5VS
1 U2 9 SI7326DN-T1-E3_PAK1212-8
B+ 2 1 U30
5 3 2 1

1
0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0805_10V4Z
5 3 2

10U_0805_10V4Z

0.1U_0402_16V4Z

10U_0805_10V4Z
R581 1 5 3
1

10U_0805_10V4Z
1 1 C669 1 1 1 1

C671

C672

C673

C674

C679

C680
10U_0805_10V4Z
D R583 330K_0402_5% D
1

4
C675 10U_0805_10V4Z 1

4
2

C681
330K_0402_5%
2 2 2 2 2 2
2

2 RUNO N_3VS

1
2 R U NON

3
R U NON

1
R584
6

470_0402_5% R650
R585 SUSP 5 1K_0402_5%

2
470_0402_5% 1
SUSP 2 01/03 Sparate+5VS Q10B

2
2N7002DW-7-F_SOT363-6 C676 1
Q10A 1 and +3VS power 0.01U_0402_16V7K C770
1

2N7002DW-7-F_SOT363-6 C677 2 0.1U_0402_25V4K

4700P_0402_25V7K timing
2
2

+3VALW to +3VS_NV Transfer +1.8VS to +1.8VS_NV Transfer +1.5V to +1.5VS_NV Transfer

B+ +3VALW SI7326DN-T1-E3_PAK1212-8 +3VS_NV +1.8VS_NV +1.5V +VDD_MEM
U48 S G@
400 mA B+ +1.8VS SI7326DN-T1-E3_PAK1212-8
100 mA SI7326DN-T1-E3_PAK1212-8
4.64A
1 U49 S G@ U50 S G@
2 1 1
1

0.1U_0402_16V4Z

10U_0805_10V4Z

0.1U_0402_16V4Z
5 3 2 2

1
470_0402_5%

330K_0402_5%

470_0402_5%

470_0402_5%
10U_0805_10V4Z

0.1U_0402_16V4Z
C SG@ 5 3 5 3 C
1 1

R913

C1074
R912 SG@ 1 1 S G@ 1 1

R918

C1076

R594
330K_0402_5% C1073 S G@ S G@ SG@ SG@ SG@
4

C1075

C1081

C1079

2N7002DW-7-F_SOT363-6 R917
10U_0805_10V4Z S G@ S G@
2

4
2 S G@ 2
2

2
2 2 2 2
2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6
DGP U _PWR_EN#
NV VDD_PG#
3

SG@

6
R915 SG@ Q14A SG@ NV VDD_PG#
470_0402_5% R916 SG@ Q17A S G@ Q18A
5 DGP U _PWR_EN 2 1K_0402_5%
<14,23,45,47> DGP U_PWR_EN
5 NV VDD_PG 2 NV VDD_PG 2
<47> NV VDD_PG
2

SG@ Q14B 1
4

2
2N7002DW-7-F_SOT363-6 SG@ S G@ Q17B 1 SG@

1
3
C1077 2N7002DW-7-F_SOT363-6 C1078
0.01U_0402_16V7K 0.1U_0402_25V4K
2
2 5

SG@ Q18B

4
2N7002DW-7-F_SOT363-6

Discharge circuit DIM LED +5VS

Q26
+5VS_LED

+5VS +3VS +1.5VS + VCCP +1.5V +0.75VS SI2301BDS-T1-E3_SOT23-3

S
3 1

D
1

1
R588 R589 R590 R591 R592 R593 1
B R582 C670 B

G
2
470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 10K_0402_5% 0.1U_0402_16V4Z
2

2
2
2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

2
D IM_LED#
6

1
Q9A Q9B Q8A Q8B Q7A Q7B D
DI M_LED 2 Q27
<37> DIM_LED
SUSP 2 SUSP 5 SUSP 2 SUSP 5 S Y SON# 2 SUSP 5 G 2N7002_SOT23-3
S

3
1

+3VL +3VL
1

R586 R587

100K_0402_5% 100K_0402_5%
2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6
2

<45> S Y SON# S USP <45>

6

Q6A Q6B
A A

<31,37,38,48> S Y SON 2 5 SUSP# <31,37,41,44,45>

1

H1 H2 H3 H4 H5 H6 H7 H8 H11 H12 H13 H14 H15 H16 H17 H18 FM1 FM2
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA 1 1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

FM3 FM4 DC/DC Interface

1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1 1 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev

http://laptop-motherboard-schematic.blogspot.com/ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C alpella DI S LA 4743P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: Monday, April 13, 2009 Sheet 39 of 49
5 4 3 2 1
 A B C D

+3VALW

PQ3

3
T P0610K-T1-E3_SOT23-3
+3VL
1 P R9 2 connect to KBC pin97
100K_0402_5% BATT
1
2 AC_LED# <37> 1

499K_0402_1% 340K_0402_1%
P R1 1
+5VALW
ADP_ID <37>

0.01U_0402_25V7K
2 1

PC12

2
1

1
P C1
PR8 PD4 @1000P_0402_50V7K

P R4 1
2K_0402_5% P R2
10K_0402_5%
VIN

2
1

2
RLZ3.6B_LL34
AD P _SIGNAL 1 2

8
P R3 P R5
10K_0402_5% 3 10K_0402_5%

P
J DC +
PL1 1 2 1 BATT_OVP <37>
HCB2012KF-121T50_0805 0
6 2
GND -

G
105K_0402_1%
5 AD P IN 1 2
GND

P R6 1
0.01U_0402_25V7K
4 PL2

4
4

1
3 HCB2012KF-121T50_0805 P U1A
3

100P_0402_50V8J

P C6
2 1 2 LM358ADT_SO8
2

1000P_0402_50V7K
1

2
1
2

100P_0402_50V8J
P D1

2
1

1
P C5
ACES_87302-0441

P C4
P C3
2

2
P C2

1000P_0402_50V7K
@PJSOT 24C_SOT23-3
1

2 2

VMB
JBATT PL3 BATT
HCB2012KF-121T50_0805
1 1 2
BATT+ PL4
2 EC_SMD HCB2012KF-121T50_0805
PH1 under CPU botten side :
SMD EC_SMC
SMC
3
4
1 2 CPU thermal protection at 90 +-3 degree C
B/I
1

1
7 5
GND TS
P D2
8 6 PC8 P C9
2

2
GND GND 1000P_0402_50V7K 0.01U_0402_50V4Z P R7
3
SUYIN_200275MR006G113ZL 1 +5VS 604K_0402_1%
2 1 2
3
P D3 CPU 3

3
PJSOT 24C_SOT23-3
1
1

2
1

1
P R14 P H1
PJSOT 24C_SOT23-3
100_0402_5% 10K_T H11-3H103FT_0603_1%
2

PR13 EN0 <42>

2

2
100_0402_5% SMB_EC_DA1 SMB_EC_DA1 <37,38> PR10

8
200K_0402_1%

1
D
1 2 5

P
SMB_EC_CK1 + PQ1
SMB_EC_CK1 <37,38> 7 2
0 G SSM3K7002FU_SC70-3
+5VALW 1 2 6
-

G
BAT _ID <41> PR11 PU1B S

3
1
150K_0402_1%

4
1

1
LM358ADT_SO8

1
P C10 PR12
PR16
+3VL 2.49K_0402_1% P R15
6.49K_0402_1% 0.22U_0603_10V7K
2

1 2 150K_0402_1% PC11
2

2
1000P_0402_50V7K

2
1

PR17
1K_0402_5%
2

BATT_TEMP <37>

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Connector/CPU_OTP
Size D o cument Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

A
http://laptop-motherboard-schematic.blogspot.com/ B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D ate:
Calpella DIS LA4743P
Monday, April 13, 2009
D
Sheet 40 of 49
0.1
 A B C D

P4 B+

PQ102
BATT
V IN P2
AO 4 407_SO8
PQ101 PQ103
PR102
1 8
AO 4 433_SO8 AO 4 409_SO8 1 4 PL101 2 7
HCB2 0 1 2KF-121T50_0805 3 6
8 1 1 8 2 3 1 2 CHG _ B+ 5
7 2 2 7 PR103
6 3 3 6 4 7 K_0402_5%

4
1
0 .0 12_2512_1% 1

4 .7 U_0805_25V6-K

4 .7 U_0805_25V6-K

4 .7 U_0805_25V6-K
5 5 1 2 1 2
PR101 V IN

1
4 7 P_0402_50V8J

4 7 K_0402_5% PR104 ACDET PC102

1
0 .1 U_ 0603_25V7K

PC1 03

PC1 04

PC1 05
1 2 0_0402_5% 1 U_ 0 6 03_6.3V6M
<37> AC_ SET 1 2 ACSET

2
1

3
PR1 05
PC1 01

1
0 .1 U_ 0603_16V7K
1 0 K_0402_5%

PC1 08
1

1
2

2
A CN
A CP
1

2 0 0 K_0402_5%
2 PC1 07 PR1 40 ACO F F#

2
1

1 0 0 K_0402_5%

PC106

PR106
@0 .0 1 U_0402_16V7K

1
2

2
PR107 C H G EN# CHG _ B+

2
47K_0402_1% PQ104 PR1 08
1 2 2 DT A1 4 4 EUA_SC70-3 10_1206_5%
1

1
1 2 2 ACO F F <37>

LPREF

ACSET

ACDET

ACP
LPMD

ACN

CHGEN
PQ105 29
TP

5
DT C1 1 5 EUA_SC70-3 PR110 PC110
3

PQ107 0_0402_5% 1 U_ 0 8 05_25V6K PQ108

3
1

SSM3 K7 0 0 2FU_SC70-3 D PR1 09 1 2 8 AO N7 4 0 8 L _ DFN8-5 PQ106

<3 1 ,3 7,39,44,45> SUSP# 28 1 2
1 5 0 K_0402_5% IADSLP PVCC PR1 42 DT C1 1 5 EUA_SC70-3
2
G 0_0402_5% PC111

2
S 9 27 BST _ CHG
1 2 1 2 4
3

AGND BTST PR1 39

PC1 12 BQ 2 4 7 40VREF PU1 0 1 0_0402_5% 0 .1 U_ 0402_10V7K
1 2 10
VREF
BQ 2 4 7 4 0 RHDR_ QFN28_5X5
HIDRV
26 D H_ CHG1 2 D H _ CHG 1
PL102 PR112
BATT

3
2
1
PR1 11 PQ109 1 U_ 0 6 03_6.3V6M +3VL 1 0 U_ L F 9 1 9 AS-100M-P3_4.5A_20% 0 .0 15_1206_1%
1

3K_0402_1% D L X_ CHG
11 25 1 2 1 2
P A C IN SSM3 K7 0 0 2 FU_SC70-3 VDAC PH
1 2 2

1
G PD1 02

5
6
7
8
S PR113 V A DJ 12 24 R E GN 2 1 PR1 41
3

PD1 01 1 4 3 K_0402_1% VADJ REGN @4 .7_1206_5%

4 .7 U_ 0805_25V6-K

4 .7 U_ 0805_25V6-K

4 .7 U_ 0805_25V6-K

4 .7 U_ 0805_25V6-K

4 .7 U_ 0805_25V6-K
ACO F F# 1 2 PR114 1 SS3 5 5_SOD323-2
@0_0402_5% 13 23 D L _ CHG

2 2
EXTPWR LODRV

1
1 SS3 5 5_SOD323-2
<37> VCT RL 1 2

PC113

PC114

PC115

PC116

PC122
4
2 1 14 22 PC135 2

2
ISYNSET PGND
1

@4 7 0 P_0603_50V8J

1
1

DPMDET
PC117 PR115 PQ110 1 2

IADAPT

SRSET

CELLS

1
1 U_ 0 6 03_10V6K 100K_0402_1% PC119

SRN
2

3
2
1
SRP
BAT
PR1 16 AO 4 468_SO8
2

39K_0402_5% 1 U_ 0 6 03_10V6K PC118

2
0 .1 U_ 0 402_10V7K

15

16

17

18

19

20

21
PR117
100K_0402_5% BQ 2 4 7 4 0VREF

IADAPT
PR118 1 2

1
10K_0402_5%
1 2 4 7 K_0402_5%
<37> ADP_I

1
D
0 .2 2 U_0603_10V7K

PR119

1 0 0 P_0402_50V8J
1

1
PQ111 2 BAT _ ID <40>

2
PC1 20

PC1 21
SSM3 K7 0 0 2 FU_SC70-3 G
S

BATT
2

3
Charge Detector

0 .1 U_ 0603_25V7K
V IN
PR1 20
2 1 IREF <37>

1
PC124
133K_0402_1%
2

1
PC123 1
PD104 0 .1 U_ 0 402_10V7K PR122

2
1 SS3 55_SOD323-2 PR121 6 8 1 K_0402_1%
200K_0402_1% 1 2
2

PR123
1

2
1M_0402_5%
1 2
1VIN_1

3
PR1 24 3

+3VL V IN 1 K_ 0402_5%
V IN 1 2
PR1 25 +3VL ACIN <37>

1
47_1206_5%
PR1 26
1
1 0 K_0402_5%

100K_0402_1% PR127
2

V IN PR130 1 0 K_0402_1%
1

8
+3VL
1 0 K_0402_1%

PR1 28

2 .1 5K_0402_1% PU1 0 2B

2
1 2 5

P
+
1

PR129

7 P A C IN
2

O
1

1
1 0 0 K_0402_5%

PR131 6
-

G
1 3 3 K_0402_1% PC125 C H G EN#
2

1
PR1 32

0 .1 U_ 0603_25V7K PC1 26 L M3 93DG_SO8

2

4
PR133

1
0 .0 4 7 U_0402_16V7K 1 0 K_0603_0.1%
2

PR134
2

2
1

D PD103
3 10K_0402_5%
P

2
+ PQ112 RL Z4 .3 B_LL34
1 2
O
1

2 G SSM3 K7 0 0 2 FU_SC70-3

2
-
G

PU1 0 2A S
PR135
3

L M3 93DG_SO8 F ST CHG#
4

1 0 K_ 0603_0.1% PR1 36
6 0 .4K_0402_1%
2

D V IN_ 1
1 2
1 .2 4 VREF <37> F ST CHG 2 PQ113
G SSM3 K7 0 0 2 FU_SC70-3
S
3

STD_ADP <37>
PU1 0 4

4 3 1 .2 4 VREF
ACDET REF CATHODE
1 2

1
PC127 2
PR137 NC
2 2 P_ 0 402_50V8J
1

100K_0402_1%

20K_0402_1% 5 1

2
ANODE NC
PR138

L MV4 3 1ACM5X_SOT23-5
4 4
2

Security Classification
2007/05/29
Compal Secret Data
2008/05/29 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
Charger
http://laptop-motherboard-schematic.blogspot.com/
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Do cu me n t Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Calpella DIS LA4743P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: Mo n d a y, Ap ril 13, 2009 Sheet 41 of 49
A B C D
 A B C D E

2VREF_51125

1
1 1
PC302
0.22U_0603_10V7K

2
PR301 PR302
13.7K_0402_1% 30.9K_0402_1%
1 2 1 2

PR303 PR304
B+ B++
20K_0402_1% 20K_0402_1%
B++
PL301 1 2 1 2
HCB2012KF-121T50_0805

1 2 +3VLP

E NTRIP2

E NTRIP1
PR305 PR306

10U_1206_25V6M
0.1U_0402_25V6

0.1U_0402_25V6
1000P_0402_50V7K

4.7U_0805_25V6-K

1000P_0402_50V7K
105K_0402_1% 115K_0402_1%
1

1
1 2 1 2

1
PC313

PC301

PC303

PC316

PC304

PC305
PQ301
2

2
AON7408L_DFN8-5

2
6

5
1
PC306 PQ302

ENTRIP2

VFB2

TONSEL

VREF

VFB1

ENTRIP1
4 10U_0805_6.3V6M 25 AON7408L_DFN8-5
P PAD

2
UG1_3V
7 24 4
2 VO2 VO1 2

1
2
3
8 23 PR308 PC308
PR307 VREG3 PGOOD 0_0402_5% 0.1U_0402_10V7K
PR309 1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2 PR310

3
2
1
0_0402_5% 0_0402_5% VBST2 VBST1 0_0402_5%
PL302 1 2 PC307 U G_3V 10 21 U G_5V 1 2 PL303
4.7UH_SIQB74B-4R7PF_4A_20% 0.1U_0402_10V7K DRVH2 DRVH1 4.7UH_PCMC063T-4R7MN_5.5A_20%
2 1 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP LL2 LL1
5

5
LG_3V 12 19 LG_5V
DRVL2 DRVL1

1
4.7_1206_5%
PQ303

SKIPSEL
1
4.7_1206_5%

PR316
VREG5
1
PR315

VCLK
PC309 PR312

GND
1

EN0

VIN
+ 1M_0402_1%

680P_0603_50V8J
4 1 2 4 + PC310
B++

2
150U_B_6.3VM_R45M

680P_0603_50V8J

PU301 150U_B_6.3VM_R45M
2

13

14

15

16

17

18
2 TPS51125RGER_QFN24_4X4 PQ304

1
2

PC315
1

1
<40> EN0
PC314

AON7406L_DFN8-5 STL8NH3LL
1
2
3

3
2
1
VL PR317

2
PR311
2

191K_0402_1% 1 2 R_EC_RSMRST# <13>

1
PC311 0_0402_5%
10U_0805_10V6K

2
1
B++
PC312

2
3 0.1U_0603_25V7K 3
E NTRIP1

2VREF_51125
E NTRIP2
1

D D
PQ305 2 2 PQ306
SSM3K7002FU_SC70-3 G G SSM3K7002FU_SC70-3
S S +3VLP +3VL
3

PJP301
PJP302
2 1
+5VALWP 1 2 +5VALW (4.5A,180mils ,Via NO.= 9)
PR313 P AD-OPEN 2x2m
100K_0402_5%
P A D-OPEN 4x4m
1 2
VL PJP303

+3VALWP
1 2 +3VALW (3A,120mils ,Via NO.= 6) VL +5VL
PQ307
1

D SSM3K7002FU_SC70-3 PJP304
P A D-OPEN 4x4m
2 2 1
G EC_ON <37>
S P AD-OPEN 2x2m
3

PR314
100K_0402_5%
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3.3VALWP/5VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev

http://laptop-motherboard-schematic.blogspot.com/ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom C alpella DI S LA 4743P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: Monday, April 13, 2009 Sheet 42 of 49
A B C D E
 5 4 3 2 1

CPU_B+

1000P_0402_50V7K

10U_1206_25V6

10U_1206_25V6

0.1U_0402_25V6

2
PR402

1
D 0_0603_5% D
G FXVR_IMON <9>

PC401

PC406

0.22U_0603_25V7K

0.22U_0402_6.3V6K
PR401

PC402

PC403

22.6K_0402_1%
+ 5VALW 2 1

1 1

1
1_0603_5%

1
PC408

PR403

PC409
PC407

2
1U_0603_6.3V6M

2
PR404
10_0402_5% VSS_AXG_SENSE
1 2 ISUM+

5
6
7
8
I SUM- PQ401
1 2 BST_GFX 1 2 1 2 AO4474_SO8
<9> VSS_AXG_SENSE PC411

1
1000P_0402_50V7K PR405 PC410
PC413 2.2_0603_5% 0.22U_0603_16V7K 4
<9> VCC_AXG_SENSE 330P_0402_50V7K
1 2

29

10

11

12

13

14
2

9
PR406
+VGA_CORE 10_0402_5% PC412

AGND

RTN

ISUM

VDD

VIN

IMON

BOOT
ISUM+
1 2 330P_0402_50V7K PR407

3
2
1
0_0603_5%

7 15 D H_GFX 1 2 DH_GFX1 +VGA_CORE

VSEN UGATE PL402
6 PU401 16 LX_GFX 4 1
FB ISL62881HRZ-T _QFN28_4X4 PHASE

5
5 17 3 2
COMP VSSP

1
C 4 18 DL_GFX C
VW LGATE PR408 0.56UH_MMD-10CZ-R56M-M1_19A_20%
PR410

1
PR413 PR414 PC418 PR409 2 1 3 19 1 2 + 5VALW 4.7_1206_5%
8.66K_0402_1% 825K_0402_1% 1000P_0402_50V7K 47K_0402_1% RBIAS VCCP PR411 PR412
0_0603_5% 4

1
2 20 3.65K_0805_1% 0_0402_5%

2
PGOOD VID0
2 1 1 2 1 2 2 1
PC419 PH401
1 21

2
CLK_EN# VID1

2
DPRSLPVR
PC417 2.2U_0603_6.3V6K 1 2 1 2

3
2
1
100P_0402_50V8J +VGA_CORE PR415

VR_ON
PQ402 PC420 10KB_0603_5%_ERT J1VR103J
2.61K_0402_1%

VID6

VID5

VID4

VID3

VID2

1
PC422 T PCA8028_PSO8 680P_0603_50V7K
22P_0402_50V8J
2 1 2 1 1 2 2 1

28

27

26

25

24

23

22
1 PR418
@1.91K_0402_1%

@10K_0402_1%
2
11K_0402_1%
1

1
PC421 PR416 PR417
PR419

PR420
150P_0402_50V8J 17.8K_0402_1% 8.06K_0402_1% PC423
0.1U_0402_16V7K
1 2
2

G F XVR_PWRGD
1 2
PC424
GFXVR_CLKEN#

2
0_0402_5% 2 1 PR421 0.033U_0402_16V7K
0_0402_5% PR422 G F XVR_VID_0 <9> PR423 PR424
2 1
0_0402_5% PR425 G F XVR_VID_1 <9>
2 1 3.01K_0402_1% 100_0402_1%
B 0_0402_5% PR426 G F XVR_VID_2 <9> PR429 B
2 1
0_0402_5% PR427 G F XVR_VID_3 <9> 82.5_0402_1%
2 1

1
0_0402_5% PR428 G F XVR_VID_4 <9>
2 1 1 2 1 2
0_0402_5% PR430 G F XVR_VID_5 <9>
2 1

2
0_0402_5% PR431 G F XVR_VID_6 <9> PC425
2 1
0_0402_5% PR432 G FXVR_EN <9> 0.01U_0402_16V7K PC426
2 1
G FXVR_DPRSLPVR <9>
180P_0402_50V8J

1
ISUM+

I SUM-

A A

Security Classification
2008/10/31
Compal Secret Data
2009/10/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VCCGFX
Size D o cument Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C u s tom Calpella DIS LA4743P
http://laptop-motherboard-schematic.blogspot.com/
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: Monday, April 13, 2009 Sheet 43 of 49
5 4 3 2 1
 5 4 3 2 1

<9> VTT_SELECT
D D

1
PR520
PR517 174K_0402_1%
0_0402_5%
VT T _SENSE 2 1

2
<9> VTT_SENSE
PR501 PR502
PR518 26.7K_0402_1% 10.5K_0402_1% PR503 PR504
10_0402_5% 75K_0402_1% 29.4K_0402_1%
+1.1VTT 2 1 1 2 1 2 1 2 1 2 +1.05VSP
B+++

2
PR505 B+++ B+
1000P_0402_50V7K

0.1U_0402_25V6

0_0402_5% PL502
4.7U_0805_25V6-K

10U_1206_25V6

HCB2012KF-121T50_0805
2 1

1
1

1
PC501

PC511

PC502

PC520
2

0.1U_0402_25V6
<6> VT T PWRGOOD

10U_1206_25V6

1000P_0402_50V7K
C C
8
7
6
5

PC521
PU501 PQ501

PC503

PC505
PQ502 AON7408L_DFN8-5

VO2

VFB2

TONSEL

GND

VFB1

VO1
AO4474_SO8 PC524 25

2
@ 0.022U_0402_25V7K P PAD

4 7 24 4
PGOOD2 PGOOD1
PC507
PC506 PR506 8 23 PR507
EN2 EN1 0.1U_0402_10V7K
0.1U_0402_10V7K 0_0402_5% 0_0402_5%
+1.1VTT 2 1 2 1 BST_1.1VTT 9 22 BST _1.05V 2 1 1 2
1
2
3

3
2
1
VBST2 VBST1
+1.05VSP
PL503 UG1_1.1VTT 2 1 UG_1.1VTT 10 21 UG_1.05V 2 1 UG1_1.05V PL501
0.47UH_FDV0630-R47M-P3_18A_20% 0_0402_5% PR508 DR VH2 DR VH1 PR509 2.2UH_PCMC063T -2R2MN_8A_20%
2 1 LX_1.1VTT 11 20 LX_1.05V 0_0402_5% 1 2
LL2 LL1
LG_1.1VTT 12 19 LG_1.05V
DR VL2 DR VL1
5

PR515
1

5
1 4.7_1206_5% PQ504

PGND2

PGND1
V5FILT

220U_B2_2.5VM_R25M
TRIP2

TRIP1
T PCA8028_PSO8 PQ503 1

V5IN
PC523

330U_X_2VM_R6M

+ FDMC8296_POWER33-8-5 PR516

PC508
4.7_1206_5% +
4 T PS51124RGER_QFN24_4x4
1 2

13

14

15

16

17

18
2 4

1 2
2

2
PC518
2

1
2
3

B 680P_0603_50V7K PR510 PR511 PC519 B

3
2
1

2
14.7K_0402_1% 12.1K_0402_1% 680P_0603_50V7K
1 2
+ VCCP

1
PR513
0_0402_5% PR512
1 1 2 1 0_0402_5%
<31,37,39,41,45> SUSP# 1 2 SUSP#
PC517

330U_X_2VM_R6M

PC522

330U_X_2VM_R6M

+ + 1 2 + 5VALW
PR514
2 2 3.3_0402_5%
1

1
PC514 PC515 PC512
1U_0603_10V6K 4.7U_0805_10V6K @0.1U_0402_16V7K
PC513
2

2
@0.1U_0402_16V7K

PJP501

+1.05VSP 1 2 +1.05VS (6A,240mils ,Via NO.= 12)

P AD -OPEN 4x4m

A A
PJP502

+1.1VTT 1 2 + VCCP (14A,240mils ,Via NO.= 28)

P AD -OPEN 4x4m

1
PJP503
2
Security Classification
2007/05/29
Compal Secret Data
2008/05/29 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
P AD -OPEN 4x4m
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.1VTTP/1.1VSP
Size D o cument Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Calpella DIS LA4743P 0.1

http://laptop-motherboard-schematic.blogspot.com/
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: Monday, April 13, 2009 Sheet 44 of 49
5 4 3 2 1
 5 4 3 2 1

D D

+1.5V

P U 601
1 6
VIN VCNTL +5VALW

@ 1 0U_0805_10V4Z
2 5
GND NC

P C 602

1
P C 601 3 7

1
VREF NC
1 0U_0805_10V4Z

2
P R 601 P C 603
4 8
1K_0402_1% VOUT NC 1U_0603_16V6K

2
9

2
TP
G 2 9 92F1U_SO8

1 2
<39> SYSON#

0.1U_0402_16V7K
P R 602 +0.75VSP

1
@ 0_0402_5%
P Q601
S S M 3K7002FU_SC70-3 P R 603

1
D
1K_0402_1%
1 2 2 P C 605
<39> SUSP

P C604
P R 604 G 10U_0805_6.3V6M

2
0_0402_5% S

3
1
C P C 606 C

2
@ 0.1U_0402_16V7K + 5 VALW

1
P C 609 + 1.5VS
1U_0603_6.3V6M

2
6
P U603

1
5

VCNTL
VIN P C 610
7
POK 10U_0805_10V6K
9

2
VIN
3
<14,23,39,47> DGPU_PWR_EN VOUT
1 2 8
EN VOUT
4 +1.1V_PCIE
P R 606

GND
1

1
P JP601 0_0402_5% 2
FB P C 612
+ 0.75VSP 1 2 + 0.75VS (2A,80mils ,Via NO.= 4)
P C 611 22U_0805_6.3V6M

2
1
+ 5 V ALW @ 0.01U_0402_16V7K
P A D - O P EN 3x3m

1
+ 3VS P R 607
P C 618 15K_0402_1% P C613

2
1
1U_0603_6.3V6M A P L5913-KAC-TRL_SO8 @47P_0402_50V8J

2
P JP603
1 2 + P C IE (2A,80mils ,Via NO.= 4)

2
+ 1 . 1V_PCIE

1
P C615
P A D - O P EN 3x3m

6
P U 602 10U_0805_10V6K

2
B 5 P R 608 B

VCNTL
VIN 39.2K_0402_1%
7
P JP602 POK
4

2
VOUT
+ 1 .8VSP 1 2 + 1.8VS (1.5A,60mils ,Via NO.= 3)
VOUT
3 +1.8VSP
P A D - O P EN 3x3m
S U S P# 1 2 8 2
<31,37,39,41,44> SUSP# P R 609 EN FB

GND
1

1
0_0402_5% 9
TP P C616
P C 617 22U_0805_6.3V6M
2

2
1
0.01U_0402_16V7K

1
P R 611
15K_0402_1% P C 614

2
A PL5915KAI-TRL_SO8 150P_0402_50V8J

2
1
P R 610
12K_0402_1%

A A

S ecurity Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/11/23 Deciphered Date 2007/11/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
0.75VP/1.8VSP/1.1V_PCIE
Size D o c u m ent Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Ca lp e lla DI S LA4 743P 0 .1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D a te: Monday, April 13, 2009 Sheet 45 of 49
5 4 3 2 1

http://laptop-motherboard-schematic.blogspot.com/
 8 7 6 5 4 3 2 1

+VCCP CPU_B+ PL202

HCB2 0 1 2KF-121T50_0805
2 1 B+

2
@ @ @ PL205

1K_0402_1%

1K_0402_1%

1K_0402_1%

1K_0402_1%

1K_0402_1%

1K_0402_1%

1K_0402_1%
HCB2 0 1 2KF-121T50_0805

1 0 0 U_25V_M

1 0 0 U_25V_M
1 0 0 0 P_0402_50V7K
0 .1 U_0402_25V6

1 0 U_1206_25V6

1 0 U_1206_25V6
2 1
1 1

PR276

PR277

PR278

PR279

PR280

PR283

PR284

PC209

PC202
PR201 0_0402_5%

1
+ +

PC203

PC205

PC206
H <9> H_ VID0 1 2 H

PC204
PR202 0_0402_5%
<9> H_ VID1 1 2

2
PR203 0_0402_5% 2 2

5
6
7
8
<9> H_ VID2 1 2
PR204 0_0402_5% PQ202
<9> H_ VID3 1 2 AO 4 474_SO8
PR205 0_0402_5%

2
1 2 @ @ @
<9> H_ VID4

1K_0402_1%

1K_0402_1%

1K_0402_1%
PR206 0_0402_5% 4
<9> H_ VID5 1 2
PR207 0_0402_5%

PR2187

PR2186

PR2185
<9> H_ VID6 1 2

3
2
1
2

2
PR209 0_0402_5% @ PR208 PC210

1K_0402_1%

1K_0402_1%

1K_0402_1%

1K_0402_1%
<37> V R_ O N 1 2 0_0603_5% 0 .2 2 U_ 0603_10V7K
BO O ST _ CPU2 2 1 1 2 PR213
PR2 81 0_0603_5% 0 .3 6 UH_ PCMC1 0 4 T - R36MN1R17_30A_20%

PR2174

PR2175

PR2189

PR2188
+VCCP 2 1 UG AT E_ CPU2 2 1
G PL201 G
1K_0402_1% PR2 10 499_0402_1%
<9> H_ DPRSL PVR 1 2 P HASE_ CPU2 4 1 +VCC_ CO RE
2 PR290 1 LF2 3 2

5
@ 1 K_ 0402_1% V 2N

3 .6 5K_0603_1%

10K_0402_5%
PQ203

1
+3VS <19> CL K_ EN# PR212 PR2 11
1 .9 1K_0402_1% 4 .7 _1206_5% PR216

PR2 15
1 2 CL K_ EN# 1_0402_5%
1

PR2 14
L G AT E_ CPU2 4

2
PR217

6 8 0 P_0603_50V7K
PR2 19 VSUM-

1
0_0402_5% 1 .9 1 K_0402_1% T PCA8 0 2 8 - H_ SO P-ADVANCE8-5
2

3
2
1

PC2 11
1 2

2
<13,19> VGATE @ PR221 1 K_ 0402_5% IS EN2
+ VCCP 1 2
VSUM+
F F
PR222 0_0402_5%
<9> H_ PSI# 1 2
PR2 82
2 1
1 K_ 0402_1%
1 2
PR223 1 4 7 K_0402_1%
PR224 PC212
1 U_ 0 6 03_10V6K
40
39
38
37
36
35
34
33
32
31

+VCCP
68_0402_5% PU2 01 1 2
DPRSLPVR
VR_ON
CLK_EN#

VID6
VID5
VID4
VID3
VID2
VID1
VID0

1 2
<6> H_ PRO CHO T# 30
PR225 0_0402_5% BOOT2
29
UGATE2
1 28
PGOOD PHASE2
2 27
PSI# VSSP2
3 26
RBIAS LGATE2
4 25 +5 VALW
VR_TT# VCCP
E 5 24 E
NTC PWM3
6 23
VW LGATE1
7 22
COMP VSSP1
8 21
FB PHASE1
1 2 9
ISEN3
UGATE1

10 ISL 6 2 8 8 3 HRZ-T_QFN40_5X5
BOOT1

ISEN2
ISUM+
2 4 9 K_0402_1%

8 .0 6 K_0402_1%

1 0 0 0 P_0402_50V7K

1 U_ 0 603_10V6K
ISEN1

ISUM-

PC221
VSEN

1 2
IMON
VDD
RTN

VIN

2 2 P_ 0 402_50V8J 41
AGND
1

1
PR234 @

PC222

PC223

0_0402_5%
PR235

PR228
11
12
13
14
15
16
17
18
19
20
2

3 9 0 P_0402_50V7K
1 2
2

PR236
562_0402_1%PC2 24
PR239 0_0402_5%
1 2 1 2 1 2
PC2 25
1 0 P_0402_50V8K PR2 38 PR2 42 0_0402_5% IMVP_ IMO N <9>
D 2 .4 3 K_0402_1% 1 2 CPU_B+ D
0 .2 2 U_0603_25V7K

1 2 1 2
PC227
1 5 0 P_ 0402_50V8J PR2 41 PR2 44 1_0402_5%
4 1 2 K_0402_1% 1 2 C PU_B+
+5 VALW
1

1
1 U_ 0 603_10V6K

0 .2 2 U_0603_25V7K
PC228

PC229

PC230

IS EN2
0 .2 2 U_ 0402_10V4Z

0 .2 2 U_ 0402_10V4Z

PR2 46
2

1 0 0 0P_0402_50V7K
0 .1 U_0402_25V6

1 0 U_1206_25V6
IS EN1 8 .2 5K_0402_1%

5
6
7
8

1 0 U_1206_25V6
2

PQ205

1
PC2 34
VSSSENSE AO 4 474_SO8
BO O ST_ CPU1

PC2 35

PC2 36

PC2 37
PR243
1

1
PC232

PC233

0_0603_5%

2
UG AT E_ CPU1 2 1 4
2

PR2 48 PC240
C 0_0603_5% 0 .2 2 U_ 0603_10V7K C

3
2
1
VSUM+ 2 1 1 2 0 .3 6 UH_ PCMC1 0 4 T - R36MN1R17_30A_20%

PL204
82.5_0402_1%

P HASE_ CPU1 4 1 +VCC_ CO RE

1
0 .0 4 7 U_0603_16V7K

2 .6 1K_0402_1%

1
0 .2 2 U_0603_10V7K

PR251

LF1 3 2

5
@2 7 0 0P_0402_50V7K
PR250

PR253 V 1N
1

1
0 .0 1 U_0402_25V7K

1 2 PQ206 4 .7 _1206_5%

10K_0402_5%
PR2 57
2

3 .6 5K_0603_1%
> V C CSENSE PR252 0_0402_5% 1_0402_5%
PC2 42 2

PC2 43 2

2
1

PC241

PR255

PR256
T PCA8 0 2 8 - H_ SO P-ADVANCE8-5
1

PC245 L G AT E_ CPU1 4

2
PC2 44

3 3 0 P_0402_50V7K
2

2
3 3 0 P_0402_50V7K

6 8 0 P_0603_50V7K
2

1
PC248

PC246
VSUM-

3
2
1

2
1

B B
1 1 K_0402_1%

PR260
1

1
PR262

PC2 47 1 .1 K_0402_1% PH2 0 2

1 0 0 0 P_0402_50V7K 1 2 PR261
PR2 63 0_0402_5% 0_0402_5% 1 0 KB_ 0 6 0 3 _ 5 %_ERTJ1VR103J IS EN1
2

<9> VSSSENSE 1 2
2

VSUM+
2

PC2 49 100_0402_1%
1 21 2 VSUM-

1 2 0 0 P_0402_50V7K PR2 65
Iccmax= 35A
I_TDC=TDB
0 .1 U_ 0402_16V7K
1
PC2 50

OCP=TDBA, Intel spec=TDBA

2

A A
Security Classification
2007/05/29
Compal Secret Data
2008/05/29 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_CORE
http://laptop-motherboard-schematic.blogspot.com/
Size Do cu me n t Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Calpella DIS LA4743P 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: Mo n d a y, April 13, 2009 Sheet 46 of 49
8 7 6 5 4 3 2 1
 A B C D

1 1

PR701
0_0402_5%
1 2
<14,23,39,45> DGPU_PWR_EN

1
PL701
PC701
@1000P_0402_50V7K HCB1608KF-121T30_0603

2
VGA_B+ 1 2 B+

@0.1U_0402_25V6

4.7U_0805_25V6-K

4.7U_0805_25V6-K

1000P_0402_50V7K

1
1

1
PC708

PC703

PC704

PC710
PC705
2200P_0402_50V7K

2
2

2
5
+ 5VALW
1+5VALW

BST _VGA 1 2 1 2

PR704 PC706
2 0_0402_5% 0.1U_0402_10V7K 4 2

PR702 PQ701

15

14
1
316_0402_1% PU701 AON7408L_DFN8-5
PR705

EN_PSV

TP

VBST
255K_0402_1%
2

3
2
1
1 2 2 13 D H _ VGA 1 2 D H _VGA_1 PL702
TON DRVH PR707 0.82UH_PCMC063T -R82MN_13A_20%
PR703
+ N VVDDP 2 1 3 12 LX_VGA 0_0402_5% 1 2 +NVVDDP
VOUT LL
0_0402_5%
4 11 1 2
V5FILT TRIP

470U_D2_2VM_R4.5M

22U_0805_6.3V6M

22U_0805_6.3V6M
PR706 1
+VGA_COREP1 1 2 5 10 + 5VALW 7.15K_0402_1%
VFB V5DRV

5
6
7
8

1
PC709

PC711

PC712
PR720 +
1

1
PR708 6 9 PC707 PQ702 4.7_1206_5%
PGOOD DRVL

PGND
PC702 5.11K_0402_1% 4.7U_0805_10V6K

GND

2
1

1U_0603_10V6K 2
2

2
1 2 PR721

1
PC713 0_0402_5% D L _VGA 4

8
PC716
@1000P_0402_50V7K T PS51117RGYR_QFN14_3.5x3.5 680P_0603_50V7K
2

2
N VVDD_PG <39>
1

AO4714_SO8

3
2
1
PR714 PR713
0_0402_5% 10_0402_5%
1
2

PQ713A
PR718 2N7002KDW-2N_SOT363-6
PR711
+NVVDD_SENSE

75K_0402_1% 1 2 6 1
+NVVDDP

3 3
2

38.3K_0402_1%
2

1 2
PR717 GPU_VID1 <24>
1

1
PR712 10K_0402_1%
+ N VVDD_SENSE PC715
GPU_VID1 GPU_VID0 +NVVDD
76.8K_0402_1% 0.022U_0402_16V7K PR719
2

10K_0402_5%
1 0 0.9V
2

2
0 1 0.85V
0 0 0.8V
PQ713B
3

2N7002KDW-2N_SOT363-6
PR715
10K_0402_1%
5 1 2
GPU_VID0 <24>
4

PC714
0.022U_0402_16V7K PR716
2

10K_0402_5%
2

4 4

PJP701

+ N VVDDP 1 2 + N VVDD (11A,489mils ,Via NO.= 22)

P AD -OPEN 4x4m
Security Classification Compal Secret Data Compal Electronics, Inc.
PJP702 Issued Date 2007/05/29 Deciphered Date 200810/11 Title

1 2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_CORE
Size D o cument Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
P AD -OPEN 4x4m

A
http://laptop-motherboard-schematic.blogspot.com/
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D ate: Monday, April 13, 2009
Calpella DIS LA4743P
D
Sheet 47 of 49
0.1
 A B C D

1 1

PL902
PR901
0_0402_5% HCB1608KF-121T30_0603
1 2 1.5V_B+ 1 2 B+
1,37,38,39> SYSON
1

0.1U_0402_25V6

10U_1206_25V6

1000P_0402_50V7K
PC901
@ 1000P_0402_50V7K
2

1
PC906

PC903

PC904
+ 5VALW PC905

2
5
1+5VALW

BST _1.5V
1 2 1 2
PQ901
PR902 AON7408L_DFN8-5
0_0402_5% 0.1U_0402_10V7K

PR903 D H _1.5V 4

15

14
1
316_0402_1% PU901
PR904

EN_PSV

TP

VBST
2 255K_0402_1% 2
2

1 2 2 13 D H_1.5V_1 1 2 PL901

3
2
1
TON DRVH PR905 0_0402_5% 2.2UH_PCMC063T -2R2MN_8A_20%
PR906
2 1 3 12 LX_1.5V 1 2
+1.5VP VOUT LL +1.5VP
0_0402_5%
4 11 1 2
V5FILT TRIP

330U_B2_2.5VM_R15M
5 10 + 5VALW PR907 13.7K_0402_1% PQ902
VFB V5DRV

4.7U_0805_6.3V6K
FDMC8296_POWER33-8-5 PR909 1
1

1
PC907 6 9 D L_1.5V PC908 4.7_1206_5%
PGOOD DRVL

2
PGND

PC909

PC910
1U_0603_10V6K 4.7U_0805_10V6K +

GND
4
2

1
7 2

2
PC913
680P_0603_50V8J

3
2
1
T PS51117RGYR_QFN14_3.5x3.5

1
PR908
+1.5VP 1 2
10.2K_0603_0.1%

OCP=9.8913(min)
MOSTemperature Factor=1.3 (100C)
1

3 PR911 3

10K_0603_0.1%
2

PJP901

+1.5VP 1 2 +1.5V (6A,240mils ,Via NO.= 12)

P AD -OPEN 4x4m

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5VP
Size D o cument Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

A
http://laptop-motherboard-schematic.blogspot.com/ B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D ate:
Calpella DIS LA4743P
Monday, April 13, 2009
D
Sheet 48 of 49
0.1
 A B C D E

Version Change List ( P. I. R. List ) for Power Circuit

Item Page# Title Date Request Issue Description Solution Description Rev.
Owner
1 1

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Changed-List History-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev

http://laptop-motherboard-schematic.blogspot.com/
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom C alpella DI S LA 4743P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: Monday, April 13, 2009 Sheet 49 of 49
A B C D E