EC 381

Digital Systems I

Lecture # 10
Topics
 XOR and XNOR gates
 Odd function
 Parity generation and checking
 Buffer
 Negative Logic
 Combinational circuits design

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Exclusive OR and XNOR
 Symbol is 
 .

 XNOR gate (with 2-inputs performs a “equivalence

operation”):

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Uses for XOR / XNOR
 SOP Expressions for XOR/XNOR:
• The XOR function is: X  Y = X Y + X Y
• The eXclusive NOR (XNOR) function, know also as
equivalence is: XY = XY+XY
 Uses for the XOR and XNORs gate include:
• Adders/subtractors/multipliers
• Counters/incrementers/decrementers
• Parity generators/checkers
 Strictly speaking, XOR and XNOR gates do not
exist for more than two inputs. Instead, they are
replaced by odd and even functions.
Additional Gates and Circuits –
Exclusive-OR Function
 This function is equal to one only if either x or y is equal
to one but not both
 Sometimes, we can find an XOR gate “hidden” or “buried”
inside of a lot of AND, OR and NOT gates. If we can “find”
and “extract” the XOR gate, we can take advantage of it to get
a large savings in circuit size.

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XOR Postulates and Theorems
 Exclusive NOR (XNOR) can be generated by taking the
complement of an XOR operation
 (x  y)’ = xy + x’y’
 The following identities apply to XOR
 x0=x
 x  1 = x’
 xx=0
 x  x’ = 1
 x  y’ = x’  y = (x  y)’
 XOR is also commutative and associative

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XOR Implementations

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Odd Function
 The XOR operation with three or more variables can be
converted into an ordinary Boolean function by replacing the 
with its equivalent Boolean expression
 A  B  C = (AB’ + A’B)C’ + (AB + A’B’)C
 AB’C’ + A’BC’ + ABC + A’B’C
 ∑ (1, 2, 4, 7)
 This function is equal to 1 only if one variable is equal to 1 or if
all three variables are equal to 1.
 Each of these binary numbers (1, 2, 4, 7) has an odd number of
1’s.
 This is defined as an odd function.
 The complement of an odd function is an even function.
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Odd Function

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Odd Function

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 Odd/Even Function Implementation
 Design a 3-input odd function with 2-input XOR:
 3-input odd function:
X
F = (X  Y)  Z Y
F
Z

 Design a 4-input even function with 2-input XOR

and XNOR gates:
W
 4-input even function: X
F
F = (W  X)  (Y  Z) Y
Z
Additional Gates and Circuits –
Parity Generation and Checking
 XOR functions are very useful in systems requiring error-
detection and correction codes.
 A parity bit is an extra bit included with a binary message to
make the number of 1’s either odd or even.
 A circuit that generates a parity bit is called a parity
generator.
 The circuit that checks the parity is called a parity checker.

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Parity Bit Generator

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Even-Parity Checker

 An error is detected if the checked parity does not

correspond with the one transmitted.

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Buffer
 A buffer is a gate with the function F = X
X F
X F
0 0
 In terms of Boolean function, 1 1
a buffer is the same as a connection!
 So why use it?
• A buffer is used to amplify an input signal
• Permits more gates to be attached to output
• Also, increases the speed of circuit operation
Additional Gates and Circuits –
 Hi-Impedance Output
 Logic gates introduced thus far …
• Have 1 and 0 output values
• Cannot have their outputs connected together
 Three-state logic adds a third logic value:
• Hi-Impedance output: Hi-Z
 What is Hi-Impedance output?
• The output appears to be disconnected from the input
• Behaves as an open circuit between gate input & output
 Hi-Z state makes a gate output behave differently:
• Three output values: 1, 0, and Hi-Z
• Hi-impedance gates can connect their outputs together
Additional Gates and Circuits –
The 3-State Buffer (Tri-State)
 IN = data input Symbol
 EN = Enable control input
IN OUT
 OUT = data output
 If EN = 0 then OUT = HI-Z EN
• Regardless of the value on IN
• Output disconnected from input Truth Table
 If EN = 1, then OUT =IN EN IN OUT
• Output follows the input value
0 X Hi-Z
 Variations: 1 0 0
• EN can be inverted
1 1 1
• OUT can be inverted
• By addition of bubbles to signals
Additional Gates and Circuits –
 Wired Output: Resolving Output Value
 The output of 3-state buffers can be wired together
 At most one 3-state buffer can be enabled. Resolved
output is equal to the output of the enabled 3-state buffer
 If multiple 3-state buffers are enabled at the same time
then conflicting outputs will burn the circuit
EN0
O0 Resolution Table
IN0
O0 O1 O2 OUT
EN1 0 or 1 Hi-Z Hi-Z O0
O1 OUT Hi-Z 0 or 1 Hi-Z O1
IN1
Hi-Z Hi-Z 0 or 1 O2
EN2 Hi-Z Hi-Z Hi-Z Hi-Z
O2 0 or 1 0 or 1 0 or 1 Burn
IN2
Additional Gates and Circuits –
Positive and Negative Logic
 Using H to signify a logic 1 (true) is known as
positive logic
 Using H to signify 0 is known as negative logic

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Negative Logic
 Assign 0 to H

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AND Gate Specification

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Positive vs. Negative Logic

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Bottom Line
 Not much real change
 Negative logic functions are just duals of positive logic
ones
 OR -> AND
 AND -> OR

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Combinational Circuit

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Design Procedure
1. From the specifications of the circuit, determine the
required number of inputs and outputs and assign a
symbol to each.
2. Draw the Block diagram of the circuit.
3. Derive the truth table that defines the required
relationship between inputs and outputs.
4. Obtain the simplified Boolean functions for each output
as a function of the input variables.
5. Draw the logic diagram and verify the correctness of
the design (manually or by simulation).
6. Implement or realize the circuit.
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Example
 Design a 3-input majority function. The output is
equal to 1 if the input variables have more 1's than 0's.
The output is 0 otherwise.

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1. Let inputs be (X,Y,Z). Assume X to be the most
significant bit.
Assume output to be F
2. Derive Truth table

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3. Simplify F

4. Draw logic diagram

 (SOP)

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