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# Lecture 15

EC381
Digital Systems I
University of Tripoli

Digital Systems 1
Goals
 Previously, we studied Combinational circuits, or networks.

##  These are time independent because the inputs, once provided,

immediately establish what the outputs will be.

##  We now continue to consider Sequential Networks

 These are time dependent in that the initial values of the circuit
outputs are used to provide input to the same circuit.

##  This is called feedback.

Digital Systems 2
Goals
 The properties of sequential networks yield the capability to design
memory circuits

##  characterized by internal states or secondary states that describe the

behavior and values in a circuit before and after inputs are applied.

##  Synchronous - behavior is governed by the inputs only during

specific discrete time intervals

##  Asynchronous - behavior is governed by the inputs immediately as

they are applied

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Goals
• We can include storage elements into a circuit that act like
memory and store a system state. Now, we have a sequential circuit!
• Outputs are then a function of both the current circuit inputs and
the system state (i.e., what happened in the circuit before… history
is present!).

Inputs . . Outputs
. Combinational .
Logic Gates

Memory Elements
(Flip-Flops)
Clock

Digital Systems 4
Clock signals
 Clock signals are particularly important to understand for
designing synchronous sequential circuits (aka clocked sequential
circuits).
 A clock signal is used to control the behavior of a circuit at
discrete instances in time; it does this by controlling/determining
how and when memory elements can change their outputs.

Digital Systems 5
Clock signals
 Clock signals are periodic signals (so they have a frequency and a
period).
 We can use clocks to control when things happen in a circuit
because their transitions from 01 and 10 occur at discrete
instances in time.
 The 0  1 transition is often called the rising edge of the clock.
 The 1  0 transition is often called the falling edge of the clock.

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Storage Elements
 There are two types of storage elements: 1) Latches and 2) Flip-
flops.

Digital Systems 7
Latches

##  Latches are one type of storage element.

 They are level sensitive storage elements – what does level
sensitive mean?
 Level sensitive mean that latches operate (i.e., they perform their function)
when a control signal is at either logic level 0 or 1 and not at logic
transitions from 01 or 10.
 Latches are not necessarily useful for clocked sequential circuits,
but they are useful for asynchronous sequential circuits.
 They also help to understand the behavior of flip-flops (another type of
storage element which is useful for clocked sequential circuits).
 There are different types of latches.

Digital Systems 8
SR latch (NOR implementation)
 Consider the following circuit built from two NOR gates. Note
the “cross-coupled” gates that introduce a combinational loop
into the circuit.

Characteristic Table

Undesired

Digital Systems 9
SR latch (NOR implementation)
 In general, the outputs are complements of each other (this is why
they are labeled Q and ):
 When S=1, R=0 the output is Q=1, !Q=0 and the circuit in the set state.
 When S=0, R=1 the output is Q=0, !Q=1 and the circuit in the reset state.
 S=1 (active high) implies set (Q=1) and R=1 (active high) implies
reset (Q=0).
 When S=0, R=0 the output holds at its previous value (storage).
 Exception: When S=1, R=1 the output is Q=!Q=0 which is not
desirable and we should avoid this combination of inputs. We
always want to complementation property at the outputs.

Digital Systems 10
S’R’ latch (NAND implementation)
 Consider the following circuit build from 2 NAND gates. Again,
note the cross-coupled gates and the combinational loop.

Reset

Set

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Gated latches (1)
 We can add an additional control input that acts as an enable
signal. The purpose of the enable signal is to control whether or
not the latch functions (vs. just “holding its current state”).
 Consider adding some extra NAND gates in front of an S’R’
Latch.

Digital Systems 12
Gated latches (2)

 When the control input C=0 the inputs to the latch are both 1
which puts the S’R’ latch into its hold state. So, the latch outputs
will not change regardless of the S and R values.

Digital Systems 13
Gated latches (3)

 When the control input C=1 the S and R inputs will reach the
latch and we can analyze the behavior.
 The NAND gates at the input to the latch result in active high
inputs:
 S=1 (and R=0) causes a set (Q=1).
 R=1 (and S=0) causes a reset (Q=0).

Digital Systems 14
D latch
 We sometimes had an undesirable situation where we cannot
determine the latch output (both outputs had same value).
 To avoid this situation we can construct a latch where S and R
can never be the same value.

 We still have the set and reset states. Notice that because of the
control signal, we still have a hold state too. But, we avoid the
undesirable situation in which the outputs of the latch are the
same (and break the complementation property).
Digital Systems 15
Schematic symbols (1)

Digital Systems 16
Schematic symbols (2)
 For a D Latch, the control input is required, since it is via the
control input that we have the hold state.

Digital Systems 17
Potential issues with latches
 Latches do not allow for precise control because they are level
sensitive; e.g., consider a d-latch with a clock signal connected to
the control input – the output of the latch can change anytime
while the clock is high.
 This creates an interval in time over which the state, or output, of
the memory element can change rather that an instant in time at
which the state, or output, of the memory element can change.
 It would be better to only allow the output to change when the
clock edge makes a transition from 0  1 (rising edge triggering)
or 1  0 (falling edge triggering). This gives even more precise
control!

Digital Systems 18
Flip-flops
 Recall that latches are level sensitive devices and do not give
precise control with respect to when their outputs change.

##  We want changes only in the instance of time when some clock

signal makes a transition from either 0  1 (rising edge
triggering) or 1  0 (falling edge triggering).

##  Flip-flops are storage elements that are edge-triggered.

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What does triggering mean?
 Response to positive level (a latch) – large window of time for output to
change.

 Positive Edge Triggering. The input to the flip-flop just before the clock
changes from 0 -> 1 causes the output to change just after the clock changes
from 0 -> 1.

 Negative Edge Triggering. The input to the flip-flop just before the clock
changes from 1 -> 0 causes the output to change just after the clock changes
from 1 -> 0.

Digital Systems 20
Master-slave DFF (negative edge-triggered)
 Consider a circuit constructed with 2, D-Latches (one master and one slave):

 While CLK=1, Y will follow input D via the master latch, but Q will not
follow Y (it is in hold state) and will hold its current value.
 When CLK=0 (at the moment of change), Y will be disconnected from D and
will hold its current value. Q will follow Y via the master latch.
 The effect is that the value of D just prior to the falling edge of the clock will
get “transferred” to the output Q just after the falling edge of the clock.

Digital Systems 21
Master-slave DFF (positive edge triggered)
 We can make a positive edge triggered DFF simply by changing
the inversion of the clock signal
 Output of master latch, Y, follows D when clock is low (slave in hold).
 Output of slave latch, Q, follows Y when clock is high (master in hold).

Digital Systems 22
Schematic symbols for DFF

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