Systèmes embarqués à

microprocesseurs

Introduction aux PSoC 5

Vincent SZYMANSKI

9 septembre 2015
Plan de l’exposé

I. General Overview
II. Architecture
III. Processor : ARM Cortex M3
IV. Processor : ARM Cortex M3
A. Harvard architecture
B. Features of ARM Cortex M3 processor
C. ARM Pipe-line
D. CPU Registers
E. Memory Map
F. Bit banding
V. PSoC 5 Ecosystem
VI. Development kit

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I. I

I. General Overview

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I. I

Objectives

Understand hardware structure of PSoC 5 components

Understand Comprendre le mécanisme de construction d’un projet
avec PSoC Creator
Savoir compiler, construire, programmer et debugger des applications
PSoC Creator
Savoir créer des applications simples utilisant les périphériques tels
que : le character lcd, les broches d’entrée/sort

Vincent SZYMANSKI (I.U.T. de Saint-Etienne) 4 / 43 9 septembre 2015 – C.E.M.

I. I

PSoC 5 Ecosystem

Hardware :
I Processor ARM Cortex M3 32 bits (data bus)
I Universal Digital Blocks : UDB
I Peripherals : GPIO, ADC, DAC, UART, I2 C, SPI, CAN, . . .
I memories : RAM, EEPROM, FLASH
I DMA
I more : Verilog
Software : PSoC Creator (last 3.2)

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I. I

Applications

Processors for embedded applications can be divided in 2 main types :

those with MMU a which can host Linux kernel and OS
ß HOSTED
DATA BUS ≥ 32 bits
those without MMU which cannot support a Linux OS like
ß BARE METAL or FREE STANDING UNIT
Mostly DATA BUS ≤ 32 bits
PSoC 5 processors are FREE STANDING UNIT

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II. II.

II. Architecture

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II. II.

CPU Subsytem

processor : ARM Cortex M3

I 32-bit databus system
I up to 80 MHz system clock
I ARM v7 architecture
I single cycle 3-stage pipeline
I Harvard architecture - RISC
powerful DMA
on-chip debug and trace
power management

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III. Processor : ARM Cortex M3

III. Processor : ARM Cortex M3

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III. Processor : ARM Cortex M3

Processor ARM Cortex M3

Harvard architecture (vs Von Neumann)

Physical separation of data memory and program memory.
Access to each of these memories is via two separate buses
Advantage : can simultaneously transfer data and instructions to
execute
Performance increased compared to the same technology on Von
Neumann model but at the cost of increased complexity.
RISC (vs CISC) : Reducted Instruction Set Computer
3 levels of pipe-line
Up to 80 MHz

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IV. Processor : ARM Cortex M3

IV. Processor : ARM Cortex M3

A. Harvard architecture
B. Features of ARM Cortex M3 processor
C. ARM Pipe-line
D. CPU Registers
E. Memory Map
F. Bit banding

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IV. Processor : ARM Cortex M3
A. Harvard architecture

IV. Processor : ARM Cortex M3

A. Harvard architecture
B. Features of ARM Cortex M3 processor
C. ARM Pipe-line
D. CPU Registers
E. Memory Map
F. Bit banding

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IV. Processor : ARM Cortex M3
A. Harvard architecture

Processor ARM Cortex M3

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IV. Processor : ARM Cortex M3
B. Features of ARM Cortex M3 processor

IV. Processor : ARM Cortex M3

A. Harvard architecture
B. Features of ARM Cortex M3 processor
C. ARM Pipe-line
D. CPU Registers
E. Memory Map
F. Bit banding

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IV. Processor : ARM Cortex M3
B. Features of ARM Cortex M3 processor

Processor ARM Cortex M3

Greater performance efficiency : alllowing more work to be done

without increasing the frequency of power requirements.
Low power consumption : enabling longer battery life, especially in
portable products including wireless networking applications.
Enhanced determinism : guaranteeing that critical tasks and
interrupts are serviced as quickly as possible and in a known number
of cycles.
Ease of use : providing easier programmability and debugging for the
growing number of 8-bit and 16-bit users migrating to 32 bits.
Lower cost solutions : reducing 32-bit based system costs close to
those of legacy 8-bit and 16-bit devices and enabling low-end, 32-bit
microcontrollers to be priced at less than US $1 for the first time.
Wide choice of development tools : from low-cost or free compilers to
full-featured development suites from many development tool vendors

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IV. Processor : ARM Cortex M3
B. Features of ARM Cortex M3 processor

Features of the ARM Cortex M3

Harvard bus architecture

3 stage pipeline with branch speculation
Configurable nested vectored interrupt controller (NVIC)
Wake-up Interrupt Controller (WIC)
enables ultra low-power standby operation
Extended configurability of debug and trace capabilities
more flexibility for meeting specific market requirements
Optional components for specific market reqs
I Memory Protection Unit (MPU)
I Embedded Trace Macrocell TM (ETMTM
Physical IP support Power Management KitTM (PMK) + low-power
standard celle libraries and memories enable 0.18µm Ultra Low
Leakage (ULL) process

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IV. Processor : ARM Cortex M3
B. Features of ARM Cortex M3 processor

Features of the ARM Cortex M3

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IV. Processor : ARM Cortex M3
B. Features of ARM Cortex M3 processor

Features of the ARM Cortex M3

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IV. Processor : ARM Cortex M3
B. Features of ARM Cortex M3 processor

Features of the ARM Cortex M3

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IV. Processor : ARM Cortex M3
B. Features of ARM Cortex M3 processor

Features of the ARM Cortex M3

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IV. Processor : ARM Cortex M3
B. Features of ARM Cortex M3 processor

Features of the ARM Cortex M3

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IV. Processor : ARM Cortex M3
B. Features of ARM Cortex M3 processor

Features of the ARM Cortex M3

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IV. Processor : ARM Cortex M3
B. Features of ARM Cortex M3 processor

Havard & Von Neumann architecture

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IV. Processor : ARM Cortex M3
B. Features of ARM Cortex M3 processor

RISC vs CISC

CISC = Complex Instruction Set Computer

RISC = Reducted Instruction Set Computer

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IV. Processor : ARM Cortex M3
B. Features of ARM Cortex M3 processor

RISC application systems

By the beginning of the 21st century, the majority of low end and mobile
systems relied on RISC architectures. Examples include :
The ARM architecture dominates the market for low power and low
cost embedded systems (typically 200–1800 MHz in 2014). It is used
in a number of systems such as most Android-based systems, the
Apple iPhone and iPad, RIM devices, Nintendo Game Boy Advance
and Nintendo DS, etc.
The MIPS line, (at one point used in many SGI computers) and now
in the PlayStation, PlayStation 2, Nintendo 64, PlayStation Portable
game consoles, and residential gateways like Linksys WRT54G series.
Hitachi’s SuperH, originally in wide use in the Sega Super 32X,
Saturn and Dreamcast, now developed and sold by Renesas as the
SH4
Atmel AVR used in a variety of products ranging from Xbox handheld
controllers to BMW cars.

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IV. Processor : ARM Cortex M3
C. ARM Pipe-line

IV. Processor : ARM Cortex M3

A. Harvard architecture
B. Features of ARM Cortex M3 processor
C. ARM Pipe-line
D. CPU Registers
E. Memory Map
F. Bit banding

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IV. Processor : ARM Cortex M3
C. ARM Pipe-line

ARM Cortex Pipeline

Harvard architecture, Separate Instruction & Data buses, enable parallel

fetch & store, Advanced 3-Stage Pipeline includes branch forwarding &
speculation.

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IV. Processor : ARM Cortex M3
D. CPU Registers

IV. Processor : ARM Cortex M3

A. Harvard architecture
B. Features of ARM Cortex M3 processor
C. ARM Pipe-line
D. CPU Registers
E. Memory Map
F. Bit banding

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IV. Processor : ARM Cortex M3
D. CPU Registers

ARM Cortex Pipeline

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IV. Processor : ARM Cortex M3
E. Memory Map

IV. Processor : ARM Cortex M3

A. Harvard architecture
B. Features of ARM Cortex M3 processor
C. ARM Pipe-line
D. CPU Registers
E. Memory Map
F. Bit banding

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IV. Processor : ARM Cortex M3
E. Memory Map

Memory Map

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IV. Processor : ARM Cortex M3
E. Memory Map

Memory Map

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IV. Processor : ARM Cortex M3
E. Memory Map

Memory Map

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IV. Processor : ARM Cortex M3
E. Memory Map

Memory Map

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IV. Processor : ARM Cortex M3
F. Bit banding

IV. Processor : ARM Cortex M3

A. Harvard architecture
B. Features of ARM Cortex M3 processor
C. ARM Pipe-line
D. CPU Registers
E. Memory Map
F. Bit banding

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IV. Processor : ARM Cortex M3
F. Bit banding

Bit banding

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IV. Processor : ARM Cortex M3
F. Bit banding

Bit banding

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IV. Processor : ARM Cortex M3
F. Bit banding

Bit banding

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IV. Processor : ARM Cortex M3
F. Bit banding

Bit banding

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V. III.

V. PSoC 5 Ecosystem

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V. III.

IDE or EDA PSoC Creator

The software used to develop PSoC 5 applications is PSoC Creator.

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V. III.

Analog Subsytem

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VI. IV.

VI. Development kit

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