Beruflich Dokumente
Kultur Dokumente
- A Design Perspective
E. KONGUVEL
Teaching Fellow
Department of Electronics Engineering, Anna University – MIT.
MOS TRANSISTOR
PRINCIPLES
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The MOS(FET) Transistor
• Workhorse of contemporary digital design.
• Performs very well as switch & introduces few
parasitic effects.
• Advantages – Integration density:
– Possibility of producing large & complex circuits in an
economical way.
First Glance:
• Four terminal device:
– Voltage applied at Gate determines amount of current flow
between Source and Drain.
– Body terminal is secondary because it only serves to
modulate the device characteristics and parameters.
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The MOS(FET) Transistor
Switch Operation:
• When applied gate voltage is larger than given voltage
(Threshold Voltage VT), a conducting channel is
formed between Drain & Source.
• In presence of Voltage difference between Drain &
Source, electrical current flows.
• Conductivity of channel is controlled by gate voltage.
• i.e., Larger the voltage difference between Gate &
Source, Smaller the resistance of channel & Larger the
current.
• When gate voltage is lower than VT, the Switch is
considered to be open.
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The MOS(FET) Transistor
Types of MOSFET:
NMOS PMOS
n+ Drain & Source regions p+ Drain & Source regions
p substrate n substrate
n channel p channel
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The MOSFET under static conditions
Threshold Voltage:
• Assume VGS = 0 / Drain, Source & Bulk are GNDed.
– Drain & Source are connected by back-to-back PN junctions.
– Source (N) – Substrate (P) – Drain (N).
– The device at 0 V bias.
– Considered to be OFF.
– High resistance between Source & Drain.
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The MOSFET under static conditions
Threshold Voltage:
• Positive voltage is applied to Gate:
– Gate & Substrate forms the plate of the capacitor with gate
oxide as dielectric.
– Positive charges accumulates on Gate & Negative charges on
substrate.
– Hence depletion region is formed below the gate.
– Width of depletion layer:
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The MOSFET under static conditions
Threshold Voltage:
• Gate Voltage still increases:
– At a critical point semi-conductor surfaces inverts to n-type
material.
– Strong inversion occurs @ voltage equals twice of Fermi
potential. (-0.3 V for typical p-substrates)
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The MOSFET under static conditions
Threshold Voltage:
• But for n-channel devices:
– Substrate Bias Voltage (VSB) is applied.
– This causes surface potential required for strong inversion to
increase. So,
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The MOSFET under static conditions
Resistive Operation:
• Now VGS > VT & Small VDS is applied:
– Voltage difference causes ID to flow.
– ID as a function of VGS & VDS.
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The MOSFET under static conditions
Resistive Operation:
• Combining all above relations,
IDdx = μnCoxW(VGS – V(x) – VT)dV.
– Integrating ID over the length of the channel,
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The MOSFET under static conditions
Resistive Operation:
• Gain factor kn:
Gain factor kn = Product of kn‟ & W/L ratio.
• Relationship between VDS & ID:
– For smaller VDS, quadratic factor can be ignored
– So, linear dependence between VDS & ID.
– Region under the curve is resistive or linear region
– Property: A continuous conductive channel between
source & drain.
Effective Channel Width and Length:
W = Wd – ΔW
L = Ld – ΔL
where d subscript denotes drawn size
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The MOSFET under static conditions
The Saturation Region:
VDS further increased (VDS > VGS - VT):
– Channel voltage larger than threshold voltage ceases to hold
at VGS – V(x) < VT.
– Induced charge becomes zero and channel disappears or
pinched-off.
– This happens at VGS – VDS ≤ VT.
– Voltage at induced channel remains at VGS – VT & ID remains
constant.
– Replacing VDS by VGS – VT
in ID (for resistive operation),
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The MOSFET under static conditions
Velocity Saturation:
• Behaviors of short-channel devices varies from
resistive and saturation modes.
• From Velocity equation, Velocity is proportional to
electric field, independent of value of that field.
• At high field strengths, carriers fail to follow linear
model.
• When electric field reaches
a critical value ξc, velocity
saturates due to scattering
effects.
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The MOSFET under static conditions
Velocity Saturation:
• For p-type silicon, critical field is 1.5 V/μm and saturation
velocity υsat is 105m/s.
• Inference:
– Only few volts requires to saturate an NMOS of 1μm.
– Can be easily achieved in short channel devices.
– Holes in n-type silicon saturates at same velocity but requires
higher electric field.
– Velocity saturation effects are less pronounced in PMOS
devices.
• Impact:
– Velocity as a function of electrical field can be approximated
as,
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The MOSFET under static conditions
Velocity Saturation:
• The drain current ID, after considering revised
velocities,
• Inference:
– For Long channel devices, κ approaches 1.
• Simplifies to traditional current
– For short channel devices, κ will be less than 1.
• Current is less than expected.
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The MOSFET under static conditions
Velocity Saturation:
Observations:
• For short channel device, κ is less than 1. Device enters
saturation before VDS reaches VGS – VT.
Hence, short-channel devices experiences an
extended saturation region and tend to operate more
often in saturation conditions.
• IDSAT has a linear dependence
w.r.t VGS for short-channel
devices whereas it has
squared dependence in
long-channel devices.
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The MOSFET under static conditions
Drain current versus Voltage charts:
ID vs. VDS (Parameter - VGS):
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The MOSFET under static conditions
Drain current versus Voltage charts:
ID vs. VGS (Fixed VDS):
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The MOSFET under static conditions
PMOS Characteristics (?):
i. Similar
characteristics
& relations.
ii. All voltages &
currents are
reversed.
iii.Third-
quadrant
curves.
iv.Velocity
saturation
effects are poor.
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The MOSFET under static conditions
Problem(s):
1. Determine the mode of operation of NMOS transistor
and drain current ID for each of the biasing
configurations given below.
Transistor data: kn‟ = 115 µA/V2, VT = 0.43 V and
λ = 0.06 V-1. Assume W/L = 1.
i. VGS = VDS = 2.5 V.
ii. VGS = 3.3 V, VDS = 2.2 V.
iii. VGS = 0.6 V, VDS = 0.1 V.
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The MOSFET under static conditions
Problem(s):
1. Determine the mode of operation of PMOS transistor
and drain current ID for each of the biasing
configurations given below.
Transistor data: kn‟ = 30 µA/V2, VT = -0.4 V and
λ = -0.1 V-1. Assume W/L = 1.
i. VGS = -0.5 V, VDS = -1.25 V.
ii. VGS = -2.5 V, VDS = -1.8 V.
iii. VGS = -2.5 V, VDS = -0.7 V.
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The MOSFET under static conditions
Sub-threshold Conduction:
• On log-scale of ID – VGS curves, it is apparent that MOS
transistor is already partially conducting below threshold
voltage: - Sub-threshold or weak-inversion.
• On strong inversion, ample carriers are available for conduction,
so for very low VGS voltages, smaller currents are available.
• For VGS < VT, ID decays in an
exponential fashion, similar to a
bipolar transistor.
• In absence of conducting
channel, n+ (source) – p (bulk) –
n+ (drain) forms a parasitic
bipolar transistor.
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The MOSFET under static conditions
Sub-threshold Conduction:
• So, ID can be approximated as,
mV/decade
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The MOSFET under static conditions
Sub-threshold Conduction:
• For n = 1, S = 60mV/decade @ room temperature & for n = 1.5,
S = 90mV/decade.
• By reducing temperature T, current roll-off factor can further be
decreased.
• Value of n is determined by intrinsic topology & structure. So to
decrease n, requires a different process technology.
• Generally, ID must be as close as possible to zero at VGS = 0.
• In dynamic circuits (in presence of sub-threshold current), it can
be achieved by a firm lower bound on value of threshold voltage
of devices.
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The MOSFET: Manual Analysis
Unified Model (?):
• Complex deep-submicron
– Non-linear
– Second order effects.
• Simple and Tangible analytical model – Unified Model.
– Simplifies to the available current equations.
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The MOSFET: Manual Analysis
Unified Model (?):
• Five parameters to be employed: - VTO, γ, VDSAT, k‟& λ.
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The MOSFET: Dynamic Behavior
• Dynamic response:
– A function of time it takes to (dis)charge the parasitic
capacitances that are intrinsic to the device and the extra
capacitances introduced by the interconnecting lines and
load.
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The MOSFET: Dynamic Behavior
Channel Capacitances:
• Gate-to-Channel capacitances (CGC):
– Gate-to-Source (CGCS) Depends on:
– Gate-to-Drain (CGCD) i. Operating regions
– Gate-to-Body (CGCB) ii. Terminal Voltages
i. When VGS = 0,
Capacitance exists b/w
Gate & Body (WLCox).
ii. When VGS increases,
depletion region forms,
CGC decreases.
iii.At VGS = VT, channel
forms, CGCB drops to 0.
iv. At VDS = 0, capacitance
divides b/w Source &
Drain.
CGCS = CGCD = WLCox/2
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The MOSFET: Dynamic Behavior
Channel Capacitances:
Gate-Channel Capacitance vs. VDS/(VGS-VT):
(Degree of Saturation)
When saturation
increases,
i. CGCD drops to 0.
ii. CGCS increases to
2WLCox/3 from
WLCox/2.
iii.So, CGC also
decreases.
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The MOSFET: Dynamic Behavior
Channel Capacitances:
Avg. Distribution of Channel Capacitance:
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The MOSFET: Dynamic Behavior
Junction Capacitances:
• Final Capacitive Component:
– By Reverse biased Source-Body & Drain-Body PN junctions.
• Two Components:
– Bottom Plate Junction
• Source Region (ND) &
Substrate (NA)
• Cbottom = CjWLS.
– Side-wall Junction
• Source Region (ND) &
p+ Channel-stop implant
• Csw = C‟jswxj(W + 2 x LS)
• Total Capacitance:
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The MOSFET: Dynamic Behavior
Capacitive Device Model:
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The MOSFET: Dynamic Behavior
Source-Drain Resistance:
• RC – Contact Resistance.
• R□ – Sheet Resistance
(Constant = 20 ~ 100 Ω /□).
• Lowering R, Gain ID.
• Silicidation: Covering the drain and
source regions with low-resistivity
materials (Titanium/Tungsten).
(R□ = 1 ~ 4 Ω /□).
• „W‟ should be larger.
• Careful Layout is necessary.
EC7651/EC8651/VE7103/NE7081 - EK. 38
The MOSFET: Dynamic Behavior
Problem:
Consider an NMOS transistor with the following parameters:
tox = 6nm, L = 0.24 µm, W = 0.36 µm, LD = LS = 0.625 µm,
CO = 3 x 10-10 F/m, Cjo = 2 x 10-3 F/m2, Cjsw0 = 2.75 x 10-10 F/m.
Determine the zero-bias value of all relevant capacitances.
(Assume: Ɛox = 3.97 x Ɛo = 3.97 x 8.854 x 10-12 F/m)
EC7651/EC8651/VE7103/NE7081 - EK. 39
The MOSFET: SECONDARY EFFECTS
Deep Sub-Micron Realm:
1. Threshold Variations
2. Hot-Carrier Effects
3. CMOS Latchup
1. Threshold Variations:
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The MOSFET: SECONDARY EFFECTS
2. Hot Carrier Effects:
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The MOSFET: SECONDARY EFFECTS
3. CMOS Latchup:
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The MOSFET: PROCESS VARIATIONS
Important Factors:
1. Variations in the process parameters (Threshold Voltage):
– Impurity Concentration Densities
– Oxide Thickness
– Diffusion depths
2. Variations in the Dimensions – (W/L ratio):
– Limited resolution in lithographic process
Uncorrelated Deviations:
• Circuit performance – transistor current.
• Threshold Voltage – Oxide thickness, substrate, poly silicon,
impurity level & surface charge.
• Process Transconductance – Mobility – Oxide thickness.
• W & L ratio by field oxide and poly-silicon definition –
Photolithographic process.
“Economic Dilemma for the Designer” – Ends in
Optimization with Simulations
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The MOSFET: PROCESS VARIATIONS
• Fast and Slow Device models
• Best (or Worst Cases) models
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The MOSFET: TECHNOLOGY SCALING
• Spectacular increase in integration density and computational
complexity.
• Advances in device manufacturing technology:
– Reduction in feature size.
EC7651/EC8651/VE7103/NE7081 - EK. 45
The MOSFET: TECHNOLOGY SCALING
Full Scaling (Constant Electrical Field Scaling)
• Voltages and Dimensions are scaled by same factor S.
• Goal: Keeping Electrical Field Patterns as Same.
• Advantages:
– Greater Device Density (Area)
– Higher Performance (Intrinsic Delay )
– Reduced Power Consumption (P)
• Ron : Constant since both Voltage and Currents are scaling down.
• Improved performance is solely due to Capacitance.
• Effects:
– Speed increases linearly
– Power scales down quadratically
::: Unsustainable Practically :::
EC7651/EC8651/VE7103/NE7081 - EK. 46
The MOSFET: TECHNOLOGY SCALING
Fixed-Voltage Scaling:
• Full Scaling is not feasible:
– To keep new devices
compatible with existing
components, voltages cannot
be scaled arbitrarily.
– Multiply supply voltages add
costs to the system
• Designers adhere to well-
defined standards for supply
voltages and signal levels.
• Higher Voltage level causes
Power Dissipation.
• Other effects:
– Hot-carrier effect
– Oxide breakdown ::: Unsustainable Practically :::
EC7651/EC8651/VE7103/NE7081 - EK. 47
The MOSFET: TECHNOLOGY SCALING
General Scaling:
• Supply voltages are not scaling as fast as the technology (Slide 47)
• Why not Full-Scaling?
(Because no convincing effect for keeping higher voltages)
– Voltages (Built-in Junc. Potential, Silicon Band-Gap) can‟t be
scaled.
– Scaling of VT is limited too. (Difficult to turn ON/OFF device)
• So independent voltage & dimensions scaling may be considered
• Dimensions by S & Voltages by U (For U = 1, this becomes
fixed-voltage scaling model).
• General-scaling model offers a performance scenario identical to
the full- and the fixed scaling, while its power dissipation lies
between the two models (for S > U > 1).
EC7651/EC8651/VE7103/NE7081 - EK. 48
The MOSFET: TECHNOLOGY SCALING
Scaling Scenarios:
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The MOSFET: TECHNOLOGY SCALING
Verifying the Model:
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The MOSFET: TECHNOLOGY SCALING
Verifying the Model:
FinFET Dual Gate
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The MOSFET: Summary
• MOSFET – Voltage Controlled Device
– Cut-off, Linear & Saturation
– Switch: On & Off Concepts
• Substantial Deviations:
– Velocity Saturation – Quadratic to Linear dependence of current to
voltage.
– Sub-Threshold Conduction – Device to conduct even in low voltages
(<VT)
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CMOS INVERTER
EC7651/EC8651/VE7103/NE7081 - EK. 53
Design Metrics
• Cost
– Complexity
– Area
• Integrity & robustness
– Steady-state (Static) response
• Performance
– Transient (Dynamic) response
• Energy efficiency
– Energy/Power consumption
EC7651/EC8651/VE7103/NE7081 - EK. 54
The Static CMOS inverter
EC7651/EC8651/VE7103/NE7081 - EK. 55
The Static CMOS inverter
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CMOS inverter - properties
• High noise margins
– Voltage swing is equal to supply voltage
• Ratio-less
– Logic levels doesn‟t depend on device sizes
• Low output impedance
– Direct path b/w Output and Supply/GND
• High input resistance
• Gate of MOS transistor is an insulator
• No direct path b/w Supply & GND
• Doesn‟t consume static power
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Voltage Transfer Characteristics of PMOS
EC7651/EC8651/VE7103/NE7081 - EK. 58
Load curves for NMOS & PMOS
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VTC of CMOS inverter
EC7651/EC8651/VE7103/NE7081 - EK. 60
Transient Response
• CL
– (Drain Capa. + I/O wire
Capa.)
• Td α RpCL
• Faster Gate:
Low Rp/Small CL
EC7651/EC8651/VE7103/NE7081 - EK. 61
CMOS inverter: Static Behavior
• Switching Threshold
• Noise Margins
• Device Variations
• Scaling the Supply Voltage
EC7651/EC8651/VE7103/NE7081 - EK. 62
Switching threshold
• Switching threshold, Vm : Vin = Vout.
• At the intersection, VGS = VDS.
• By equating the current through transistors in velocity
saturation, (neglecting channel length modulation),
EC7651/EC8651/VE7103/NE7081 - EK. 64
Switching threshold
• VM for an inverter with long-channel devices and low
supply voltage,
– Non-occurrence of velocity saturation.
EC7651/EC8651/VE7103/NE7081 - EK. 65
Switching threshold (Problem)
• On deriving the ratio of sizes of PMOS and NMOS, for a
0.25µm process, assuming the supply voltage of 2.5V for
the following parameters.
VTn = 0.43, VTp = -0.4, kn‟ = 115 x 10-6A/V2,
kp‟ = -30x10-6A/V2, VDSATn = 0.63V and VDSATp = -1V.
Ans: 3.5
EC7651/EC8651/VE7103/NE7081 - EK. 66
Switching Threshold vs. PMOS/NMOS ratio
Inference 1:
VM is relatively
insensitive to device
size ratio.
3 – 1.22V
2.5 – 1.18V
2 – 1.13V
Inference 2:
Shifting the transient
region of VTC.
(Asymmetrical VTC)
EC7651/EC8651/VE7103/NE7081 - EK. 67
Demonstration for Inference 2:
EC7651/EC8651/VE7103/NE7081 - EK. 68
Noise Margin
• g = dVout/dVin.
• Piece wise linear approx.
• Width of the transition region VIL
to VIH.
EC7651/EC8651/VE7103/NE7081 - EK. 69
Noise Margin
• For determining mid-point of gain:
• Considering current equations (including velocity saturation &
channel length effects),
EC7651/EC8651/VE7103/NE7081 - EK. 71
Scaling supply voltage
• Technology Scaling: Forces supply voltage to reduce at rates
similar to device dimensions but rather VT is constant.
• From equation, Gain increases
as supply voltage reduces.
• For fixed „r‟, VM is proportional
to VDD.
• Plotting VTC with different supply voltages:
For 0.5 to 2.5V:
– Width of transition region is 10% wider for 0.5V.
– Width of transition region is 17% wider for 2.5V.
For 50mV to 200mV:
– Transistor VT is same.
– Still VTC is obtained, even though supply voltage is not enough
to turn the device ON.
– Subthreshold conduction provides this VTC. (On & Off)
EC7651/EC8651/VE7103/NE7081 - EK. 72
Scaling supply voltage
• Device scaling reduces supply voltage
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CMOS inverter: Dynamic Behavior
EC7651/EC8651/VE7103/NE7081 - EK. 74
Computing the Capacitances
Parasitic capacitances, influencing the transient
behavior of the cascaded inverter pair
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Computing the Capacitances
• Load Capacitance CL breaks down into
following components:
– Gate Drain capacitance Cgd12
– Diffusion capacitances
• Cdb1
• Cdb2
– Wiring capacitance Cw
– Gate capacitance of fanout
• Cg3
• Cg4
EC7651/EC8651/VE7103/NE7081 - EK. 76
Gate Drain capacitance Cgd12
• M1 & M2 are either in cut-off or saturation mode in first half
cycle: Contribution is only by Overlap cap. Of M1 and M2.
• Channel cap. has no role (as it is between G & Bulk or G & S).
• Miller effect:
– During transitions, terminals moving in opp. directions
– Therefore, Capacitor voltage = 2 * Output swing
– Cgd = 2 CGDOW.
EC7651/EC8651/VE7103/NE7081 - EK. 77
Diffusion capacitances Cdb1 & Cdb2
• Due to reverse biased pn junction (Drain & Bulk)
– Non-linear capacitor (depends on applied voltage)
• To linearize it, a multiplication factor Keq is used,
– Cj0 = Junc. Capacitance under zero-bias.
EC7651/EC8651/VE7103/NE7081 - EK. 78
Diffusion capacitances Cdb1 & Cdb2 : Problem
Keq for 2.5-V CMOS inverter:
EC7651/EC8651/VE7103/NE7081 - EK. 80
Wiring capacitance Cw
• Wiring capacitance depends on
– Length
– Width
• Function of
– Distance of fanout from the driving gate
– Number of fanout gates
• Growing in importance with scaling of the technology
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Gate capacitance of fanout Cg3 & Cg3
• Fanout capacitances equal to total gate capacitances
• First approximation:
– Assumption: All the components of Gate capacitances are
connected between Vout and GND (or VDD).
– Ignores miller effect on gate-drain capacitances.
– This has a relatively minor effect on the accuracy, since we
can safely assume that the connecting gate does not switch
before the 50% point is reached, and Vout2, therefore,
remains constant in the interval of interest
EC7651/EC8651/VE7103/NE7081 - EK. 82
Gate capacitance of fanout Cg3 & Cg3
• Second approximation
– Channel capacitance is constant not exactly as previous
discussions.
– Channel capacitance varies from 2/3 WLCox (Saturation) to
WLCox (Cut-off / Linear).
– Drop in transition.
– One transistor is Linear
– And one in Saturation
– 10% of error in ignoring above discussions.
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An Example with Layout of two chained minimum size inverters:
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Components of CL:
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Propagation Delay: First Order Analysis
• By integrating capacitor (dis)charge current,
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Propagation Delay: First Order Analysis
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Propagation Delay: First Order Analysis
• Optimization of Gate delay:
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Techniques to minimize propagation delay:
• Reduce CL:
– Internal diffusion capacitance + interconnect capacitance +
fanout capacitance
– Careful Layout & Small drain diffusion area
• Increase W/L ratio:
– Most powerful & effective performance optimization
– Avoid self-loading
– Reduces speed !
• Increase VDD:
– Reduces delay
– Trade off b/w energy dissipation & performance
– Avoid reliability concerns
• Oxide breakdown & hot-electron effects
EC7651/EC8651/VE7103/NE7081 - EK. 89
Propagation Delay: Design Perspective
• NMOS to PMOS ratio
• Sizing Inverters
• Sizing a Chain of Inverters
• Right number of stages
• Rise-Fall time of the input
• Delay in Interconnections
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NMOS to PMOS ratio:
• Widened PMOS to match Resistance
• Ratio of 3 ~ 3.5
• To get symmetric VTC & Equal transition delays
• But minimizing overall propagation delay is not
possible considering symmetry & noise margins
– Widening PMOS improves tpLH but degrades tpHL because
of parasitic capacitance.
• Considering two cascaded CMOS inverters,
• If β = (W/L)p/(W/L)n
{Cdp1 = Cdn1; Cgp2 = Cgn2}
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NMOS to PMOS ratio:
• Sub. CL in tp,
• r = Reqp/Reqn
• Partial diff wrt β,
• If (Cdn1+Cdn2)>>Cw, β = √r
• Smaller devices yield a faster design at the expense of
symmetry & noise margin
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Sizing Inverters
• Symmetrical inverter
– Rise and fall delays are identical in PMOS & NMOS
• Load capacitance: CL = Cint + Cext
• Propagation delay,
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Sizing Inverters
• Conclusions:
• Intrinsic delay is independent of the sizing of the gate
– Is determined only by technology & inverter layout
• Maximizing S Maximum Gain
– Eliminating impact of external load & reducing delay to
intrinsic.
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Sizing a Chain of Inverters
• Sizing of a gate when embedded in a real
environment
• Relationship b/w gate capacitance & intrinsic o/p C.
• γ = proportionality factor
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Sizing a Chain of Inverters
• Delay of jth inverter,
• Total delay:
• F = Effective fan-out
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Choosing the right number of stages
• If no. of stages are high, intrinsic delays dominants
– First component
• If no. of stages are low, effective fan-out dominants
– Second component
• Differentiating minimum delay expression,
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Choosing the right number of stages
• Higher values of fan-out:
– Doesn‟t effect the delay
– Reduces number of buffer stages
– Reduces implementation area
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Rise-Fall time of the Input signal
• All the expressions derived assuming
– Abrupt change in input signal
– Only one device is in on state
• In reality,
– Input changes gradually or temporarily
– Devices conduct simultaneously
– This affects current for (dis)charging and impacts tp
Propagation Delay
vs.
Slope of input signal
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Rise-Fall time of the Input signal
• Revised propagation delay:
Robustness:
Symmetrical VTC
Full logic swing
High noise margin Most Contemporary Design
Low power consumption:
In steady state operation
• So, EC = EVDD/2
• Remaining power – Dissipated in the device.
• Dissipation doesn‟t depend on size.
• Advances on Technology
– Higher values of f01
– Total capacitance CL increases as gate count increases
• Switching activity f01
– Easily computed for one inverter
– Complex for higher-order gates and circuits
– Depends on the input signal
Pdyn = CEFFVDD2f
CL Ipeak Ileak
Dominant Factor Kept within Bounds Ignorable @ present
α – Technology parameter
Taking Derivative
Average Power
(Over One Cycle)
Vin : 01
Vout : 10
Designing Combinational
Logic Gates in CMOS
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Introduction
Combinational Logic:
“Non-Regenerative circuits”
• At any point in time, output of the circuit is related to
its current input signals by some Boolean expression
• No intentional relationship between i/p & o/p
Sequential Logic:
“Regenerative circuits”
• Output is not only a function of current input data but
also previous values of input signals.
• Connecting (some) output intentionally to the input
• Sense of “Remembering” the history
• Combinational Logic + Module to hold the state
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Introduction
• Function: Combinational Logic
– Numerous Logic Styles
• Emphasis:
– Application depended
• Metrics:
– Area Sequential Logic
– Speed
– Energy
– Power
– Reliability
– Sensitivity to noise
NMOS in Series:
NMOS in Parallel:
Steps:
1. Derive pull down network
i. Series NMOS = AND
ii. Parallel NMOS = OR
2. Use duality to derive pull up network
[Break PDN into subnets (SNs)]
1. No. of transistors
• 2N transistors for N input gate
• Increase in overall capacitance
• L H delay increases with fan-in, when
capacitance increases as resistance remains
unchanged
2. Propagation delay
• Series connection of transistors causes additional
slow-down
• Quadratic delay (H L)
I. Transistor sizing
II. Progressive transistor sizing
III. Input Reordering
IV. Logic Restructuring
• Consider,
• Modified to,
• Power consumption,
CLVDD2f01
• Switching activity:
– Static Component: Function of topology of logic network
– Dynamic component: Timing behavior
Transition Probability
N0 : Number of Zero entries α01 ?
For 2 i/p NOR
N1 : Number of One entries For 2 i/p NAND
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Power Consumption in C-CMOS
Signal Statistics:
• In 2 input NOR gate: For uncorrelated inputs,
• Power:
Advantages:
• Provides rail-to-rail swing
• Static dissipation is eliminated
• No simultaneous NMOS/load devices conduct
Disadvantages:
• Power dissipation due to cross-over currents
• Transition period (both are simultaneously ON)
• Increasing complexity
• Advantages:
– No. of Transistors: 4 (2 + 2 for inverting B)
– Using C-CMOS: 6 transistors
Solutions:
1. Level Restoration
2. Multiple-threshold transistors
3. Transmission gate logic
• Basic Principles
• Speed and Power dissipation
• Signal integrity issues
• Cascading dynamic gates
Example:
• Precharge time:
– Time takes to charge CL
– Logic in the gate cannot be utilized
– Dead zone !! (Other functions can be used)
1. Charge leakage
2. Charge sharing
3. Capacitive coupling
4. Clock feedthrough
1. Charge Leakage:
• Operation of dynamic gate
relies on dynamic storage of
output value on capacitor
• If PDN is off, o/p should
remain at pre-charged state
of VDD.
• But due to leakage currents,
charge gradually leaks
Designing Sequential
Logic Circuits in CMOS
EC7651/EC8651/VE7103/NE7081 - EK. 212
Schema
Introduction
Static Latches and Registers
◦ Bistability principle
◦ Static SR Flip-Flops
◦ Multiplexer based Latches
◦ Master-Slave Edge-Triggered Register
◦ Low-Voltage Static Latches
Dynamic Latches and Registers
◦ Dynamic Transmission-Gate Edge-Triggered Registers
◦ C2MOS – A Clock-Skew Insensitive Approach
◦ True Single-Phase Clocked Register (TSPCR)
Pipelining: An approach to Optimize Sequential Circuits
Perspective: Choosing a Clocking Strategy
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Introduction
Combinational Logic:
◦ O/P is the function current i/p values
◦ It doesn’t remembers history of inputs
Sequential Logic:
◦ O/P is not only the function of current i/p values but
also upon preceding i/p values
◦ Remembers some of the history – requires memory.
Example: Finite State Machine
Flip-flops
Rotated to
accentuate
Vi2 = Vo1
Meta-stable Stable
Point: Points:
C A&B
It is must
to have
W/L ratio
of M5 & M6
larger than
3 to switch
SR FF.
iii.Delay of the
transient solely
determined by
M3-M4.
iv.Delay:
tpQ < tpQbar
Setup time:
◦ Time before the rising edge of the CLK that the input data
D must be valid.
◦ i.e., How long D is stable such that QM samples the
value?
◦ D has to propagate through I1, T1, I3 & I2 (To ensure
node voltages on both terminal of T2 are same) before
rising edge of the CLK.
◦ Therefore, Setup time = [(3 X tpd_inv) + tpd_tx].
Hold time:
◦ Time that the input is stable after rising edge of the CLK
◦ T1 turns off when CLK is high & any changes in D after
CLK going high are not seen by input .
◦ Therefore, Hold time = 0.
Propagation delay:
◦ Time takes for QM to propagate to Q
◦ Since, delay of I2 is included in setup time, I4 is valid
before rising edge of the clock.
◦ Therefore, delay tc-q is delay through T3 & I6.
◦ tc-q = tpd_tx + tpd_inv.
Timing Analysis:
◦ Case 1:
Setup time = 210ps
Correct value of D is sampled; Q remains at VDD.
◦ Case 2:
Setup time = 200ps
Incorrect value propagates, Q transitions to 0.
QM goes to high when output of I2 starts to fall.
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Static Latches and Registers
Timing Properties of Master-Slave Edge-Triggered Registers:
Setup time analysis:
i. Input transition at
least one setup
time before rising
edge of CLK.
iii.Tc-q(LH) = 160 ps
iv.Tc-q(HL) = 180 ps
When CLK = 0:
i. M1, M4, M9, M10 are ON,
sampling D to node Y.
When CLK = 0:
i. Both inverters are disabled,
latch is in hold mode.
Logic Latch
CLK = 0 Precharge Hold
CLK = 1 Evaluate Evaluate
Logic Latch
CLK = 0 Evaluate Evaluate
CLK = 1 Precharge Hold
Testing and
Implementation Strategies
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PART – A
• Introduction
• Test Procedure
• Design for Testability
– Issues in DFT
– Ad Hoc testing
– Scan based test
– Boundary Scan design
– Built-in Self-Test (BIST)
• Test pattern generation
– Fault Models
– Automatic Test-Pattern Generation (ATPG)
– Fault Simulation
• Combinational block:
– For N input, 2N patterns of input
– If single pattern takes 1μS, total
module test will take 1S.
• Sequential block:
– 2N+M input patterns
– If M = 10, total module will take
16 minutes
– If M = 50 (in modern μPs), take
billion years.
• Test Procedure:
i. An excitation vector is entered through Scan In.
ii. Excitation is applied and propagated.
iii. Result is shifted out through Scan Out.
• Overhead Reduction
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Design for Testability
Scan-based Test:
Register extended with serial scan:
Test
Low: Normal
High: Test Mode
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Design for Testability
Boundary Scan design:
• Problem? Testing printed circuits boards are easy.
– Abundant availability of test points
– Testing every pin in the package
– Recently, Controllability & Observability is reduced.
Boundary Scan:
• I/O pins of all
components are
connected.
• Normal Mode: I/O
operation
• Test Mode: Vectors
can be scanned in and
out.
Stimulus Generator:
a) Exhaustive approach:
• Test length is 2N, where N is number of inputs.
• All detectable faults will be detected.
• Ex.: N-bit counter
b) Random approach:
• Randomly chosen subset of 2N input patterns.
• Ex.: Linear Feedback Shift Register (LFSR)
• Repetition after 2N-1 states.