New digital phase meter concept and its

application
Cite as: Review of Scientific Instruments 68, 1894 (1997); https://doi.org/10.1063/1.1147963
Submitted: 21 August 1996 . Accepted: 06 January 1997 . Published Online: 04 June 1998

H. P. Lio, and M. S. Young

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Review of Scientific Instruments 68, 1894 (1997); https://doi.org/10.1063/1.1147963 68, 1894

© 1997 American Institute of Physics.

New digital phase meter concept and its application
H. P. Lio and M. S. Younga)
Department of Electrical Engineering, National Cheng-Kung University, 70101 Tainan, Taiwan,
Republic of China
~Received 21 August 1996; accepted for publication 6 January 1997!
A new concept for digital phase meters, which in practical embodiment provides most of the
commonly desired performance features such as wide bandwidth, high resolution, high speed
measurement, etc., is presented. This meter emulates a Vernier caliper and inherits its
characteristics. Phase difference may be measured in any period of the measured signals. In the
basic theory, two phase-locked-loop circuits are used as frequency multipliers which divide each
period of the input signals into multiple equal time slots, thereby emulating the divisions of space
inscribed on the scales of a caliper. A simple ‘‘pseudophase detector’’ made of a D-type flip–flop
is used to compare the location of the time slots on both of the scales, just as we use the Vernier
caliper. The new meter’s resolution remains very high at both very high input frequencies and
output data rates and while maintaining a wide input bandwidth; a resolution of 100 at 10 MHz input
and 10 MHz output is easily attainable with off-the-shelf components requiring no clock rate higher
than 100 MHz. In addition to a discussion of the theory, experimental results of a test embodiment
are presented. Using a 10 MHz clock, a rather crude test circuit could detect a delay time of 400 ns
between an original and delayed 40 kHz signal, equivalent to a resolution of ;65 000. © 1997
American Institute of Physics. @S0034-6748~97!01904-7#

I. INTRODUCTION An ‘‘accumulated’’ type of phase meter, modified from the

Phase measurement is a basic technique like the mea-
surements of voltage, current, and frequency. Presently,
many analog physical signals are modulated as phase shift.1
Engineers have also used the phase modulation technique for
information exchange within or between computer networks
or communication systems. During the demodulation step,
the phase measurement technique determines the quality and
accuracy of the modulated information. Scientists have de-
signed various digital phase meters to meet the requirements
of different applications.2–5 However, most contemporary
digital phase meters have a limited number of outstanding
characteristics. When scientists choose a deficient phase
meter for their experiments, they have to focus on a limited
set of what they guess to be the important parts of the data
and sacrifice other details in the experiment. If available
digital phase meters had sufficiently improved characteris-
tics, more and improved data would result from their experi-
ments.
Among digital phase meters, the ‘‘conventional’’ digital
phase meter, made from a gated counter as shown in Fig.
1~a!, is used to measure the phase difference in each signal
period.6 One serious disadvantage of this method is the need
for an ultrahigh frequency counter clock when we simulta-
neously require both high resolution and high signal fre-
quency. The product of the reciprocal of resolution and the
signal frequency equals the required frequency of the counter
clock, but practical application is limited by the speed of
digital circuitry. With reference to the example given above,
a conventional meter at 10 MHz input and 1/100 resolution
would require a 10 GHz clock, compared to the VIPM ~Ver-
nier inspired phase meter! requirement of a 100 MHz clock.
a!
To whom correspondence should be addressed.
‘‘conventional’’ one as shown in Fig. 1~b!, was designed to
accumulate the counts in N periods to improve the
resolution.7 For N times improvement of resolution, it has to
waste N signal periods to wait for only one average phase
difference data, thus limiting output data rate. The ‘‘hetero-
dyne’’ phase meter, shown in Fig. 1~c!, was developed to
measure high-frequency signals with high resolution.8 In this
kind of phase meter, a local oscillator signal is mixed with
both input signals, generating two low beat-frequency sig-
nals ~equal to the difference between signal frequency and
local oscillator frequency! which then are low-pass filtered.
Next, a normal phase measurement circuit for low-frequency
signals is added to compare the output of the two low pass
filters ~LPFs!. Because of the signal frequency reduction
characteristic, the heterodyne phase meter is usually used in
applications requiring ultrahigh frequency as in the GHz
range, but then conventionally outputs data in the range of
perhaps a few words per second, much less than that from
the meters described previously.
Digital phase meters based on the digital signal process-
ing ~DSP! technique or other special methods have also been
developed.4,9–12 These meters usually have high resolution
for phase measurement but a narrow input signal frequency
band. The performance of the microprocessor together with
the resolution and speed of the analog to digital ~AD! con-
verter severely confine input bandwidth. Thus, all these de-
vices have specific problems that limit their capacities for
phase measurement.
In many applications, a digital phase meter with com-
plete capabilities is needed, capabilities such as high resolu-
tion, wide bandwidth, high speed, frequency invariance, etc.
For example, if a single phase meter were capable of both
high speed measurement and high resolution, it could mea-
sure all the information distributed around a fusion plasma or

1894 Rev. Sci. Instrum. 68 (4), April 1997 0034-6748/97/68(4)/1894/8/$10.00 © 1997 American Institute of Physics
FIG. 1. ~a! In ‘‘conventional’’ digital phase meters, phase difference in each period is measured by counting a gate and a period. The error is 61 count. ~b!
In modified conventional digital phase meters, phase difference in N periods is measured by counting N gates and N periods. Error is reduced to 61/N count.
~c! Block diagram of typical heterodyne phase meter. Ultrahigh frequency input signals mixed with local oscillator produce low frequency beat signals with
conserved phase relations.

a fluid with a multiplexer in real time. Measured data could
then be immediately reconstructed into two-dimensional in-
formation. Because of the need to analyze data with a digital
computer, only digital phase meters are discussed in this ar-
ticle.
In this article, a new concept for digital phase meters is
presented. This concept is based on the emulation of the
Vernier caliper and provides a meter that can meet most of
the performance requirements mentioned above. A meter de-
signed in accordance with this concept uses two frequency
multipliers, as opposed to the ‘‘conventional’’ meter’s single
multiplier. Using two multipliers allows us to magnify the
resolution to nearly the square of a conventional meter’s
resolution. And the Vernier inspired phase meter ~VIPM!
still measures the phase difference once in a period as the
conventional meter does.
Practical VIPM designs could be applied in widespread
fields. A typical application would be an echo detector for
sonar or radar, and the experimental results of such systems
are excellent.
II. THEORY
The VIPM concept for a high resolution, fast speed,
wide-band, frequency-invariant digital phase meter is based
on an emulation of that traditional tool, the ‘‘Vernier cali-
per.’’ VIPM theory may be understood by a study of the
construction of this traditional and highly successful device.
The Vernier caliper theory itself is just a typical application
of the Theory of Numbers. In the VIPM, the function of the
Vernier caliper in the space domain is simply transferred into
the time domain.
For purposes of explanation, the basic construction and
operation of the Vernier caliper is described as follows. A
Vernier caliper is composed of two scales, the main scale
and the movable Vernier scale as shown in Fig. 2. The unit
length L ~L usually equals to the length of Vernier scale! are
divided into equal segments of physical length by inscribing
lines into the metal of the caliper scales. If unit length L on
the Vernier scale is further divided into N divisions and on
the main scale into M divisions ~where M 5 cN 2 1, c is a
positive integer and c52, in Fig. 2!, it can be found that the
smallest physical length measurable with the caliper is

Rev. Sci. Instrum., Vol. 68, No. 4, April 1997 Phase meter 1895

FIG. 2. Vernier caliper: measured length Y 5216/1014/20052.62 cm is
read out with resolution 0.05 mm, unit L539 mm, M 539, N520, p52,
q56, r54. Measured in inches, the length Y 5110/1614/12851.0725 in.,
read out with resolution 1/128 in.; unit L515/16 in., M 515, N58, p51,
q50, r54, and the constant c52.
L/ @ N(cN 2 1) # long. Transforming from physical distance to
temporal length of wave period degrees, VIPM sets L equal
to the wave period of the signal in question, and the caliper
divisions are replaced with equal time slots within the pe-
riod. Cutting the periods into multiple equal time slots may
be easily accomplished using a phase-locked-loop ~PLL! cir-
cuit. Except for the building materials and the domains being
measured, the difference between a real Vernier caliper and
the VIPM is only the measurement range. With a real caliper,
the user may measure a physical length less or more than the
unit length L, while with VIPM, the measured phase differ-
ence will always be less than a period. Frequency multiply-
ing PLL circuits generate the dividing lines ‘‘inscribed’’ on
VIPM’s two temporal scales, one scale for each input signal.
After thus emulating the caliper hardware, provision
must be made for operating and reading the hardware. A
human operator uses hands and eyes to operate a caliper,
whereas all the operations in the new meter are done auto-
matically by electrical circuit. The basic operation of the
Vernier caliper contains three procedures as follows:
~1! As with a mechanical Vernier caliper, it is necessary
to locate the left-hand side of the target next to the zero point
of the main scale. The resulting location of the right-hand
side of the target in terms of the main scale indicates the
most significant part of the measured result. This is similar to
the operation of a normal ruler.
~2! Next, the Vernier scale is moved to the right until its
zero point is aligned with the right-hand side of the target.
~3! The lines on the Vernier scale are compared with
those on the main scale. It is necessary to find the position
1896 Rev. Sci. Instrum., Vol. 68, No. 4, April 1997
where the lines on both scales are the closest, which is to say
where they change from lagging to leading. An example of
this position is shown in the zoomed circle in Fig. 2. The
reading on Vernier scale at this position represents the least
significant part of the measured result.
If the lengths L on both scales are divided into M ~on the
main scale! and N ~on the Vernier scale! divisions, a given
measured length Y may be represented as
Y 5p1L S q
1
r
1
M MN MN
t
, D ~1!
where M 5cN21,0<p,0 < q , M ,0 < r , N,0 < t , 1.
In Eq. ~1!, p, q, and r are all integers, and t is a real
number. On a mechanical Vernier caliper, the value p repre-
sents the integer part of the real measured length out of the
unit length L ~see Fig. 2!, i.e., p52 in the value 2.62 cm. In
VIPM theory, because L is set to period, and target ~phase
difference! value is always less than 1 period, the value of
P is always zero. The value of q and r are read from the
main scale and the Vernier scale, respectively. The value t is
the residual part of the length Y that is less than the resolu-
tion of the Vernier caliper. After correct operation, the posi-
tion of the lines on the main scale is
q1s
Y m 5 p1L , ~2!
M
where 0<s and s is an integer.
The position of the lines on the Vernier scale is
m
Y v 5Y 1L , ~3!
N
where m 5 0,1,...,N, and m is an integer.
The difference of Y m and Y v between the lines on both
scales is
S D
r t m s
D5Y v 2Y m 5L 1 1 2
MN MN N M
S D
r1m ~ cN21 ! 2sN t
5L 1 . ~4!
N ~ cN21 ! MN
The smallest D equals Lt/M N when m 5 r and s 5 cr. This
proves that the user can get value r by locating the two
closest lines or, more usefully for VIPM, the lag/lead change
between the two scales. If we compare the other lines with
m 5 k and s 5 ck ~where k is a positive integer!, we find the
interesting fact that Eq. ~4! becomes
r2k1t
D5L , ~5!
MN
when k . r,D,0 and k , r,D . 0. From observation, the dif-
ference between the lines, D, is not usually zero but is rather
some positive or negative value. A circuit like the proposed
phase detector can emulate procedure ~3!, outputting a low/
high state change as the lag/lead relation becomes a lead/lag
relation. From the above discussion regarding Vernier cali-
pers, it can be seen that we can measure a given length Y by
using the following equation:
Phase meter
FIG. 3. Original VIPM prototype contains two frequency multipliers for
dividing signal periods into multiple time slots, one pseudodetector for com-
paring time slots, and two latches for storing phase difference.
FIG. 4. Timings of test points in block diagram.

Y 5 p1L S q
1
M MN
r
. D quencies. Two digital counters in this part are used to count
the positions of the time slots in the base signals. The clocks
Values p and q can be read on the main scale and r can be for these counters are the main clock and the Vernier clock.
read on the Vernier scale. This result also proves that the The most significant word ~MSW! of the measured value is
resolution equals 1/M N. read in almost the same as in a conventional phase meter.6
~2! The second part of the concept requires locating the
position of the closest lines ~lag/lead change point!. A
III. SYSTEM DESIGN ‘‘pseudo’’ phase detector is used to compare the phase be-
A. Principle of the phase meter tween the main clock and Vernier clock, which is to say the
relative positions of the slots on both scales. The term
Electronic instruments which accord with the description
‘‘pseudo’’ comes from the fact that phase detection is done
in the theory section may be designed to measure phase dif-
between main clock and Vernier clock signals instead of
ference or time difference. To avoid confusion, the term
base signals. An output level change from the pseudophase
‘‘base signal~s!’’ will be used for the signal pairs undergoing
detector acts as a switch signal for the timing circuit in the
phase comparison. A block diagram of the VIPM is shown in
Vernier scale counter to get the least significant word ~LSW!.
Fig. 3. Timings corresponding to the points in the block dia-
For designs using c51, a single D-type flip–flop is the best
gram are shown in Fig. 4. The proposed concept contains
component that we have found.
three basic requirements and the following description sum-
~3! The third part requires translating the comparison
marizes these requirements.
into recorded and useful data. Maximum value for the signal
~1! The first part of the concept requires emulation of the
period as well as the measured difference value are both
Vernier caliper’s hardware and operation procedures ~1! and
necessary for phase ‘‘percentage’’ computation. Two edge-
~2!. The basic VIPM circuit in the block diagram uses two
triggered registers are used to latch the MSW and LSW of
PLL frequency multipliers and is a suitable circuit, but other
the measured value. The measured value will be MSW3
circuits having the following features can do this job.
N1LSW. The maximum value of the measured value is M
There must be two digital clock sources whose fre-
3 N, or equivalent to one signal period, since phase value is
quency are M and N times the base signal frequencies; they
always less than one period. Data stored in the registers are
generate the equal time slots ‘‘inscribed’’ on the two scales.
transferred to a suitable computation module for storage and
These clocks are called ‘‘main clock’’ for the main scale and
or conversion into equivalent phase in degrees or periods.
‘‘Vernier clock’’ for the Vernier scale. The main clock and
Vernier clock must be kept synchronous with their respective
B. Circuit design of the application
base signals. This synchronization implies, in main and Ver-
nier slot relations, the duplication of the phase or time dif- Our experiments have shown that the accuracy of the
ference between base signals. The constant c is given a value two PLL multipliers is a crucial factor. The individual insta-
of 1 in order to minimize the main and Vernier clock fre- bilities of their outputs are seriously compounded when they

Rev. Sci. Instrum., Vol. 68, No. 4, April 1997 Phase meter 1897

FIG. 5. In modified VIPM, frequency divider replaces frequency multiplier.
Oscillator provides main scale time slots ~base signal A!. Oscillator output is
also divided to generate echo pulse output which returns as phase-delayed
base signal B, controlled experimental delay produced by external digital
delay element. This modified prototype dramatically reduces damping effect
from dual PLL multipliers.
interact in the phase detector. Our initial test embodiment of
the basic multiplier/multiplier ~the circuit in main/Vernier
scale! circuit used inexpensive and relatively unstable VCOs
and final circuit accuracy thereby suffered from unacceptable
levels of instability. Results were, however, instructive and
showed that low pass filtering in the PLL feedback loops was
especially important for stability with the ICs we were using.
We are redesigning this test embodiment for maximized sta-
bility by using voltage controlled crystal oscillator ~VCXO!
PLL with better LPF and related components. Experimental
results from this pending embodiment will be presented in a
subsequent paper. If results from these pending experiments
are encouraging, alternative LPF such as digital LPF will be
considered, along with total integration on a single chip, for
maximum stability.
Different architectures may be produced from the new
concept. To demonstrate a practical and well-performing em-
bodiment, we present here a multiplier/divider configuration.
The multiplier/multiplier PLL error amplification disappears
in this configuration. A quality system of this VIPM varia-
tion can be easily embodied using low grade components.
An echo detector is a suitable application for this sort of
system, and thus a block diagram for a VIPM echo detector
is shown in Fig. 5, as was prepared for experiment. Timing
and applied theory are the same as in the principles section.
The difference is the construction of the ‘‘main scale.’’
For the echo detector, the main scale contains a clock
source and a frequency divider. A stable crystal oscillator
1898 Rev. Sci. Instrum., Vol. 68, No. 4, April 1997
FIG. 6. Measured results of stable test. Curve is straight except for distor-
tion peaks at multiples of ~uncertain due to uncertain ripple counter module
number-see text! ;256 times measurement value. LPF delay times, modi-
fied by different capacitances, C1 and C2, generate different gain errors.
whose frequency is 10 MHz serves as the main clock and
provides base signal A. A divide-by-255 counter made of a
74HC4040 ~12-stage binary ripple counter! and 74LS688
~magnitude comparator! divides the main clock signal,
thereby generating the base signal A as precursor to base
signal B ~frequency ;40 kHz!. The counts of the counter are
fed into the MSW latch, which in conjunction with the 10
MHz signal ‘‘slots’’ emulate the main scale. The 40 kHz
signal is converted to sound, broadcast, returns with a delay
and becomes base signal B.
As in the example in the principles section, the ‘‘Vernier
scale’’ is provided slots by a PLL frequency multiplier. The
main components of the frequency multiplier are a
74HC4046 ~CMOS PLL chip! and a 74HC4040. The resis-
tance and capacitance of the voltage controlled oscillator
~VCO! are R158.2 kV ~connected to pin 11 of a DIP pack-
age!, R2515 kV ~connected to pin 12! and C512 nF. Phase
comparator II ~manufacturer’s name for one of the phase
detectors within the PLL! is chosen for the phase detector.
The resistance of the passive LPF is Ra54.7 kV ~connected
to pin 13, output of the phase comparator!, and Rb52 kV
~connected to pin 9, input of the VCO!. Capacitance of the
LPF is changed as shown in Figs. 6 and 7 for studying the
characteristics of the circuit. Only eight stages of the
74HC4040 counter are used for the factor 256 frequency
divider.
In our experimental echo detector, the time or phase dif-
ference between the base signals is generated by delaying the
output signal of the main scale and feeding it to the input of
Vernier scale.
Fast-series D-type flip–flop 74F74 is specifically chosen
as the pseudo-phase detector because slower flip–flops gave
Phase meter

FIG. 7. Results of dynamic test. When sudden change in phase difference
was less than 1.3°, then stabilization time was less than 10 signal periods.
LPF capacitance had strong effect in circuit accuracy. With suitably tuned
LPF and within the 1.3° limit, test circuit stabilization time was low enough
to monitor very rapid changes of phase difference with very high fidelity.
Experiments are in progress to extend the 1.3° limit and to improve LPF-
dependent fidelity.
dramatically inferior results in our tests. The registers are
made of two 74LS374. The tri-state outputs of the registers
are controlled by other circuits in the next section. From the
theoretical factors of the main scale ~M 5255! and the Ver-
nier scale ~N5256!, the resolution of this meter will be
1/~2553256! period ~less than 0.00551°!. The measured
value will be MSW32561LSW.
IV. TESTING THE SYSTEM
A. Tools for calibration and data acquisition
Several additional circuits were used in our experiments:
~1! An accurate time or phase difference generator was
developed. Although some articles have provided different
calibration methods,13 we found a simple single component
for generating an accurate and tiny delay time. We used a
programmable delay line ~DS1020! to create delay time in
steps of 2 ns, from 2 ns up to 510 ns. Delay times could be
quickly inserted between base signals by sending parallel
8-bit binary values into the delay line chip.
~2! A register with a delayed trigger signal is utilized for
dynamic tests, in which separate and sequential halves com-
plete one full procedure. Dissimilar phase differences are
measured in the former and latter halves of the complete
procedure. At the start of the second half, a sudden signal
change is introduced by writing into the programmable delay
line a binary value ~preset in the register! specifying the new
delay time.
~3! A phase-meter/computer interface card was designed
for data acquisition. Because the measured 16-bit data are
updated in the registers once a base signals period, current
Rev. Sci. Instrum., Vol. 68, No. 4, April 1997
data must be transferred to another buffer prior to the next
data. A 16-bit wide 32 K word RAM with an address gen-
erator automatically stores all the data measured during an
experiment. An interface circuit on the interface card con-
nects to the computer and makes the buffer available to the
computer.
B. Experimental procedure
Two methods are used to test the performance of an
application.
~1! A stable test with a constant phase difference: this
test is designed to check basic characteristics of measure-
ment such as accuracy, linearity, and resolution. During the
experiment, binary values suitable for use in the delay line
are generated in steps of 1 from 0 up to 255 by the computer
program which controls the experimental procedure. These
values are sequentially loaded into the delay line, thereby
generating a series of 256 phase differences. Delay value is
incremented by one binary digit after receiving 32 K signal
periods ~i.e., receiving 32 K signal pulses!. Results are auto-
matically recorded.
~2! A dynamic test with a sudden change of phase dif-
ference during the procedure: this test is designed to deter-
mine the response time. The experiment managing program
generates a series of binary values in steps of 1 from 1 to
255, incrementing this value after each 32 K signal periods.
These binary values are sent to the delay line. But, in con-
trast to the former experiment, the delay line is set at zero
delay for the first half of each group of 32 K signal pulses.
This is done by disabling the delay control buffer after each
increment in delay control value. Then, 16 K signal pulses
after each increment of delay value, the delay control value
buffer is enabled. Enabling the delay line abruptly like this
causes a sudden phase shift and therefore a sudden change in
the data measured by the phase meter. In this test, we mea-
sure the time from the enabling of the delay line to the time
that the measured data return to stability.
V. RESULTS AND DISCUSSIONS
Results of the stable test are shown in Fig. 6.
Programmed/theoretical phase differences are shown on the
X axis; two dimensions, delay time, and equivalent phase
difference are listed. Measured phase differences are shown
on the Y axis; two dimensions, measured raw data value, and
equivalent phase difference are listed. Results of the dynamic
test are shown in Fig. 7. Programmed/theoretical phase
change is shown on the X axis in both delay time and equiva-
lent phase difference. The time required for measured phase
value to become stable is shown on the Y axis. Here the
dimension is in the number of base signal periods.
Results will now be discussed in terms of the features
mentioned at the beginning of this article.
A. Accuracy
Even though an apparent offset and gain error accom-
pany the results, the curve of the measured phase difference
Phase meter 1899
versus the programmed one is still straight. A total offset of
;1.3° or 92 ns exists even though the theoretical phase dif-
ference is zero when the programmed value in the delay line
is zero. The major source of errors may be simply belong to
main and Vernier scale. Similar MSW offset and gain error
can be found in any papers on ‘‘conventional’’ phase meters,
because the total conventional system is almost the same as
VIPM main scale. However, the VIPM LSW error is com-
plex because of the interaction between both scales via the
pseudo-phase detector. The choice of the PLL’s on-board
type II comparator, an edged controlled phase detector, re-
duces the phase offset in the Vernier scale. When the PLL
circuit is in lock condition, the phase can be theoretically
kept zero between both input signals of the edged-controlled
phase comparator II. Phase adjustment circuits may be in-
serted into suitable nodes in both scales to help eliminate the
offset.
The gain observed in the results curve was greater than
we predicted. Ignoring some minor details, we can say that
the accumulated delay time from using a ripple counter and
magnitude comparator makes the exact module number of
the counter uncertain but larger than the one listed on the
data sheet. The delay time of the LPF also magnifies the
gain. In Fig. 6, it can be seen that using a larger capacitance
in the LPF resulted in higher gain measurements from the
meter. This was not anticipated when we designed the ex-
periment and, as discussed, has led to our ongoing work to
improve these parameters.
Additional factor in gain error: as a result of the ripple
counter and its unknown real module number in our experi-
mental hardware, the unknown real resolution of our experi-
mental results is higher than that theoretically calculated. For
this reason, the measured phase difference is proportional to
and larger than the programmed phase difference. In light of
our current experience, in order to reduce this gain error, we
would substitute a synchronous frequency counter for the
ripple counter.
However, the experimental results curves remain en-
couragingly linear and give us hope for future results that are
more than industrially useful, perhaps even approaching the-
oretical limits. We are additionally considering digital data
correction, thereby bypassing the problems of parts accuracy.
The pseudo-phase detector should be a fast switch to
latch the current count in the Vernier scale. A slow switch
would give more offset for the measurement of tiny phase
differences. Moreover, from our experimental experience, a
slow D-type flip–flop has poor noise rejection.
B. Regular noise
The curves in Fig. 6 show that distortion occurs in regu-
lar narrow regions located at multiples of 256-times-
measured ~raw data! value. This distortion seems character-
istic of any practical VIPM circuit. There are two main
reasons: the ‘‘nonmatched offset’’ between the two scales
and the damping effect of the PLL circuit.
An errorless ideal circuit derives its results by using the
equation ~MSW3256!1LSW. When the LSW changes
across 255 or 0, the MSW should increase or decrease at the
1900 Rev. Sci. Instrum., Vol. 68, No. 4, April 1997
same time. We call this phenomenon ‘‘match.’’ Unfortu-
nately, the practical offsets for the MSW and LSW are nor-
mally nonmatched. The resulting nonsimultaneous changes
of the LSW and MSW give an intense reading change at the
time of the ~approximately! 256 crossover. The height and
width of the peak distortion should be 256 ~in raw data! and
the nonmatch offset error. This distortion peak could be re-
duced by offset adjustment. This adjustment for peak reduc-
tion is different from the offset adjustment in the prior sec-
tion. The phase offsets in both scales should be adjusted in
the opposite direction in order to approach simultaneous
change for MSW and LSW.
Damping effects from the echo detector’s PLL circuit
Vernier scale also generate serious distortion. Replacing the
relatively unstable VCO with a more stable VCXO would
presumably decrease the damping effect and the width of the
distortion peak.
Several additional logic circuits could further reduce or
remove peak distortion, but optimal choice depends on the
purpose and practical circuit of the meter. A simple example
is presented for situations involving slow change of mea-
sured value: the unmatched offset is first suitably adjusted so
that the MSW increases or decreases when the LSW changes
across 128 instead of 255. Then, a circuit would increase or
decrease the subsequent MSW if the LSW changes from 0 to
255 or vice versa. The final raw data are then subtracted by
the preset unmatched-offset 128. If the true absolute differ-
ence between successive measured raw data is less than 128,
with or without damping, simultaneous change of MSW and
LSW never happens. This arrangement avoids the distortion
peaks from the two causes listed above.
We will further discuss the various types of error correc-
tion and circuit stabilization, when ongoing experiments are
completed, in our next article.
C. High speed
In Fig. 7, there are three curves corresponding to differ-
ent capacitances of the passive LPF in the PLL. When the
phase change is less than 1.3° in curve C3, the circuit re-
quires less than 10 base signal periods for the measured
phase value to become stable. By comparison, an accumu-
lated type phase meter ~as mentioned in the Introduction!
with the same resolution and measured value stabilization
time of 10 base signal periods would require a 256 MHz
clock, or an internal frequency nearly 25 times that of the
admittedly crude VIPM used in our experiment.
The measurement stabilization speed depends primarily
on the configuration and the adjustment of the LPF in the
PLL. Details regarding LPF design have been presented in
many publications.
D. Bandwidth
In Eq. ~1!, the constant c is taken as one. One of the
advantages of this is the easy design of the pseudophase
detector. A more important objective, however, is to reduce
the frequencies of the main clock and Vernier clock. Reso-
lution of VIPM is equal to 1/N(N 2 1) signal period. Thus,
Phase meter
the frequency of the main clock and Vernier clock in a VIPM 1
M. S. Young and Y. C. Li, Rev. Sci. Instrum. 63, 5435 ~1992!.
2
approach is the mere square root of the clock frequency in a A. V. Ardenne, J. D. O’Sullivan, and A. D. Dianous, IEEE Trans Instrum.
Meas. IM-32, 370 ~1983!.
conventional meter of the same resolution. By using the new 3
M. S. Beg and M. S. J. Asghar, Int. J. Electron. 57, 767 ~1984!.
concept, even a low speed digital circuit can be used to build 4
A. Bertholds and R. Dandliker, Electron. Lett. 21, ~1985!.
a digital phase meter for wide-band base signals. 5
H. R. Kolslowski, Meas. Sci. Technol. 5, 307 ~1994!.
Theoretical analysis demonstrates that the VIPM concept 6
R. E. S. Abdel-Aal, Electronics 156 ~1981!.
is excellent. Initial tests demonstrate that practical embodi-
7
T. S. Rathore and L. S. Mombasawala, Proc. IEEE 72, 397 ~1984!.
8
A. Dziadowiec, M. Lescure, and J. Boucher, IEEE Trans Instrum. Meas.
ments of the new concept encouragingly or adequately fulfill
IM-33, 55 ~1984!.
theoretical expectations. Auxiliary circuits such as offset 9
K. M. Ibrahim and M. A. H. Abdul-Karim, IEEE Trans Instrum. Meas.
compensation need to be developed and added for practical IM-36, 711 ~1987!.
10
designs. Although mistakes in our initial test circuits and low S. M. Mahmud, A. Rusek, and S. Ganesan, IEEE Trans Instrum. Meas. 37,
quality components degraded our experimental results, these 374 ~1988!.
11
S. M. Mahmud, presented at the Instrumentation and Measurement Tech-
results still show that the VIPM approach to digital phase nology Conference, IEEE, 25 ~1989!.
meter design improved most of the performance features 12
S. M. Mahmud, IEEE Trans Instrum. Meas. 38, 954 ~1989!.
listed in the Introduction. 13
R. S. Turgel, IEEE Trans Instrum. Meas. IM-34, 509 ~1985!.

Rev. Sci. Instrum., Vol. 68, No. 4, April 1997 Phase meter 1901