Transactional Memory Architecture and Implementation

for IBM System z

Christian Jacobi, Timothy Slegel, Dan Greiner – IBM Systems and Technology Group

• IBM zEC12 – available since September 2012

• Transactional Execution (TX)

• Regions of code bounded by TBEGIN and TEND
• Supports nesting (flattened model)
• All or none of the instructions inside the TX complete
• Rollback of stores/registers if transaction aborts
• Transactional lock elision
@abort:
@abort:
TRANSACTION
TRANSACTION BEGIN
BEGIN IF
IF (count
(count << threshold)
threshold)
IF
IF LOCK!=0
LOCK!=0 THEN
THEN ABORT
ABORT retry
retry transaction
transaction
..
.. perform
perform critical
critical section
section ..
.. ELSE
ELSE
TRANSACTION
TRANSACTION END
END OBTAIN
OBTAIN LOCK
LOCK
..
.. perform
perform critical
critical section..
section..
RELEASE
RELEASE LOCK
LOCK

• Code optimization for compiler speculation

IF
IF (cond
(cond &&
&& C!=0)
C!=0) TRANSACTION
TRANSACTION BEGIN
BEGIN
A=B/C
A=B/C A=B/C
A=B/C ;;
;; aborts
aborts if
if C=0
C=0
STORE
STORE A,
A, mem
mem STORE
STORE A,mem
A,mem ;;
;; speculative
speculative store
store
ELSE
ELSE IF(!cond)
IF(!cond)
..
.. TABORT
TABORT
ENDIF
ENDIF TRANSECTION
TRANSECTION END
END zEC12 Implementation:
• L1-Data Cache tracks transactional state for each cache line
• Lock-free data structures
• TX-read bit set during execution
• More powerful than compare & swap type algorithms
• TX-dirty bit set during L1 write back
• We provide guaranteed transactions to simplify
• Gathering Store Cache buffers stores before L2
programming
• Dual-usage: reduce traffic to store-in L3
• 64 entries x 128 byte capacity
• Programming example:
• CAM compare for gathering
• Abort handling
• Clear pending stores from store queue
• Clear all TX stores from Gathering Store Cache
• Clear dirty cache lines from L1
• L1/L2 track XIs from L3 and compare against TX footprint
• XI-reject :“stiff-arm” other CPU to try finish transaction
• Abort transaction after XI-reject thresholds
• Elaborate mechanisms to guarantee eventual successful
completion of constrained transactions
• Reduce speculation, branch prediction, O-O-O for
uni-processor interference
• Random delays tailored to specific circumstances and
interlocks between processors for MP interference
• TBEGIN features: • Escalation controlled by millicode
• GPR save mask
• Authority controls for Access Registers and FPRs • New instruction that software can use to help handle normal
• Optional Transaction Diagnostic Block – contains debug TXs to increase likely-hood of success after an abort
information in the even the transaction aborts • Performance example:
• Optional program interrupt filtering controls

• Constrained Transactions
• Processor guarantees transaction will eventually
complete; no need for software fallback path
• Limitations (constraints) on types and number of
instructions and range of storage accesses permitted

• Software RAS and Debugging Features

• Break-point (PER) facilitation by allowing event to trigger
on TEND so debugger can resume break-points
• Under software control, processor can generate random
aborts for software testing
© 2012 IBM Corporation