Micro architecture of 8088/8086

EXECUTION UNIT BUS INTERFACE UNIT (BIU)

(EU) 16
AX 16
BX CS
CX DS
DX
ES
SI
DI SS
SP IP
BP
ADDRESS
MULTIPLEXED BUS GENERATION
& BUS
CONTROL

INSTRUCTION
OPERANDS

QUEUE
6 BYTES
ALU (8086)
4 BYTES
8 (8088)
FLAGS 1
 Software Model of the 8086/8088 μP
8088/8086 MPU 000016 External memory
Address space
IP 0000H
Code segment
CS (64 K bytes)
DS
SS Data segment
ES (64 K bytes) Input/
output
address
AH AL AX
Stack segment space
BH BL BX
CH CL CX (64 K bytes)
DH DL DX
FFFFH
SP
Extra segment
BP
(64 K bytes)
SI
DI
SR FFFF 16 2
Memory space
 Memory address space & data
organization
> 8088/8086 μP ■ Memory address space
supports 1 MB of 8088/8086 μP
external memory. FFFFF
> The memory space is FFFFE
FFFFD
organized as a FFFFC

consecutive addresses
over the range
00000H to FFFFFH 4
3
2
1
0
3
 Segment Registers & Memory
Segmentation
■ Active segments of memory FFFFFH

CS

SS
CS
SS
DS DS
ES
8088/8086 ES

00000H
4
 Need For Memory Segmentation
■ By segmentation, memory is divided into
four 64KB memory segments.
■ Due to segmentation, the 8086 μP only has
to work with 16 bit effective addresses to
access any location in the segment.
■ Hence 8086 only has to manipulate and
store 16-bit address components.
■ Due to memory segmentation 8086 μP can
be configured as a multi-user system with
time sharing mode.
5
 Need For Memory Segmentation
■ Each user can have distinct segments of
memory allotted.
■ Segmentation makes it easy to switch from
one user’s program to another user’s program.
■ Segmentation provides an upward
compatibility with 8-bit μP (8085).

6
 Instruction Pointer
■ Instruction Pointer (IP) register is a 16-
bit register that identifies the location
of the next word of instruction code to
be fetched from the current code
segment.
■ IP contains the offset of the next word
of instruction code.
■ The 20-bit physical address for the
next code is generated using CS & IP.
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 Data Registers
■ Four General purpose data registers
are:
■ Accumulator register, AX
■ Base register, BX
■ Count Register, CX
■ Data register, DX

8
 Data Registers
■ Dedicated register functions
Register Operations
AX Word multiply, word divide, word I/O
AL Byte multiply, Byte divide, Byte I/O,
translate, decimal arithmetic
AH Byte multiply, Byte divide
BX Translate
CX String operations, Loops
CL Variable shift and rotate
DX Word multiply, word divide, indirect I/O
9
 Pointer & Index Registers
■ Two pointer registers are: Stack Pointer (SP)
and Base Pointer (BP)
■ Two index registers are : Source Index (SI)
and Destination Index (DI)
■ The pointer and index registers store an
address known as offset address.
■ An offset address represents the displacement
of a storage location in memory from the
segment base address in a segment.
10
 Status Register
■ Status registers are also known as flags
registers.
■ Flag register is a 16-bit register and it
contains 9 flag bits.
■ The nine flags may be divided into six status
flags and three control flags.
■ Status flags indicates conditions that are
produced as the result of executing an
instruction.

11
 Status Register
■ Flag Register is as shown below:
O D I T S Z A P C
U U U U U U U
F F F F F F F F F

Overflow Flag Carry Flag

Direction Flag Parity Flag

Interrupt Flag Auxiliary Carry Flag

Trap Flag Zero Flag

Sign Flag

12
Generating a Memory Address

1 0
5 OFFSET VALUE OFFSET

000 SEGMENT
SEGMENT REGISTER
0 ADDRESS

ADDER

1 0
9 20 BIT PHYSICAL ADDRESS
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 Generating a Memory Address
■ Example 1.4
Calculate the values of each of the physical
addresses that follows. Assume all numbers
are hexadecimal numbers.
(a) 1000H:1234H
(b) 0100H:ABCDH
■ ans:10000H+1234H=11234H
■ ans: 01000H+ABCDH=0BBCDH

14
 Generating a Memory Address
■ Example 1.5
■ If the current values in the code segment
register and the instruction pointer are
0200h and 01ACh, respectively, what
physical address is used in the next
instruction fetch ?
■ Ans: CS=0200h, IP=01ACh

Physical address = CS:IP

02000h+01ACh=021ACh

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