2015 IEEE International Microwave and RF Conference (IMaRC)
Multi-Cascode Cell Design for Increased Broadband
Power 0.1μm GaAs pHEMT MMICs up to V-Band
Priya Shinghal, Christopher I. Duff, Robin Sloan,
MCS Group, School of EEE
The University of Manchester
Manchester, UK
priya.shinghal@postgrad.manchester.ac.uk
Abstract— A comparative analysis of the DC and RF
performance between single and multi-cascode cells for high
frequencies (to V-band) and higher power MMIC operation is
presented. This paper compares the power capabilities of a 0.1
μm GaAs pHEMT 2x25 μm single cascode cell with that of a 2x12
μm double-stacked (multi) cascode cell for the design of
enhanced output power, broadband MMICs. A load line
comparison for the two types of cascode cells shows that a similar
maximum output power (Pdcmax) can be obtained from a 2x12 μm
double-stacked cascode, when driven over a higher drain voltage
swing at lower current, to that from a 2x25 μm single cascode.
Moreover, measured data confirms higher Maximum Available
Gain (MAG) up to 47 GHz and higher reverse isolation up to 75
GHz for double-stacked class-A operation. Also, a larger
bandwidth can be achieved using the smaller devices with lower
capacitances. Considering stability, 2x12 μm double-stacked
configuration exhibits a lower negative output resistance as
compared to the 2x25 μm single cascode. Thus, double-stacked
(multi) cascode cell shows better RF performance, with no
significant increase in unit cell layout width as compared to
single cascode cell, leading to its potential utilization in the design
of GaAs pHEMT based, high power MMICs such as Travelling
Wave Amplifiers (TWA) up to V-band.
Keywords— pHEMT, multi-cascode, MMIC, voltage swing,
power Travelling Wave Amplifier (TWA)
I. INTRODUCTION
Monolithic Microwave Integrated Circuits (MMICs) are
essential for the compact performance required of RF front
ends. MMIC designs using cascode topologies are widely used
for the design of wide-band circuits [1, 2]. Multi-cascode cells
allow extension of the benefits to high power applications [3].
As shown in Fig. 1, by stacking more than one common-gate
(CG) transistor in series with the common-source transistor,
multi-cascode cells potentially provide a higher maximum
output voltage swing and thus higher power capability, than a
single cascode topology. Multi-cascode CMOS circuits have
been demonstrated for high power, low noise applications but
over narrow bandwidths [4, 5].
The present work highlights the potential capability of a 0.1
μm GaAs pHEMT-based multi-cascode cell for high power
978-1-5090-0157-6/15/$31.00 ©2015 IEEE
Steven Cochran
Keysight Technologies
Santa Rosa, California, USA
and broadband MMIC design, such as Travelling Wave
Amplifiers (TWA), with no significant addition in layout area.
A comparison of measured DC-IV and RF performance of
2x25 μm single and 2x12 μm double-stacked cascode cells is
presented. These device sizes are chosen for comparison
because the drain -source saturation current (Ids sat) of a 2x25
μm device is approximately double that of a 2x12 μm device,
while the 2x12 μm double-stacked cascode can be operated at
double the drain -source voltage (Vds). By trading current for
voltage, the 2x12 μm double-stacked cascode employs smaller
devices with inherently lower parasitics and therefore enhanced
bandwidth, with no tradeoff in maximum DC output power.
II. DC ANALYSIS
Conventionally, the single cascode cell (Fig.1 (a)) is a
series connection of a common-source (CS) field effect
transistor (CSFET), T1 and a common-gate field effect
transistor (CGFET), T2, here each being 2x25 μm. In contrast,
the double-stacked (multi) cascode cell (Fig.1 (b)) replaces T2
with a pair of series connected CGFETs, whereby all devices
are 2x12 μm. The input RF signal is applied to the gate of the
CSFET for both cell types. The RF output is obtained from the
drain terminal of the topmost device i.e., T2 in case of the
single cascode; T3 for the double-stacked cascode.
Besides increased DC supply voltage, the addition of the
second CGFET, T3 increases the output resistance of the
cascode cell, wherein the maximum output resistance is limited
by the leakage current at the output [6]. This is due to the
division of the total supply voltage Vdd between Vds1, Vds2 and
Vds3 (Fig.1 (b)). Thus, the supply voltage of a multi-cascode
cell having N FETs connected in series can be equal to N times
the peak Vds limit across one FET. This implies that a multi-
cascode cell provides increased voltage limits for power
applications, compared to the single cascode cell.
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(a) (b)
Fig.1. Schematic of (a) Single cascode cell (b) Double-stacked cascode cell.
This is evident from Figs. 2 and 3, which show the
measured and simulated output characteristics of a 2x25 μm
single cascode cell and 2x12 μm double-stacked cascode cell
respectively. The gate-to-source voltage Vgs of CSFET was
varied from -1.0 V to 0 V for both cascode cells. The two
CGFETs of 2x12 μm double-stacked cascode cell were biased
at the gate terminal to achieve correct quiescent condition and
to observe the benefit of double-stack configuration. The 2x12
μm double-stacked cascode cell has 29% higher Vdsmax value
and 15% lower drain-to-source saturation current (Ids sat) to
2x25 μm single cascode cell, thereby allowing a higher RF
voltage swing along the (increased resistance) load line, traded
with reduced current for comparable output power
characteristics, with reduced parasitics and higher frequency of
operation. Vdsmax was determined from the Vgdmax value for each
FET which is limited to 9V for this process. The CSFET (T1)
being the input device in the stacked configuration is the
current source to the CGFET next in stage. The CSFET is
biased close to the knee on DC-IV characteristics.
The measured and simulated DC parameters of a 2x25 μm
single cascode cell are in good agreement, while, the measured
drain current of 2x12 μm double-stacked cascode cell is 2 mA
higher than simulated. This could be due to the model fit under
the stacked cascode conditions.
Fig.2. Measured and simulated output characteristics of 2x25 μm single
cascode cell. Vg1 as indicated (Vgs), Vg2 = 0 V
Fig.3. Measured and simulated output characteristics of 2x12 μm double-
stacked cascode cell. Vg1 as indicated (Vgs), Vg2 = 1.5 V, Vg3 = 1.5 V
III. FABRICATION AND RF MEASUREMENT
The 2x25μm single and 2x12 μm double-stacked cascode
cells have been designed and fabricated (Fig.4) on a 2 mil thick
GaAs substrate using the PP10-10 process of WIN
Semiconductors Corp., Taiwan, a commercial GaAs foundry
[7]. The device pullouts and cascode cell sections have been
measured on-wafer over the frequency band of 45 MHz –
75 GHz using an Agilent 8510 XF VNA and Cascade
Microtech probe station. In-house, on-wafer calibration
standards have also been defined and employed for LRRM
calibration with Cascade Microtech WinCAL. Sensitivity to
probe landing position was taken in to account while
performing RF measurements [8]. The two cells were biased
for class-A amplifier operation.
Fig.5 provides a comparison between measured Maximum
Available Gain (MAG) for the two cells. As expected, the 2x12
μm double-stacked cascode cell MAG is increased over that of
the 2x25 μm single cascode cell by up to 4 dB, up to 47 GHz.
Above this frequency, the MAG is lower; however further
investigations into the optimum bias point should yield
improved gain performance over this frequency band. The
ripples observed in MAG value for the 2x12 μm triple cascode
cell between 30 to 40 GHz can be attributed to the value of S12
in this region of frequency being close to the noise floor of the
measurement instrument, as is evident from Fig.6. The
measured reverse isolation of the 2x12 μm double-stacked
cascode cell is improved over that of 2x25 μm single cascode
cell up to 75 GHz, as shown in Fig.6. At differing frequencies,
the highest magnitude values are -31.9 dB and -22.36 dB
respectively, with important application implications for inter-
stage isolation and prevention of mixer bounce.
(a) (b)
Fig.4. Fabricated (a) 2x25 μm single cascode (b) 2x12 μm double-stacked
cascode
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Fig.5. Measured Maximum Available Gain (dB) of 2x25 μm single (Vdd = 3.5
V, Vg1 = -0.4 V, Vg2 = 0 V) and 2x12 μm double- stacked cascode cell (Vdd =
3.5 V, Vg1 = -0.4 V, Vg2 = 0 V, Vg3 = 0 V)
Fig.7 shows the measured input and output return loss
characteristics of the cells. Potential instability can result from
a negative output resistance component in the output
impedance (apparent from traces outside the unity reflection
coefficient magnitude periphery of the Smith chart). This is a
typical feature of the cascode topology in general, mainly due
to the grounding inductance of the CGFET [9]; appropriate
MMIC design techniques are adopted to ensure stability at all
frequency points of interest. It is observed that the 2x12 μm
double-stacked cascode cell has a lower negative resistance
component in the output impedance and therefore is more
stable as compared to the 2x25 μm single cascode cell, under
same device bias conditions. It is envisaged to include double-
stacked cascode topology based MMIC circuit design
examples in an extended version of the paper.
The saturated power (Psat) for this device will not have a
significance as a figure of merit as the device is not matched to
the optimum impedance for maximum output power.
Moreover, it should be emphasized that the multi-cascode
topology is a way to add current drive to TWAs which is not
yet at the breakdown limit but which otherwise would be at the
reverse feed-thru limit.
Fig.6. Measured reverse isolation (dB) of 2x25 μm single (Vdd = 3.5 V, Vg1 =
-0.4 V, Vg2 = 0 V) and 2x12 μm double-stacked cascode cells (Vdd = 3.5 V,
Vg1 = -0.4 V, Vg2 = 0 V, Vg3 = 0 V)
Fig.7. Measured input and output return loss of 2x25 μm single (Vdd = 3.5 V,
Vg1 = -0.4 V, Vg2 = 0 V) and 2x12 μm double-stacked cascode cells (Vdd = 3.5
V, Vg1 = -0.4 V, Vg2 = 0 V, Vg3 = 0 V)
IV. CONCLUSION
Through comparison of the measured DC-IV and RF
performance of 0.1 μm GaAs pHEMT based cascode cells, it is
shown that the addition of a second common-gate FET to form
a double-stacked 2x12 μm cascode cell outperforms the
conventional 2x25 μm single cascode cell under RF figures of
merit up to V-band frequencies, with increased maximum DC
output power capabilities. The 2x12 μm double-stacked
cascode shows higher measured MAG than the 2x25 μm single
cascode, by 4 dB up to 47 GHz.
The highest reverse isolation magnitude of the double-
stacked cascode is -31.9 dB; the single cascode -22.4 dB over a
frequency range up to 75 GHz. The 2x12 μm double-stacked
cascode cell output is less potentially unstable than 2x25 μm
single cascode. Occupying little additional layout unit cell
width, the multi-cascode topology shows capability for
increased output power of compact, broadband, high power
MMICs such as TWAs.
ACKNOWLEDGMENTS
Dr. Graham Parkinson at the Millimeter-Wave Laboratory,
MCS Group, School of EEE, The University of Manchester,
Schlumberger FFTF for PhD financial support and to the
Keysight University Relations Grant #3774.
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