2016 IEEE 7th Control and System Graduate Research Colloquium (ICSGRC 2016), 8 August 2016, UiTM Shah

Alam, Malaysia

Simulation of a 41-level Inverter Built By Cascading

Two Symmetric Cascaded Multilevel Inverter
Ahmad Syukri Mohamad
Norman Mariun
Department of Avionics,
Center for Advance Power and Energy Research,
Malaysian Institute of Aviation Technology,
Department of Electric and Electronic Engineering,
Universiti Kuala Lumpur,
Faculty of Engineering, Universiti Putra Malaysia,
Malaysia
Malaysia
ahmadsyukri@unikl.edu.my
norman@upm.edu.my

Abstract—The main disadvantage for cascaded multilevel
inverter is the high number of switching device it needs in an
installation. To reduce total harmonics distortion (THD) of the
output waveform, the number of output voltage level has to be
increased, hence the higher number of switching devices. This
consequently increases the installation cost, inverter size and
voltage losses at the load terminals. In this paper a new cascaded
multilevel inverter concept is proposed with a small number of
switching devices and dc sources needed. The 41-level inverter
consist of several high voltage and low voltage dc sources. The
switching strategy of the inverter is the low voltage dc sources
are switched in several times in a half cycle of the output. The
41-level cascaded multilevel inverter operation is then
demonstrated by the Matlab simulation.
Index Terms—cascaded multilevel inverter, reduced switching
devices, minimum conducting switches, low THD
I. INTRODUCTION
Multilevel inverter is becoming significantly popular
choice in many industrial applications, from oil and gas,
power plant to power quality devices [1]-[2]. The multilevel
inverter concept can be traced back to the early 1990s, where
several technical papers started to show more interests on it
[3]. However, the concept actually can be found in several
literatures dated back to 1979 [4] and 1983 [5]. The main
operational objective of a multilevel inverter is to synthesize
a sinusoidal output voltage waveform from several levels of
voltages.
The amount of the total harmonics distortion (THD) in the
output voltage waveform is inversely proportion with the
number of output voltage levels, as shown in Table I. So, in
order to reduce the THD levels of the output voltage
waveform, the number of the output voltage levels must be
increased, consequently requiring a higher number of
switching devices in the inverter circuit [6]. This will bring
other problems, mainly the high number of the power
switching devices needed in the cascaded multilevel inverter
design [7]-[10].
With high number of switching devices and their
associated driver circuits, the size of the overall inverter
circuit will be increased. The high number of power switches
also increases the power losses in the overall inverter circuit
(generally as heat) and also reduces the output voltage at the
output terminal due to the accumulation of voltage drops
across each of the conducting switches along the current path
of the output.
So, it is practical to reduce the number of power switches
and its associated driver circuits in order to reduce the heat
TABLE I . THD MEASUREMENTS OF A CASCADED MULTILEVEL
INVERTER OUTPUT WITH DIFFERENT OUTPUT VOLTAGE
LEVEL ARRANGEMENTS
Number of DC sources Output voltage levels THD (%)
3 7-level 12.230
5 11-level 7.587

The main problem with multilevel inverter is the 10 21-level 3.898

prevalent harmonics content in the output voltage waveform.
This is caused by the nature of the multilevel inverter 15 31-level 2.625
operation where the synthesized output waveform is actually
20 41-level 1.980
a series of cascaded square waves switched to imitate as close
as possible to a clean sinusoidal waveform.

978-1-5090-1175-9/16/$31.00 ©2016 IEEE 12

 2016 IEEE 7th Control and System Graduate Research Colloquium (ICSGRC 2016), 8 August 2016, UiTM Shah Alam, Malaysia
Figure 1. Cascaded H-bridge multilevel inverter
losses and output voltage losses. If this can be successfully
done, this will increase the overall efficiency of the inverter
while decreasing the THD levels of the output voltage.
The popular cascaded H-bridge multilevel inverter
comprises of several dc sources each connected to a single-
phase full-bridge or H-bridge inverter as shown in Fig. 1.
Each full-bridge can produce three levels of output voltage,
+Vdc, 0 and –Vdc correspondingly. When combined together,
by using carefully orchestrated timing and programming of
the switches, the cells are connected in cascade one cell at a
time cumulatively. The output voltage, VL will be in a form
of a stepped sinusoidal wave with the number of voltage
levels is mathematically related to the number of cells used in
the cascaded H-bridge multilevel inverter. The number of the
output voltage levels, m is defined by
m = 2n + 1 (1)
where n is the number of voltage sources or cells used in the
cascaded H-bridge multilevel inverter. This formula is
generally used in all of the cascaded multilevel inverter
design and the numerical relationship is shown in Table I.
For an 11-level output, the cascaded H-bridge design
uses 5 dc cells and 20 switches. While for a 21-level cascaded
H-bridge multilevel inverter, 10 dc cells and 40 switches are
used. Consequently, to get 41-level cascaded H-bridge
multilevel inverter with 20 dc cells, an incredible 80 switches
are used.
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Figure 2. The cascaded multilevel inverter topology in [6]
A topology presented in [6] (see Fig. 2) however
successfully demonstrated a dramatically reduction in the
total number of switches used in a cascaded multilevel
inverter circuit. For an 11-level inverter with 5 dc cells, a
total of 10 switches used to construct the inverter. If the
topology used to build a 21-level inverter with 10 dc cells, 15
switches are used. To build a 41-level inverter with 20 dc
sources based on the topology, 25 switches are needed.
II. THE 41-LEVEL “CASCADED SYMMETRIC CASCADED
MULTILEVEL INVERTER” CIRCUIT
The topology in [6] impressively shows reduction in the
number of overall switches. For a 41-level inverter, the
inverter circuit needs 20 dc sources and 25 switches.
Although this is already a considerable improvement
compared to the 80 switches cascaded H-bridge needed to
build a similar 41-level output, the amount required is still
high.
A new switching strategy is proposed in order to further
reduce the number of dc sources, and subsequently the
number of overall switches in a cascaded multilevel inverter
circuit. From the opposite perspective, based on the same
switching strategy, using a relatively smaller dc sources and
number of switches, a higher number of output voltage level
can be achieved, thus further reducing the output THD level
and bring the output waveform shape much more closer to a
clean sinusoidal waveform.
 2016 IEEE 7th Control and System Graduate Research Colloquium (ICSGRC 2016), 8 August 2016, UiTM Shah Alam, Malaysia
Figure 3. The 41-level cascaded symmetric cascaded multilevel inverter
A circuit as shown in Fig. 3 is proposed in order to
achieve this objective. Two symmetric cascaded multilevel
inverter connected into two stages – the first stage (A stage)
has three dc sources, VA1, VA2 and VA3; while there are five
dc sources the second stage (B stage), VB1, VB2, VB3, VB4 and
VB5, where
VA1 = VA2 = VA3
VB1 = VB2 = VB3, = VB4 = VB5
Both stages has different voltage value, with stage A has
higher voltage than stage B. The aggregate value of all series
stage B dc sources however must be equal to one dc source in
stage A.
If VB1 is equal to a voltage unit similar to a symmetrical
cascaded multilevel inverter described in [6];
VB1 = Vdc
then the relationship between the dc sources between the two
stages is
VA1 = 5VB1 = 5Vdc
The stage B dc sources are connected to the stage A dc
sources in a way where the stage B dc sources are ‘interlaced’
between stage A dc sources. The two stages will only
synthesize the half-wave output at Vo. The H-bridge will
create the positive and negative cycles of the sinusoidal
output waveform at the load terminal, VL.
Although it seems quite similar to an asymmetric
cascaded multilevel inverter switching strategy, this method
is different as it is actually two symmetric cascaded
multilevel inverter connected in cascade. A more proper
description for this topology is “cascaded symmetric
cascaded multilevel inverter”.
Table II and Table III describe the switches states of the
circuit in Fig 3 in order to create the desirable output
waveform. While Fig 4(a) shows the half-wave diagram of 41-
level conventional symmetric cascaded multilevel inverter
switching strategy, while Fig 4(b) shows the half-wave
illustration of the 41-level cascaded symmetric cascaded
multilevel inverter based on the proposed switching strategy
of the circuit in Fig 3.
III. SIMULATION RESULTS
The proposed 41-level inverter is simulated using Matlab
Simulink to validate its function and verify its output. Two
symmetric inverter is cascaded – a 7-level inverter and an 11-
level inverter. Both inverters share a same H-bridge which
will create both positive and negative cycle of the output
sinusoidal waveform at the load (see Fig. 3).
The 7-level inverter has three 85V dc sources with
maximum voltage of 255V, while the 11-level inverter has
five 17V dc sources with maximum voltage of 85V. The load
is 1000VA with a power factor of 0.9. The load employed is a
series R-L load, where Z = 51.84 + j0.08.
The preferred power switch is MOSFET as it has very fast
switching time, simple gate circuit, virtually no gate current
and negligible gate circuit loss [11]. Power MOSFET also can
(2) be paralleled easily [12]. The MOSFETs internal on condition
resistance, Ron in this simulation is 0.1Ω for each MOSFET.
(3)
Using Table II and Table III as the switching states for the
inverter, the timing is calculated so that the inverter output is
240Vrms, 50Hz, with a peak voltage of 340V.
The result is shown in Fig. 5. The output voltage is a
stepped sinusoidal wave with a value of 239.2Vrms, which is
resembles almost exactly a clean sine wave with a THD level
of 1.992% while the load current is 4.154A (rms), with a THD
level of only 0.1%. Both THD levels are safely below the limit
(4) set by IEEE Std. 519-1992 and its latest revised version, IEEE
Std. 519-2014.
IV. CONCLUSION
(5) The proposed switching strategy and the suggested
topology is tested and validated using Matlab Simulink
simulations. The voltage drop at the output terminal is low
because the current path of the proposed topology is consisted
only four switched on MOSFETs compared to other topology
such as cascaded H-bridge topology which has a very high
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 2016 IEEE 7th Control and System Graduate Research Colloquium (ICSGRC 2016), 8 August 2016, UiTM Shah Alam, Malaysia

number of switched on power switches at any time of
operation. The output THD level also well below the required
maximum 5% THD level set by the IEEE standard.
REFERENCES
[1] L.G. Franquelo, J. Rodriguez, J.I. Leon, S. Kouro, R. Portillo, M.A.M.
Prats, “The age of multilevel converters arrives”, Ind. Electron. Mag.
IEEE, Vol 2(2) (2008) p. 28 – 39
[2] M. Malinowski, K. Gopakumar, J. Rodriguez, M.A. Pe´rez, “A Survey
on Cascaded Multilevel Inverters”, IEEE Trans. Ind. Electron. Vol
57(7) (2010) pp. 2197 – 2206
[3] J. S. Lai, F. Z. Peng, “Multilevel converters-a new breed of power
converters”, IEEE Trans. Ind. App, Vol 32(3), 1996, pp. 509 – 517
[4] F. Z. Peng, W. Qian, and D. Cao, “Recent advances in multilevel
converter/inverter topologies and applications,” in Conf. Rec. IEEJ Int.
Power Electron. Conf., Sapporo, Japan, Jun. 2010, pp. 492–501
[5] P. M. Bhagwat and V. R. Stefanovic, “Generalized structure of a
multilevel PWM inverter,” IEEE Trans. Ind. App, vol. IA-19, no. 6,
1983, pp. 1057–1069
[6] A. Syukri Mohamad, N. Mariun, N. Sulaiman, M.A.M. Radzi, “A new
cascaded multilevel inverter topology with minimum number of
conducting switches”, 2014 IEEE Innovative Smart Grid Technologies
- Asia (ISGT Asia), 2014, p. 164-169
[7] S. Khomfoi, L. M. Tolbert, Chapter 17, Multilevel Power Converters,
in Power Electronics Handbook (Third Edition), Academic Press,
2011, p. 455-486
[8] K. Corzine, Chapter 6 Multilevel Converters, in The Power Electronics
Handbook, Industrial Electronics Series, CRC Press, 2002, p. 1-23
[9] E. Babaei, S.H. Hosseini, G.B. Gharehpetian, M. Tarafdar Haque, M.
Sabahi, “Reduction of dc voltage sources and switches in asymmetrical
multilevel converters using a novel topology”, Electr. Power Syst. Res.
Vol 77(8) (2007) p. 1073-1085
[10] E. Babaei, S. H. Hosseini, “New cascaded multilevel inverter topology
with minimum number of switches”, Energy Convers. Manag. Vol
50(11) (2009) p. 2761-2767
[11] K. Rajashekara, Chapter 1 Power Electronics – Overview, in The
Power Electronics Handbook, Industrial Electronics Series, CRC Press,
2002, p. 3-10
[12] V. Barkhordarian, Chapter 1 Power Electronics – MOSFETs, in The
Power Electronics Handbook, Industrial Electronics Series, CRC Press,
2002, p. 46-61

TABLE II
VALUES OF V0 FOR STATES OF SWITCHES

Switch SA0 SA1 SA2 SA3 SB0 SB1 SB2 SB3 SB4 SB5 Vo Vo unit value
On Off Off Off On Off Off Off Off Off 0V 0Vdc
On Off Off Off Off On Off Off Off Off VB1 Vdc
On Off Off Off Off Off On Off Off Off VB1 + VB2 2Vdc
On Off Off Off Off Off Off On Off Off VB1 + VB2 + VB3 3Vdc
On Off Off Off Off Off Off Off On Off VB1 + VB2 + VB3 +VB4 4Vdc
Off On Off Off On Off Off Off Off Off VA1 5Vdc
Off On Off Off Off On Off Off Off Off VA1 + VB1 6Vdc
Off On Off Off Off Off On Off Off Off VA1 + VB1 + VB2 7Vdc
Off On Off Off Off Off Off On Off Off VA1 + VB1 + VB2 + VB3 8Vdc
Off On Off Off Off Off Off Off On Off VA1 + VB1 + VB2 + VB3+VB4 9Vdc
States

Off Off On Off On Off Off Off Off Off VA2 10Vdc
Off Off On Off Off On Off Off Off Off VA2 + VB1 11Vdc
Off Off On Off Off Off On Off Off Off VA2 + VB1 + VB2 12Vdc
Off Off On Off Off Off Off On Off Off VA2 + VB1 + VB2 + VB3 13Vdc
Off Off On Off Off Off Off Off On Off VA2 + VB1 + VB2 + VB3+VB4 14Vdc
Off Off Off On On Off Off Off Off Off VA3 15Vdc
Off Off Off On Off On Off Off Off Off VA3 + VB1 16Vdc
Off Off Off On Off Off On Off Off Off VA3 + VB1 + VB2 17Vdc
Off Off Off On Off Off Off On Off Off VA3 + VB1 + VB2 + VB3 18Vdc
Off Off Off On Off Off Off Off On Off VA3 + VB1 + VB2 + VB3+VB4 19Vdc
Off Off Off Off Off Off Off Off On VA3 + VB1 + VB2 + VB3+VB4+VB5 20Vdc

TABLE III
VALUES OF VL FOR STATES OF H-BRIDGE SWITCHES
SH1 SH2 SH3 SH4 VL
On Off On Off +V0
Off On Off On -V0

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2016 IEEE 7th Control and System Graduate Research Colloquium (ICSGRC 2016), 8 August 2016, UiTM Shah Alam, Malaysia

Figure 5. Half-wave DC sources switching strategy:- a) conventional; b)proposed

Figure 4. The 41-level cascaded symmetric cascaded multilevel inverter

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