Beruflich Dokumente
Kultur Dokumente
Slave receiver
Following the address reception and after clearing ADDR, the slave receives bytes from the
SDA line into the DR register via the internal shift register. After each byte the interface
generates in sequence:
An acknowledge pulse if the ACK bit is set
The RxNE bit is set by hardware and an interrupt is generated if the ITEVFEN and
ITBUFEN bit is set.
If RxNE is set and the data in the DR register is not read before the end of the next data
reception, the BTF bit is set and the interface waits until BTF is cleared by a read from
I2C_SR1 followed by a read from the I2C_DR register, stretching SCL low (see Figure 272
Transfer sequencing).
1. The EV1 event stretches SCL low until the end of the corresponding software sequence.
2. The EV2 software sequence must be completed before the end of the current byte transfer
3. After checking the SR1 register content, the user should perform the complete clearing sequence for
each flag found set.
Thus, for ADDR and STOPF flags, the following sequence is required inside the I2C interrupt routine:
READ SR1
if (ADDR == 1) {READ SR1; READ SR2} if
(STOPF == 1) {READ SR1; WRITE CR1}
The purpose is to make sure that both ADDR and STOPF flags are cleared if both are found set.
2
26.3.3 I C master mode
2
In Master mode, the I C interface initiates a data transfer and generates the clock signal. A
serial data transfer always begins with a Start condition and ends with a Stop condition.
Master mode is selected as soon as the Start condition is generated on the bus with a
START bit.
The following is the required sequence in master mode.
Program the peripheral input clock in I2C_CR2 Register in order to generate correct
timings
Configure the clock control registers
Configure the rise time register
Program the I2C_CR1 register to enable the peripheral
Set the START bit in the I2C_CR1 register to generate a Start condition
The peripheral input clock frequency must be at least:
2 MHz in Sm mode
4 MHz in Fm mode
Start condition
Setting the START bit causes the interface to generate a Start condition and to switch to
Master mode (MSL bit set) when the BUSY bit is cleared.
Note: In master mode, setting the START bit causes the interface to generate a ReStart condition at
the end of the current byte transfer.
Once the Start condition is sent:
The SB bit is set by hardware and an interrupt is generated if the ITEVFEN bit is set.
Then the master waits for a read of the SR1 register followed by a write in the DR register
with the Slave address (see Figure 273 and Figure 274 Transfer sequencing EV5).
Master transmitter
Following the address transmission and after clearing ADDR, the master sends bytes from the
DR register to the SDA line via the internal shift register.
The master waits until the first data byte is written into I2C_DR (see Figure 273 Transfer
sequencing EV8_1).
When the acknowledge pulse is received, the TxE bit is set by hardware and an interrupt is
generated if the ITEVFEN and ITBUFEN bits are set.
If TxE is set and a data byte was not written in the DR register before the end of the last data
transmission, BTF is set and the interface waits until BTF is cleared by a read from I2C_SR1
followed bya write to I2C_DR, stretching SCL low.
Closing the communication
After the last byte is written to the DR register, the STOP bit is set by software to generate a
Stop condition (see Figure 273 Transfer sequencing EV8_2). The interface automatically goes
back to slave mode (MSL bit cleared).
Note: Stop condition should be programmed during EV8_2 event, when either TxE or BTF is set.
Master receiver
2
Following the address transmission and after clearing ADDR, the I C interface enters Master
Receiver mode. In this mode the interface receives bytes from the SDA line into the DR
register via the internal shift register. After each byte the interface generates in sequence:
S Header A Address A
EV5 EV9 EV6
1. The EV5, EV6 and EV9 events stretch SCL low until the end of the corresponding software sequence.
2. The EV7 software sequence must complete before the end of the current byte transfer.In case EV7
software sequence can not be managed before the current byte end of transfer, it is recommended to
use BTF instead of RXNE with the drawback of slowing the communication.
When 3 bytes remain to be read:
RxNE = 1 => Nothing (DataN-2 not read).
DataN-1 received
BTF = 1 because both shift and data registers are full: DataN-2 in DR and DataN-1 in
the shift register => SCL tied low: no other data will be received on the bus.
Clear ACK bit
Read DataN-2 in DR => This will launch the DataN reception in the shift register
DataN received (with a NACK)
Program START/STOP
Read DataN-1
RxNE = 1
Read DataN
The procedure described above is valid for N>2. The cases where a single byte or two bytes
are to be received should be handled differently, as described below:
Case of a single byte to be received:
– In the ADDR event, clear the ACK bit.
– Clear ADDR
– Program the STOP/START bit.
– Read the data after the RxNE flag is set.
Figure 276. Method 2: transfer sequence diagram for master receiver when N=2
S Header A Address A
EV5 EV9 EV6
1. The EV5, EV6 and EV9 events stretch SCL low until the end of the corresponding software sequence.
2. The EV6_1 software sequence must complete before the ACK pulse of the current byte transfer.
S Address A Data1 NA P
EV5 EV6_3 EV7
10- bit master receiver
S Header A Address A
EV5 EV9 EV6
Sr Header A Data1 NA P
EV5 EV6_3 EV7
1. The EV5, EV6 and EV9 events stretch SCL low until the end of the corresponding software sequence.
26.3.6 SMBus
Introduction
The System Management Bus (SMBus) is a two-wire interface through which various devices
2
can communicate with each other and with the rest of the system. It is based on I C principles
of operation. SMBus provides a control bus for system and power management related tasks.
A system may use SMBus to pass messages to and from devices instead of toggling
individual control lines.
The System Management Bus Specification refers to three types of devices. A slave is a
device that is receiving or responding to a command. A master is a device that issues
commands, generates the clocks, and terminates the transfer. A host is a specialized master
that provides the main interface to the system's CPU. A host must be a master-slave and must
support the SMBus host notify protocol. Only one host is allowed in a system.
2
Similarities between SMBus and I C
2 wire bus protocol (1 Clk, 1 Data) + SMBus Alert line optional
Master-slave communication, Master provides clock
Multi master capability
2
SMBus data format similar to I C 7-bit addressing format (Figure 269).
2
Differences between SMBus and I C
2
The following table describes the differences between SMBus and I C.
2
Table 188. SMBus vs. I C
SMBus 2
I C
Max. speed 100 kHz Max. speed 400 kHz
Min. clock speed 10 kHz No minimum clock speed
35 ms clock low timeout No timeout
Logic levels are fixed Logic levels are VDD dependent
Different address types (reserved, dynamic etc.) 7-bit, 10-bit and general call slave address types
Different bus protocols (quick command, process No bus protocols
call etc.)
Device identification
Any device that exists on the System Management Bus as a slave has a unique address
called the Slave Address. For the list of reserved slave addresses, refer to the SMBus
specification version. 2.0 (http://smbus.org/).
Bus protocols
The SMBus specification supports up to nine bus protocols. For more details of these
protocols and SMBus address types, refer to SMBus specification version. 2.0. These
protocols should be implemented by the user software.
A host which does not implement the SMBA signal may periodically access the ARA.
For more details on SMBus Alert mode, refer to SMBus specification version 2.0.
Timeout error
2
There are differences in the timing specifications between I C and SMBus.
SMBus defines a clock low timeout, TIMEOUT of 35 ms. Also SMBus specifies TLOW:
SEXT as the cumulative clock low extend time for a slave device. SMBus specifies TLOW:
MEXT as the cumulative clock low extend time for a master device. For more details on these
timeouts, refer to SMBus specification version 2.0.
The status flag Timeout or Tlow Error in I2C_SR1 shows the status of this feature.
Master transmitter: In the interrupt routine after the EOT interrupt, disable DMA
requests then wait for a BTF event before programming the Stop condition.
Master receiver: when the number of bytes to be received is equal to or greater than two,
the DMA controller sends a hardware signal, EOT_1, corresponding to the last but one
2
data byte (number_of_bytes – 1). If, in the I2C_CR2 register, the LAST bit is set, I C
automatically sends a NACK after the next byte following EOT_1. The user can generate
a Stop condition in the DMA Transfer Complete interrupt routine if enabled.
1. Set the I2C_DR register address in the DMA_SxPAR register. The data will be moved to
this address from the memory after each TxE event.
2. Set the memory address in the DMA_SxMA0R register (and in DMA_SxMA1R register in
the case of a bouble buffer mode). The data will be loaded into I2C_DR from this memory
after each TxE event.
3. Configure the total number of bytes to be transferred in the DMA_SxNDTR register.
After each TxE event, this value will be decremented.
4. Configure the DMA stream priority using the PL[0:1] bits in the DMA_SxCR register
5. Set the DIR bit in the DMA_SxCR register and configure interrupts after half transfer or
full transfer depending on application requirements.
6. Activate the stream by setting the EN bit in the DMA_SxCR register.
When the number of data transfers which has been programmed in the DMA Controller
registers is reached, the DMA controller sends an End of Transfer EOT/ EOT_1 signal to the
2
I C interface and the DMA generates an interrupt, if enabled, on the DMA stream interrupt
vector.
Note: Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is used for transmission.
Note: Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is used for reception.
2
26.4 I C interrupts
2
The table below gives the list of I C interrupt requests.
2
Table 189. I C Interrupt requests
Interrupt event Event flag Enable control bit
Start bit sent (Master) SB
Address sent (Master) or Address matched (Slave) ADDR
10-bit header sent (Master) ADD10 ITEVFEN
Stop received (Slave) STOPF
Data byte transfer finished BTF
Receive buffer not empty RxNE ITEVFEN and ITBUFEN
Transmit buffer empty TxE
Note: SB, ADDR, ADD10, STOPF, BTF, RxNE and TxE are logically ORed on the same interrupt
channel.
BERR, ARLO, AF, OVR, PECERR, TIMEOUT and SMBALERT are logically ORed on the
same interrupt channel.
2
Figure 278. I C interrupt mapping diagram
ITEVFEN
SB
ADDR
ADD10
STOPF it_event
BTF
TxE
ITBUFEN
RxNE
ITERREN
BERR
ARLO it_error
AF
OVR
PECERR
TIMEOUT
SMBALERT
MS42082V1
2
26.5 I C debug mode
®
When the microcontroller enters the debug mode (Cortex -M3 core halted), the SMBUS
timeout either continues to work normally or stops, depending on the
DBG_I2Cx_SMBUS_TIMEOUT configuration bits in the DBG module. For more details,
refer to Section 31.16.2: Debug support for timers, watchdog, bxCAN and I2C on
2
26.6 I C registers
Refer to for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits).
2
26.6.1 I C Control register 1 (I2C_CR1)
Address offset: 0x00
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWRST ALERT PEC POS ACK STOP START NO ENGC ENPEC ENARP SMB SMBU PE
Res. STRETCH TYPE Res. S
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Note: When the STOP, START or PEC bit is set, the software must not perform any write access to
I2C_CR1 before this bit is cleared by hardware. Otherwise there is a risk of setting a second
STOP, START or PEC request.
26.6.2 2
I C Control register 2 (I2C_CR2)
Address offset: 0x04
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rw rw rw rw rw rw rw rw rw rw rw
– SB = 1 (Master)
– ADDR = 1 (Master/Slave)
– ADD10= 1 (Master)
– STOPF = 1 (Slave)
– BTF = 1 with no TxE or RxNE event
– TxE event to 1 if ITBUFEN = 1
– RxNE event to 1if ITBUFEN = 1
Bit 8 ITERREN: Error interrupt enable
0: Error interrupt disabled
1: Error interrupt enabled
– BERR = 1
– ARLO = 1
– AF = 1
– OVR = 1
– PECERR = 1
– TIMEOUT = 1
– SMBALERT = 1
Bits 7:6 Reserved, must be kept at reset value
Bits 5:0 FREQ[5:0]: Peripheral clock frequency
The FREQ bits must be configured with the APB clock frequency value (I2C peripheral
connected to APB). The FREQ field is used by the peripheral to generate data setup and
hold times compliant with the I2C specifications. The minimum allowed frequency is 2
MHz, the maximum frequency is limited by the maximum APB frequency and cannot
exceed 50 MHz (peripheral intrinsic maximum limit).
0b000000: Not allowed
0b000001: Not allowed
0b000010: 2 MHz
...
0b110010: 50 MHz
Higher than 0b100100: Not allowed
2
26.6.3 I C Own address register 1 (I2C_OAR1)
Address offset: 0x08
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADD ADD[9:8] ADD[7:1] ADD0
MODE Reserved
rw rw rw rw rw rw rw rw rw rw rw
2
26.6.4 I C Own address register 2 (I2C_OAR2)
Address offset: 0x0C
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved ADD2[7:1] ENDUAL
rw rw rw rw rw rw rw rw
2
26.6.5 I C Data register (I2C_DR)
Address offset: 0x10
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved DR[7:0]
rw rw rw rw rw rw rw rw
2
26.6.6 I C Status register 1 (I2C_SR1)
Address offset: 0x14
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMB TIME PEC OVR AF ARLO BERR TxE RxNE STOPF ADD10 BTF ADDR SB
ALERT OUT Res. ERR Res.
rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 r r r r r r r
2
26.6.7 I C Status register 2 (I2C_SR2)
Address offset: 0x18
Reset value: 0x0000
Note: Reading I2C_SR2 after reading I2C_SR1 clears the ADDR flag, even if the ADDR flag was
set after reading I2C_SR1. Consequently, I2C_SR2 must be read only when ADDR is found
set in I2C_SR1 or when the STOPF bit is cleared.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Note: Reading I2C_SR2 after reading I2C_SR1 clears the ADDR flag, even if the ADDR flag was set
after reading I2C_SR1. Consequently, I2C_SR2 must be read only when ADDR is found set in
I2C_SR1 or when the STOPF bit is cleared.
26.6.8 2
I C Clock control register (I2C_CCR)
Address offset: 0x1C
Reset value: 0x0000
Note:
fPCLK1 must be at least 2 MHz to achieve Sm mode I²C frequencies. It must be at least 4
MHz to achieve Fm mode I²C frequencies. It must be a multiple of 10MHz to reach the
400 kHz maximum I²C Fm mode clock.
The CCR register must be configured only when the I2C is disabled (PE = 0).
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2
26.6.9 I C TRISE register (I2C_TRISE)
Address offset: 0x20
Reset value: 0x0002
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved TRISE[5:0]
rw rw rw rw rw rw
2
26.6.10 I C register map
2
The table below provides the I C register map and reset values.
2
Table 190. I C register map and reset values
Offset Register
I2C_CR1 Reserved
0x00
0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0
I2C_CR2 Reserved FREQ[5:0]
0x04
Reset value 0 0 0 0 0 0 0 0 0 0 0
I2C_OAR1 Reserved Reserved ADD[9:8] ADD[7:1]
0x08
0
Reset value 0 0 0 0 0 0 0 0 0 0
I2C_OAR2 Reserved ADD2[7:1]
0x0C
Reset value 0 0 0 0 0 0 0 0
I2C_DR Reserved DR[7:0]
0x10
Reset value 0 0 0 0 0 0 0 0
I2C_SR1 Reserved
0x14
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2C_SR2 Reserved PEC[7:0]
0x18
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2C_CCR Reserved CCR[11:0]
0x1C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2C_TRISE Reserved TRISE[5:0]
0x20
Reset value 0 0 0 0 1 0
LIN Master Synchronous Break send capability and LIN slave break detection
capability
– 13-bit break generation and 10/11 bit break detection when USART is hardware
configured for LIN
Through these pins, serial data is transmitted and received in normal USART mode as
frames comprising:
An Idle Line prior to transmission or reception
A start bit
A data word (8 or 9 bits) least significant bit first
0.5,1, 1.5, 2 Stop bits indicating that the frame is complete
This interface uses a fractional baud rate generator - with a 12-bit mantissa and 4-bit
fraction
A status register (USART_SR)
Data register (USART_DR)
A baud rate register (USART_BRR) - 12-bit mantissa and 4-bit fraction.
A Guardtime Register (USART_GTPR) in case of Smartcard mode.
Refer to Section 27.6: USART registers for the definition of each bit.
The following pin is required to interface in synchronous mode:
CK: Transmitter clock output. This pin outputs the transmitter data clock for synchronous
transmission corresponding to SPI master mode (no clock pulses on start bit and stop bit,
and a software option to send a clock pulse on the last data bit). In parallel data can be
received synchronously on RX. This can be used to control peripherals that have shift
registers (e.g. LCD drivers). The clock phase and polarity are software programmable. In
Smartcard mode, CK can provide the clock to the smartcard.
Transmission and reception are driven by a common baud rate generator, the clock for each is
generated when the enable bit is set respectively for the transmitter and receiver.
The details of each block is given below.
27.3.2 Transmitter
The transmitter can send data words of either 8 or 9 bits depending on the M bit status.
When the transmit enable bit (TE) is set, the data in the transmit shift register is output on
the TX pin and the corresponding clock pulses are output on the CK pin.
Character transmission
During a USART transmission, data shifts out least significant bit first on the TX pin. In this
mode, the USART_DR register consists of a buffer (TDR) between the internal bus and the
transmit shift register (see Figure 279).
Every character is preceded by a start bit, which is a logic level low for one bit period. The
character is terminated by a configurable number of stop bits.
The following stop bits are supported by USART: 0.5, 1, 1.5 and 2 stop bits.
Note: The TE bit should not be reset during transmission of data. Resetting the TE bit during the
transmission will corrupt the data on the TX pin as the baud rate counters will get frozen.
The current data being transmitted will be lost.
An idle frame will be sent after the TE bit is enabled.
Configurable stop bits
The number of stop bits to be transmitted with every character can be programmed in
Control register 2, bits 13,12.
1. 1 stop bit: This is the default value.
2. 2 stop bits: This is supported by normal USART, single-wire and modem modes.
3. 0.5 stop bit: To be used when receiving data in Smartcard mode.
4. 1.5 stop bits: To be used when transmitting and receiving data in Smartcard mode.
Procedure:
1. Enable the USART by writing the UE bit in USART_CR1 register to 1.
2. Program the M bit in USART_CR1 to define the word length.
3. Program the number of stop bits in USART_CR2.
4. Select DMA enable (DMAT) in USART_CR3 if Multi buffer Communication is to take
place. Configure the DMA register as explained in multibuffer communication.
5. Select the desired baud rate using the USART_BRR register.
6. Set the TE bit in USART_CR1 to send an idle frame as first transmission.
7. Write the data to send in the USART_DR register (this clears the TXE bit). Repeat this for
each data to be transmitted in case of single buffer.
8. After writing the last data into the USART_DR register, wait until TC=1. This indicates
that the transmission of the last frame is complete. This is required for instance when
the USART is disabled or enters the Halt mode to avoid corrupting the last transmission.
the data in the TDR register and which is copied in the shift register at the end of the current
transmission.
When no transmission is taking place, a write instruction to the USART_DR register places
the data directly in the shift register, the data transmission starts, and the TXE bit is
immediately set.
If a frame is transmitted (after the stop bit) and the TXE bit is set, the TC bit goes high. An
interrupt is generated if the TCIE bit is set in the USART_CR1 register.
After writing the last data into the USART_DR register, it is mandatory to wait for TC=1
before disabling the USART or causing the microcontroller to enter the low-power mode
(see Figure 282).
The TC bit is cleared by the following software sequence:
1. A read from the USART_SR register
2. A write to the USART_DR register
Note: The TC bit can also be cleared by writing a ‘0’ to it. This clearing sequence is recommended
only for Multibuffer communication.
Break characters
Setting the SBK bit transmits a break character. The break frame length depends on the M bit
(see Figure 280).
If the SBK bit is set to ‘1’ a break character is sent on the TX line after completing the current
character transmission. This bit is reset by hardware when the break character is completed
(during the stop bit of the break character). The USART inserts a logic 1 bit at the end of the
last break frame to guarantee the recognition of the start bit of the next frame.
Note: If the software resets the SBK bit before the commencement of break transmission, the break
character will not be transmitted. For two consecutive breaks, the SBK bit should be set after
the stop bit of the previous break.
Idle characters
Setting the TE bit drives the USART to send an idle frame before the first data frame.
794/1133 RM0008 Rev 18
RM0008 Universal synchronous asynchronous receiver transmitter (USART)
27.3.3 Receiver
The USART can receive data words of either 8 or 9 bits depending on the M bit in the
USART_CR1 register.
Note: If the sequence is not complete, the start bit detection aborts and the receiver returns to the
idle state (no flag is set) where it waits for a falling edge.
The start bit is confirmed (RXNE flag set, interrupt generated if RXNEIE=1) if the 3 sampled
bits are at 0 (first sampling on the 3rd, 5th and 7th bits finds the 3 bits at 0 and second
sampling on the 8th, 9th and 10th bits also finds the 3 bits at 0).
The start bit is validated (RXNE flag set, interrupt generated if RXNEIE=1) but the NE noise
flag is set if, for both samplings, at least 2 out of the 3 sampled bits are at 0 (sampling on the
3rd, 5th and 7th bits and sampling on the 8th, 9th and 10th bits). If this condition is not met,
the start detection aborts and the receiver returns to the idle state (no flag is set).
If, for one of the samplings (sampling on the 3rd, 5th and 7th bits or sampling on the 8th, 9th
and 10th bits), 2 out of the 3 bits are found at 0, the start bit is validated but the NE noise flag
bit is set.
Character reception
During a USART reception, data shifts in least significant bit first through the RX pin. In this
mode, the USART_DR register consists of a buffer (RDR) between the internal bus and the
received shift register.
Procedure:
1. Enable the USART by writing the UE bit in USART_CR1 register to 1.
2. Program the M bit in USART_CR1 to define the word length.
3. Program the number of stop bits in USART_CR2.
4. Select DMA enable (DMAR) in USART_CR3 if multibuffer communication is to take
place. Configure the DMA register as explained in multibuffer communication. STEP 3
5. Select the desired baud rate using the baud rate register USART_BRR
6. Set the RE bit USART_CR1. This enables the receiver which begins searching for a
start bit.
When a character is received
The RXNE bit is set. It indicates that the content of the shift register is transferred to the
RDR. In other words, data has been received and can be read (as well as its
associated error flags).
An interrupt is generated if the RXNEIE bit is set.
The error flags can be set if a frame error, noise or an overrun error has been detected
during reception.
In multibuffer, RXNE is set after every byte received and is cleared by the DMA read to
the Data Register.
In single buffer mode, clearing the RXNE bit is performed by a software read to the
USART_DR register. The RXNE flag can also be cleared by writing a zero to it. The
RXNE bit must be cleared before the end of the reception of the next character to avoid
an overrun error.
Note: The RE bit should not be reset while receiving data. If the RE bit is disabled during
reception, the reception of the current byte will be aborted.
Break character
When a break character is received, the USART handles it as a framing error.
Idle character
When an idle frame is detected, there is the same procedure as a data received character
plus an interrupt if the IDLEIE bit is set.
Overrun error
An overrun error occurs when a character is received when RXNE has not been reset. Data
can not be transferred from the shift register to the RDR register until the RXNE bit is cleared.
The RXNE flag is set after every byte received. An overrun error occurs if RXNE flag is set
when the next data is received or the previous DMA request has not been serviced. When an
overrun error occurs:
The ORE bit is set.
The RDR content will not be lost. The previous data is available when a read to
USART_DR is performed.
The shift register will be overwritten. After that point, any data received during overrun is
lost.
An interrupt is generated if either the RXNEIE bit is set or both the EIE and DMAR bits
are set.
The ORE bit is reset by a read to the USART_SR register followed by a USART_DR
register read operation.
Note: The ORE bit, when set, indicates that at least 1 data has been lost. There are two
possibilities:
if RXNE=1, then the last valid data is stored in the receive register RDR and can be
read,
if RXNE=0, then it means that the last valid data has already been read and thus there is
nothing to be read in the RDR. This case can occur when the last valid data is read in the
RDR at the same time as the new (and lost) data is received. It may also occur when the
new data is received during the reading sequence (between the USART_SR register read
access and the USART_DR read access).
Noise error
Over-sampling techniques are used (except in synchronous mode) for data recovery by
discriminating between valid incoming data and noise.
RX LINE
Sample
clock 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
6/16
7/16 7/16
Framing error
A framing error is detected when:
The stop bit is not recognized on reception at the expected time, following either a de-
synchronization or excessive noise.
When the framing error is detected:
The FE bit is set by hardware
The invalid data is transferred from the Shift register to the USART_DR register.
No interrupt is generated in case of single byte communication. However this bit rises at
the same time as the RXNE bit which itself generates an interrupt. In case of multibuffer
communication an interrupt will be issued if the EIE bit is set in the USART_CR3
register.
The FE bit is reset by a USART_SR register read operation followed by a USART_DR
register read operation.
4. 2 stop bits: Sampling for 2 stop bits is done on the 8th, 9th and 10th samples of the first
stop bit. If a framing error is detected during the first stop bit the framing error flag will be
set. The second stop bit is not checked for framing error. The RXNE flag will be set at the
end of the first stop bit.
USARTDIV is an unsigned fixed point number that is coded on the USART_BRR register.
Note: The baud counters are updated with the new value of the Baud registers after a write to
USART_BRR. Hence the Baud rate register value should not be changed during
communication.
Example 2:
To program USARTDIV = 0d25.62
This leads to:
DIV_Fraction = 16*0d0.62 = 0d9.92
The nearest real number is 0d10 = 0xA
DIV_Mantissa = mantissa (0d25.620) = 0d25 = 0x19
Then, USART_BRR = 0x19A hence USARTDIV = 0d25.625
Example 3:
To program USARTDIV = 0d50.99
This leads to:
DIV_Fraction = 16*0d0.99 = 0d15.84
The nearest real number is 0d16 = 0x10 => overflow of DIV_frac[3:0] => carry must be
added up to the mantissa
DIV_Mantissa = mantissa (0d50.990 + carry) = 0d51 = 0x33
Then, USART_BRR = 0x330 hence USARTDIV = 0d51.000
limit of the achievable baud rate can be fixed with this data.
Only USART1 is clocked with PCLK2 (72 MHz max). Other USARTs are clocked with
PCLK1 (36 MHz max).