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High Performance, Energy Efficient Master-Slave Flip-Flop Circuits
Uming Kol,and Poras T. Balsara2
‘Texas Instruments Incorporated, P. 0. Box 655303, M I S 8316, Dallas, TX 75265, uko@daldd.sc.ti.com
Dept. of Elect. Engg., University of Texas at Dallas, P.O. Box 830668, EC33, Richardson, TX 75083
This paper investigates performance, power and energy e&iency of several
CMOS master-slave D-fEip-JIops (DFFs). To improve performance and energy
eficiency, a push-pull DFF and a push-pull isolatwn DFF are proposed
Among the $ve DFFs compared, the proposed push-pull kolation circuit is
found to be the fastest with the highest energy e&iency and a minimum data
pulse width property. Effects of using DPL circuit and tri-state push-pull driver
are studied. The impact of scaling supply voltage alone and scaling transistor
threshold voltage with supply voltage on speed and power consumption of these
circuits is also examined.
I. Introduction
DFFs are one of major functions in finite state machines (FSM) which in turn is
the critical part of control logic. It has been reported in [I] that the control logic
of a microprocessor can occupy 20% of the processor’s power. As more
advanced architecture concepts, such as register renaming and out-of-order
execution in a superscalar microprocessor [2], continue to prevail, the control
logic will likely be more complicated and it power dissipation will likely grow
beyond this current level. In addition, to boost processor clock frequency,
modem processors typically adopt superpipelined execution [2] which uses DFFs.
Enhancing DFFs’ speed can either lead to a higher clock rate or allow more logic
depths between two pipeline registers. In this paper, we compare area, speed, and
power of five different DFF implementations: a regular low-risk DFF [3], a low-
area DFF, a low-power DFF [4], a proposed push-pull DFF for performance, and
another proposed push-pull isolation DFF (PPI-DW) for performance and energy
efficiency. Discussion is then extended to the use of double pass-transistor logic
(DPL) for speed [5] and tr-stated circuit for reducing short-circuit power
dissipation. Lastly, effects rf scding supply voltage at constant threshold
voltage, as well as scaling threshold voltage with supply voltage are examined.
11. Design Techniques and Comparison of Energy Efficiency
A conventional negative edge-triggered DFF consists of two level-sensitive
latches or 16 MOSFETs is illustrated in Fig. I(@. The speed of this regular DFF
is limited by two-gate delay (245 ps, Table I) after the clock signal, C, transitions
from logic 1 to 0. The advantage of this DFF design is that it involves minimum
design risk. A common approach to reduce area overhead of the regular DFF is to
remove the two feedback transmission gates. This low-area DFF is depicted in
Fig. l(b), and it uses 25% fewer transistors. Although the strength of feedback
inverters has been weakened to minimize the short-circuit power dissipation due
to voltage contention, this low-area DFF still consumes 18% more total power
and is 42% slower (or 76% more energy, Table I) than that of the regular DFF.
One approach to optimize for power dissipation is to replace the inverter and
transmission gate in the feedback path of Fig. I(a) with a single tr-state inverter,
which is referred to as a low-power DFF [4] as shown in Fig. l(c). The tri-state
inverter avoids short-circuit power dissipation in the feedback path, and yields
only 1% reduction in total power and 3% (Table I) slower speed when compared
to the regular DFF. Considering area and energy efficiency, the low-power DFF
is comparable to the regula DFF. To optimize for speed, an inverter and
transmission gate are added between outputs of the master and slave latches to
accomplish a push-pull effect at the slave latch, as depicted in Fig. 1(d). This
adds four MOSFETs, but reduces the clock-to-output (C-to-Q) delay from two
gates in a regular DFF to one gate. One method to reduce the transistor count is
to use nMOSFET for latches’ input [6]. However, the output of the nMOSFET
can only reach a voltage level of Vdd-Vtwhen it is at logic I, causing a power
overhead up to 50% [5]. A second issue of the nMOSFET input is the speed
degradation due to a slow transition from logic 0 to logic 1. Therefore, a full
transmission gate is kept in the push-pull DFF. To offset the four added
1
16
MOSFETs for push-pull, the two transmission gates in feedback paths are
eliminated. Compared to the regular DFF, this push-pull DFF is 31% faster but
with a 22% power overhead.
To optimize for energy usage in the push-pull DFF, two pMOSFETs are added to
isolate the feedback path. This push-pull isolation DFF (PPI-DFF) increases the
transistor count to 18, but achieves 16% reduction in total power and a speedup of
25% (Table I) relative to the previous push-pull DFF. Compared to the regular
DFF, PPI-DFF improves speed by 56% at an expense of 6% more power. Energy
efficiency of this PPI-DFF is enhanced by 45%-122% when compared to the
previous four DFFs. Applying a DPL [5] input (Fig. I(f)) to the PPI-DFF can
result in a 20% reduction in the setup time. However, when D is at logic 1 and C
switches from logic 1 to 0, a DC-path exists (INK-P2-P1-C) leading to a 60%
power overhead. Another option is to use a tri-state inverter to replace the push-
pull driver of PPI-DFF, as shown in Fig. 1(g). Though this approach reduces the
short-circuit power of the push-pull driver, it weakens the drive strength due to
stacked MOSFETs and is 10% less efficient in energy compared to the PPI-DFE
HI.Effects of Scaling V, and v d d
SPICE simulation results for various supply voltages (vdd) using the same device
models with constant threshold voltages (VJ are summarized in Fig.2-Fig. 5. In
Fig. 2, speed of the low-area DFF degrades faster than others under low voltages,
as it takes longer to resolve the logic value. In Fig. 3, the push-pull and low-area
DFFs consistently dissipate higher power due to voltage contention in feedback
loops. For a v d d range of 1.5-3.5V, PPI-DFF’s energy efficiency is 42-51%
higher than that of the regular, low-power, and push-pull DFFs, and is 218-272%
higher than that of the low-area DFF (Fig. 4). From 3.5V to 1.5V of Vdd, on an
average, energy efficiency is improved by a factor of 2. At lSV, the minimum
data pulse width of low-area and push-pull DFFs degrades to 3ns while the other
three DFFs maintain at 0.7ns, which strongly suggests the former should be
avoided in low-voltage, high-performance applications (Fig. 5). Scaling V, with
Vdd can maintain a proper signal-to-noise ratio [5]. Assuming V, can be kept at 1/
5 of Vdd, the effects of scaling both simultaneously down to a Vdd of 1.OV are
summarized in Fig. &Fig. 9. In contrast to Fig. 4, Fig. 8 indicates that energy
efficiency is improved by a factor of 5.7 when Vdd is scaled from 3.5V down to
1 .OV. From Fig. 5 to Fig. 9 at a v d d of 1.5V, minimum data pulse of low-area and
push-pull DFFs improves by a factor of 5.8 as the V, scaling reduces effects of
voltage contention, while that of the other DFFs improve only by a factor of 1.8.
IV. Conclusions
Though the low-area DFF uses up to 33% fewer transistors, the internal voltage
contention consumes up to 122% more energy than the rest of DFFs. Compared
to a regular DFF, a low-power and a push-pull DFF improve power dissipation by
1% and delay by 31%, respectively, but end up with a comparable energy
efficiency. The proposed PPI-DFF improves speed by 56% at the expense of only
6% of more power, when compared to a regular DFF. Energy efficiency of this
PPI-DFF is 45-122% higher than that of the other DFFs. On an average, while
scaling supply voltage from 3.5 to 1.xV enhances energy efficiency by a factor of
2, scaling it with threshold voltage can boost the efficiency by a factor of 5.7.
References
[I] IBM, “Blue Lightning Technology Preview,” IBM, 1993.
[2] M. Johnson, “Superscalar Microprocessor Design,” Prentice Hall, NJ, 1991.
[3] N. Weste er al., “Principles of CMOS VLSI Design,” Addison-Wesley, 1993.
[4] G. Gerosa et al., “2.2W, 80MHz Superscalar RISC Processor,” JSSC, 12/1994.
[5] U. KOet al., “Low Power Techniques for HP Adder,” Trans. on VLSI, 6/1995.
[6] R. Hossain er al., “Low Power Design with DET FF,” Trans. on VLSI, 6/1994.
0-7803-3036-6195/$4.00 01995 IEEE
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2 17