Acer TravelMate 6252 6292 - QUANTA ZU1 - REV 3B PDF

5 4 3 2 1
ZU1 SYSTEM BLOCK DIAGRAM

PCI DEVICE IDSEL# REQ# / GNT# Interrupts CLOCK
DVI / 7307 CLOCK GENERATOR

Chrontel Merom 479 CPU
CB1410 AD17 REQ0# / GNT0# INTA# CK505/PCI1
CK505
(only for ezDock) uFCPGA Thermal Sensor
MR510 AD18 REQ1# / GNT1# INTB# CK505/PCI0
D D
Page 21 TIAB23 AD25 REQ2# / GNT2# INTE# CK505/PCI2
Page 2 Page 3
Page 3,4
S-VIDEO CONN FSB

Page 20
667/800 Mhz
DDRII
SDVO Dual Channel DDR2 SO-DIMM 0
LCD CONN TV 533/667 MHz
SO-DIMM 1 RJ45
(12.1"WXGA) LVDS NB Page 18
Page 20 VGA Page 12,13
Crestline
(GM965) Transformer
CRT Port Page 5~11 Page 18
Page 19
X4 DMI interface
Mini Card / Giga Lan
HDD (SATA) SATA
C
WLAN (BCM 5787)
C
Page 26
SB Page 27 Page 18
PATA PCIE-0 PCIE-1
ODD (PATA) PCI-Express
Page 26
USB 2.0 ICH8M
Azalia
Page 14~17
PCI Bus
USB Port x 3
USB0~2 Page 27
LPC
Bluetooth PCMCIA Card Reader
USB4 Page 27 1394
Controller Controller Controller
Finger Printer uR PC8763L Super I/O (CB 1410) (MR510)
USB6 Page 29 NS PC87383 (TI 43AB23)
Page 28 Page 30 Page 22 Page 23 Page 25
B B
CCD
USB8 Page 20
SPI ROM Touch Pad K/B CONN FIR PCMCIA Card Reader 1394 CONN
Page 28 Page 29 Page 29 Page 30 Page 24 Page 24 Page 25
A1A
(11/2):(1) Re-name.
HP HP AMP (2) Gerber out
Page 32 Page 31
5V/3V (ISL6236) 1.25V 1.5V 2.5V B1C
Audio Codec PCI-Express PCIE-2 (11/29):Gerber out
(ALC268) ezDockII/II+ Page 34 Page 38 C2A
INT SPK SPK AMP DVI (12/28):Gerber out
Page 32 Page 32 Connector USB3
USB VCORE(ISL6262A) Discharge D3A
PCIE , Lan ,1394 (2/12):Gerber out
Ser & Par Port 1394*2 Page 35 Page 38
Line in & MIC E3A
Page 32 Page 31 PS2 , VGA, DVI TV out / CRT (4/2):Gerber out
Switch
SPDIF,SM BUS Page 20
VTT 1.05V (SC411) Charger (ISL6251)
A
MediaBay A
Express Card Audio Page 36 Page 39
MDC 1.5 10/100/1G Switch 1.8V (TPS51116)

Page 31 Page 33 Page 18 PROJECT : ZU1
Page 37 Quanta Computer Inc.
Size Document Number Rev
Block Diagram 3B
Date: Tuesday, April 10, 2007 Sheet 1 of 39
5 4 3 2 1
5 4 3 2 1
ClockL55 Generator E3A:(3/16) Change C542 from 0805(CH6102K9A01) to 0603(CH6101M9905) base on ME request(HDD Mylar issue)
Clock Gen I2C

+3V C288 .1U_4
BKP1608HS181-T_6
C655
C542 0_6 C294 .1U_4 +3V
*4.7U_6 R436
10U_6 C287 10U_8
ICS9LPRS365BGLFT Q21
RHU002N06 R197
SLG8SP512T: AL8SP512K05
2
A1A:(9/24)
ICS FAE suggest to change C540 .1U_4 U19 <Description> 10K_4
C542,C287 from 4.7uF to 10uF VDD_CK_VDD_PCI 2 48 A1A:(9/20) remove IO_VOUT 3 1 CGDAT_SMB
VDD_PCI IO_VOUT 13,16,18,27,33 PDAT_SMB
C292 .1U_4 VDD_CK_VDD_48 9
A1A:(9/28) VDD_CK_VDD_SRC VDD_48 CGCLK_SMB
16 VDD_PLL3 SCLK 64
D Reverse RC0603 footprint for EMI VDD_CK_VDD_REF 61 63 CGDAT_SMB D
VDD_REF SDA
0_6 C319 .1U_4 VDD_CK_VDD_SRC
CK505 +3V
39 VDD_SRC SRC5/PCI_STOP# 38 PM_STPPCI# 16
R199 VDD_CK_VDD_CPU 55 37 PM_STPCPU# 16 Q20
VDD_CPU SRC5#/CPU_STOP# RHU002N06 R195
2
+1.25V_VDD 12 54 CLK_CPU_BCLK_R RP36 1 2 0X2
VDD_96_IO CPU0 CLK_CPU_BCLK 3
0_6 C318 .1U_4 20 53 CLK_CPU_BCLK#_R 3 4 10K_4
VDD_PLL3_IO CPU0# CLK_CPU_BCLK# 3
R444 26 3 1 CGCLK_SMB
VDD_SRC_IO_1 13,16,18,27,33 PCLK_SMB
45 51 CLK_MCH_BCLK_R RP35 1 2 0X2
VDD_SRC_IO_3 CPU1 CLK_MCH_BCLK 5
36 50 CLK_MCH_BCLK#_R 3 4
VDD_SRC_IO_2 CPU1# CLK_MCH_BCLK# 5
49 VDD_CPU_IO
SRC8/ITP 47
A1A:(9/20) remove SATACLKREQ function, change R188 value from 475ohm to 22 ohm 46
SRC8#/ITP#
R188 22_4 PCI_CLK_510_R 1 35 CLK_PCIE_3GPLL#_R RP34 3 4 0X2
23 PCI_CLK_510 PCI0/CR#_A SRC10# CLK_PCIE_3GPLL# 6
SRC10 34 CLK_PCIE_3GPLL_R 1 2 CLK_PCIE_3GPLL 6 Pin Active Control signal
R434 33_4 PCI_CLK_CB714_R 3
22 PCI_CLK_CB714 PCI1/CR#_B
+3V R429 10K_4 33 PCIE_CLK_RBS_R R194 475_4 CLK_MCH_OE# 6
R433 33_4 PCLK_1394_R SRC11/CR#_H PCIE_CLK_RBS#_R R185 475_4 32 Low SRC9/9#
25 PCLK_1394 4 PCI2/TME SRC11#/CR#_G 32 PCIE_CLKREQ# 33
R187 33_4 PCLK_591_R 5 30 CLK_PCIE_EZ1_R RP29 3 4 0X2
28 PCLK_591 PCI3 SRC9 PCIE_CLK1+ 33
+3V R428 *10K_4 31 CLK_PCIE_EZ1#_R 1 2 PCIE_CLK1- 33
33 Low SRC10/10#
R431 22_4 PCI_CLK_SIO_R SRC9#
27,30 PCI_CLK_SIO 6 PCI4/SRC5_EN
R427 10K_4 44
R186 22_4 PCLK_ICH_R SRC7/CR#_F A1A:(9/24) Base on above table, SWAP SRC3 and SRC9
7 PCIF5/ITP_EN SRC7#/CR#_E 43
+3V R181 *10K_4
CG_XIN 60 41 CLK_PCIE_ICH_R RP37 1 2 0X2
15 PCLK_ICH XTAL_IN SRC6 CLK_PCIE_ICH 15
R182 10K_4 40 CLK_PCIE_ICH#_R 3 4
SRC6# CLK_PCIE_ICH# 15
CG_XOUT 59 XTAL_OUT CLK_PCIE_MINI1_R RP30 +3V
SRC4 27 3 4 0X2 CLK_PCIE_MINI1 27
R430 33_4 FSA 10 28 CLK_PCIE_MINI1#_R 1 2
16 CLKUSB_48 USB_48/FSA SRC4# CLK_PCIE_MINI1# 27
CLK_BSEL0 R426 2.2K_4
C CLK_BSEL1 CLK_PCIE_LAN_R RP31 C
57 FSB/TEST/MODE SRC3/CR#_C 24 3 4 0X2 CLK_PCIE_LAN 18
25 CLK_PCIE_LAN#_R 1 2 R184 10K_4 PCIE_CLKREQ#
SRC3#/CR#_D CLK_PCIE_LAN# 18
CLK_BSEL2 R441 10K_4 FSC 62 REF0/FSC/TESTSEL CLK_PCIE_SATA_R RP32
SRC2/SATA 21 3 4 0X2 CLK_PCIE_SATA 14
R442 22_4 8 22 CLK_PCIE_SATA#_R 1 2
16 14M_ICH VSS_PCI SRC2#/SATA# CLK_PCIE_SATA# 14
11 VSS_48
A1A:(9/24) Add PCIE_CLKREQ# PU to +3V
R443 22_4 15 17 DREFSSCLK_R RP41 1 2 0X2
30 SIO_14M VSS_IO SRC1/SE1 DREFSSCLK 6
19 18 DREFSSCLK#_R 3 4
A1A:(9/24) FAE : (14M_ICH and SIO_14M) signals trace should be equal length VSS_PLL3 SRC1#/SE2 DREFSSCLK# 6
52 VSS_CPU
23 13 DREFCLK_R RP33 3 4 0X2
VSS_SRC1 SRC0/DOT96 DREFCLK 6
29 14 DREFCLK#_R 1 2
A1A:(9/24) ICS FAE suggest R change from 22 to 33 ohm VSS_SRC2 SRC0#/DOT96# DREFCLK# 6
42 VSS_SRC3
A1A:(9/20) change R186 value from 33ohm to 22 ohm(Intel check list 1.301) 58 56
VSS_REF CKPWRGD/PWRDWN# CK_PWRGD 16
ICS9LPRS365AGLFT/ SLG8SP512T During initial power-up be used to
sample FSB speed with FSA/B/C
C2A:(12/26) Base on vendor-FCE suggestion,

change C310/C299 from CH03306JBD7 (33p) to CH02706JB06(27p) C2A:(12/12)change from +1.05V to +1.25V.
Because VDD_IO will drop out when high loading
C310 27P_4 CG_XIN <check list>
Clock Gen Differential IO power

(1)PCI2/TME: PU be used, the CK505 cannot over clock any of the clock for Trust Mode security purposes.
2
Y2
(2)PCI4/SRC5_EN: PU be used, the CK505 will be configured to use Pin37/38 to SRC5 clock. +1.25V_VDD +1.25V
14.318MHZ If PD be detect at powe-on,the CK505 will setting Pin 37/38 to PCI_STOP/CUP_SOTP
(Default is setting to PCI_STOP/CUP_SOTP)
1
C299 27P_4 CG_XOUT L26

BKP1608HS181-T_6
<check list> (3)PCIF5/ITP_EN: PU be used, the CK505 will be configured to use Pin46/47 to CPU ITP clock. <Description>
XTAL length < 500mils If PD be detect at powe-on,the CK505 will setting Pin 46/47 to SRC8 C320 C309 C300 C301 C316 C314 C317 C290 C315 C291 C293
B (Default is setting to SRC8) B
*10U_8 *10U_8 *10U_8 10U_8 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4
(4)SLG8SP512 Pin 6 select Pin 17, 18 output is LCDCLK or 27 M, PD is LCDCLK, PU is 27 M ,

Pin 37, 38 will fixed be use CPU_Stop and PCI_Stop.
0.1U close to each VDD_IO Power pin
(5)SLG505YC64 CK505 Standar parts follow standar setting
CPU Clock select

BSEL Frequency Select Table
R180 0_4 CLK_BSEL0
3 CPU_BSEL0 MCH_BSEL0 6
FSC FSB FSA Frequency
+1.05V_CPU R425 *56_4
0 0 0 266Mhz
R179 *1K_4
0 0 1 133Mhz
R440 0_4 CLK_BSEL1 0 1 1 166Mhz

R439 *0_4 0 1 0 200Mhz

A1A: (9/20) Remove 0ohm
A A
+1.05V_CPU R198 *1K_4 1 1 0 400Mhz
1 1 1 Reserved
R448 0_4 CLK_BSEL2
1 0 1 100Mhz
PROJECT : ZU1
R449 *0_4
1 0 0 333Mhz
Size
Quanta Computer Inc.
Document Number Rev
+1.05V_CPU R447 *1K_4
CLK. GEN./ CK505 3B
C2A: (12/10) no stuff R179,R198,R447 for auto CPU frequence selection (follow ZD1,ZO1)
5 4 3 2 1
5 4 3 2 1
CPU Thermal monitor

U30A
5 H_A#[16:3]
H_A#3 J4 H1
A[3]# ADS# H_ADS# 5
CPU(HOST)
ADDR GROUP 0
H_A#4 L5 E2
A[4]# BNR# H_BNR# 5 +3V
H_A#5 L4 G5
A[5]# BPRI# H_BPRI# 5
H_A#6 K5
H_A#7 A[6]#
M3 A[7]# DEFER# H5 H_DEFER# 5
H_A#8 N2 F21
A[8]# DRDY# H_DRDY# 5
H_A#9 J1 E1
A[9]# DBSY# H_DBSY# 5
H_A#10 N3
H_A#11 A[10]#
P5 A[11]# BR0# F1 H_BREQ#0 5
H_A#12 P2 A1A:(9/29) change SMBUS from MBCLK/MNDATA to 2ND_MBCLK/2ND_MBDATA
CONTROL
H_A#13 A[12]#
L2 A[13]# IERR# D20 H_IERR# R109 56.2_4 +1.05V_CPU
H_A#14 P4 B3 +3V R388 R387 R385
A[14]# INIT# H_INIT# 14
H_A#15 P1
H_A#16 A[15]# Q31 10K_4 10K_4 200_6
R1 A[16]# LOCK# H4 H_LOCK# 5
2
D RHU002N06 LM86VCC D
5 H_ADSTB0# M1 ADSTB[0]#
5 H_REQ#[4:0] RESET# C1 H_CPURST# 5
H_REQ#0 K3 F3 28 2ND_MBCLK 3 1 C466
REQ[0]# RS[0]# H_RS#0 5
H_REQ#1 H2 F4
REQ[1]# RS[1]# H_RS#1 5
H_REQ#2 K2 G3 .1U_4
REQ[2]# RS[2]# H_RS#2 5
H_REQ#3 J3 G2 +3V
REQ[3]# TRDY# H_TRDY# 5
H_REQ#4 L1 U27
REQ[4]# Q30 H_THERMDA
5 H_A#[35:17] HIT# G6 H_HIT# 5
2
H_A#17 Y2 E4 RHU002N06 8 1
A[17]# HITM# H_HITM# 5 SCLK VCC
H_A#18 U5
H_A#19 A[18]# C461
R3 A[19]# BPM[0]# AD4 28 2ND_MBDATA 3 1 7 SDA DXP 2
ADDR GROUP 1
H_A#20 W6 AD3
H_A#21 A[20]# BPM[1]# A1A: (9/4) +3V 2200P_4
XDP/ITP SIGNALS
U4 A[21]# BPM[2]# AD1 6 ALERT# DXN 3
H_A#22 Y5 AC4 Remove XDP/ITP signals
H_A#23 A[22]# BPM[3]# H_THERMDC
U1 A[23]# PRDY# AC2 4 OVERT# GND 5
H_A#24 R4 AC1 A1A: (9/26) Add (U27/Pin6) PU to 3V R389
H_A#25 A[24]# PREQ# XDP_TCK A1A: (10/30) remove R389, already PU in ICH8
T5 A[25]# TCK AC5
H_A#26 T3 AA6 XDP_TDI *10K_4 MAX6657
A[26]# TDI
H_A#27 W2 A[27]# TDO AB3 16 THERM_ALERT# R390 *0_4 THERM_ALERT#_R ADDRESS: 98H
H_A#28 W5 AB5 XDP_TMS
H_A#29 A[28]# TMS XDP_TRST# +3V R381 10K_4 CPUFAN#_ON
Y4 A[29]# TRST# AB6 <check list>
H_A#30 U2 C20 XDP_DBRESET# R112 0_4 Layout Note:Routing 10:10 mils and away
A[30]# DBR# SYS_RST# 16
H_A#31 V4
H_A#32 W3
A[31]# from noise source with ground gard
H_A#33 A[32]# R107 1k_4
AA4 A[33]# THERMAL +1.05V_CPU
H_A#34 AB2
H_A#35 A[34]#
AA3 A[35]# PROCHOT# D21 H_PROCHOT_R# R111 0_4
H_PROCHOT# 35
5 H_ADSTB1# V1 ADSTB[1]# THERMDA A24 H_THERMDA
CPU FAN
B25 H_THERMDC D3A:(2/28)
THERMDC Implement PROCHOT method +3V
14 H_A20M# A6 A20M# (1)R107 was changed to 1K ohm.
ICH
A5 C7 THERMTRIP#_PWR <check list>

14 H_FERR# FERR# THERMTRIP# (2)R111 was changed to 0 ohm.
14 H_IGNNE# C4 IGNNE# Default PU 56ohm if no use.
C A1A: (9/26) Add CPUFAN#_ON to (U28/PIN1) C
R173 0_4 H_STPCLK_R# D5
Serial R NC, If connect to power side PU 68ohm. Serial R 2.2K A1A: (10/23) Add Diode D39 and PU +5V for (U28/Pin1) R70
14 H_STPCLK# STPCLK# C2A:(12/12) Add level shift circuit (follow ZO1), remove D39,no stuff R383.
14 H_INTR C6 LINT0 H CLK
B4 A22 E3A:(3/14) Add C653 base in G995 failure rate issue 10K_4
14 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 2
14 H_SMI# A3 SMI# BCLK[1] A21 CLK_CPU_BCLK# 2
+3V +5V
+5V
TP_CPU_RSVD01 M4 C653
T55 RSVD[01]
TP_CPU_RSVD02 N5 28 FANSIG
T50 RSVD[02]
TP_CPU_RSVD03 T2 R383 2.2U_6
T56 RSVD[03] CN23
TP_CPU_RSVD04 V3 *10K_4 U28
T53 RSVD[04]
2
RESERVED
TP_CPU_RSVD05 B2 2 3 TH_FAN_POWER
T108 RSVD[05] VIN VO 1 4
TP_CPU_RSVD06 C3 5
T48 RSVD[06] GND 2
TP_CPU_RSVD07 D2 CPUFAN#_ON 1 3 CPUFAN#_ON_R 1 6
T52 RSVD[07] /FON GND 3 5
TP_CPU_RSVD08 D22 7 C99 C96 C106
T5 RSVD[08] GND
TP_CPU_RSVD09 D3 Q34 4 8 PTI_CWY030-B0G1Z
T54 RSVD[09] 28 CPUFAN# VSET GND
TP_CPU_RSVD10 F6 10U_8 .01U_4 *.01U_4
T49 RSVD[10] 2N7002E G995
Merom Ball-out Rev 1a FANPWR = 1.6*VSET

5 H_D#[15:0] H_D#[47:32] 5
U30B G995/Pin1- internal pull high (+5V) A1A: (9/24) change FAN CONN (follow ZC3)
H_D#0 E22 Y22 H_D#32
H_D#1 D[0]# D[32]# H_D#33
F24 D[1]# D[33]# AB24
H_D#2 E26 V24 H_D#34
H_D#3 D[2]# D[34]# H_D#35
G22 D[3]# D[35]# V26
DATA GRP 0
H_D#4 F23 V23 H_D#36

H_D#5 D[4]# D[36]# H_D#37
G25 D[5]# D[37]# T22
H_D#6 E25 U25 H_D#38
D[6]# D[38]#
PU/PD (ITP700) Thermal Trip
H_D#7 E23 U23 H_D#39
H_D#8 D[7]# D[39]# H_D#40
K24 Y25
DATA GRP 2
H_D#9 D[8]# D[40]# H_D#41 +1.05V_CPU

G24 D[9]# D[41]# W22
H_D#10 J24 Y23 H_D#42
B H_D#11 D[10]# D[42]# H_D#43 B
J23 D[11]# D[43]# W24
H_D#12 H22 W25 H_D#44 +1.05V_CPU
D[12]# D[44]#
3
H_D#13 F26 AA23 H_D#45
H_D#14 D[13]# D[45]# H_D#46
K22 D[14]# D[46]# AA24
H_D#15 H23 AB25 H_D#47
D[15]# D[47]# Q18 R183 D19
5 H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 5 6,16,35 DELAY_VR_PWRGOOD 2
5 H_DSTBP#0 H26 DSTBP[0]# DSTBP[2]# AA26 H_DSTBP#2 5
H25 U22 FDV301N *10K_4 *BAS316
5 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 5
5 H_D#[31:16] H_D#[63:48] 5
1
H_D#16 N22 AE24 H_D#48 XDP_TMS R157 39_4 +1.05V_CPU C271 *1U_6
H_D#17 D[16]# D[48]# H_D#49
K25 D[17]# D[49]# AD24
H_D#18 P26 AA21 H_D#50
H_D#19 D[18]# D[50]# H_D#51
R23 D[19]# D[51]# AB22
H_D#20 L23 AB21 H_D#52 XDP_TDI R150 150_4
D[20]# D[52]# A1A: (9/26)
DATA GRP 1
H_D#21 M24 AC26 H_D#53 R174

H_D#22 D[21]# D[53]# H_D#54 change name from THERM_SYS_PWR to SYS_SHDN#
L22 D[22]# D[54]# AD20
H_D#23 M23 AE22 H_D#55 56.2_4 Q19
D[23]# D[55]#
2
H_D#24 P25 AF23 H_D#56 MMBT3904
+1.05V_CPU H_D#25 D[24]# D[56]# H_D#57
P23 D[25]# D[57]# AC25
H_D#26 P22 H_D#58 THERMTRIP#_PWR
DATA GRP 3
D[26]# D[58]# AE21 1 3 SYS_SHDN# 34

<Check list & CRB> H_D#27 T24 AD21 H_D#59 <Check list & CRB>
H_D#28 D[27]# D[59]# H_D#60 XDP_TCK R152 27_4
Layout note: Z=55 ohm R24 D[28]# D[60]# AC22 Layout note: L<0.5"
H_D#29 L25 AD23 H_D#61
H_GTLREF<0.5" H_D#30 T25
D[29]# D[61]#
AF22 H_D#62 COMP0/2 Z=27.4ohm
H_D#31 D[30]# D[62]# H_D#63 COMP1/3 Z=54.9 R175 *0_4
N25 D[31]# D[63]# AC23 PM_THRMTRIP# 6,14
R92 L26 AE25 XDP_TRST# R151 680_4
5 H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 5
1K_4 M26 AF24
5 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 5
5 H_DINV#1 N24 DINV[1]# DINV[3]# AC20 H_DINV#3 5 <CRB & Design guide>
Layout Note:Connect from
H_GTLREF AD26 R26 COMP0 R89 27.4_6 <CRB & Design guide>
R94 *1K_4CPU_TEST1 C23 GTLREF
MISC
COMP[0]
U26 COMP1 R91 54.9_4 SB and daisy chain to CPU A1A: (9/4) <checklist>
A TEST1 COMP[1] CORE VR.Not use T Retain the termination resistors Layout Note: Thermal trip should connect to ICH8 & GMCH without T-ing A
R93 *1K_4CPU_TEST2 D25 AA1 COMP2 R172 27.4_6
CPU_TEST3 C24 TEST2 COMP[2]
Y1 COMP3 R169 54.9_4 connect.(SB/VR/CPU/NB) on these signals even when ITP700Flex (ZS1 default NC)
T4 TEST3 COMP[3] is not implemented.
C132 *.1U_4
CPU_TEST4 AF26
CPU_TEST5 AF1 TEST4
T57 TEST5 DPRSTP# E5 ICH_DPRSTP# 6,14,35
CPU_TEST6 A26 B5
T6 TEST6 DPSLP# H_DPSLP# 14
R90 D24
DPWR# H_DPWR# 5
2K_6 B22 D6
2 CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGD 14
B23 D7
2
2
CPU_BSEL1
CPU_BSEL2 C21
BSEL[1]
BSEL[2]
SLP#
PSI# AE6
H_CPUSLP# 5
PSI# 35
PROJECT : ZU1
A1A: (9/22) Remove H_PWRGD_XDP
Merom Ball-out Rev 1a
Size
Document Number Rev
CPU(1 of 2)/FAN/Thermal 3B
5 4 3 2 1
5 4 3 2 1
CPU(Power)
VCC_CORE
U30D
A4 VSS[001] VSS[082] P6
A8 VSS[002] VSS[083] P21
A11 VSS[003] VSS[084] P24
A14 VSS[004] VSS[085] R2
U30C A16 R5
VSS[005] VSS[086]
A7 VCC[001] VCC[068] AB20 <REV.NO. 0.5/REF.NO.19343> A19 VSS[006] VSS[087] R22
C517 C222 C481 C483 C499 C479 C513 C515 C221 C498 A9 AB7 A23 R25
VCC[002] VCC[069] VSS[007] VSS[088]
A10 AC7 AF2 T1
D 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 A12
VCC[003] VCC[070]
AC9
Ivcc Max 52A B6
VSS[008] VSS[089]
T4 D
VCC[004] VCC[071] VSS[009] VSS[090]
A13 VCC[005] VCC[072] AC12 B8 VSS[010] VSS[091] T23
A15 VCC[006] VCC[073] AC13 Ivccp Max 6A(VCCP supply before Vcc stable) B11 VSS[011] VSS[092] T26
A17 VCC[007] VCC[074] AC15 Max 2A(VCCP supply after Vcc stable) B13 VSS[012] VSS[093] U3
A18 VCC[008] VCC[075] AC17 B16 VSS[013] VSS[094] U6
A20 VCC[009] VCC[076] AC18 B19 VSS[014] VSS[095] U21
B7 AD7 Ivcca Max 130mA B21 U24
VCC[010] VCC[077] VSS[015] VSS[096]
B9 VCC[011] VCC[078] AD9 B24 VSS[016] VSS[097] V2
B10 VCC[012] VCC[079] AD10 C5 VSS[017] VSS[098] V5
B12 VCC[013] VCC[080] AD12 C8 VSS[018] VSS[099] V22
C478 C480 C482 C514 C502 C171 C191 C172 C512 C521 B14 AD14 C11 V25
VCC[014] VCC[081] +1.05V_CPU VSS[019] VSS[100]
B15 VCC[015] VCC[082] AD15 C14 VSS[020] VSS[101] W1
10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 B17 AD17 C16 W4
VCC[016] VCC[083] VSS[021] VSS[102]
B18 VCC[017] VCC[084] AD18 C19 VSS[022] VSS[103] W23
B20 VCC[018] VCC[085] AE9 C2 VSS[023] VSS[104] W26
C9 VCC[019] VCC[086] AE10 C22 VSS[024] VSS[105] Y3
C10 VCC[020] VCC[087] AE12 C25 VSS[025] VSS[106] Y6
C12 AE13 C250 C154 C153 C251 C249 C152 D1 Y21
VCC[021] VCC[088] VSS[026] VSS[107]
C13 VCC[022] VCC[089] AE15 D4 VSS[027] VSS[108] Y24
C15 AE17 .1U_6 .1U_6 .1U_6 .1U_6 .1U_6 .1U_6 D8 AA2
VCC[023] VCC[090] VSS[028] VSS[109]
C17 VCC[024] VCC[091] AE18 D11 VSS[029] VSS[110] AA5
DESIGN GUIDE C18 VCC[025] VCC[092] AE20 D13 VSS[030] VSS[111] AA8
C230 C223 C500 C503 C231 C501 D9 AF9 D16 AA11
CHANGE FROM 22UF *20 TO 10UF *32 D10
VCC[026] VCC[093]
AF10 D19
VSS[031] VSS[112]
AA14
10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 VCC[027] VCC[094] VSS[032] VSS[113]
D12 VCC[028] VCC[095] AF12 D23 VSS[033] VSS[114] AA16
D14 VCC[029] VCC[096] AF14 D26 VSS[034] VSS[115] AA19
D15 VCC[030] VCC[097] AF15 E3 VSS[035] VSS[116] AA22
D17 VCC[031] VCC[098] AF17 E6 VSS[036] VSS[117] AA25
D18 AF18 <CRB> +1.05V_CPU +1.05V E8 AB1
VCC[032] VCC[099] VSS[037] VSS[118]
E7 VCC[033] VCC[100] AF20 R for test only E11 VSS[038] VSS[119] AB4
E9 VCC[034] E14 VSS[039] VSS[120] AB8
E10 G21 CPU_G21 R108 0_4 R176 0_1210 E16 AB11
C VCC[035] VCCP[01] CPU_V6 R159 0_4 VSS[040] VSS[121] C
E12 VCC[036] VCCP[02] V6 E19 VSS[041] VSS[122] AB13
E13 VCC[037] VCCP[03] J6 E21 VSS[042] VSS[123] AB16
C516 C193 C504 C192 C173 C484 E15 K6 + C280 E24 AB19
10U_8 VCC[038] VCCP[04] VSS[043] VSS[124]
E17 VCC[039] VCCP[05] M6 <Check list> F5 VSS[044] VSS[125] AB23
10U_8 10U_8 10U_8 10U_8 10U_8 CH61001ME96 E18 J21 330U_7343 ESR=12m ohm F8 AB26
<Description> VCC[040] VCCP[06] VSS[045] VSS[126]
E20 VCC[041] VCCP[07] K21 F11 VSS[046] VSS[127] AC3
F7 VCC[042] VCCP[08] M21 F13 VSS[047] VSS[128] AC6
F9 VCC[043] VCCP[09] N21 F16 VSS[048] VSS[129] AC8
F10 VCC[044] VCCP[10] N6 F19 VSS[049] VSS[130] AC11
F12 VCC[045] VCCP[11] R21 F2 VSS[050] VSS[131] AC14
F14 VCC[046] VCCP[12] R6 F22 VSS[051] VSS[132] AC16
F15 VCC[047] VCCP[13] T21 F25 VSS[052] VSS[133] AC19
+ C198 + C217 + C197 F17 T6 G4 AC21
VCC[048] VCCP[14] +1.5V VSS[053] VSS[134]
F18 VCC[049] VCCP[15] V21 <CRB> G1 VSS[054] VSS[135] AC24
F20 VCC[050] VCCP[16] W21 .01U near to B26 ball G23 VSS[055] VSS[136] AD2
330U_7343 *330U_7343330U_7343 AA7 G26 AD5
VCC[051] +VCCA_PROC R386 0_6 VSS[056] VSS[137]
AA9 VCC[052] VCCA[01] B26 H3 VSS[057] VSS[138] AD8
A1A:(10/13) stuff C198, unstuff C217 AA10 C26 H6 AD11
(base on layout location) VCC[053] VCCA[02] VSS[058] VSS[139]
AA12 VCC[054] H21 VSS[059] VSS[140] AD13
AA13 AD6 VCC_CORE C472 C471 H24 AD16
VCC[055] VID[0] H_VID0 35 VSS[060] VSS[141]
AA15 VCC[056] VID[1] AF5 H_VID1 35 J2 VSS[061] VSS[142] AD19
<Check list> AA17 AE5 .01U_4 10U_8 J5 AD22
Option1:330U*6(ESR=1.5m ohm aggregate , ESL=0.8nH/6) and 22U*20(ESR=3mohm typ/20 , ESL=0.6nH/20) AA18 VCC[058] VID[3] AF4 H_VID3 35 J22 VSS[063] VSS[144] AD25
AA20 AE3 R156 J25 AE1
Option2:330U*6(ESR=1.5m ohm aggregate , ESL=1.8nH/6) and 22U*32(ESR=3mohm typ/32 , ESL=0.6nH/32) VCC[059] VID[4] H_VID4 35 VSS[064] VSS[145]
AB9 VCC[060] VID[5] AF3 H_VID5 35 K1 VSS[065] VSS[146] AE4
AC10 AE2 100_6 K4 AE8
AB10 VCC[062] K23 VSS[067] VSS[148] AE11
AB12 VCC[063] K26 VSS[068] VSS[149] AE14
AB14 VCC[064] VCCSENSE AF7 VCCSENSE 35 L3 VSS[069] VSS[150] AE16
AB15 VCC[065] L6 VSS[070] VSS[151] AE19
AB17 VCC[066] L21 VSS[071] VSS[152] AE23
AB18 VCC[067] VSSSENSE AE7 VSSSENSE 35 L24 VSS[072] VSS[153] AE26
B B
M2 VSS[073] VSS[154] A2
Merom Ball-out Rev 1a M5 AF6
VSS[074] VSS[155]
. <Demo board> M22 VSS[075] VSS[156] AF8
R160 Routing 27.4ohm with 50mils spacing M25 AF11
VSS[076] VSS[157]
N1 AF13
100_6 PU/PD near to CPU 1" N4
VSS[077] VSS[158]
AF16
VSS[078] VSS[159]
N23 VSS[079] VSS[160] AF19
N26 VSS[080] VSS[161] AF21
P3 VSS[081] VSS[162] A25
VSS[163] AF25
Merom Ball-out Rev 1a

.
A A
PROJECT : ZU1
CPU(2 of 2) 3B
5 4 3 2 1
5 4 3 2 1
D3A:(2/1) Change 965GM from ES sample to QS sample

NB(HOST) Change U29 P/N from AJ0QN120T37 to AJ0QP200T09
H_A#[35:3] 3
U29A
3 H_D#[63:0]
J13 H_A#3
H_D#0 H_A#_3 H_A#4
E2 H_D#_0 H_A#_4 B11
+1.05V_GMCH H_D#1 G2 C11 H_A#5
H_D#2 H_D#_1 H_A#_5 H_A#6
G7 H_D#_2 H_A#_6 M11
H_D#3 M6 C15 H_A#7
H_D#4 H_D#_3 H_A#_7 H_A#8
H7 H_D#_4 H_A#_8 F16
H_D#5 H3 L13 H_A#9
R86 H_D#6 H_D#_5 H_A#_9 H_A#10
D G4 H_D#_6 H_A#_10 G17 D
H_D#7 F3 C14 H_A#11
221_4 H_D#8 H_D#_7 H_A#_11 H_A#12
N8 H_D#_8 H_A#_12 K16
H_D#9 H2 B13 H_A#13
H_SWING H_D#10 H_D#_9 H_A#_13 H_A#14
M10 H_D#_10 H_A#_14 L16
H_D#11 N12 J17 H_A#15
H_D#12 H_D#_11 H_A#_15 H_A#16
N9 H_D#_12 H_A#_16 B14
R85 C137 <check list> H_D#13 H5 K19 H_A#17
H_D#14 H_D#_13 H_A#_17 H_A#18
0.1U close to B3 P13 H_D#_14 H_A#_18 P15
100_4 .1U_4 H_D#15 K9 R17 H_A#19
H_D#16 H_D#_15 H_A#_19 H_A#20
M2 H_D#_16 H_A#_20 B16
H_D#17 W10 H20 H_A#21
H_D#18 H_D#_17 H_A#_21 H_A#22
Y8 H_D#_18 H_A#_22 L19
H_D#19 V4 D17 H_A#23
H_D#20 H_D#_19 H_A#_23 H_A#24
M3 H_D#_20 H_A#_24 M17
H_D#21 J1 N16 H_A#25
H_D#22 H_D#_21 H_A#_25 H_A#26
N5 H_D#_22 H_A#_26 J19
H_D#23 N3 B18 H_A#27
H_D#24 H_D#_23 H_A#_27 H_A#28
W6 H_D#_24 H_A#_28 E19
H_D#25 W9 B17 H_A#29
H_D#26 H_D#_25 H_A#_29 H_A#30
N2 H_D#_26 H_A#_30 B15
H_RCOMP H_D#27 Y7 E17 H_A#31
H_D#28 H_D#_27 H_A#_31 H_A#32
Y9 H_D#_28 H_A#_32 C18 H_A#[35:32] are not supported in
<check list> H_D#29 P4 A19 H_A#33 Calero Interposer
R95 H_D#30 H_D#_29 H_A#_33 H_A#34
10:20 mils(Width:Spacing) W3 B19
C
H_D#31 N1
H_D#_30 H_A#_34
N19 H_A#35 Crestline support 36 bit address C
24.9_4 H_D#32 H_D#_31 H_A#_35
AD12 H_D#_32
H_D#33 AE3 G12
H_D#_33 H_ADS# H_ADS# 3
H_D#34 AD9 H17
HOST
H_D#_34 H_ADSTB#_0 H_ADSTB0# 3
H_D#35 AC9 G20
H_D#_35 H_ADSTB#_1 H_ADSTB1# 3
H_D#36 AC7 C8
H_D#_36 H_BNR# H_BNR# 3
H_D#37 AC14 E8
H_D#_37 H_BPRI# H_BPRI# 3
H_D#38 AD11 F12
H_D#_38 H_BREQ# H_BREQ#0 3
H_D#39 AC11 D6
H_D#_39 H_DEFER# H_DEFER# 3
H_D#40 AB2 C10
+1.05V_GMCH H_D#_40 H_DBSY# H_DBSY# 3
H_D#41 AD7 AM5
H_D#_41 HPLL_CLK CLK_MCH_BCLK 2
H_D#42 AB1 AM7
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# 2
H_D#43 Y3 H8
H_D#_43 H_DPWR# H_DPWR# 3
H_D#44 AC6 K7
H_D#_44 H_DRDY# H_DRDY# 3
H_D#45 AE2 E4
H_D#_45 H_HIT# H_HIT# 3
R87 H_D#46 AC5 C6
H_D#_46 H_HITM# H_HITM# 3
H_D#47 AG3 G10
H_D#_47 H_LOCK# H_LOCK# 3
54.9_4 <check list> H_D#48 AJ9 B7
H_D#_48 H_TRDY# H_TRDY# 3
Impedance 55ohm H_D#49 AH8
H_SCOMP H_D#50 H_D#_49
AJ14 H_D#_50
H_D#51 AE9
H_D#52 H_D#_51
AE11 H_D#_52 H_DINV#[3:0] 3
H_D#53 AH12 K5 H_DINV#0
H_D#54 H_D#_53 H_DINV#_0 H_DINV#1
AJ5 H_D#_54 H_DINV#_1 L2
B H_D#55 AH5 AD13 H_DINV#2 B
+1.05V_GMCH H_D#56 H_D#_55 H_DINV#_2 H_DINV#3
AJ6 H_D#_56 H_DINV#_3 AE13
H_D#57 AE7 H_D#_57 H_DSTBN#[3:0] 3
H_D#58 AJ7 M7 H_DSTBN#0
H_D#59 H_D#_58 H_DSTBN#_0 H_DSTBN#1
AJ2 H_D#_59 H_DSTBN#_1 K3
H_D#60 AE5 AD2 H_DSTBN#2
R88 H_D#61 H_D#_60 H_DSTBN#_2 H_DSTBN#3
AJ3 H_D#_61 H_DSTBN#_3 AH11
<check list> H_D#62 AH2 H_D#_62 H_DSTBP#[3:0] 3
54.9_4 Impedance 55ohm H_D#63 AH13 L7 H_DSTBP#0
H_D#_63 H_DSTBP#_0 H_DSTBP#1
H_DSTBP#_1 K2
H_SCOMP# AC2 H_DSTBP#2
H_SWING H_DSTBP#_2 H_DSTBP#3
B3 H_SWING H_DSTBP#_3 AJ10
H_RCOMP C2
+1.05V_GMCH H_RCOMP H_REQ#[4:0] 3
M14 H_REQ#0
H_SCOMP H_REQ#_0 H_REQ#1
W1 H_SCOMP H_REQ#_1 E13
H_SCOMP# W2 A11 H_REQ#2
H_SCOMP# H_REQ#_2 H_REQ#3
H_REQ#_3 H13
B6 B12 H_REQ#4
3 H_CPURST# H_CPURST# H_REQ#_4
R392 E5
3 H_CPUSLP# H_CPUSLP# H_RS#[2:0] 3
E12 H_RS#0
1K_4 H_RS#_0 H_RS#1
H_RS#_1 D7
D8 H_RS#2
H_AVREF H_RS#_2
B9 H_AVREF
H_DVREF A9 H_DVREF
A A
R391 C473 <check list> CRESTLINE_1p0
0.1U close to B9
2K_4 .1U_4
PROJECT : ZU1
A1A:(9/20) remove R74 (0 ohm) Size Document Number Rev
GMCH HOST(1 of 7) 3B

5 4 3 2 1
5 4 3 2 1
U29B
MCH_RSVD1 P36 U29C +VCC_PEG

T39 RSVD1
MCH_RSVD2 P37 AV29
T46 RSVD2 SM_CK_0 M_CLK_DDR0 13
MCH_RSVD3 R35 BB23 J40
T36 RSVD3 SM_CK_1 M_CLK_DDR1 13 20 INT_LVDS_PWM L_BKLT_CTRL
MCH_RSVD4 N35 BA25 H39 N43 EXP_A_COMPX R164 24.9_4
T43 RSVD4 SM_CK_3 M_CLK_DDR3 13 20 INT_LVDS_BLON L_BKLT_EN PEG_COMPI
MCH_RSVD5 AR12 AV23 +3V R146 10K_4 E39 M43
T9 RSVD5 SM_CK_4 M_CLK_DDR4 13 L_CTRL_CLK PEG_COMPO
MCH_RSVD6 AR13 R154 10K_4 E40
T12 RSVD6 L_CTRL_DATA
MCH_RSVD7 AM12 AW30 C37
T8 RSVD7 SM_CK#_0 M_CLK_DDR#0 13 20 INT_LVDS_EDIDCLK L_DDC_CLK
MCH_RSVD8 AN13 BA23 D35 J51
T11 RSVD8 SM_CK#_1 M_CLK_DDR#1 13 20 INT_LVDS_EDIDDATA L_DDC_DATA PEG_RX#_0
MCH_RSVD9 J12 AW25 K40 L51 PEG_RXN1 PEG_RXN1 21
T10 RSVD9 SM_CK#_3 M_CLK_DDR#3 13 20 INT_LVDS_DIGON L_VDD_EN PEG_RX#_1
RSVD
MCH_RSVD10 AR37 AW23 N47
T45 RSVD10 SM_CK#_4 M_CLK_DDR#4 13 PEG_RX#_2
MCH_RSVD11 AM36 R148 2.4K_4 LVDS_IBG L41 T45
T42 RSVD11 LVDS_IBG PEG_RX#_3
MCH_RSVD12 AL36 BE29 L43 T50
T38 RSVD12 SM_CKE_0 M_CKE0 12,13 T47 LVDS_VBG PEG_RX#_4
MCH_RSVD13 AM37 AY32 N41 U40
D T40 RSVD13 SM_CKE_1 M_CKE1 12,13 LVDS_VREFH PEG_RX#_5 D
MCH_RSVD14 D20 BD39 N40 Y44
T21 RSVD14 SM_CKE_3 M_CKE3 12,13 LVDS_VREFL PEG_RX#_6
SM_CKE_4 BG37 M_CKE4 12,13 20 INT_TXLCLKOUT- D46 LVDSA_CLK# PEG_RX#_7 Y40
20 INT_TXLCLKOUT+ C45 LVDSA_CLK PEG_RX#_8 AB51
C157 .1U_4 BG20 D44 W49
SM_CS#_0 M_CS#0 12,13 LVDSB_CLK# PEG_RX#_9
SM_CS#_1 BK16 M_CS#1 12,13 E42 LVDSB_CLK PEG_RX#_10 AD44
LVDS
SM_CS#_2 BG16 M_CS#2 12,13 PEG_RX#_11 AD40
MCH_RSVD20 H10 BE13 G51 AG46
T7 RSVD20 SM_CS#_3 M_CS#3 12,13 20 INT_TXLOUT0- LVDSA_DATA#_0 PEG_RX#_12
MCH_RSVD21 B51 E51 AH49
MUXING
T103 RSVD21 20 INT_TXLOUT1- LVDSA_DATA#_1 PEG_RX#_13
MCH_RSVD22 BJ20 BH18 F49 AG45
T84 RSVD22 SM_ODT_0 M_ODT0 12,13 20 INT_TXLOUT2- LVDSA_DATA#_2 PEG_RX#_14
MCH_RSVD23 BK22 BJ15 AG41
GRAPHICS
T86 RSVD23 SM_ODT_1 M_ODT1 12,13 PEG_RX#_15
MCH_RSVD24 BF19 BJ14
T13 RSVD24 SM_ODT_2 M_ODT2 12,13
MCH_RSVD25 BH20 BE16 G50 J50
T25 RSVD25 SM_ODT_3 M_ODT3 12,13 20 INT_TXLOUT0+ LVDSA_DATA_0 PEG_RX_0
MCH_RSVD26 BK18 E50 L50 PEG_RXP1 PEG_RXP1 21
T83 RSVD26 20 INT_TXLOUT1+ LVDSA_DATA_1 PEG_RX_1
MCH_RSVD27 BJ18 BL15 M_RCOMP F48 M47
T82 RSVD27 SM_RCOMP 20 INT_TXLOUT2+ LVDSA_DATA_2 PEG_RX_2
MCH_RSVD28 BF23 BK14 M_RCOMP# U44
T30 RSVD28 SM_RCOMP# SMDDR_VREF PEG_RX_3
MCH_RSVD29 BG23 T49
T15 RSVD29 PEG_RX_4
MCH_RSVD30 BC23 BK31 SM_RCOMP_VOH G44 T41
T33 RSVD30 SM_RCOMP_VOH LVDSB_DATA#_0 PEG_RX_5
MCH_RSVD31 BD24 BL31 SM_RCOMP_VOL B47 W45
DDR
T17 RSVD31 SM_RCOMP_VOL LVDSB_DATA#_1 PEG_RX_6
12,13 M_A_A14 BJ29 RSVD32 B45 LVDSB_DATA#_2 PEG_RX_7 W41
12,13 M_B_A14 BE24 RSVD33 SM_VREF_0 AR49 SMDDR_VREF_MCH R83 0_6
PEG_RX_8 AB50
MCH_RSVD34 BH39 AW4 Y48
T44 RSVD34 SM_VREF_1 PEG_RX_9
MCH_RSVD35 AW20 R84 *10K_6 +1.8VSUS_GMCH E44 AC45
T18 RSVD35 LVDSB_DATA_0 PEG_RX_10
MCH_RSVD36 BK20 R82 *10K_6 A47 AC41
MCH_RSVD37 C48 A45 AH47
PCI-EXPRESS
MCH_RSVD38 D47 B42 DREFCLK AG49
T51 RSVD38 DPLL_REF_CLK DREFCLK 2 PEG_RX_13
MCH_RSVD39 B44 C42 DREFCLK# AH45
T95 RSVD39 DPLL_REF_CLK# DREFCLK# 2 PEG_RX_14
MCH_RSVD40 C44 H48 DREFSSCLK AG42
T96 RSVD40 DPLL_REF_SSCLK DREFSSCLK 2 PEG_RX_15
MCH_RSVD41 A35 H47 DREFSSCLK#
T90 RSVD41 DPLL_REF_SSCLK# DREFSSCLK# 2
MCH_RSVD42 B37 INT_TV_COMP E27 N45 C_PEG_TXN0
T91 RSVD42 20 INT_TV_COMP TVA_DAC PEG_TX#_0
MCH_RSVD43 B36 K44 INT_TV_Y/G G27 U39 C_PEG_TXN1
T89 RSVD43 PEG_CLK CLK_PCIE_3GPLL 2 20 INT_TV_Y/G TVB_DAC PEG_TX#_1
CLK
MCH_RSVD44 B34 K45 INT_TV_C/R K27 U47 C_PEG_TXN2
T88 RSVD44 PEG_CLK# CLK_PCIE_3GPLL# 2 20 INT_TV_C/R TVC_DAC PEG_TX#_2
TV
MCH_RSVD45 C34 N51 C_PEG_TXN3
C T87 RSVD45 PEG_TX#_3 C
DMI_TXN[3:0] 15 F27 TVA_RTN PEG_TX#_4 R50
C2A:(12/26) Intel schematic Rev1.5: J27 T42
change ball-C48 from RSVD48 to LVDSA_DATA#_3 DMI_TXN0 TVB_RTN PEG_TX#_5
DMI_RXN_0 AN47 L27 TVC_RTN PEG_TX#_6 Y43
change ball-D47 from RSVD47 to LVDSA_DATA_3 AJ38 DMI_TXN1 W46
change ball-B44 from RSVD39 to LVDSB_DATA#_3 DMI_RXN_1 DMI_TXN2 R417 2.2K_4 TV_DCONSEL_0 PEG_TX#_7
DMI_RXN_2 AN42 +3V M35 TV_DCONSEL_0 PEG_TX#_8 W38
change ball-C44 from RSVD40 to LVDSB_DATA_3 AN46 DMI_TXN3 R415 2.2K_4 TV_DCONSEL_1 P33 AD39
DMI_RXN_3 DMI_TXP[3:0] 15 TV_DCONSEL_1 PEG_TX#_9
PEG_TX#_10 AC46
AM47 DMI_TXP0 R153 *0_4 AC49
DMI_RXP_0 DMI_TXP1 R145 *0_4 PEG_TX#_11
2 MCH_BSEL0 P27 CFG_0 DMI_RXP_1 AJ39 PEG_TX#_12 AC42
N27 AN41 DMI_TXP2 AH39
2 MCH_BSEL1 CFG_1 DMI_RXP_2 PEG_TX#_13
N24 AN45 DMI_TXP3 AE49
2 MCH_BSEL2 CFG_2 DMI_RXP_3 DMI_RXN[3:0] 15 PEG_TX#_14
MCH_CFG_3 C21 AH44
T24 CFG_3 PEG_TX#_15
MCH_CFG_4 C23 AJ46 DMI_RXN0
T26 CFG_4 DMI_TXN_0
11 MCH_CFG_5 F23 CFG_5 DMI_TXN_1 AJ41 DMI_RXN1 19 INT_CRT_BLU
INT_CRT_BLU H32 CRT_BLUE PEG_TX_0 M45 C_PEG_TXP0
MCH_CFG_6 N23 AM40 DMI_RXN2 G32 T38 C_PEG_TXP1
T19 CFG_6 DMI_TXN_2 CRT_BLUE# PEG_TX_1
MCH_CFG_7 G23 AM44 DMI_RXN3 INT_CRT_GRN K29 T46 C_PEG_TXP2
T27 CFG_7 DMI_TXN_3 DMI_RXP[3:0] 15 19 INT_CRT_GRN CRT_GREEN PEG_TX_2
MCH_CFG_8 J20 J29 N50 C_PEG_TXP3
DMI
T22 CFG_8 CRT_GREEN# PEG_TX_3

CFG
11 MCH_CFG_9 C20 CFG_9 DMI_TXP_0 AJ47 DMI_RXP0 19 INT_CRT_RED

INT_CRT_RED F29 CRT_RED PEG_TX_4 R51
VGA
MCH_CFG_10 R24 AJ42 DMI_RXP1 E29 U43
T32 CFG_10 DMI_TXP_1 CRT_RED# PEG_TX_5
MCH_CFG_11 L23 AM39 DMI_RXP2 W42
T23 CFG_11 DMI_TXP_2 PEG_TX_6
11 MCH_CFG_12 J23 CFG_12 DMI_TXP_3 AM43 DMI_RXP3 PEG_TX_7 Y47
11 MCH_CFG_13 E23 CFG_13 19 INT_CRT_DDCCLK K33 CRT_DDC_CLK PEG_TX_8 Y39
MCH_CFG_14 E20 G35 AC38
T20 CFG_14 19 INT_CRT_DDCDAT CRT_DDC_DATA PEG_TX_9
MCH_CFG_15 K23 R416 30_4 HSYNC1 F33 AD47
T28 CFG_15 19 INT_HSYNC CRT_HSYNC PEG_TX_10
11 MCH_CFG_16 M20 R411 1.3K_6 CRTIREF C32 AC50
MCH_CFG_17 CFG_16 R418 30_4 VSYNC1 E33 CRT_TVO_IREF PEG_TX_11
T29 M24 19 INT_VSYNC AD43
GRAPHICS VID
MCH_CFG_18 CFG_17 CRT_VSYNC PEG_TX_12

T34 L32 CFG_18 PEG_TX_13 AG39
11 MCH_CFG_19 N33 CFG_19 PEG_TX_14 AE50
11 MCH_CFG_20 L35 CFG_20 PEG_TX_15 AH43
E35 T37 CRESTLINE_1p0

B R158 0_4 PM_BMBUSY#_R GFX_VID_0 T93 B
16 PM_BMBUSY# G41 PM_BM_BUSY# GFX_VID_1 A39
3,14,35 ICH_DPRSTP# R424 0_4 ICH_DPRSTP#_R L39 C38 T92
PM_DPRSTP# GFX_VID_2 T94
13 PM_EXTTS#0 L36 PM_EXT_TS#_0 GFX_VID_3 B39
PM
13 PM_EXTTS#1 R147 0_4 PM_EXTTS#1_R J36 E36 T41

PM_EXT_TS#_1 GFX_VR_EN
3,16,35 DELAY_VR_PWRGOOD AW49 PWROK
R115 100_4RST_IN#_MCH AV20
15 PLTRST#_NB RSTIN# +1.25V_AXD
3,14 PM_THRMTRIP# R116 PM_THRMTRIP#_GMCH N20
*0_4
R149 0_4PM_DPRSLPVR_GMCH G36 THERMTRIP# C_PEG_TXP0 C270 .1U_4
16,35 PM_DPRSLPVR DPRSLPVR SDVOB_R+ 21
C_PEG_TXN0 C272 .1U_4 SDVOB_R- 21
AM49 R155 C_PEG_TXP1 C278 .1U_4 SDVOB_G+ 21
CL_CLK CL_CLK0 16
AK50 C_PEG_TXN1 C277 .1U_4 SDVOB_G- 21
CL_DATA CL_DATA0 16
T105 TP_MCH_NC1 BJ51 AT43 1K_4 C_PEG_TXP2 C276 .1U_4 SDVOB_B+ 21
NC_1 CL_PWROK MPWROK 16,28
TP_MCH_NC2 C_PEG_TXN2 C275 .1U_4
ME
T106 BK51 AN49 CL_RST#0 16 SDVOB_B- 21

TP_MCH_NC3 NC_2 CL_RST#
T107 BK50 NC_3 CL_VREF AM50 +1.25V_CL_VREF C_PEG_TXP3 C273 .1U_4 SDVOB_CLK+ 21
T102 TP_MCH_NC4 BL50 C_PEG_TXN3 C274 .1U_4 SDVOB_CLK- 21
TP_MCH_NC5 NC_4
T99 BL49
TP_MCH_NC6 NC_5 C246 R161
T80 BL3
TP_MCH_NC7 NC_6
T78 BL2 NC_7
NC
T76 TP_MCH_NC8 BK1 .1U_4 392_6

TP_MCH_NC9 NC_8
T75 BJ1 H35 SDVO_CTRLCLK 21
TP_MCH_NC10 NC_9 SDVO_CTRL_CLK
T77 E1 K36
MISC
NC_10 SDVO_CTRL_DATA SDVO_CTRLDATA 21

T81 TP_MCH_NC11 A5 G39 CLK_MCH_OE#
NC_11 CLK_REQ# CLK_MCH_OE# 2
T104 TP_MCH_NC12 C51 G40
NC_12 ICH_SYNC# MCH_ICH_SYNC# 16
T100 TP_MCH_NC13 B50
TP_MCH_NC14 NC_13
T101 A50
TP_MCH_NC15 NC_14
T97 A49 NC_15 TEST_1 A37 GMCH_TEST1 R143 0_4
T79 TP_MCH_NC16 BK2 R32 GMCH_TEST2 R129 20K_4
NC_16 TEST_2
CRESTLINE_1p0
+1.8VSUS_GMCH R133 1K_4 SM_RCOMP_VOH

A A
R117 150_4 INT_TV_COMP
R114 C207 C177
M_RCOMP# +1.8VSUS_GMCH +3V R118 150_4 INT_TV_Y/G
3.01K_4 .01U_4 2.2U_6
R113 150_4 INT_TV_C/R
R105 SM_RCOMP_VOL
R106 R423 10K_4 CLK_MCH_OE#
20_4 PROJECT : ZU1
20_4 R421 10K_4 PM_EXTTS#0 R119 150_4 INT_CRT_BLU
R123 C194 C180
M_RCOMP R419 10K_4 PM_EXTTS#1 R122 150_4 INT_CRT_GRN
Size
Document Number Rev
1K_4 .01U_4 2.2U_6
R126 150_4 INT_CRT_RED GMCH DMI/VIDEO(2 of 7) 3B
5 4 3 2 1
5 4 3 2 1
NB(Memory controller)
13 M_A_DQ[63:0] 13 M_B_DQ[63:0]
U29D U29E
D M_A_DQ0 AR43 BB19 M_B_DQ0 AP49 AY17 D
SA_DQ_0 SA_BS_0 M_A_BS#0 12,13 SB_DQ_0 SB_BS_0 M_B_BS#0 12,13
M_A_DQ1 AW44 BK19 M_B_DQ1 AR51 BG18
M_A_DQ2 BA45 BF29 M_B_DQ2 AW50 BG36
M_A_DQ3 AY46 M_B_DQ3 AW51
SA_DQ_3 M_A_CAS# 12,13 SB_DQ_3 M_B_CAS# 12,13
M_A_DQ4 AR41 BL17 M_B_DQ4 AN51 BE17
M_A_DQ5 SA_DQ_4 SA_CAS# M_B_DQ5 SB_DQ_4 SB_CAS#
AR45 SA_DQ_5 M_A_DM[7:0] 13 AN50 SB_DQ_5 M_B_DM[7:0] 13
M_A_DQ6 AT42 AT45 M_A_DM0 M_B_DQ6 AV50 AR50 M_B_DM0
M_A_DQ7 SA_DQ_6 SA_DM_0 M_A_DM1 M_B_DQ7 SB_DQ_6 SB_DM_0 M_B_DM1
AW47 SA_DQ_7 SA_DM_1 BD44 AV49 SB_DQ_7 SB_DM_1 BD49
M_A_DQ8 BB45 BD42 M_A_DM2 M_B_DQ8 BA50 BK45 M_B_DM2
BF48 SA_DQ_9 SA_DM_3 AW38 BB50 SB_DQ_9 SB_DM_3 BL39
M_A_DQ10 BG47 AW13 M_A_DM4 M_B_DQ10 BA49 BH12 M_B_DM4
BJ45 SA_DQ_11 SA_DM_5 BG8 BE50 SB_DQ_11 SB_DM_5 BJ7
M_A_DQ12 BB47 AY5 M_A_DM6 M_B_DQ12 BA51 BF3 M_B_DM6
BG50 SA_DQ_13 SA_DM_7 AN6 AY49 SB_DQ_13 SB_DM_7 AW2
M_A_DQ14 BH49 M_B_DQ14 BF50
SA_DQ_14 M_A_DQS[7:0] 13 SB_DQ_14 M_B_DQS[7:0] 13
M_A_DQ15 BE45 AT46 M_A_DQS0 M_B_DQ15 BF49 AT50 M_B_DQS0
A
SA_DQ_15 SA_DQS_0 SB_DQ_15 SB_DQS_0
B
M_A_DQ16 AW43 BE48 M_A_DQS1 M_B_DQ16 BJ50 BD50 M_B_DQS1
M_A_DQ17 SA_DQ_16 SA_DQS_1 M_A_DQS2 M_B_DQ17 SB_DQ_16 SB_DQS_1 M_B_DQS2
BE44 SA_DQ_17 SA_DQS_2 BB43 BJ44 SB_DQ_17 SB_DQS_2 BK46
M_A_DQ18 BG42 BC37 M_A_DQS3 M_B_DQ18 BJ43 BK39 M_B_DQS3
BE40 SA_DQ_19 SA_DQS_4 BB16 BL43 SB_DQ_19 SB_DQS_4 BJ12
M_A_DQ20 M_A_DQS5 M_B_DQ20 M_B_DQS5
MEMORY
BF44 SA_DQ_20 SA_DQS_5 BH6 BK47 SB_DQ_20 SB_DQS_5 BL7
MEMORY
M_A_DQ21 BH45 BB2 M_A_DQS6 M_B_DQ21 BK49 BE2 M_B_DQS6
BG40 SA_DQ_22 SA_DQS_7 AP3 M_A_DQS#[7:0] 13 BK43 SB_DQ_22 SB_DQS_7 AV2 M_B_DQS#[7:0] 13
M_A_DQ23 BF40 AT47 M_A_DQS#0 M_B_DQ23 BK42 AU50 M_B_DQS#0
M_A_DQ24 SA_DQ_23 SA_DQS#_0 M_A_DQS#1 M_B_DQ24 SB_DQ_23 SB_DQS#_0 M_B_DQS#1
C
AR40 SA_DQ_24 SA_DQS#_1 BD47 BJ41 SB_DQ_24 SB_DQS#_1 BC50 C
M_A_DQ25 AW40 BC41 M_A_DQS#2 M_B_DQ25 BL41 BL45 M_B_DQS#2
AT39 SA_DQ_26 SA_DQS#_3 BA37 BJ37 SB_DQ_26 SB_DQS#_3 BK38
M_A_DQ27 AW36 BA16 M_A_DQS#4 M_B_DQ27 BJ36 BK12 M_B_DQS#4
AW41 SA_DQ_28 SA_DQS#_5 BH7 BK41 SB_DQ_28 SB_DQS#_5 BK7
M_A_DQ29 AY41 BC1 M_A_DQS#6 M_B_DQ29 BJ40 BF2 M_B_DQS#6
AV38 SA_DQ_30 SA_DQS#_7 AP2 BL35 SB_DQ_30 SB_DQS#_7 AV3
M_A_DQ31 AT38 M_B_DQ31 BK37
SA_DQ_31 M_A_A[13:0] 12,13 SB_DQ_31 M_B_A[13:0] 12,13
M_A_DQ32 AV13 BJ19 M_A_A0 M_B_DQ32 BK13 BC18 M_B_A0
SA_DQ_32 SA_MA_0 SB_DQ_32 SB_MA_0
SYSTEM
M_A_DQ33 AT13 BD20 M_A_A1 M_B_DQ33 BE11 BG28 M_B_A1

SA_DQ_33 SA_MA_1 SB_DQ_33 SB_MA_1
SYSTEM
M_A_DQ34 AW11 BK27 M_A_A2 M_B_DQ34 BK11 BG25 M_B_A2
M_A_DQ35 SA_DQ_34 SA_MA_2 M_A_A3 M_B_DQ35 SB_DQ_34 SB_MA_2 M_B_A3
AV11 SA_DQ_35 SA_MA_3 BH28 BC11 SB_DQ_35 SB_MA_3 AW17
M_A_DQ36 AU15 BL24 M_A_A4 M_B_DQ36 BC13 BF25 M_B_A4
AT11 SA_DQ_37 SA_MA_5 BK28 BE12 SB_DQ_37 SB_MA_5 BE25
M_A_DQ38 BA13 BJ27 M_A_A6 M_B_DQ38 BC12 BA29 M_B_A6
BA11 SA_DQ_39 SA_MA_7 BJ25 BG12 SB_DQ_39 SB_MA_7 BC28
M_A_DQ40 BE10 BL28 M_A_A8 M_B_DQ40 BJ10 AY28 M_B_A8
BD10 SA_DQ_41 SA_MA_9 BA28 BL9 SB_DQ_41 SB_MA_9 BD37
M_A_DQ42 BD8 BC19 M_A_A10 M_B_DQ42 BK5 BG17 M_B_A10
AY9 SA_DQ_43 SA_MA_11 BE28 BL5 SB_DQ_43 SB_MA_11 BE37
M_A_DQ44 BG10 BG30 M_A_A12 M_B_DQ44 BK9 BA39 M_B_A12
AW9 SA_DQ_45 SA_MA_13 BJ16 BK10 SB_DQ_45 SB_MA_13 BG13
DDR
M_A_DQ46 BD7 M_B_DQ46 BJ8
DDR
M_A_DQ47 SA_DQ_46 M_B_DQ47 SB_DQ_46
BB9 SA_DQ_47 BJ6 SB_DQ_47 SB_RAS# AV16 M_B_RAS# 12,13
M_A_DQ48 BB5 BE18 M_B_DQ48 BF4 AY18 TP_SB_RCVEN#
SA_DQ_48 SA_RAS# M_A_RAS# 12,13 SB_DQ_48 SB_RCVEN# T14
B M_A_DQ49 AY7 AY20 TP_SA_RCVEN# M_B_DQ49 BH5 B
SA_DQ_49 SA_RCVEN# T31 SB_DQ_49
M_A_DQ50 AT5 M_B_DQ50 BG1 BC17
SA_DQ_50 SB_DQ_50 SB_WE# M_B_WE# 12,13
M_A_DQ51 AT7 BA19 M_B_DQ51 BC2
SA_DQ_51 SA_WE# M_A_WE# 12,13 SB_DQ_51
M_A_DQ52 AY6 M_B_DQ52 BK3
BB7 SA_DQ_53 BE4 SB_DQ_53
M_A_DQ54 AR5 M_B_DQ54 BD3
AR8 SA_DQ_55 BJ2 SB_DQ_55
M_A_DQ56 AR9 M_B_DQ56 BA3
AN3 SA_DQ_57 BB3 SB_DQ_57
M_A_DQ58 AM8 M_B_DQ58 AR1
AN10 SA_DQ_59 AT3 SB_DQ_59
M_A_DQ60 AT9 M_B_DQ60 AY2
AN9 SA_DQ_61 AY3 SB_DQ_61
M_A_DQ62 AM9 M_B_DQ62 AU2
AN11 SA_DQ_63 AT2 SB_DQ_63
CRESTLINE_1p0 CRESTLINE_1p0
A A
PROJECT : ZU1
MCH DDR(3 of 7) 3B

5 4 3 2 1
5 4 3 2 1
+3V_VCCSYNC +1.05V_VCC_GMCH
NB(Power-1) R136 10_4 VCCGFPLLOW D13 1 2 PDZ5.6B
+1.05V_VCC_GMCH
+VGFX_CORE_INT ADD 10ohm
U29G THEY ONLY USE IN UMA (GM OR GML)
+1.05V_VCC_GMCH
AT35 U29F
VCC_1
AT34 VCC_2 VCC_AXG_NCTF_1 T17
AH28 VCC_3 VCC_AXG_NCTF_2 T18 +1.05V AB33 VCC_NCTF_1
AC32 VCC_5 VCC_AXG_NCTF_3 T19 AB36 VCC_NCTF_2
D
AC31 VCC_4 VCC_AXG_NCTF_4 T21 AB37 VCC_NCTF_3 D
AK32 T22 + C95 C225 C199 C216 C208 AC33 T27
VCC_6 VCC_AXG_NCTF_5 A1A(10/23): Short R116 VCC_NCTF_4 VSS_NCTF_1
AJ31 VCC_7 VCC_AXG_NCTF_6 T23 AC35 VCC_NCTF_5 VSS_NCTF_2 T37
AJ28 T25 330U_7343 22U_8 .22U_4 .22U_4 .1U_4 AC36 U24
VCC_8 VCC_AXG_NCTF_7 VCC_NCTF_6 VSS_NCTF_3
AH32 VCC_9 VCC_AXG_NCTF_8 U15 AD35 VCC_NCTF_7 VSS_NCTF_4 U28
VCC CORE
AH31 VCC_10 VCC_AXG_NCTF_9 U16 AD36 VCC_NCTF_8 VSS_NCTF_5 V31
AH29 VCC_11 VCC_AXG_NCTF_10 U17 AF33 VCC_NCTF_9 VSS_NCTF_6 V35
AF32 VCC_12 VCC_AXG_NCTF_11 U19 AF36 VCC_NCTF_10 VSS_NCTF_7 AA19
VCC_AXG_NCTF_12 U20 AH33 VCC_NCTF_11 VSS_NCTF_8 AB17
VSS NCTF
VCC_AXG_NCTF_13 U21 AH35 VCC_NCTF_12 VSS_NCTF_9 AB35
VCC_AXG_NCTF_14 U23 AH36 VCC_NCTF_13 VSS_NCTF_10 AD19
R127 0_4+1.05V_VCC_GMCH_VCC13 R30 U26 A1A:(9/26) Change +VCC_CFXCORE_INT to +1.05V AH37 AD37
VCC_13 VCC_AXG_NCTF_15 +1.05V VCC_NCTF_14 VSS_NCTF_11
VCC_AXG_NCTF_16 V16 AJ33 VCC_NCTF_15 VSS_NCTF_12 AF17
V17 A1A(10/23): Short R115,R117 AJ35 AF35
VCC_AXG_NCTF_17 VCC_NCTF_16 VSS_NCTF_13
VCC_AXG_NCTF_18 V19 AK33 VCC_NCTF_17 VSS_NCTF_14 AK17
VCC_AXG_NCTF_19 V20 AK35 VCC_NCTF_18 VSS_NCTF_15 AM17
V21 +VGFX_CORE_INT AK36 AM24
VCC_AXG_NCTF_20 VCC_NCTF_19 VSS_NCTF_16
VCC_AXG_NCTF_21 V23 AK37 VCC_NCTF_20 VSS_NCTF_17 AP26
VCC_AXG_NCTF_22 V24 AD33 VCC_NCTF_21 VSS_NCTF_18 AP28
+1.8VSUS_GMCH Y15 AJ36 AR15
+1.8VSUS
POWER VCC_AXG_NCTF_23 VCC_NCTF_22 VSS_NCTF_19
VCC NCTF
VCC_AXG_NCTF_24 Y16 AM35 VCC_NCTF_23 VSS_NCTF_20 AR19
VCC_AXG_NCTF_25 Y17 AL33 VCC_NCTF_24 VSS_NCTF_21 AR28
AU32 Y19 + C464 + C463 C156 C150 C164 C182 C151 C155 AL35
VCC_SM_1 VCC_AXG_NCTF_26 VCC_NCTF_25
AU33 VCC_SM_2 VCC_AXG_NCTF_27 Y20 AA33 VCC_NCTF_26
AU35 Y21 330U_7343 .47U_6 1U_6 10U_8 22U_8 .1U_4 .1U_4 AA35
VCC_SM_3 VCC_AXG_NCTF_28 330U_7343 VCC_NCTF_27
AV33 VCC_SM_4 VCC_AXG_NCTF_29 Y23 AA36 VCC_NCTF_28
C210 + C144 C215 C232 AW33 Y24 AP35
AW35 VCC_SM_6 VCC_AXG_NCTF_31 Y26 AP36 VCC_NCTF_30
.1U_4 330U_7343 22U_8 22U_8 AY35 Y28 AR35
BA32 VCC_SM_8 VCC_AXG_NCTF_33 Y29 AR36 VCC_NCTF_32
C BA33 VCC_SM_9 VCC_AXG_NCTF_34 AA16 Y32 VCC_NCTF_33
C
BA35 AA17 Y33
BB33
BC32
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
AB16
AB19
Y35
Y36
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
POWER
BC33 VCC_SM_13 VCC_AXG_NCTF_38 AC16 Y37 VCC_NCTF_37 VSS_SCB1 A3
BC35 VCC_SM_14 VCC SM VCC_AXG_NCTF_39 AC17 T30 VCC_NCTF_38 VSS_SCB2 B2
VSS SCB
BD32 VCC_SM_15 VCC_AXG_NCTF_40 AC19 T34 VCC_NCTF_39 VSS_SCB3 C1
BD35 VCC_SM_16 VCC_AXG_NCTF_41 AD15 T35 VCC_NCTF_40 VSS_SCB4 BL1
BE32 VCC_SM_17 VCC_AXG_NCTF_42 AD16 U29 VCC_NCTF_41 VSS_SCB5 BL51
BE33 VCC_SM_18 VCC_AXG_NCTF_43 AD17 U31 VCC_NCTF_42 VSS_SCB6 A51
BE35
BF33
VCC_SM_19 VCC GFX NCTF VCC_AXG_NCTF_44 AF16
AF19
U32
U33
VCC_NCTF_43
BF34 VCC_SM_21 VCC_AXG_NCTF_46 AH15 U35 VCC_NCTF_45
BG32 AH16 U36 +1.25V +1.05V
BG33 VCC_SM_23 VCC_AXG_NCTF_48 AH17 V32 VCC_NCTF_47
BG35 AH19 V33 R576 R578
BH32 VCC_SM_25 VCC_AXG_NCTF_50 AJ16 V36 VCC_NCTF_49
BH34 VCC_SM_26 VCC_AXG_NCTF_51 AJ17 V37 VCC_NCTF_50
BH35 AJ19 *0_6 0_6
VCC_SM_27 VCC_AXG_NCTF_52
BJ32 VCC_SM_28 VCC_AXG_NCTF_53 AK16 VCC_AXM_1 AT33
BJ33 VCC_SM_29 VCC_AXG_NCTF_54 AK19 VCC_AXM_2 AT31
+1.05V
VCC AXM
BJ34 VCC_SM_30 VCC_AXG_NCTF_55 AL16 VCC_AXM_3 AK29
BK32 VCC_SM_31 VCC_AXG_NCTF_56 AL17 VCC_AXM_4 AK24
BK33 VCC_SM_32 VCC_AXG_NCTF_57 AL19 VCC_AXM_5 AK23
BK34 VCC_SM_33 VCC_AXG_NCTF_58 AL20 AL24 VCC_AXM_NCTF_1 VCC_AXM_6 AJ26
BK35 VCC_SM_34 VCC_AXG_NCTF_59 AL21 AL26 VCC_AXM_NCTF_2 VCC_AXM_7 AJ23
BL33 VCC_SM_35 VCC_AXG_NCTF_60 AL23 AL28 VCC_AXM_NCTF_3
AU30 AM15 C188 C179 C206 C186 C178 C189 AM26
VCC_SM_36 VCC_AXG_NCTF_61 VCC_AXM_NCTF_4
VCC AXM NCTF

VCC_AXG_NCTF_62 AM16 AM28 VCC_AXM_NCTF_5
+VGFX_CORE_INT AM19 22U_8 .22U_4 .22U_4 .1U_4 .1U_4 .1U_4 AM29
B VCC_AXG_NCTF_63 VCC_AXM_NCTF_6 B
R20 VCC_AXG_1 VCC_AXG_NCTF_66 AM23 AM33 VCC_AXM_NCTF_9
T14 VCC_AXG_2 VCC_AXG_NCTF_67 AP15 AP29 VCC_AXM_NCTF_10
W13 VCC_AXG_3 VCC_AXG_NCTF_68 AP16 AP31 VCC_AXM_NCTF_11
W14 VCC_AXG_4 VCC_AXG_NCTF_69 AP17 AP32 VCC_AXM_NCTF_12
Y12 VCC_AXG_5 VCC_AXG_NCTF_70 AP19 AP33 VCC_AXM_NCTF_13
AA20 VCC_AXG_6 VCC_AXG_NCTF_71 AP20 AL29 VCC_AXM_NCTF_14
AA28 VCC_AXG_9 VCC_AXG_NCTF_74 AP24 AR31 VCC_AXM_NCTF_17
AB21 VCC_AXG_10 VCC_AXG_NCTF_75 AR20 AR32 VCC_AXM_NCTF_18
AB24 VCC_AXG_11 VCC_AXG_NCTF_76 AR21 AR33 VCC_AXM_NCTF_19
AB29 VCC_AXG_12 VCC_AXG_NCTF_77 AR23
AC20 VCC_AXG_13 VCC_AXG_NCTF_78 AR24
VCC GFX
AC21 VCC_AXG_14 VCC_AXG_NCTF_79 AR26

AC23 VCC_AXG_15 VCC_AXG_NCTF_80 V26
AC24 V28 CRESTLINE_1p0
VCC_AXG_16 VCC_AXG_NCTF_81
AC26 VCC_AXG_17 VCC_AXG_NCTF_82 V29
AC28 Y31 C2A:(12/12)Change Crestline VCC_AXM to 1.25V,
VCC_AXG_18 VCC_AXG_NCTF_83 reference to SR ww48 MoW.
AC29 VCC_AXG_19
AD20 reserved 0 ohm resister (R576)
VCC_AXG_20
AD23 VCC_AXG_21
AD24 AW45 VCCSM_LF1 C2A:(12/12)Change Crestline VCC_AXM from +1.25V to +1.05V,
VCC_AXG_22 VCC_SM_LF1 VCCSM_LF2 reserved 0 ohm resister (R578)
AD28 VCC_AXG_23 VCC_SM_LF2 BC39
VCC SM LF
AF21 BE39 VCCSM_LF3

VCC_AXG_24 VCC_SM_LF3 VCCSM_LF4
AF26 VCC_AXG_25 VCC_SM_LF4 BD17
AA31 BD4 VCCSM_LF5
VCC_AXG_26 VCC_SM_LF5 VCCSM_LF6
AH20 VCC_AXG_27 VCC_SM_LF6 AW8
A AH21 AT6 VCCSM_LF7 A
VCC_AXG_28 VCC_SM_LF7
AH23 VCC_AXG_29
AH24 C145 C147 C136 C158 C238 C224 C252
VCC_AXG_30
AH26 VCC_AXG_31
AD31 .1U_4 .1U_4 .22U_4 .22U_4 .47U_6 1U_6 1U_6
VCC_AXG_32
AJ20
AN14
VCC_AXG_33
VCC_AXG_34
PROJECT : ZU1
GMCH Power-1(4 of 7) 3B
CRESTLINE_1p0
5 4 3 2 1
5 4 3 2 1
NB(Power-2) +3V_VCCSYNC
CRT/TV Disable/Enable guideline
LVDS Disable/Enable guideline
External VGA with EV@part,Internal VGA with IV@ part
+3V R130 0_6
If SDVO Disable If SDVO enable If SDVO enable
<Description> C205 Ball Enable Disable Ball Enable Disable Signal LVDS Disable LVDS Disable LVDS enable
<FAE>
INT VGA disable .1U_4 VCCA_CRT 3.3V GND VCCA_C_TVO 3.3V GND VCCD_LVDS GND 1.8V 1.8V
+1.25V L53 10UH_8
VCCSYNC connect to GND VCCD_CRT 1.5V GND VCCD_TVO 1.5V 1.5V VCCA_LVDS GND GND 1.8V
+ C527 C262 VCCDQ_CRT 1.5V GND VCCABG_DAC 3.3V GND VCCTX_LVDS GND GND 1.8V
+3V L18 BKP1608HS181-T_6
470U_7343 .1U_4 VCCA_A_TVO 3.3V GND VSSABG_DAC GND GND
C226 C522 C220 R412 EXTERNAL INTERNAL
D VCCA_B_TVO 3.3V GND VCC_SYNC 3.3V GND D
*22U_8 .1U_4 22N_4 *0_4
+1.05V_GMCH
U29H
+1.05V
J32 VCCSYNC VTT_1 U13
+1.25V L25 10UH_8 +3V_TV_DAC R128 0_6 U12
+3V_VCCA_CRT_DAC VTT_2 A1A(10/23): Short R122
A33 VCCA_CRT_DAC_1 VTT_3 U11
C505 C508 R132 B33 U9 C142 C126 C148 C134 + C462
+ C528 C264 VCCA_CRT_DAC_2 VTT_4
VTT_5 U8
CRT
.1U_4 22N_4 *0_4 U7 4.7U_8 4.7U_8 2.2U_8 .47U_6 330U_7343
470U_7343 .1U_4 +3V_VCCA_DAC_BG VTT_6
A30 VCCA_DAC_BG VTT_7 U5
VTT_8 U3
B32 U2 +1.25V_AXD
VSSA_DAC_BG VTT_9
VTT_10 U1
VTT_11 T13
VTT
+1.25V_VCCA_DPLLA B49 T11 R121 0_6 +1.25V
VCCA_DPLLA VTT_12
VTT_13 T10
+1.25V_VCCA_DPLLB H49 T9
<Description> VCCA_DPLLB VTT_14 C187 C195
VTT_15 T7
PLL
+1.25V L49 BKP1608HS181-T_6 +1.25VM_VCCA_HPLL AL2 T6
VCCA_HPLL VTT_16 1U_6 *22U_8
VTT_17 T5
C469 C138 +1.25VM_VCCA_MPLL AM2 T3
VCCA_MPLL VTT_18
VTT_19 T2
22U_8 .1U_4 R3
VTT_20
A LVDS
+1.8VSUS_VCC_TX_LVDS A41 R2 R405 0_6 +1.25V
VCCA_LVDS VTT_21
VTT_22 R1
C244 B41
L50 BKP1608HS181-T_6 VSSA_LVDS C477 C475
1000P_4 AT23
VCC_AXD_1 1U_6 10U_8
VCC_AXD_2 AU28
C133 K50 AU24
VCCA_PEG_BG VCC_AXD_3
AXD
C R384 R166 0_8 +3V_VCCA_PEG_BG C
+3V VCC_AXD_4 AT29
0.5_6 .1U_4 K49 AT25
VSSA_PEG_BG VCC_AXD_5
A PEG
C266 AT30
C465 V1.25M_MPLL_RC
22U_8 VCC_AXD_6 R165 0_6 +1.25V
.1U_4 +1.25V_VCCD_PEG_PLL U51 AR29
VCCA_PEG_PLL VCC_AXD_NCTF C265
+1.25V R120 0_6 +1.25VM_VCCA_SM AW18 B23 +1.25V_VCC_AXF .1U_4

VCCA_SM_1 VCC_AXF_1
AV19 B21
VCCA_SM_2
POWER VCC_AXF_2
AXF
C143 C165 C159 C176 C168 AU19 A21
+ VCCA_SM_3 VCC_AXF_3 L19 1UH_8
AU18 VCCA_SM_4 +1.8VSUS_GMCH
100U_7343 *22U_8 4.7U_6 22U_8 1U_6 AU17 AJ50 +1.25V_VCC_DMI
VCCA_SM_5 VCC_DMI C170 C211
A SM
AT22 R134 1_6 +V1.8_SMCK_RC C233 22U_8
VCCA_SM_7
AT21 VCCA_SM_8 VCC_SM_CK_1 BK24 +1.8VSUS_VCC_SM_CK .1U_4 22U_8
SM CK
AT19 VCCA_SM_9 VCC_SM_CK_2 BK23
B1D:(12/9) change C143 from CH71002MJC8 to CH7102MT804 (Z-limit issue) AT18 BJ24
R124 0_6 VCCA_SM_10 VCC_SM_CK_3
+1.25V AT17 VCCA_SM_11 VCC_SM_CK_4 BJ23
AR17 VCCA_SM_NCTF_1
C200 C203 C213 C201 AR16 VCCA_SM_NCTF_2
+3V_TV_DAC +1.8VSUS
L51 *1U_6 *1U_6 22U_8 .1U_4 A43 +1.8VSUS_VCC_TX_LVDS L21 1UH_8
VCC_TX_LVDS
A CK
BKP1608HS181-T_6 +1.25VM_VCCA_SM_CK BC29 VCCA_SM_CK_1
+3V BB29 VCCA_SM_CK_2
C40 C239 + C526
VCC_HV_1 +3V_VCC_HV
C489 C487 R404 C25 B40
VCCA_TVA_DAC_1 VCC_HV_2
HV
B25 1000P_4 220U_7343
.1U_4 22N_4 *0_4 VCCA_TVA_DAC_2
C27 VCCA_TVB_DAC_1
B27 VCCA_TVB_DAC_2 VCC_PEG_1 AD51
TV
B28 VCCA_TVC_DAC_1 VCC_PEG_2 W50
+VCC_PEG
PEG
A28 VCCA_TVC_DAC_2 VCC_PEG_3 W51
R131 *0_4 V49
B VCC_PEG_4 B
VCC_PEG_5 V50
D TV/CRT
R138 0_6 +1.5V_VCCD_CRT M32
+1.5V_VCCD_TVDAC VCCD_CRT
L29 VCCD_TVDAC
C488 C493 R402 AH50
VCC_RXR_DMI_1
DMI
+1.5V_VCCD_QDAC N28 AH51
.1U_4 22N_4 *0_4 VCCD_QDAC VCC_RXR_DMI_2
C485 +1.25V R81 0_6 +1.25VM_MCH_VCCD_HPLL AN2 VCCD_HPLL L54 91nH
VTTLF1 A7 +1.05V
VTTLF
22U_8 C128 +1.25V_VCCD_PEG_PLL U48 F2
VCCD_PEG_PLL VTTLF2 A1A: (9/20) Remove R138 0 ohm
VTTLF3 AH1
.1U_4 C259 J41 C284 + C529
VCCD_LVDS_1 LVDS C129 C470 C146
H42 VCCD_LVDS_2
C492 C494 C495 R401 .1U_4 10U_8 220U_7343
.47U_4 .47U_4 .47U_4
10U_8 .1U_4 22N_4 *0_4 +1.25V L24 BKP1608HS181-T_6
CRESTLINE_1p0 <FAE>
VCC_RXR_DMI and VCC_PEG
R168 C268 connect to+1.05V
1_8 .1U_4
+V1.25S_PEGPLL_FB
C263
A1A: (9/20) Remove +VCC_RXR_DMI
10U_8
+1.5V R137 0_6
C196 C214
.1U_4 22N_4 +1.05V D8 2 1 +1.05V_SD

PDZ5.6B
A A
+3V_VCC_HV
+1.8VSUS R163 0_6 +1.8V_VCCD_LVDS R64
10_4
A1A:(10/18) R125 100_6 C257 C243
INTEL CRB VCCD_QDAC Filter Modification: R67 0_4
change L13 to R125(100ohm),
change R145(*0 ohm) to C507(1uF)
1U_6 *10U_8
+3V
PROJECT : ZU1
C519 C511 C507
C112
D3A:(01/02)
R125 shortage issue, Add 2nd source CS11003F953
.1U_4 22N_4 1U_6 <CRB> Quanta Computer Inc.
+1.25V AND +1.25M shall be .1U_4
D3A:(2/13) +1.5V for Calero Interposer GMCH Power-2(5 of 7) 3B
Change R125 from CS11003B900 (100 ohm 0.1%) to CS11003F953(100 ohm 1%)
5 4 3 2 1
5 4 3 2 1
NB(Power-3)
U29I
U29J
A13 VSS_1 VSS_100 AW24 C46 VSS_199 VSS_287 W11
A24 VSS_4 VSS_103 AW5 D13 VSS_202 VSS_290 W47
AA21 VSS_5 VSS_104 AW7 D24 VSS_203 VSS_291 W5
AA24 VSS_6 VSS_105 AY10 D3 VSS_204 VSS_292 W7
AA29 VSS_7 VSS_106 AY24 D32 VSS_205 VSS_293 Y13
AB20 VSS_8 VSS_107 AY37 D39 VSS_206 VSS_294 Y2
D AB23 AY42 D45 Y41 D
VSS_9 VSS_108 VSS_207 VSS_295
AB26 VSS_10 VSS_109 AY43 D49 VSS_208 VSS_296 Y45
AB28 VSS_11 VSS_110 AY45 E10 VSS_209 VSS_297 Y49
AB31 VSS_12 VSS_111 AY47 E16 VSS_210 VSS_298 Y5
AC10 VSS_13 VSS_112 AY50 E24 VSS_211 VSS_299 Y50
AC13 VSS_14 VSS_113 B10 E28 VSS_212 VSS_300 Y11
AC3 VSS_15 VSS_114 B20 E32 VSS_213 VSS_301 P29
AC39 B24 E47 T29 VSS_GMCH_T29 R409 0_4
VSS_16 VSS_115 VSS_214 VSS_302 VSS_GMCH_T31 R413 0_4
AC43 VSS_17 VSS_116 B29 F19 VSS_215 VSS_303 T31
AC47 B30 F36 T33 VSS_GMCH_T33 R414 0_4
VSS_18 VSS_117 VSS_216 VSS_304 VSS_GMCH_R28 R410 0_4
AD1 VSS_19 VSS_118 B35 F4 VSS_217 VSS_305 R28
AD21 VSS_20 VSS_119 B38 F40 VSS_218
AD26 VSS_21 VSS_120 B43 F50 VSS_219
AD29 VSS_22 VSS_121 B46 G1 VSS_220
AD3 VSS_23 VSS_122 B5 G13 VSS_221 VSS_306 AA32
AD41 VSS_24 VSS_123 B8 G16 VSS_222 VSS_307 AB32
AD45 VSS_25 VSS_124 BA1 G19 VSS_223 VSS_308 AD32
AD49 VSS_26 VSS_125 BA17 G24 VSS_224 VSS_309 AF28
AD5 VSS_27 VSS_126 BA18 G28 VSS_225 VSS_310 AF29
AD50 VSS_28 VSS_127 BA2 G29 VSS_226 VSS_311 AT27
AD8 VSS_29 VSS_128 BA24 G33 VSS_227 VSS_312 AV25
AE10 VSS_30 VSS_129 BB12 G42 VSS_228 VSS_313 H50
AE14 VSS_31 VSS_130 BB25 G45 VSS_229
AE6 VSS_32 VSS_131 BB40 G48 VSS_230
AF20 BB44 G8
AF23
AF24
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
BB49
BB8
H24
H28
VSS_231
VSS_232
VSS_233
AF31 VSS_36 VSS_135 BC16 H4 VSS_234
C AG2 VSS_37 VSS_136 BC24 H45 VSS_235 C
AG38 VSS_38 VSS_137 BC25 J11 VSS_236
AG43 VSS_39 VSS_138 BC36 J16 VSS_237
AG47 VSS_40 VSS_139 BC40 J2 VSS_238
AG50 VSS_41 VSS_140 BC51 J24 VSS_239
AH3 VSS_42 VSS_141 BD13 J28 VSS_240
AH40 BD2 J33
AH41
AH7
VSS_43
VSS_44
VSS_45
VSS_142
VSS_143
VSS_144
BD28
BD45
J35
J39
VSS_241
VSS_242
VSS_243
VSS
AH9 VSS_46 VSS_145 BD48
AJ11 VSS_47 VSS_146 BD5 K12 VSS_245
AJ13 VSS_48 VSS_147 BE1 K47 VSS_246
AJ21 VSS_49 VSS_148 BE19 K8 VSS_247
AJ24 VSS_50 VSS_149 BE23 L1 VSS_248
AJ29 VSS_51 VSS_150 BE30 L17 VSS_249
AJ32 VSS_52 VSS_151 BE42 L20 VSS_250
AJ43 VSS_53 VSS_152 BE51 L24 VSS_251
AJ45 VSS_54 VSS_153 BE8 L28 VSS_252
AJ49 VSS_55 VSS_154 BF12 L3 VSS_253
AK20 VSS_56 VSS_155 BF16 L33 VSS_254
AK21 VSS_57 VSS_156 BF36 L49 VSS_255
AK26 VSS_58 VSS_157 BG19 M28 VSS_256
AK28 VSS_59 VSS_158 BG2 M42 VSS_257
AK31 VSS_60 VSS_159 BG24 M46 VSS_258
AK51 VSS_61 VSS_160 BG29 M49 VSS_259
AL1 VSS_62 VSS_161 BG39 M5 VSS_260
AM11 VSS_63 VSS_162 BG48 M50 VSS_261
AM13 VSS_64 VSS_163 BG5 M9 VSS_262
B AM3 VSS_65 VSS_164 BG51 N11 VSS_263 B
AM4 VSS_66 VSS_165 BH17 N14 VSS_264
AM41 VSS_67 VSS_166 BH30 N17 VSS_265
AM45 VSS_68 VSS_167 BH44 N29 VSS_266
AN1 VSS_69 VSS_168 BH46 N32 VSS_267
AN38 VSS_70 VSS_169 BH8 N36 VSS_268
AN39 VSS_71 VSS_170 BJ11 N39 VSS_269
AN43 VSS_72 VSS_171 BJ13 N44 VSS_270
AN5 VSS_73 VSS_172 BJ38 N49 VSS_271
AN7 VSS_74 VSS_173 BJ4 N7 VSS_272
AP4 VSS_75 VSS_174 BJ42 P19 VSS_273
AP48 VSS_76 VSS_175 BJ46 P2 VSS_274
AP50 VSS_77 VSS_176 BK15 P23 VSS_275
AR11 VSS_78 VSS_177 BK17 P3 VSS_276
AR2 VSS_79 VSS_178 BK25 P50 VSS_277
AR39 VSS_80 VSS_179 BK29 R49 VSS_278
AR44 VSS_81 VSS_180 BK36 T39 VSS_279
AR47 VSS_82 VSS_181 BK40 T43 VSS_280
AR7 VSS_83 VSS_182 BK44 T47 VSS_281
AT10 VSS_84 VSS_183 BK6 U41 VSS_282
AT14 VSS_85 VSS_184 BK8 U45 VSS_283
AT41 VSS_86 VSS_185 BL11 U50 VSS_284
AT49 VSS_87 VSS_186 BL13 V2 VSS_285
AU1 VSS_88 VSS_187 BL19 V3 VSS_286
AU23 VSS_89 VSS_188 BL22
AU29 VSS_90 VSS_189 BL37
AU3 BL47 CRESTLINE_1p0
VSS_91 VSS_190
AU36 VSS_92 VSS_191 C12
AU49 VSS_93 VSS_192 C16
A A
AU51 VSS_94 VSS_193 C19
AV39 VSS_95 VSS_194 C28
AV48 VSS_96 VSS_195 C29
AW1 VSS_97 VSS_196 C33
AW12 C36
AW16
VSS_98
VSS_99
VSS_197
VSS_198 C41 PROJECT : ZU1
CRESTLINE_1p0 Quanta Computer Inc.
GMCH Power-3(6 of 7) 3B

5 4 3 2 1
5 4 3 2 1
Strap table
All strap are sampled with respect to the leading edge of the GMCH Power OK(PWROK) Signal
CFG[17:3] Have internal Pull-up
CFG[18:19] Have internal Pull-down
Any CFG signal strapping option not list below should be left NC Pin
Pin Name Strap description Configuration
CFG[2:0] FSB Frequency Select 010 = FSB 800MHz

D 011 = FSB 667MHz D
CFG[4:3] Reserved
CFG5 DMI X2 Select 0 = DMI X2

1 = DMI X4(Default)
CFG6 Reserved
CFG7 CPU Strap 0 = Reserved

1 = Mobile CPU(Default)
CFG8 Low power PCI Express 0 = Normal mode

1 = Low Power mode
CFG9 PCI Express Graphics Lane Reversal 0 = Reverse Lanes

1 = Normal operation(Default)
CFG[11:10] Reserved
C C
CFG[13:12] XOR/ALLZ 00 = Reserved
01 = XOR Mode Enable
10 = All-Z Mode Enabled
11 = Normal operation(Default)
CFG[15:14] Reserved
CFG16 FSB Dynamic ODT 0 = Dynamic ODT disable

1 = Dynamic ODT Enable(Default)
CFG[18:17] Reserved
SDVO_CTRLDATA SDVO Present 0 = No SDVO Card present(Default)

1 = SDVO Card Present
CFG19 DMI Lane Reversal 0 = Normal operation(Default)

1 = Reverse Lanes
CFG20 SDVO/PCIe concurrent 0 = Only SDVO or PCIE x1 is operation(Default)

1 = SDVO and PCIE x1 are operating simultaneously via the PEG port
B B
DMI X2 Select DMI Lane Reversal XOR /ALLz /Clock Un-gating PCI Express Graphics SDVO Present
MCH_CFG_5 Low = DMIX2 MCH_CFG_19 Low = Normal operation(Default) MCH_CFG_12MCH_CFG_13 Configuration MCH_CFG_9 Low = Reverse Lane Strap define at External
High = IDMIX4(Default) High = Reverse Lane High = Normal operation(Default)
DVI control page
0 0 Clock gating disable
+3V
6 MCH_CFG_5 6 MCH_CFG_9
0 1 XOR Mode Enable
1 0 ALL-z Mode Enable

R394 R396
R420
*4.02K_4 1 1 Normal operation(Default) *4.02K_4
*4.02K_4
6 MCH_CFG_19
FSB Dynamic ODT SDVO/PCIE Concurrent operation
Low = Only SDVO or PCIE X1 is
MCH_CFG_16 Low = ODT Disable MCH_CFG_20 operational(Default)
High = ODT Enable(Default) High = SDVO andPCIE X1 are operating
simultaneously via the PEG port
6 MCH_CFG_12
A 6 MCH_CFG_13 A
6 MCH_CFG_16 +3V
R397 R395
R393
*4.02K_4 *4.02K_4
*4.02K_4 R422 PROJECT : ZU1
*4.02K_4
6 MCH_CFG_20 GMCH Strap(7 of 7) 3B
5 4 3 2 1
1 2 3 4 5 6 7 8
DDR2 Dual channel A/B PU
A A
M_A_A[13..0]
M_A_A[13..0] 7,13
M_B_A[13..0]
M_B_A[13..0] 7,13
DDRII A CHANNEL DDRII B CHANNEL
SMDDR_VTERM SMDDR_VTERM
C160 C219 C163 C254 C212 C247 C162 C184 C241 C229 C260 C245 C161 C255 C190 C166 C183 C167 C237 C248 C256 C209 C169 C253 C258 C204
.1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4
Place one cap close to every 2 pull-up resistor terminated to SMDDR_VTERM
B B
M_A_A3 RP16 1 2 56X2 SMDDR_VTERM

M_A_A1 3 4
M_A_A7 RP21 1 2 56X2 M_A_A8 RP20 1 2 56X2 SMDDR_VTERM

M_A_A5 3 4 M_A_A6 3 4
M_A_A2 RP17 1 2 56X2 RP28 1 2 56X2

6,13 M_CKE3
M_A_A4 3 4 7,13 M_B_BS#2 3 4
M_A_A11 RP26 1 2 56X2 RP4 1 2 56X2

7,13 M_A_BS#0
6,13 M_CKE1 3 4 6,13 M_ODT1 3 4
M_A_A12 RP24 1 2 56X2

M_A_A9 3 4 6,13 M_ODT3 RP1 1 2 56X2
6,13 M_CS#2 3 4
RP27 1 2 56X2
7,13 M_A_BS#2
3 4 M_A_A10 RP12 1 2 56X2
6,13 M_CKE0
7,13 M_A_CAS# 3 4
M_A_A0 RP11 1 2 56X2

3 4 RP7 1 2 56X2
7,13 M_A_BS#1 7,13 M_A_WE#
6,13 M_CS#1 3 4
C C
7,13 M_A_RAS# RP8 1 2 56X2

6,13 M_CS#0 3 4
M_B_A10 RP10 1 2 56X2 SMDDR_VTERM

3 4 7,13 M_B_WE# RP5 1 2 56X2
7,13 M_B_BS#0
7,13 M_B_CAS# 3 4
M_B_A3 RP13 1 2 56X2

M_B_A1 3 4 M_B_A7 RP25 1 2 56X2
6,13 M_CKE4 3 4
M_B_A0 RP9 1 2 56X2

3 4 RP6 1 2 56X2
7,13 M_B_BS#1 6,13 M_CS#3
7,13 M_B_RAS# 3 4
M_B_A6 RP18 1 2 56X2

M_B_A11 3 4 6,13 M_ODT0 RP2 1 2 56X2
M_A_A13 3 4
M_B_A12 RP19 1 2 56X2

M_B_A5 3 4 6,13 M_ODT2 RP3 1 2 56X2
M_B_A13 3 4
M_B_A2 RP15 1 2 56X2

M_B_A4 3 4
M_B_A8 RP22 1 2 56X2

D M_B_A9 3 4 D
INTEL FAE (08/17)

ADD MA14 FOR DUAL LAYERS RAM PROJECT : ZU1
R144 56_4 SMDDR_VTERM
6,13
6,13
M_A_A14
M_B_A14
R135 56_4 Quanta Computer Inc.
DDR RES. ARRAY 3B

1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
DDR2 Dual channel A/B CONN

SMDDR_VREF_DIMM
M_A_DM[0..7] 7
SMDDR_VREF_DIMM
M_B_DM[0..7] 7
M_A_DQ[0..63] 7 M_B_DQ[0..63] 7
+1.8VSUS
M_A_DQS[0..7] 7 M_B_DQS[0..7] 7
+1.8VSUS +1.8VSUS +1.8VSUS +1.8VSUS
M_A_DQS#[0..7] 7 M_B_DQS#[0..7] 7
CN24
M_A_A[0..13] 7,12 M_B_A[0..13] 7,12
CN25 1 2
VREF VSS46 M_B_DQ4
1 VREF VSS46 2 3 VSS47 DQ4 4
3 4 M_A_DQ4 M_B_DQ0 5 6 M_B_DQ1
M_A_DQ6 VSS47 DQ4 M_A_DQ0 M_B_DQ5 DQ0 DQ5 + C135 C496 C523 C218 C510 C525
5 DQ0 DQ5 6 7 DQ1 VSS15 8
M_A_DQ5 7 8 9 10 M_B_DM0
DQ1 VSS15 M_A_DM0 M_B_DQS#0 VSS37 DM0 330U_7343 2.2U_6 2.2U_6 2.2U_6 2.2U_6 2.2U_6
9 VSS37 DM0 10 11 DQS#0 VSS5 12
M_A_DQS#0 11 12 M_B_DQS0 13 14 M_B_DQ2
M_A_DQS0 DQS#0 VSS5 M_A_DQ7 DQS0 DQ6 M_B_DQ6
13 DQS0 DQ6 14 15 VSS48 DQ7 16
15 16 M_A_DQ1 M_B_DQ7 17 18
M_A_DQ2 VSS48 DQ7 M_B_DQ3 DQ2 VSS16 M_B_DQ12
17 DQ2 VSS16 18 19 DQ3 DQ12 20
A M_A_DQ3 M_A_DQ13 M_B_DQ13 A
19 DQ3 DQ12 20 21 VSS38 DQ13 22
21 22 M_A_DQ9 M_B_DQ9 23 24
M_A_DQ12 VSS38 DQ13 M_B_DQ8 DQ8 VSS17 M_B_DM1
23 DQ8 VSS17 24 25 DQ9 DM1 26
M_A_DQ8 25 26 M_A_DM1 27 28
DQ9 DM1 M_B_DQS#1 VSS49 VSS53 +1.8VSUS SMDDR_VREF_DIMM +3V
27 VSS49 VSS53 28 29 DQS#1 CK0 30 M_CLK_DDR3 6
M_A_DQS#1 29 30 M_B_DQS1 31 32
DQS#1 CK0 M_CLK_DDR0 6 DQS1 CK0# M_CLK_DDR#3 6
M_A_DQS1 31 32 33 34
DQS1 CK0# M_CLK_DDR#0 6 VSS39 VSS41
33 34 M_B_DQ11 35 36 M_B_DQ14
M_A_DQ11 VSS39 VSS41 M_A_DQ14 M_B_DQ10 DQ10 DQ14 M_B_DQ15 C174 C202 C520 C497 C307 C308 C113 C118
35 DQ10 DQ14 36 37 DQ11 DQ15 38
M_A_DQ15 37 38 M_A_DQ10 39 40
DQ11 DQ15 VSS50 VSS54 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 2.2U_6 2.2U_6 .1U_4
39 VSS50 VSS54 40
41 42
PC4800 DDR2 SDRAM

M_B_DQ20 VSS18 VSS20 M_B_DQ16
41 VSS18 VSS20 42 43 DQ16 DQ20 44
M_A_DQ17 43 44 M_A_DQ21 M_B_DQ17 45 46 M_B_DQ21
M_A_DQ20 DQ16 DQ20 M_A_DQ16 DQ17 DQ21
PC4800 DDR2 SDRAM

45 DQ17 DQ21 46 47 VSS1 VSS6 48
47 48 M_B_DQS#2 49 50 PM_EXTTS#1 6
M_A_DQS#2 VSS1 VSS6 M_B_DQS2 DQS#2 NC3 M_B_DM2
49 DQS#2 NC3 50 PM_EXTTS#0 6 51 DQS2 DM2 52 Close to DIMM0
M_A_DQS2 51 52 M_A_DM2 53 54
SO-DIMM (200P)
DQS2 DM2 M_B_DQ22 VSS19 VSS21 M_B_DQ18
53 VSS19 VSS21 54 55 DQ18 DQ22 56
SO-DIMM (200P)
57 DQ19 DQ23 58 59 VSS22 VSS24 60
59 60 M_B_DQ29 61 62 M_B_DQ24
M_A_DQ24 VSS22 VSS24 M_A_DQ29 M_B_DQ28 DQ24 DQ28 M_B_DQ25
61 DQ24 DQ28 62 63 DQ25 DQ29 64
M_A_DQ25 63 64 M_A_DQ28 65 66 +1.8VSUS
DQ25 DQ29 M_B_DM3 VSS23 VSS25 M_B_DQS#3
65 VSS23 VSS25 66 67 DM3 DQS#3 68
M_A_DM3 67 68 M_A_DQS#3 69 70 M_B_DQS3
DM3 DQS#3 M_A_DQS3 NC4 DQS3
69 NC4 DQS3 70 71 VSS9 VSS10 72
71 72 M_B_DQ26 73 74 M_B_DQ31
M_A_DQ26 VSS9 VSS10 M_A_DQ30 M_B_DQ27 DQ26 DQ30 M_B_DQ30 + C127 C490 C234 C509 C491 C518
73 DQ26 DQ30 74 75 DQ27 DQ31 76
M_A_DQ27 75 76 M_A_DQ31 77 78
DQ27 DQ31 VSS4 VSS8 330U_7343 2.2U_6 2.2U_6 2.2U_6 2.2U_6 2.2U_6
77 VSS4 VSS8 78 6,12 M_CKE3 79 CKE0 CKE1 80 M_CKE4 6,12
6,12 M_CKE0 79 CKE0 CKE1 80 M_CKE1 6,12 81 VDD7 VDD8 82
B B
81 VDD7 VDD8 82 83 NC1 A15 84
83 NC1 A15 84 7,12 M_B_BS#2 85 A16_BA2 A14 86 M_B_A14 6,12 INTEL FAE (08/17)
7,12 M_A_BS#2 85 86 M_A_A14 6,12 87 88
87
A16_BA2 A14
88 M_B_A12 89
VDD9 VDD11
90 M_B_A11 ADD MA14 FOR DUAL LAYERS RAM
M_A_A12 VDD9 VDD11 M_A_A11 M_B_A9 A12 A11 M_B_A7
89 A12 A11 90 91 A9 A7 92
M_A_A9 91 92 M_A_A7 M_B_A8 93 94 M_B_A6 +1.8VSUS SMDDR_VREF_DIMM +3V
A9 A7 INTEL FAE (08/17) A8 A6
M_A_A8 93 94 M_A_A6 95 96
95
A8 A6
96
ADD MA14 FOR DUAL LAYERS RAM M_B_A5 97
VDD5 VDD4
98 M_B_A4
M_A_A5 VDD5 VDD4 M_A_A4 M_B_A3 A5 A4 M_B_A2
97 A5 A4 98 99 A3 A2 100
M_A_A3 99 100 M_A_A2 M_B_A1 101 102 M_B_A0 C242 C524 C506 C185 C304 C306 C100 C110
M_A_A1 A3 A2 M_A_A0 A1 A0
101 A1 A0 102 103 VDD10 VDD12 104
103 104 M_B_A10 105 106 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 2.2U_6 2.2U_6 .1U_4
VDD10 VDD12 A10/AP BA1 M_B_BS#1 7,12
M_A_A10 105 106 7,12 M_B_BS#0 107 108
A10/AP BA1 M_A_BS#1 7,12 BA0 RAS# M_B_RAS# 7,12
7,12 M_A_BS#0 107 BA0 RAS# 108 M_A_RAS# 7,12 7,12 M_B_WE# 109 WE# S0# 110 M_CS#2 6,12
7,12 M_A_WE# 109 WE# S0# 110 M_CS#0 6,12 111 VDD2 VDD1 112
111 VDD2 VDD1 112 7,12 M_B_CAS# 113 CAS# ODT0 114 M_ODT2 6,12
113 114 115 116 M_B_A13
7,12 M_A_CAS# CAS# ODT0 M_ODT0 6,12 6,12 M_CS#3 S1# A13
115 116 M_A_A13 117 118 Close to DIMM1
6,12 M_CS#1 S1# A13 VDD3 VDD6
117 VDD3 VDD6 118 6,12 M_ODT3 119 ODT1 NC2 120
6,12 M_ODT1 119 ODT1 NC2 120 121 VSS11 VSS12 122
121 122 M_B_DQ37 123 124 M_B_DQ36
123 DQ32 DQ36 124 125 DQ33 DQ37 126
M_A_DQ37 125 126 M_A_DQ33 127 128
DQ33 DQ37 M_B_DQS#4 VSS26 VSS28 M_B_DM4
127 VSS26 VSS28 128 129 DQS#4 DM4 130
M_A_DQS#4 129 130 M_A_DM4 M_B_DQS4 131 132
M_A_DQS4 DQS#4 DM4 DQS4 VSS42 M_B_DQ39
131 DQS4 VSS42 132 133 VSS2 DQ38 134
133 134 M_A_DQ35 M_B_DQ34 135 136 M_B_DQ33 +3V
M_A_DQ39 VSS2 DQ38 M_A_DQ38 M_B_DQ35 DQ34 DQ39
135 DQ34 DQ39 136 137 DQ35 VSS55 138
M_A_DQ34 137 138 139 140 M_B_DQ44
DQ35 VSS55 M_A_DQ44 M_B_DQ40 VSS27 DQ44 M_B_DQ45
139 VSS27 DQ44 140 141 DQ40 DQ45 142
M_A_DQ40 141 142 M_A_DQ45 M_B_DQ41 143 144
M_A_DQ41 DQ40 DQ45 DQ41 VSS43 M_B_DQS#5 Q13 R53 R54
143 DQ41 VSS43 144 145 VSS29 DQS#5 146
C M_A_DQS#5 M_B_DM5 M_B_DQS5 C
145 VSS29 DQS#5 146 147 DM5 DQS5 148
2
M_A_DM5 147 148 M_A_DQS5 149 150 RHU002N06 10K_4 10K_4
DM5 DQS5 M_B_DQ46 VSS51 VSS56 M_B_DQ42
149 VSS51 VSS56 150 151 DQ42 DQ46 152
M_A_DQ42 151 152 M_A_DQ43 M_B_DQ43 153 154 M_B_DQ47 3 1 DDRDAT_SMB
DQ42 DQ46 DQ43 DQ47 2,16,18,27,33 PDAT_SMB
M_A_DQ46 153 154 M_A_DQ47 155 156
DQ43 DQ47 M_B_DQ53 VSS40 VSS44 M_B_DQ52
155 VSS40 VSS44 156 157 DQ48 DQ52 158
M_A_DQ49 DQ48 DQ52 M_A_DQ52 DQ49 DQ53 +3V
159 DQ49 DQ53 160 161 VSS52 VSS57 162
161 VSS52 VSS57 162 163 NCTEST CK1 164 M_CLK_DDR4 6
163 164 165 166 Q12
NCTEST CK1 M_CLK_DDR1 6 VSS30 CK1# M_CLK_DDR#4 6
165 166 M_B_DQS#6 167 168
VSS30 CK1# M_CLK_DDR#1 6 DQS#6 VSS45
2
M_A_DQS#6 167 168 M_B_DQS6 169 170 M_B_DM6 RHU002N06
M_A_DQS6 DQS#6 VSS45 M_A_DM6 DQS6 DM6
169 DQS6 DM6 170 171 VSS31 VSS32 172
171 172 M_B_DQ51 173 174 M_B_DQ55 3 1 DDRCLK_SMB
VSS31 VSS32 DQ50 DQ54 2,16,18,27,33 PCLK_SMB
175 DQ51 DQ55 176 177 VSS33 VSS35 178
177 178 M_B_DQ56 179 180 M_B_DQ60
179 DQ56 DQ60 180 181 DQ57 DQ61 182
M_A_DQ60 181 182 M_A_DQ57 183 184
DQ57 DQ61 M_B_DM7 VSS3 VSS7 M_B_DQS#7
183 VSS3 VSS7 184 185 DM7 DQS#7 186
M_A_DM7 185 186 M_A_DQS#7 187 188 M_B_DQS7
DM7 DQS#7 M_A_DQS7 M_B_DQ59 VSS34 DQS7
187 VSS34 DQS7 188 189 DQ58 VSS36 190
M_A_DQ62 189 190 M_B_DQ62 191 192 M_B_DQ63
M_A_DQ59 DQ58 VSS36 M_A_DQ58 DQ59 DQ62 M_B_DQ58 SMDDR_VREF_DIMM
191 DQ59 DQ62 192 193 VSS14 DQ63 194
193 194 M_A_DQ63 DDRDAT_SMB 195 196
DDRDAT_SMB VSS14 DQ63 DDRCLK_SMB SDA VSS13 R69 10K_4
195 SDA VSS13 196 197 SCL SA0 198
DDRCLK_SMB 197 198 R74 10K_4 +3V 199 200 R65 10K_4
+3V SCL SA0 R71 10K_4 VDD(SPD) SA1
+3V 199 VDD(SPD) SA1 200
FOX_AS0A426-NARN-7F +3V R192 0_6 SMDDR_VREF
FOX_AS0A426-N2RN-7F
SO-DIMM0 SPD Address is 0xA0 SO-DIMM1 SPD Address is 0xA4
SO-DIMM0 TS Address is 0x30 SO-DIMM1 TS Address is 0x34 R191 *10K_4 R193 *10K_4 +1.8VSUS
D D
H: 5.2mm H: 9.2mm A1A:(10/30) no stuff R192, stuff R191,R193

A1A:(11/09) stuff R192, no stuff R191,R193
CLOCK 0,1 CLOCK 3,4

CKE 0,1 CKE 2,3 PROJECT : ZU1
DDR SO-DIMM(200P) 3B
1 2 3 4 5 6 7 8
5 4 3 2 1
RTC VCCRTC
D3A:(2/1) Change ICH8M from ES sample to QS sample
Change U32 from AJ0QM740T31 to AJ0QN230T10
CHANGE FROM 18PF
D23 CH500H-40 VCCRTC C328 1U_6
+3VPCU TO 10PF
<check list>
Delay 18~25ms C548 10P_4
VCCRTC_4 D22 CH500H-40 R210 20K_6
1
R205 R246 G1 C363 Y4 R231
1K_4 1U_6 32.768KHZ 10M_6
2
D 1M_6 *SHORT_PAD U32A D
CLK_32KX1 AG25 E5
RTCX1 FWH0/LAD0 LAD0 27,28,30
C547 10P_4 CLK_32KX2 AF24 F5
RTCX2 FWH1/LAD1 LAD1 27,28,30 +1.05V_V_CPU_IO
CN12 G8
FWH2/LAD2 LAD2 27,28,30
1 1 RTCRST# AF23 F6
RTCRST# FWH3/LAD3 LAD3 27,28,30
2 2
SM_INTRUDER# AD22 C4 +1.05V_V_CPU_IO
INTRUDER# FWH4/LFRAME# LFRAME# 27,28,30
A1A:
ACS_85204-0200L (9/24) change RTC CONN (follow ZC3)
RTC
LPC
ICH_INTVRMEN AF25 G9
INTVRMEN LDRQ0# LDRQ#0 30
CMOS Setting G1 LAN100_SLP AD21 E6 LDRQ#1 R209 R222
LAN100_SLP LDRQ1#/GPIO23 T66
Clear CMOS Short B24 AF13 GATEA20 *56.2_4 *56.2_4 R237
Keep CMOS Open GLAN_CLK A20GATE GATEA20 28
A20M# AG26 H_A20M# 3
D22 56.2_4
LAN_RSTSYNC H_DPRSTP#_R R221 0_4
DPRSTP# AF26 ICH_DPRSTP# 3,6,35
A1A: 9/1 Remove GLAN C21 LAN_RXD0 DPSLP# AE26 H_DPSLP#_R R224 0_4
H_DPSLP# 3
B21 LAN_RXD1
C22 LAN_RXD2 FERR# AD24 H_FERR# 3
LAN / GLAN
VCCRTC_3
E3A:(3/30) Intel checklist Rev1.6 D21 AG29 H_PWRGD_R R220 0_4
The GLAN_COMPO/GLAN_COMPI connection to 1.5-V rail through the resistor LAN_TXD0 CPUPWRGD/GPIO49 H_PWRGD 3
E20 LAN_TXD1
remains even if non-Intel LAN is used. C20 AF27
Stuff R232 (CS02492FB29) LAN_TXD2 IGNNE# H_IGNNE# 3
+5VPCU AH21 AE24
GLAN_DOCK#/GPIO13 INIT# H_INIT# 3
INTR AC20 H_INTR 3
CPU
+1.5V_PCIE R232 24.9_4 GLAN_COMP_SB D25 AH14 RCIN#
GLAN_COMPI RCIN# RCIN# 28 +1.05V_V_CPU_IO
R201 1.2K_6
VCCRTC_1 R200 1K_4 VCCRTC_2 3 1 C25 GLAN_COMPO
NMI AD23 H_NMI 3
+3V +3V ACZ_BCLK AJ16 AG28 H_SMI#_R R219 0_4
HDA_BIT_CLK SMI# H_SMI# 3
R202 Q22 ACZ_SYNC AJ15
2
HDA_SYNC R212
STPCLK# AA24 H_STPCLK# 3
4.7K_4 MMBT3904 ACZ_RST# AE14
C HDA_RST# H_THERMTRIP_R 56.2_4 C
THRMTRIP# AE27
R467 R289 AJ17
31 ACZ_SDIN0 HDA_SDIN0
AH17 AA23 ICH_TP8 R214 24_6 R211 *0_4
31 ACZ_SDIN1 HDA_SDIN1 TP8 T59 PM_THRMTRIP# 3,6
*10K_4 *10K_4 ACZ_SDIN2 AH15 HDA_SDIN2 PDD[15:0] 26
R206 T111 ACZ_SDIN3 PDD0
IHDA
AD13 HDA_SDIN3 DD0 V1
T63 U2 PDD1 Placement close SB L<2"
15K_4 ACZ_SDOUT DD1 PDD2
AE13 HDA_SDOUT DD2 V3
RST_RBAY# T1 PDD3
RST_RBAY# DD3 PDD4 E3A:(3/14)Change R214 from CS02403F908 to CS02403F916 (Lead free)
AE10 HDA_DOCK_EN#/GPIO33 DD4 V4
RBAYON# RBAYON# AG14 T5 PDD5
HDA_DOCK_RST#/GPIO34 DD5 PDD6
DD6 AB2
SATA_LED# AF10 T6 PDD7
29 SATA_LED# SATALED# DD7 +3V +3V
T3 PDD8
C407 3900P_4 SATA_RXN0_C DD8 PDD9
26 SATA_RXN0 AF6 SATA0RXN DD9 R2
C408 3900P_4 SATA_RXP0_C AF5 T4 PDD10
26 SATA_RXP0 SATA0RXP DD10
C406 3900P_4 SATA_TXN0_C AH5 V6 PDD11
26 SATA_TXN0 SATA0TXN DD11
C405 3900P_4 SATA_TXP0_C AH6 V5 PDD12 0810 UR FAE: R273 R262
26 SATA_TXP0 SATA0TXP DD12
U1 PDD13
AG3
DD13
V2 PDD14 RCIN# DOESN'T NEED PU 10K_4 8.2K_4
SATA1RXN DD14 PDD15
AG4 SATA1RXP DD15 U6
IDE
AJ4 RCIN#
SATA1TXN PDA[2:0] 26
AJ3 AA4 PDA0 GATEA20
A1A: (9/20) Remove SATA1/SATA2 SATA1TXP DA0 PDA1
DA1 AA1
A1A: (9/20) RCIN# PU 10K
SATA
AF2 AB3 PDA2
SATA2RXN DA2
AF1 SATA2RXP
AE4 SATA2TXN DCS1# Y6 PDCS1# 26
AE3 Y5
SATA Disable SATA2TXP DCS3# PDCS3# 26
2 CLK_PCIE_SATA# AB7 SATA_CLKN DIOR# W4 PDIOR# 26

1.Connect to GND: SATA[2:0]RXp/n , SATARBIAS , SATARBIAS# , SATA_CLKP , SATACLKN 2 CLK_PCIE_SATA AC6 SATA_CLKP DIOW# W3 PDIOW# 26
2.NC: SATA[2:0]TXp/n , SATALED# DDACK# Y2 PDDACK# 26
AG1 Y3 IRQ14 26
B 3.VccSATAPLL should be connected directly to Vcc1_5,Filter cap are not required R495 24.9_4 SATA_BIAS AG2
SATARBIAS# IDEIRQ
Y1 B
4.BIOS disable SATARBIAS IORDY PIORDY 26
DDREQ W5 PDDREQ 26
<check list>
L<500mils ICH8M REV 1.0
SB Strap HDA A1A: 9/6 base on Intel design guide, add it.
XOR Chain Entrance Strap
ICH8-M Internal VR Enable strap ICH8-M LAN100_SLP Strap ACZ_SDOUT R282 33_4
(Internal VR for Vccsus1_05,VccSus1_5 and VccCL1_5) (Internal VR for VccLAN1_05 and VccCL1.05) ACZ_SDOUT_AUDIO 31
ICH_RSV0 HDA_SDOUT Description
R283 33_4
ACZ_SDOUT_MDC 31
INTVRMEN Low = Internal VR disable LAN100_SLP Low = Internal VR disable 0 0 RSVD
High = Internal VR enable(Default) High = Internal VR enable(Default)
0 1 Enter XOR Chain ACZ_SYNC R464 33_4

ACZ_SYNC_AUDIO 31
1 0 Normal opration(Default) R465 33_4

ACZ_SYNC_MDC 31
1 1 Set PCIE port config bit 1

ACZ_BCLK R462 33_4
BIT_CLK_AUDIO 31
R463 33_4
VCCRTC E3A:(4/3)Stuff R226(332K_6) and don't stuff R241 +3V BIT_CLK_MDC 31
VCCRTC to enable Internal VR for VCCCL1_05 and VCCLAN1_05.
A1A: (9/20) Change INTVRMEN from PU to PD A1A: 9/1 Disable the internal VR powering ACZ_RST# R268 33_4
ACZ_RST#_AUDIO 31,32
A A
VccLAN1_05, and VccCL1_05
R227 B1C: (11/18) Change INTVRMEN from PD to PU R272 R267 33_4
ACZ_RST#_MDC 31
332K_6 R226 *1K_6
332K_6
ICH_INTVRMEN ACZ_SDOUT
LAN100_SLP
ICH_TP3 16
PROJECT : ZU1
R228
*0_4 R241
*0_4 D3A:(2/16)ICH8M Internal VR should not be disabled.
no stuff R241, stuff R226
R457 Quanta Computer Inc.
*1K_4
D3A:(2/28) Battery life issue. Disable ICH8M Internal VR (LAN) ICH8M HOST(1 of 4) 3B
. stuff R241, no stuff R226 for C-build
5 4 3 2 1
5 4 3 2 1
SB-PCIE/USB/DMI
U32D A16 SWAP Override strap
33 PCIE_RXN1 P27 PERN1 DMI0RXN V27 DMI_RXN0 6
33 PCIE_RXP1 P26 PERP1 DMI0RXP V26 DMI_RXP0 6
C343 .1U_4 PCIE_TXN1_C N29 U29 PCI_GNT#3 Low = A16 swap override enabled
33 PCIE_TXN1 PETN1 DMI0TXN DMI_TXN0 6
C342 .1U_4 PCIE_TXP1_C N28 U28 High = Default
33 PCIE_TXP1 DMI_TXP0 6
Direct Media Interface

PETP1 DMI0TXP
to Docking
M27 PERN2 DMI1RXN Y27 DMI_RXN1 6
M26 Y26 GNT3# R301 *1K_4
PERP2 DMI1RXP DMI_RXP1 6
L29 PETN2 DMI1TXN W29 DMI_TXN1 6
L28 PETP2 DMI1TXP W28 DMI_TXP1 6
D D
PCI-Express
18 PCIE_RXN3 K27 PERN3 DMI2RXN AB26 DMI_RXN2 6
18 PCIE_RXP3 K26 PERP3 DMI2RXP AB25 DMI_RXP2 6
to LAN 18 PCIE_TXN3
C335 .1U_4 PCIE_TXN3_C J29 PETN3 DMI2TXN AA29 DMI_TXN2 6
C334 .1U_4 PCIE_TXP3_C J28 AA28
18 PCIE_TXP3 PETP3 DMI2TXP DMI_TXP2 6
27 PCIE_RXN4 H27 PERN4 DMI3RXN AD27 DMI_RXN3 6

H26 AD26 +1.5V_PCIE
27 PCIE_RXP4 PERP4 DMI3RXP DMI_RXP3 6
C337 .1U_4 PCIE_TXN4_C G29 AC29
27 PCIE_TXN4 PETN4 DMI3TXN DMI_TXN3 6
C336 .1U_4 PCIE_TXP4_C G28 AC28
27 PCIE_TXP4 PETP4 DMI3TXP DMI_TXP3 6
to WLAN F27 PERN5 DMI_CLKN T26 CLK_PCIE_ICH# 2
R244
F26 PERP5 DMI_CLKP T25 CLK_PCIE_ICH 2
E29 24.9_4
PETN5
E28 PETP5 DMI_ZCOMP Y23
Y24 DMI_IRCOMP_R
DMI_IRCOMP
D27 PERN6/GLAN_RXN
D26 PERP6/GLAN_RXP USBP0N G3 USBP0- 27
C29 PETN6/GLAN_TXN USBP0P G2 USBP0+ 27 <CRB>
C28 PETP6/GLAN_TXP USBP1N H5 USBP1- 27 DMI_IRCOMP_R<500mils
USBP1P H4 USBP1+ 27
A1A: 9/1 remove SPI interface T131 C23 H2 USBP2- 27
SPI_CLK USBP2N
T132 B23 SPI_CS0# USBP2P H1 USBP2+ 27
D3A:(2/2) Add test point for ASF function E22 J3
T133 SPI_CS1# USBP3N USBP3- 33 to Docking
SPI
USBP3P J2 USBP3+ 33
T134 D23 SPI_MOSI USBP4N K5 USBP4- 27
F21 K4 to Bluetooth
T135 SPI_MISO USBP4P USBP4+ 27
K2 USBP5-
USBP5N T114 A1A:(10/2) Remove USB5
USBOC#0 AJ19 K1 USBP5+
OC0# USBP5P T113
USBOC#1 AG16 L3
OC1#/GPIO40 USBP6N USBP6- 29 to finger printer
USBOC#2
C
USBOC#3
AG15
AE15
OC2#/GPIO41 USB USBP6P L2
M5 USBP7-
USBP6+ 29 C
OC3#/GPIO42 USBP7N T67 A1A:(10/2) Remove USB7

USBOC#4 AF15 M4 USBP7+
OC4#/GPIO43 USBP7P T69
USBOC#5 AG17 M2
OC5#/GPIO29 USBP8N USBP8- 20 to CCD
USBOC#6 AD12 M1
OC6#/GPIO30 USBP8P USBP8+ 20
USBOC#7 AJ18 N3 USBP9-
OC7#/GPIO31 USBP9N T70
USBOC#8 AD14 N2 USBP9+
OC8# USBP9P T112
USBOC#9 AH18 OC9#
USBRBIAS# F2
F3 USB_RBIAS_PN
USBRBIAS
ICH8M REV 1.0
R328
<CRB>
USB_RBIAS_PN<500mils 22.6_6
SB-PCI +3V
RP40
6 5
U32B SERR# 7 4
22,23,25 AD[0..31]
AD0 D20 A4 REQ0# REQ0# 8 3
AD0 REQ0# REQ0# 22
AD1 E19 D7 GNT0# INTH# 9 2 INTC#
AD2 D19
AD1 PCI GNT0#
E18 REQ1#
GNT0# 22
10 1 INTB#
AD2 REQ1#/GPIO50 REQ1# 23 +3V
AD3 A20 C18 GNT1#
AD3 GNT1#/GPIO51 GNT1# 23
AD4 D17 B19 REQ2# 8.2KX8
AD4 REQ2#/GPIO52 REQ2# 25
AD5 A21 F18 GNT2# +3V_S5
AD5 GNT2#/GPIO53 GNT2# 25
AD6 A19 A11 REQ3#
B AD6 REQ3#/GPIO54 RP42 B
AD7 C19 C10 GNT3#
AD8 AD7 GNT3#/GPIO55 USBOC#0
A18 AD8 6 5
AD9 B16 C17 USBOC#7 7 4 USBOC#2
AD9 C/BE0# CBE0# 22,23,25
AD10 A12 E15 USBOC#5 8 3 USBOC#3
AD10 C/BE1# CBE1# 22,23,25
AD11 E16 F16 USBOC#1 9 2 USBOC#4
AD11 C/BE2# CBE2# 22,23,25
AD12 A14 E17 +3V_S5 10 1 USBOC#6
AD12 C/BE3# CBE3# 22,23,25
AD13 G16
AD14 AD13 IRDY# 8.2KX8
A15 AD14 IRDY# C8 IRDY# 22,23,25
AD15 B6 D9
AD15 PAR PAR 22,23,25
AD16 C11 G6 USBOC#8 R264 8.2K_4 +3V_S5
AD16 PCIRST# PCIRST# 22,23,27
AD17 A9 D16 DEVSEL#
AD17 DEVSEL# DEVSEL# 22,23,25
AD18 D11 A7 PERR# USBOC#9 R251 8.2K_4 +3V_S5
AD18 PERR# PERR# 22,23,25
AD19 B12 B7 LOCK#
AD20 AD19 PLOCK# SERR# +3V
C12 AD20 SERR# F10 SERR# 22,23,25
AD21 D10 C16 STOP#
AD21 STOP# STOP# 22,23,25 RP38
AD22 C7 C9 TRDY#
AD22 TRDY# TRDY# 22,23,25
AD23 F13 A17 FRAME# REQ1# 6 5
AD23 FRAME# FRAME# 22,23,25
AD24 E11 DEVSEL# 7 4 REQ2#
AD25 AD24 PLT_RST-R# R230 0_6 FRAME# TRDY#
E13 AD25 PLTRST# AG24 PLTRST#_NB 6 8 3
AD26 E12 B10 PCLK_ICH STOP# 9 2 INTG#
AD26 PCICLK PCLK_ICH 2
AD27 D8 G7 +3V 10 1
AD27 PME# PCI_PME# 22,23,25
AD28 A6
AD29 AD28 8.2KX8 +3V
E8 AD29
AD30 D6 +3V
AD30 RP39
AD31 A3 AD31 LOCK# 6 5
IRDY# INTE#
INTA# F9
Interrupt I/F F8 INTE# C546 PERR#
7
8
4
3 INTD#
22 INTA# PIRQA# PIRQE#/GPIO2 INTE# 25
INTB# B5 G11 INTF# INTF# 9 2 REQ3#
23 INTB# PIRQB# PIRQF#/GPIO3
A INTC# C5 F12 INTG# .1U_4 +3V 10 1 INTA# A
T68 PIRQC# PIRQG#/GPIO4
INTD# A10 B3 INTH# R490 *0_4 U20
T64 PIRQD# PIRQH#/GPIO5 CRT_SENSE# 19,28,33
5
8.2KX8
ICH8M REV 1.0 PLT_RST-R# 2
4 PLTRST# 16,18,21,25,26,27,28,30,33
1
PROJECT : ZU1
TC7SH08FU R248
3
100K_6 Quanta Computer Inc.

ICH8M PCIE(2 of 4)/ BIOS 3B
5 4 3 2 1
5 4 3 2 1
SB-GPIO
U32C
PCLK_SMB AJ26 AJ12 EMAIL_LED# T145
2,13,18,27,33 PCLK_SMB SMBCLK SATA0GP/GPIO21
PDAT_SMB AD19 AJ10 BOARD_ID2
2,13,18,27,33 PDAT_SMB SMBDATA SATA1GP/GPIO19
CL_RST#1 RBAYID0
SATA
AG21 AF11
GPIO
D3A:(1/31) ASF issue:when iAMT is not implemented, 27 CL_RST#1 LINKALERT# SATA2GP/GPIO36
SMB
PCLK_SMB R474 0_4 SMLINK0 AC17 AG11 RBAYID1
ICH8M SMBus and SMLink should be connected together to support slave mode PDAT_SMB R475 0_4 SMLINK1 SMLINK0 SATA3GP/GPIO37
AE19 SMLINK1
Connect SMLINK0 to SMBCLK and SMLINK1 to SMBDATA (Add R474,R475 for debug use) AG9 14M_ICH
A1A:(9/29) no support iAMT, remove SMB_CLK_ME,SMB_DATA_ME CLK14 14M_ICH 2
RI#
Clocks
AF17 G5 CLKUSB_48 CLKUSB_48 14M_ICH
A1A: (9/11) Remove RI# RI# CLK48 CLKUSB_48 2
+3V
F4 D3 ICH8_SIO_32K T71 SIO/ PC87383 DOES NOT NEED 32KHz
30 LPC_PD# SUS_STAT#/LPCPD# SUSCLK
SYS_RST# AD15 R335 R481
3 SYS_RST# SYS_RESET#
AG23 SLP_S3# R234 100_4
SLP_S3# SUSB# 28
AG12 AF21 SLP_S4# R243 100_4 *10_4 *33_4
6 PM_BMBUSY# BMBUSY#/GPIO0 SLP_S4# SUSC# 28
R256 R254 AD18 SLP_S5#
*10K_4 *10K_4 SMB_ALERT# SLP_S5# T60 <FAE>
AG22 SMBALERT#/GPIO11
D
AH27 A1A: (9/26) Remove S4_STAT#, need be confirm? Since your CPU VRM has no C412 C559 D
R459 0_4 PM_STPPCI_ICH# S4_STATE#/GPIO26
GPIO
2 PM_STPPCI# AE20 DPRSTP# pin, connect
PM_STPCPU_ICH# STP_PCI#/GPIO15
SYS
R460 0_4 AG18 AE23 ICH_PWROK PM_DPRSLPVR to IMVP6 is correct *10P_4 *10P_4
2 PM_STPCPU# STP_CPU#/GPIO25 PWROK
+3V CLKRUN# AH11 AJ14 PM_DPRSLPVR_R R466 100_4 PM_DPRSLPVR
A1A: (9/26) change name from VR_PWRGD_CLKEN# 28,30 CLKRUN# CLKRUN#/GPIO32 DPRSLPVR/GPIO16 PM_DPRSLPVR 6,35
Power MGT
to VR_PWRGD_CK410# C338 .1U_4 PCIE_WAKE# AE17 AE21 PM_BATLOW#_R
18,27 PCIE_WAKE# WAKE# BATLOW# E3A:(3/26)
U31 SERIRQ AF12
22,23,28,30 SERIRQ SERIRQ LAN_RST# should be terminated by 8.2-10 kΩ pull down resistor to GND
1 5 THERM_ALERT# AC13 C2 DNBSWON#
3 THERM_ALERT# THRM# PWRBTN# DNBSWON# 28 A1A: 9/1 change to PLTRST# if an IntelR 82566 MM/MC integrated LAN solution is not used.->
35 VR_PWRGD_CK410# 2
3 4 VR_PWRGD_CLKEN AJ20 AH20 PM_LAN_ENABLE_R R247 *0_4 PLTRST# (1)Stuff 10k for R204
VRMPWRGD LAN_RST# PLTRST#(2)Don't stuff R456
NC7SZ04 R250 100K_4 T110 ICH_TP7 AJ22 AG27 RSMRST#_R (3)Don't stuff R247
TP7 RSMRST# 15,18,21,25,26,27,28,30,33
B1C: (11/24) add D43,D44 to stop leakage from EC to SB KBSMI# D43 BAS316 KBSMI#_ICH AJ8 E1
28 KBSMI# TACH1/GPIO1 CK_PWRGD CK_PWRGD 2 B1C:(11/20) short PWROK_EC to MPWROK
LID591# D44 BAS316 LID591#_ICH AJ9 +3V
20,28,29 LID591# TACH2/GPIO6 PWROK_EC 6,28
T120 GPIO7 AH9 E3
B1C:(11/28) change DOCKIN# from GPIO7 to GPIO12 TACH3/GPIO7 CLPWROK MPWROK 6,28 A1A:(9/16) Remove SUSM#
SCI# AE16 +3V_S5
28 SCI# GPIO8 used to control power planes to the Intel AMT sub-system
D24 DOCKIN#_ICH_R AC19 AJ25
18,33 DOCKIN# GPIO12 SLP_M#
BOARD_ID0 BAS316 AG8
BOARD_ID1 TACH0/GPIO17
AH12 GPIO18 CL_CLK0 F23 CL_CLK0 6
T128 BOARD_ID3 AE11 AE18 R233 R453
GPIO20 CL_CLK1 CL_CLK1 27
GPIO
Controller Link
ICH_GPIO22 AG10 *3.24K_6 3.24K_6
T109 ICH_GPIO27 SCLOCK/GPIO22
AH25 QRT_STATE0/GPIO27 CL_DATA0 F22 CL_DATA0 6
T61 ICH_GPIO28 AD16 AF19
A1A: (9/26) Remove SATACLKREQ# QRT_STATE1/GPIO28 CL_DATA1 CL_DATA1 27
+3V GPIO35 AG13
RST_HDD# SATACLKREQ#/GPIO35 CL_VREF0_SB
26 RST_HDD# AF9 SLOAD/GPIO38 CL_VREF0 D24
R468 ICH_GPIO39 AJ11 AH23 CL_VREF1_SB
ICH_GPIO48 SDATAOUT0/GPIO39 CL_VREF1 C357
AD10 SDATAOUT1/GPIO48
*10K_4 AJ23 C355
CL_RST# CL_RST#0 6
<check list> ACZ_SPKR AD9 .1U_4
31 ACZ_SPKR SPKR
internal PD AJ27 ICH_GPIO24 *.1U_4 R452
MEM_LED/GPIO24 A1A: (9/26) Remove (1)ME_EC_ALERT#
MISC
C R469 0_4 MCH_ICH_SYNC#_R ICH_GPIO10 R229 453_4 C
6 MCH_ICH_SYNC# AJ13 MCH_SYNC# ME_EC_ALERT/GPIO10 AJ24
AF22 ICH_GPIO14 (2)EC_ME_ALERT *453_4
EC_ME_ALERT/GPIO14
14 ICH_TP3 AJ21 TP3 WOL_EN/GPIO9 AG19
B1C:(11/24) add GPIO10 PU +3V,GPIO14 PD to GND
ICH8M REV 1.0
A1A: (9/11) Remove LAN_WOL_EN circuit
A1A:(10/12) change from +3V to +3VSUS

+3VSUS (Refer to ZC1)
B1C:(11/29) no stuff R229,R233,C355
C393 .1U_4
5
DELAY_VR_PWRGOOD 1 U21
3,6,35 DELAY_VR_PWRGOOD
4 ICH_PWROK
A1A:(9/29) no support iAMT, remove 2ND_MBCLK,2ND_MBDATA,Q11,Q12 PWROK_EC 2
3
R298 100K_4 +3V
TC7SH08FU INTEL CRB NEED THOSE PU & PD. INTEL FAE (08/17)
A1A:(9/20) Refer to ZD1, Add ICH_PWROK circuit
+3V_S5 "Add RSMRST# isolation (important!!! See ww22 Santa Rosa MoW)"
+3VSUS
SYS_RST# R263 10K_4
R207
DNBSWON# R329 *10K_4 PM_LAN_ENABLE_R R456 *10K_4 Q23 4.7K_4

No Reboot strap MMBT3906
Internal Pull up INTEL CRB SHOW IT
RSMRST#_R 3 1 RSMRST# 28
HDA_SPKR Low = Default ICH_GPIO24 R454 *10K_4
B High = No Reboot DOCKIN#_ICH_R R319 8.2K_4 B
TO ICH8 FROM uR(EC)
2
A1A:(10/30) change DOCKIN#_ICH_R PU from +3V to +3V_S5 +3V R215
+3V 10K_4
2
ACZ_SPKR R288 *10K_4 INTEL CRB: PU +3V LID591#_ICH R473 10K_4 D21
KBSMI#_ICH R480 10K_4 3 BAV99
BIOS/ ERIC: UNSTUFF

SCI# R261 10K_4
1
ICH_GPIO10 R568 10K_4
ICH_GPIO39 R470 10K_4
2
+3V INTEL CRB SHOW IT D20
ICH_GPIO22 R312 10K_4 3 BAV99
GPIO35 R265 10K_4 ICH_GPIO48 R315 10K_4
RST_HDD# R314 10K_4
THERM_ALERT# R270 8.2K_4 RBAYID0 R311 8.2K_4 PM_LAN_ENABLE_RR204 10K_4 R196
1
RBAYID1 R300 8.2K_4 2.2K_4
SERIRQ R299 10K_4
ICH_GPIO14 R569 10K_4 DISABLE LAN: STUFF
CLKRUN# R305 8.2K_4 PM_DPRSLPVR R269 100K_4
ICH_PWROK R238 10K_4

+3V_S5
ECN 2A RI# R258 10K_4 +3V +3V +3V

INTEL CRB V1.301
CL_RST#1 R242 *10K_4 Board ID ID3 ID2 ID1 ID0
CL_RST# NO NEED PU.
R472 R310 R324
A
A1A:(9/29) no support iAMT, remove PU +3V_S5 circuit (R259/R258)
With EZ Dock 0 0 0 0 A
*10K_4 *10K_4 *10K_4
PCLK_SMB R455 2.2K_4 W/O EZ Dock 0 0 0 1 BOARD_ID2 BOARD_ID1 BOARD_ID0
PDAT_SMB R255 2.2K_4

RSV 0 0 1 0
SMB_ALERT# R235 10K_4 R471 R304 R320
PCIE_WAKE# R260 1K_4 RSV 0 0 1 1 10K_4 10K_4 10K_4
PM_BATLOW#_R R245 8.2K_4

RSV 0 1 0 0 C2A:(12/12) Intel Suggest :ICH8M CPIO20 should not be pulled HIGH.
GPIO7 R259 *10K_4 ICH8M GPIO(3 of 4) 3B
C2A:(12/21) no stuff R259 to prevent leakage issue Remove BOARD_ID3 circuit(remove R474,R475)
5 4 3 2 1
5 4 3 2 1
+3V_S5 +3V
VCCRTC
C332 C352 C330 +1.05V
2
D25 D40
1U_4 .1U_4 .1U_4 U32F
AD25 A13 +1.05V_SB R505 0_1206
PDZ5.6B PDZ5.6B VCCRTC VCC1_05[01] U32E
VCC1_05[02] B13
A16 C13 A23 K7
1
R331 10_6 R266 100_6 +5VREF_SB V5REF[1] VCC1_05[03] C382 VSS[001] VSS[099]
+5V_S5 +5V T7 V5REF[2] VCC1_05[04] C14 A5 VSS[002] VSS[100] L1
D14 C373 A1A:(9/28) EMI suggest C373 from 0.1u to 10uF AA2 L13
C401 C385 +5VREF_SUS_SB VCC1_05[05] .1U_4 VSS[003] VSS[101]
G4 V5REF_SUS VCC1_05[06] E14 AA7 VSS[004] VSS[102] L15
F14 10U_8 A25 L26
.1U_4 .1U_4 VCC1_05[07] VSS[005] VSS[103]
AA25 VCC1_5_B[01] VCC1_05[08] G14 AB1 VSS[006] VSS[104] L27
AA26 L11 +1.5V AB24 L4
VCC1_5_B[02] VCC1_05[09] VSS[007] VSS[105]
AA27 VCC1_5_B[03] VCC1_05[10] L12 AC11 VSS[008] VSS[106] L5
D D
AB27 VCC1_5_B[04] VCC1_05[11] L14 AC14 VSS[009] VSS[107] M12
AB28 L16 VCCDMIPLL_ICH R239 1_8 AC25 M13
+1.5V_PCIE VCC1_5_B[05] VCC1_05[12] L27 VSS[010] VSS[108]
AB29 VCC1_5_B[06] VCC1_05[13] L17 AC26 VSS[011] VSS[109] M14
D28 L18 1UH_1210 AC27 M15
VCC1_5_B[07] VCC1_05[14] C348 C340 VSS[012] VSS[110]
D29 VCC1_5_B[08] VCC1_05[15] M11 AD17 VSS[013] VSS[111] M16
CORE
+1.5V L56 E25 M18 <Description> AD20 M17
FBMJ2125HS420-T_8 VCC1_5_B[09] VCC1_05[16] .01U_4 10U_6 VSS[014] VSS[112]
E26 VCC1_5_B[10] VCC1_05[17] P11 AD28 VSS[015] VSS[113] M23
E27 VCC1_5_B[11] VCC1_05[18] P18 AD29 VSS[016] VSS[114] M28
Intel use 0.5UH inductor + C543 C360 C346 C353 F24 T11 AD3 M29
VCC1_5_B[12] VCC1_05[19] +1.25V VSS[017] VSS[115]
F25 VCC1_5_B[13] VCC1_05[20] T18 AD4 VSS[018] VSS[116] M3
220U_7343 22U_8 22U_8 2.2U_6 G24 U11 AD6 N1
VCC1_5_B[14] VCC1_05[21] VSS[019] VSS[117]
H23 VCC1_5_B[15] VCC1_05[22] U18 AE1 VSS[020] VSS[118] N11
H24 V11 +1.25V_DMI R451 0_8 +1.05V AE12 N12
VCC1_5_B[16] VCC1_05[23] VSS[021] VSS[119]
J23 VCC1_5_B[17] VCC1_05[24] V12 AE2 VSS[022] VSS[120] N13
J24 VCC1_5_B[18] VCC1_05[25] V14 AE22 VSS[023] VSS[121] N14
+1.5V K24 V16 C544 R216 0_6 AD1 N15
VCC1_5_B[19] VCC1_05[26] VSS[024] VSS[122]
K25 VCC1_5_B[20] VCC1_05[27] V17 AE25 VSS[025] VSS[123] N16
A1A: (9/20) Change back R489 to 0 ohm L23 V18 22U_8 AE5 N17
VCC1_5_B[21] VCC1_05[28] C356 C341 C541 VSS[026] VSS[124]
L24 VCC1_5_B[22] AE6 VSS[027] VSS[125] N18
VCCA3GP
R450 0_8+1.5V_SATA R489 0_8+1.5V_APLL_RR +1.5V_APLL L25 R29 AE9 N26
VCC1_5_B[23] VCCDMIPLL .1U_4 .1U_4 4.7U_6 VSS[028] VSS[126]
M24 VCC1_5_B[24] AF14 VSS[029] VSS[127] N27
L60 C390 C396 M25 AE28 AF16 N4
10UH_8 VCC1_5_B[25] VCC_DMI[1] +1.05V_V_CPU_IO VSS[030] VSS[128]
N23 VCC1_5_B[26] VCC_DMI[2] AE29 AF18 VSS[031] VSS[129] N5
CV01001MN08 10U_6 1U_6 N24 +3V AF3 N6
VCC1_5_B[27] VSS[032] VSS[130]
N25 VCC1_5_B[28] V_CPU_IO[1] AC23 AF4 VSS[033] VSS[131] P12
P24 VCC1_5_B[29] V_CPU_IO[2] AC24 AG5 VSS[034] VSS[132] P13
P25 VCC1_5_B[30] AG6 VSS[035] VSS[133] P14
R24 AF29 +V3.3_DMI_ICH R213 0_6 AH10 P15
VCC1_5_B[31] VCC3_3[01] VSS[036] VSS[134]
R25 VCC1_5_B[32] AH13 VSS[037] VSS[135] P16
R26 AD2 +V3.3_SATA_ICH R326 0_6 AH16 P17
VCC1_5_B[33] VCC3_3[02] VSS[038] VSS[136]
R27 VCC1_5_B[34] AH19 VSS[039] VSS[137] P23
T23 AC8 +V3.3S_VCCPCORE_ICH AH2 P28
C VCC1_5_B[35] VCC3_3[03] VSS[040] VSS[138] C
T24 VCC1_5_B[36] VCC3_3[04] AD8 AF28 VSS[041] VSS[139] P29
VCCP_CORE
T27 AE8 C397 C545 AH22 R11
VCC1_5_B[37] VCC3_3[05] VSS[042] VSS[140]
T28 VCC1_5_B[38] VCC3_3[06] AF8 AH24 VSS[043] VSS[141] R12
T29 .1U_4 .1U_4 AH26 R13
C375 VCC1_5_B[39] +V3.3S_IDE_ICH VSS[044] VSS[142]
U24 VCC1_5_B[40] VCC3_3[07] AA3 AH3 VSS[045] VSS[143] R14
U25 VCC1_5_B[41] VCC3_3[08] U7 AH4 VSS[046] VSS[144] R15
1U_6 V23 V7 C395 AH8 R16
VCC1_5_B[42] VCC3_3[09] VSS[047] VSS[145]
V24 VCC1_5_B[43] VCC3_3[10] W1 AJ5 VSS[048] VSS[146] R17
V25 W6 .1U_4 R302 0_6 B11 R18
IDE
VCC1_5_B[44] VCC3_3[11] VSS[049] VSS[147]
W25 VCC1_5_B[45] VCC3_3[12] W7 B14 VSS[050] VSS[148] R28
Y25 Y7 R303 0_6 B17 R4
VCC1_5_B[46] VCC3_3[13] VSS[051] VSS[149]
B2 VSS[052] VSS[150] T12
AJ6 A8 +V3.3S_PCI_ICH R309 0_6 B20 T13
VCCSATAPLL VCC3_3[14] VSS[053] VSS[151]
VCC3_3[15] B15 B22 VSS[054] VSS[152] T14
AE7 VCC1_5_A[01] VCC3_3[16] B18 B8 VSS[055] VSS[153] T15
C384 AF7 B4 C24 T16
VCC1_5_A[02] VCC3_3[17] VSS[056] VSS[154]
ARX
AG7 VCC1_5_A[03] VCC3_3[18] B9 C26 VSS[057] VSS[155] T17
1U_6 AH7 C15 C372 C379 C388 C27 T2
VCC1_5_A[04] VCC3_3[19] VSS[058] VSS[156]
AJ7 D13 C6 U12
PCI
VCC1_5_A[05] VCC3_3[20] .1U_4 .1U_4 .1U_4 VSS[059] VSS[157]
VCC3_3[21] D5 D12 VSS[060] VSS[158] U13
AC1 VCC1_5_A[06] VCC3_3[22] E10 D15 VSS[061] VSS[159] U14
AC2 VCC1_5_A[07] VCC3_3[23] E7 D18 VSS[062] VSS[160] U15
A1A:(10/30) change to +1.5V
ATX
AC3 VCC1_5_A[08] VCC3_3[24] F11 D2 VSS[063] VSS[161] U16

AC4 VCC1_5_A[09] D4 VSS[064] VSS[162] U17
AC5 AC12 +3V_1.5V_HDA_IO_ICH R287 0_6 +3V E21 U23
VCC1_5_A[10] VCCHDA R308 *0_6 VSS[065] VSS[163]
+1.5V E24 VSS[066] VSS[164] U26
AC10 AD11 +VCCSUSHDA R286 0_6 +3V_S5 E4 U27
VCC1_5_A[11] VCCSUSHDA R313 *0_6 C377 VSS[067] VSS[165]
AC9 VCC1_5_A[12] +1.5V_S5 E9 VSS[068] VSS[166] U3
J6 TP_VCCSUS1_05_ICH_1 C380 F15 U5
VCCSUS1_05[1] TP_VCCSUS1_05_ICH_2 .1U_4 VSS[069] VSS[167]
AA5 VCC1_5_A[13] VCCSUS1_05[2] AF20 E23 VSS[070] VSS[168] V13
AA6 .1U_6 A1A:(10/25) Add +1.5V_S5 F28 V15
R327 0_6 +1.5V_USB VCC1_5_A[14] TP_VCCSUS1_5_ICH_1 VSS[071] VSS[169]
VCCSUS1_5[1] AC16 F29 VSS[072] VSS[170] V28
B B
G12 VCC1_5_A[15] F7 VSS[073] VSS[171] V29
C387 G17 J7 TP_VCCSUS1_5_ICH_2 +3V_S5 G1 W2
VCC1_5_A[16] VCCSUS1_5[2] VSS[074] VSS[172]
H7 VCC1_5_A[17] E2 VSS[075] VSS[173] W26
.1U_4 C3 +V3.3A_ICH R316 0_6 G10 W27
VCCSUS3_3[01] VSS[076] VSS[174]
AC7 VCC1_5_A[18] G13 VSS[077] VSS[175] Y28
AD7 VCC1_5_A[19] VCCSUS3_3[02] AC18 G19 VSS[078] VSS[176] Y29
AC21 C345 C369 G23 Y4
VCCSUS3_3[03] VSS[079] VSS[177]
D1 VCCUSBPLL VCCSUS3_3[04] AC22 G25 VSS[080] VSS[178] AB4
VCCPSUS
AG20 .1U_4 22N_4 G26 AB23

VCCSUS3_3[05] VSS[081] VSS[179]
F1 VCC1_5_A[20] VCCSUS3_3[06] AH28 G27 VSS[082] VSS[180] AB5
USB CORE
L6 VCC1_5_A[21] H25 VSS[083] VSS[181] AB6

C404 L7 P6 H28 AD5
VCC1_5_A[22] VCCSUS3_3[07] VSS[084] VSS[182]
M6 VCC1_5_A[23] VCCSUS3_3[08] P7 H29 VSS[085] VSS[183] U4
.1U_4 M7 C1 H3 W24
VCC1_5_A[24] VCCSUS3_3[09] +V3.3A_USB_ICH R340 0_8 VSS[086] VSS[184]
VCCSUS3_3[10] N7 H6 VSS[087]
+1.5V_SATA W23 P1 J1 A1
VCC1_5_A[25] VCCSUS3_3[11] VSS[088] VSS_NCTF[01]
VCCSUS3_3[12] P2 J25 VSS[089] VSS_NCTF[02] A2
TP_VCCLAN1_05_ICH_1 F17 P3 C415 J26 A28
VCCLAN1_05[1] VCCSUS3_3[13] VSS[090] VSS_NCTF[03]
VCCPUSB
TP_VCCLAN1_05_ICH_2 G18 P4 J27 A29

VCCLAN1_05[2] VCCSUS3_3[14] 4.7U_6 TP_VCCLAN1_05_ICH_1 C365 .1U_6 VSS[091] VSS_NCTF[04]
VCCSUS3_3[15] P5 J4 VSS[092] VSS_NCTF[05] AH1
+3V R461 0_6 +3V_VCCLAN F19 R1 TP_VCCLAN1_05_ICH_2 C371 .1U_6 J5 AH29
VCCLAN3_3[1] VCCSUS3_3[16] VSS[093] VSS_NCTF[06]
G20 VCCLAN3_3[2] VCCSUS3_3[17] R3 K23 VSS[094] VSS_NCTF[07] AJ1
C366 R5 TP_VCCSUS1_05_ICH_1 C391 .1U_6 K28 AJ2
+1.5V_VCCGLANPLL VCCSUS3_3[18] TP_VCCSUS1_05_ICH_2 C362 .1U_6 VSS[095] VSS_NCTF[08]
A24 VCCGLANPLL VCCSUS3_3[19] R6 K29 VSS[096] VSS_NCTF[09] AJ28
.1U_4 K3 AJ29
VSS[097] VSS_NCTF[10]
GLAN POWER
A26 G22 TP_VCCCL1_05_ICH TP_VCCSUS1_5_ICH_1 K6 B1

VCCGLAN1_5[1] VCCCL1_05 T62 VSS[098] VSS_NCTF[11]
A27 TP_VCCSUS1_5_ICH_2 B29
VCCGLAN1_5[2] T65 VSS_NCTF[12]
B26 A22 VCCCL1_5_INT_ICH TP_VCCCL1_05_ICH
VCCGLAN1_5[3] VCCCL1_5 T58
+1.5V R458 1_8 L57 1UH_1210 B27 ICH8M REV 1.0
VCCGLAN1_5[4] +V3.3M_ICH C364 C367
B28 VCCGLAN1_5[5] VCCCL3_3[1] F20
C361 C358 G21
<Description> VCCCL3_3[2] 1U_6 *.1U_4
B25 VCCGLAN3_3
A 10U_6 2.2U_6 A
ICH8M REV 1.0
+1.5V_PCIE
C359
R257 0_6 +3V
PROJECT : ZU1
4.7U_6
R240 0_6 +3V_GLAN
+3V
ICH8M Power(4 of 4) 3B
5 4 3 2 1
5 4 3 2 1
A1A: (9/20) Change from +3V_S5 to +3V_LAN_S5

+3V_S5
Giga LAN BCN5787M
A1A:(9/27) Change +3V_LAN_S5 to +3V_S5
10
18
27
38
50
56
4
1
6
9
C59 C46 to Docking
.1U_4
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
GND11
GND12
GND13
10U_8 TX0P 2 48 TX0P_PR
A1A:(9/28) EMI suggest C59 from 0.1u to 10uF A0 0B1 TX0P_PR 33
47 TX0N_PR
1B1 TX0N_PR 33
TX0N 3 A1 TX1P_PR
2B1 43 TX1P_PR 33
42 TX1N_PR
3B1 TX1N_PR 33
D11 BAS316
LINKLED# 1 2 LAN_MB_LINKLED# TX1P 7 37 TX2P_PR
A2 4B1 TX2P_PR 33
D10 BAS316 36 TX2N_PR
5B1 TX2N_PR 33
D 100# 1 2 TX1N 8 D
VAUX_12 D9 BAS316 A3 TX3P_PR
6B1 32 TX3P_PR 33
+3V_S5 1000# 1 2 TX3N_PR
PI3L500 7B1 31 TX3N_PR 33
TX2P 11 22
A4 0LED1 LAN_ACTLED# 33
1LED1 23 LAN_LILED# 33
C122 C61 C123 C82 C92 TX2N 12 52
C467 C457 C456 C468 A5 2LED1
.1U-16V_4 .1U-16V_4 .1U-16V_4 .1U-16V_4 .1U-16V_4 VAUX_25 46 TX0P_SYS
4.7U-10V_8 .1U-16V_4 .1U-16V_4 .1U-16V_4 0B2 TX0N_SYS
1B2 45
TX3P 14 A6
VDDP+AVDD) 41 TX1P_SYS
VAUX_12 TX3N 2B2 TX1N_SYS
15 A7 3B2 40
U10 C460 C459 +3V_S5
BCM5787MKMLG .1U-16V_4 .1U-16V_4 VAUX_25 35 TX2P_SYS
L11 BLM11A601S_6 4B2 TX2N_SYS
5B2 34
VAUX_12 BIASVDD LAN_MB_ACTLED# 19
C71 C67 C121 C79 C89 R376 LED0 TX3P_SYS
15
19
56
61
17
68
6B2 30
6
LAN_MB_LINKLED# 20 29 TX3N_SYS
4.7U-10V_8 .1U-16V_4 .1U-16V_4 .1U-16V_4 .1U-16V_4 C65 LED1 7B2
5
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDP
VDDP
VDDC .1U-16V_4 10K_4 SYS_ACTLED#
13 VDDC BIASVDD 36 54 LED2 0LED2 25
20 26 SYS_LINKLED#
VDDC L48 BLM11A601S_6 D4 BAS316 LAN_DOCKIN# 1LED2
34 VDDC 16,33 DOCKIN# 17 SEL 2LED2 51
55 23 XTALVDD
VDDC XTALVDD
60 A1A: (9/20) Add Diode for isolation A1A:(9/20) Add SYS_ACTLED#,
GND00
GND01
GND02
GND03
GND04
GND05
GND06
GND07
GND08
GND09
GND10
VDDC
L10 BLM11A601S_6 C458 0: A to B1 5 NC SYS_LINKLED#
AVDDL 39 38 .1U-16V_4 1: A to B2 U6
AVDDL AVDD L14 BLM11A601S_6 PI3L500 (LAN SW)
44
C58 C62 46
AVDDL
BCM5787M 45 AVDD_F14
13
16
21
24
28
33
39
44
49
53
55
AVDDL 10mm X 10mm AVDD
51 AVDDL
4.7U-10V_8 .1U-16V_4 68-Pin QFN 52 A1A:(9/20) the chip already integrate
AVDD
L12 BLM11A601S_6 C455 C63 internal terminators A1A: 9/6 chnage from MAX4892 to PI3L500
VAUX_12 GPHY_PLLVDD 35 .1U-16V_4 .1U-16V_4
C57 C68 GPHY_PLLVDD D3A:(1/31) Don't use AL000500005 and use AL000500030 only(change to 8KV solution)
49 TX3N
4.7U-10V_8 .1U-16V_4 TRD3- TX3P
C TRD3+ 50 C
L13 BLM11A601S_6
+3V_S5 PCIE_PLLVDD 30 48 TX2N
C77 C80 PCIE_PLLVDD TRD2- TX2P
TRD2+ 47
VAUX_25
4.7U-10V_8 .1U-16V_4 42 TX1N BLM11A601S_6 U3
Q17 L9 BLM11A601S_6 TRD1- TX1P L8 +3V_2.5V_LAN 1
27 PCIE_VDD TRD1+ 43 TCT1 MCT1 24
2
DTC144EUA R80 PCIE_SDS_VDD 33 TX0P_SYS 2 23 X-TX0P

4.7K_4 C66 C75 PCIE_VDD TX0N C449 C42 TX0N_SYS TD1+ MX1+ X-TX0N
TRD0- 41 3 TD1- MX1- 22
40 TX0P
4.7U-10V_8 .1U-16V_4 TRD0+ .1U-16V_4.1U-16V_4 +3V_2.5V_LAN 4
24 PCIE_GND TCT2 MCT2 21
3 1 PCIE_WAKE_R# 2 LINKLED# TX1P_SYS 5 20 X-TX1P
16,27 PCIE_WAKE# LINKLED# TD2+ MX2+
1 100# +3V_S5 TX1N_SYS 6 19 X-TX1N
SPD100LED# 1000# TD2- MX2-
SPD1000LED# 67
C85 .1U-16V_4 TXDP_C 26 66 LAN_MB_ACTLED# +3V_2.5V_LAN 7 18
15 PCIE_RXP3 PCIE_TXDP TRAFFICLED# TCT3 MCT3
C88 .1U-16V_4 TXDN_C 25 TX2P_SYS 8 17 X-TX2P
15 PCIE_RXN3 PCIE_TXDN TD3+ MX3+
31 8 T72 R38 R29 R66 R382 TX2N_SYS 9 16 X-TX2N
15 PCIE_TXP3 PCIE_RXDP GPIO2 C450 C38 TD3- MX3-
15 PCIE_TXN3 32 PCIE_RXDN
PCIE_WAKE_R# 12 4.7K_4 U5 +3V_2.5V_LAN 10 15
R79 0_4 -LAN_RST WAKE# *4.7K_4 .1U-16V_4.1U-16V_4 TX3P_SYS TCT4 MCT4 X-TX3P
15,16,21,25,26,27,28,30,33 PLTRST# 10 PERST# UART_MODE 9 T73 11 TD4+ MX4+ 14
A1A: (9/20) Internal PU

29 7 T3 BCM_WP 4.7K_4 BCM_SDA 1 8 SI TX3N_SYS 12 13 X-TX3N
A1A:(9/1 BCM recommend) 2 CLK_PCIE_LAN REFCLK+ GPIO1_SERIALDI 4.7K_4 BCM_SCL SI SO TD4- MX4-
2 CLK_PCIE_LAN# 28 REFCLK- GPIO0_SERIALDO 4 T2 2 SCK GND 7
Pull up Vmainprsnt (U10/Pin53) to the system main power (3.3v), BCM_RESET# 3 6 NS892402P R28 R27 R26 R25
but not the standby power . RESET# VCC +3V_S5
BCM_RESET# CS# 4 5 BCM_WP
R377 1K_4 AUX_PRES CS# WP# C52
+3V_S5 54 VAUXPRSNT
+3V R378 1K_4 VMA_PRES 53 .1U-16V_4 75_4 75_4 75_4 75_4
R806 *0_4 VMAINPRSNT BCM_SCL AT45DB011B-SC(LAN FLASH) A1A:(10/11) C31
28 LOW_PWR 3 LOW_PWR SCLK 65 MGND
63 SI Change the pin name from GND to MGND
R78 LAN_SMBC SI BCM_SDA 1500P-2KV_1808
2,13,16,27,33 PCLK_SMB 58 SMB_CLK SO 64
4.7K_4 LAN_SMBD 57 62 CS#
2,13,16,27,33 PDAT_SMB SMB_DATA CS#
C94 27P-50V_4 XTALO_R R60 200_4 XTALO 22 59 R579 D3A:(1/21) Add CableSence circuit (reserve R579)
XTALO NC/(ENERGY_DET) ENERGY_DET 28 CN19
XTALI 21 0_4
D3A:(1/21) Add CableSence circuit (unstuff R78) XTALI
+3V_S5
E3A:(3/21) Stuff R78 (Disable LAN Low Power mode) Y1 RDAC 37 R369 220_4 11
RDAC +3V_S5 YELLOW__P
3
B
E3A:(3/30) Base on PM suggestion, 25Mhz 18 LAN REGCTL25 C54 C44 B
add serial 0 ohm (R806) for debug use. R42 REGCTL25 Q9 SYS_ACTLED# 12 YELLOW_N
(default : no stuff) 1.18K_6 1 MMJT9435 .1U-16V_4 4.7U-10V_8
C114 27P-50V_4
14 LAN REGCTL12
REGCTL12 X-TX3N 1
2
4
RX2-
VAUX_25
T74 11 X-TX3P 2
NC(CLK_REQ#) C53 C51 RX2+
REG_GND 16
LAN_REG1_2V X-TX1N 3
A1A: (9/1 BCM recommend) .1U-16V_4 47U-6.3V_1210 RX1-
Change pull-up resistor value to 47-k. at pin 58 (SMB)CLK) X-TX2N 4 13
GND
TX2- GND1
3
and pin 57 (SMB_DATA) as the SM-Bus isn't used. Package Body C90 C86
10U/10V_8
Q16 X-TX2P 5 14 C445 .1U-10V_4
MMJT9435 .1U-16V_4 TX2+ GND2
1
69
A1A: (9/1 BCM recommend) X-TX1P 6 C11 .01U-16V_4

Change capacitance value from 47-uF to 10-uF. RX1+
A1A: (9/1 BCM recommend) change R42 to 1.24k as default A1A:(9/20) change from
LAN_MB_ACTLED#, LAN_MB_LINKLED# to X-TX0N 7 C36 1500P-2KV_1808
2
4
C2A: (12/12) base on BCM IEEE test result, change RDAC value from 1.24k to 1.18k TX1-
VAUX_12 SYS_ACTLED#, SYS_LINKLED#
+3V_S5 CS# SI BCM_SCL X-TX0P 8
C93 C104 TX1+
.1U-16V_4 10U-6.3V_8
R61 R379 R380 R72 R368 220_4 9 GREEN_P MGND
+3V_S5 A1A:(10/11)
4.7K_4 *4.7K_4 4.7K_4 *4.7K_4
SYS_LINKLED# 10 Change the pin name from GND to MGND in CN26.13
C651 C109 GREEN_N
CS# LAN_REG1_2V R30 1.5_1206 +3V_S5
*.1U-16V_4 *.1U-16V_4 AOP_C100D8-108A4-L
R47 *1_1206 VAUX_25

A1A:(9/21) Change CONN (refer to ZC1)
C2A:(12/28) EMI request: reserve .1U for EMI Solution
A EEPROM Strapping A1A: (9/1 BCM recommend) A
stuff R30,no stuff R47(in order to pull up C90,C86 and Q16/pin 3 to
3V_LAN rail)
SO SI CS# SCLK
24c64 1 1 0 1
AT45DB011B 1 0 1 1 PROJECT : ZU1

GigaLAN (BCM5787M) / RJ45 3B

5 4 3 2 1
1 2 3 4 5 6 7 8
CRT Select
A A
D3A:(2/12) Reserve R525 for docking CRT flicker issue

U4
16 R525 0_6 +5V
INT_CRT_RED VCC SYS_VGA_RED
6 INT_CRT_RED 4 C_A A0 2
A1 3 DOCK_R 33
INT_CRT_GRN 7 5 SYS_VGA_GRN C41
6 INT_CRT_GRN C_B B0
6 .1U_4
B1 DOCK_G 33
INT_CRT_BLU 9 11 SYS_VGA_BLU
6 INT_CRT_BLU C_C C0
C1 10 DOCK_B 33
12 C_D D0 14
D1 13
PR_INSERT_5V 1
20,33 PR_INSERT_5V SE
15 EN# GND 8
SN74CBTLV3257PWR
SEL FUNCTION
LOW IN_0
HIGH IN_1
A1A: (9/20) Remove NEZ@ ciucuit
B B
CRT CONNECTOR AND ESD

CRT_SENSE#_L D37 MTW355 CRT_SENSE# 15,28,33
C8 .1U_4
A1A:(10/18) Change CRT_SENSE# from
CRT CONN Pin11 to Pin5
D38
D1 SSM14
+5V E3A:(3/29) Stuff D38 for ESD issue MTW355
C652
D3A:(2/12) EMI suggest add C652(0.1uF) .1U_4 CRTVDD3 CN18

16
RESERVE FOR ESD

SUY_070546FR015S200ZR
6
SYS_VGA_RED L5 BLM18BA470SN1(47,300MA) CRT_R1 1 11
7
SYS_VGA_GRN L4 BLM18BA470SN1(47,300MA) CRT_G1 2 12
8
SYS_VGA_BLU L6 BLM18BA470SN1(47,300MA) CRT_B1 3 13
C C
9
4 14
R5 R6 R7 C15 C16 C17 C6 C5 C4 10
150_4 150_4 150_4 10P_4 10P_4 10P_4 10P_4 10P_4 10P_4 5 15
CRT_SENSE#_L
17
D3A:(11/30) EMI issue.

Change L4,L5,L6 from CX8BA220007 to CX8BA470003
A1A: (9/20) change name from CRTVDD3 to +5V A1A:(9/21) Change CONN P/N (Follow ZC1)
D3A:(2/12) Reserve C98 for docking CRT flicker issue
+5V
DOCK_VSYNC 33
C98
DOCK_HSYNC 33
.1U_4
A1A: (9/20) change from 39ohm to 0 ohm
+5V
U1
1 16 CRTVSYNC1 R12 0_4 L43 BLM18BA220SN1_6 CRTVSYNC
C25 VCC_SYNC SYNC_OUT2 CRTHSYNC1 R10 0_4 L44 BLM18BA220SN1_6 CRTHSYNC
SYNC_OUT1 14
.1U_4 7
C23 .22U/25V_6 VCC_DDC C439 C440
8 BYP
15 INT_VSYNC +5V
SYNC_IN2 INT_HSYNC *47P-50V_4 *47P-50V_4
+3V 2 VCC_VIDEO SYNC_IN1 13
A1A:change from 2.7k to 2.2k
C22 CRT_R1 3 10 INT_CRT_DDCCLK R16 2.2K_4 R370 R371
VIDEO_1 DDC_IN1 +3V
.1U_4 CRT_G1 4 11 INT_CRT_DDCDAT R17 2.2K_4 2.7K_4 2.7K_4
CRT_B1 VIDEO_2 DDC_IN2
5 VIDEO_3
9 DDCCLK_1
DDC_OUT1 DOCK_DDCK 33
6 12 DDCDAT_1
GND DDC_OUT2 DOCK_DDDA 33
D D
A1A:(10/18) Change net name: IP4772 CM2009: AL002009W01
from SYS_VGA_RED to CRT_R1 C7 C441 to Docking
from SYS_VGA_GRN to CRT_G1 IP4772: AL004772000
from SYS_VGA_BLU to CRT_B1 *47P-50V_4 *47P-50V_4
6 INT_HSYNC
6 INT_VSYNC A1A: (9/20) change to 30 ~ 50p, default: don't stuff PROJECT : ZU1
6 INT_CRT_DDCCLK
6 INT_CRT_DDCDAT
CRT 3B
1 2 3 4 5 6 7 8
5 4 3 2 1
LVDS
CN2
6 INT_TXLOUT2- INT_TXLOUT2- 1
INT_TXLOUT2+ 1
6 INT_TXLOUT2+ 3 3
B1C: (11/20) 5
(1) change PWM control from 965GM to EC INT_TXLOUT1- 5
6 INT_TXLOUT1- 7 7
(2) Short L7, un-stuff C28 (L-C filter will impact PWM signal) INT_TXLOUT1+ 9
(3)stuff R13,no stuff R15 6 INT_TXLOUT1+ 9
11 11
6 INT_TXLOUT0- INT_TXLOUT0- 13
C2A:(12/28) EMI request: reserve L-C footprint for debug use (R52,C650) INT_TXLOUT0+ 13
15
D3A:(2/12) Stuff R15, Change PWM control from EC to 965GM
D3A:(2/14) Acer inform no support DPST in C build, remove R15
6 INT_TXLOUT0+
INT_TXLCLKOUT-
17
19
15
17 E3A:(3/14)Change MB LCD connector pin define(CN2) and LCD cable pin define to cover production line issue
CAMERA MODULE
6 INT_TXLCLKOUT- 19 (Inverter short with signal to burn system)->ZR1 issue
INT_TXLCLKOUT+ 21
6 INT_TXLCLKOUT+ 21 (1)pin 27,29->NC
23 23
INT_LVDS_EDIDCLK 25 (2)pin 28,30->INVCC(VIN)->same as C build
6 INT_LVDS_EDIDCLK 25 (3)pin 8->INT_LVDS_EDIDDATA +3V
T142 27
T143 27 CCD_POWER
29 29 +3V 1 3
A1A:(10/2) change from USB7 to USB8 R20 0_4 USBP8-_CN 2
15 USBP8- 2
R19 0_4 USBP8+_CN +3V C30 10U_8
+
D 15 USBP8+ 4 4 D
6 Q1 R21
2
A1A: (9/20) Come from 965GM for PWM control INT_LVDS_EDIDDATA 6 AO3413 C444 1000P_4 4.7K_4
6 INT_LVDS_EDIDDATA 8 8
R15 *0_4 DISPON 10
6 INT_LVDS_PWM 10
R13 0_4 VADJNEW 12
28 CONTRAST 12 BECAUSE UR'S SUGGESTION,
C28 *.1U_4 14 R11
+3V 14 ACTICE CHANGE FROM LOW TO HIGH.
3
16 16
CCD_POWER 18 2.2K_4
DMIC-CLK R52 0_4 DMIC-CLK_1 18
31 DMIC-CLK 20 20 2 CCD_POWERON 28
DMIC-12 22 INT_LVDS_EDIDCLK
E3A:(3/15) Link C650 from DMIC-CLK to DMIC-CLK_1 31 DMIC-12 22 6 INT_LVDS_EDIDCLK
C650 LCDVCC 24
*10P_4 24 Q2
26
1
VIN R8 0_8 INVCC0 26 +3V DTC144EU
28 28 31 31
30 30 32 32
+3V ACS_88242-3001
R9
2.2K_4
1
C12
+ C13 C14 INT_LVDS_EDIDDATA
6 INT_LVDS_EDIDDATA
10U-25V_1210 1000P_4 1000P_4
2
A1A(10/5):Change C12 from CH6102M9900
to CH61004M3E5 (refer to ZC3)
E3A:(4/3) EOL issue change from CH61004M3E5 to CH61004M398 A1A: (9/20) Change LVDS CONN to 30pin
+3V (9/21)change footprint to 88242-3000-30P-RUV
C24 U2
.1U_4 6 1 LCDVCC_1 R18 0_8 LCDVCC

IN OUT
4 2 C26 C18 C20
IN GND C27 C29
DISP_ON 3 5 .1U_4 .01U_4 10U_8
6 INT_LVDS_DIGON ON/OFF GND .1U_4 10U_8
C AAT4280 C
R14
<demo circuit>
Crestline suggest 100K 100K_4
D3A:(2/12)
G73 suggest 10K(ZS1 Default) change U2 from AL004280000(AAT4280IGU-3-T1) to AL004280018(AAT4280IGU-1-T1).
8/27 change back to 100K rise time of LCDVCC is >0.5ms and <=10ms.
AL004280018 can meet this spec
TV Out (SVHS) MiniDIN 7-pin MR Sensor

D3A:(2/12) Follow ZO1 design,
Remove R24 footprint, DEL D3(BC000316Z07).
Add R73,Q36,Q37
D3A:(2/12) system sometimes will no backlight issue .

TV-CHROMA For short term solution:
change R22 from 10k(CS31002JB28) to 1K (CS21002FB24)
+3V
3
R73 R22
MR# 16,28,29
1K_4
B B
10K_4
2
D35 DISPON D2
U8 LID591# 16,28,29
3
16 +5V *DA204U BAS316
VCC
3
4 2 SYS_TV_Y/G
6 INT_TV_Y/G C_A A0 +3V
A1 3 DOCK_TV_Y/G 33
7 5 SYS_TV_C/R BL# 2 2
6 INT_TV_C/R C_B B0 EC_FPBACK# 28
6 C78
B1 DOCK_TV_C/R 33
3
9 11 SYS_TV_COMP .1U_4 Q37
6 INT_TV_COMP C_C C0
10 2N7002 Q3
DOCK_TV_COMP 33
1
C1 DTC144EUA
12 14
1
C_D D0 INT_LVDS_BLON
D1 13 6 INT_LVDS_BLON 2
PR_INSERT_5V 1
19,33 PR_INSERT_5V SE
15 8 TV-LUMA
EN# GND R23 Q36
SN74CBTLV3257PWR 2N7002
1
SEL FUNCTION
3
100K_4
LOW IN_0
HIGH IN_1 A1A: (9/20) Remove "NEZ@" circuit
1
D36
CN17 *DA204U
BLM18PG181SN1D_6
+3V
5
L3 L1 BLM18PG181SN1D_6
SYS_TV_C/R TV-CHROMA 6 4 TV-LUMA SYS_TV_Y/G
5
6 4
9 9 8 8
R2 C19 C3 C1 C9 R3
150_4 6P_4 6P_4 6P_4 6P_4 150_4 TV-COMP
A 3 3 1
A
7
3
7
A1A:(9/21) Change CONN (Follow ZC1) SUY_030107FR007S112FR

L2 BLM18PG181SN1D_6
TV-COMP SYS_TV_COMP
1
D34
*DA204U PROJECT : ZU1

R4 +3V
C2 C10
6P_4 6P_4 150_4
LVDS/MR senseor/SVIDEO 3B
5 4 3 2 1
5 4 3 2 1
SDVO-DVI
A1A:(9/21) Change R51,R56 value from 2.2k to 4.7k.
6 SDVOB_R+ (FAE suggest R value from 4K~9K)
6 SDVOB_R-
+2.5V R56 4.7K_4 SDVO_CTRLCLK
C2A:(12/12)Follow Intel New Guideline(MoW 48 update)
6 SDVOB_G+ Change R51,R56 from 4.7K to 3.9K ohm
6 SDVOB_G-
DVI_AVDD +2.5V R51 4.7K_4 SDVO_CTRLDATA
D3A:(2/6)
6 SDVOB_B+ change R51,R56 from 3.9k(CS23902FB14) to 4.7k(CS24702JB38).
6 SDVOB_B- fix ZU1 docking sometimes can't detect DVI device issue
NB internal PD for SDVO is not implement
6 SDVOB_CLK+
Nedd external PU for SDVO exist
D 6 SDVOB_CLK- D
INT- C107 .1U_4

PEG_RXN1 6
DVI_AVDD
INT+ C97 .1U_4
PEG_RXP1 6
AS->Address Select (Internal pull-up)
This pin determines the serial port address of the device (0,1,1,1,0,0,AS*,0).
When AS is low the address is 72h, when high the address is 70h.
48
47
46
45
44
43
42
41
40
39
38
37
U12
AVDD3
AVDD2
SDVOB_CLK-
SDVOB_CLK+
AGND3
SDVOB_B-
SDVOB_B+
SDVOB_G-
SDVOB_G+
AGND2
SDVOB_R-
SDVOB_R+
+2.5V R62 10K_4 R63 *100K_4
15,16,18,25,26,27,28,30,33 PLTRST#
+3V L46 BLM11A601S_6 DVI_AVDD_PLL 1 36 DVI_AVDD L16 BLM11A601S_6 +2.5V

AVDD_PLL AVDD1
2 RESET* RSV 35
C108 C115 AS 3 34 C125 C111 C124 C117
AS BSCAN INT-
6 SDVO_CTRLCLK 4 SPC SDVOB_INT- 33
.1U_4 10U_8 5 32 INT+ .1U_4 .1U_4 .1U_4 10U_8
6 SDVO_CTRLDATA SPD SDVOB_INT+
6 AGND_PLL AGND1 31
7 DGND1 DGND2 30
8 29 TMDS_HPD
SD_PROM HPDET DVI_DVDD
9 SC_PROM DVDD2 28
33 DOCK_DDC_DT 10 SD_DDC PROM2 27
33 DOCK_DDC_CK 11 SC_DDC PROM1 26
+2.5V L47 BLM11A601S_6 DVI_DVDD 12 25
DVDD1 VSWING
TGND1
TGND2
TVDD1
TVDD2
TDC0*
TDC1*
TDC2*
TDC0
TDC1
TDC2
C87 C91 C81 R50
TLC*
TLC
.1U_4 .1U_4 10U_8 1.2K_4
C C
13
14
15
16
17
18
19
20
21
22
23
24
CH7307C-DEF
to Docking DVI_TVDD L45 BLM11A601S_6 +3V

C73 C72 C74
.1U_4 .1U_4 10U_8

33 DVI_CLK-
33 DVI_CLK+
33 DVI_D0-
33 DVI_D0+
33 DVI_D1-
33 DVI_D1+
33 DVI_D2-
33 DVI_D2+
+3V +3V
R574 R575
10K_4 100K_4
TMDS_HPD
3
B B
Q33 Q35
2 2 DVI_DET
DVI_DET 33
2N7002 2N7002
1
C2A:(12/12) Intel suggest:Add hotplug circuit to DVI_DET (follow ZC1)
D3A:(1/30) remove U13,R68,R75,R73,C98 C2A:(12/22) confrim with FAE ->

1/16 confirm with CHRONTEL FAE, Due to Intel VBIOS already integrate the EEPROM function.
A he said we can remove CH9901 (U13), ZU1 will remove the U11,R57,R52,C109 to save layout space. A
If ZU1 need support HDCP,
just need change controller from CH7307 to CH7313.
CH7313 already integrated HDCP function, no need external EEPROM.
PROJECT : ZU1
DVI (CH7307) 3B
5 4 3 2 1
5 4 3 2 1
+3V
PCI_CLK_CB714 R190 *22_4 PCLK_PCM_R C302 *10p_4
C534 C532 C531 C537 R178 *0_6 PCIRST#

R177 100K_6
+3V
.1U_4 .1U_4 .1U_4 .1U_4
CB_RSMRST#
VCCD1#
VCCD0#
C281 VPPD1
C535 C536 C295 C303 .22U_6 VPPD0
D .1U_4 .1U_4 .1U_4 .1U_4 INTA# A_CRSVD/D2 D
15 INTA# A_CRSVD/D2 24
SERIRQ A_CRSVD/D14
16,23,28,30 SERIRQ A_CRSVD/D14 24
PCI_PME# R445 0_4 PCM_PME# A_CRSVD/A18
15,23,25 PCI_PME# A_CRSVD/A18 24
PCMSPK_DELAYR805 0_4
PCMSPK R804 *0_4 CB_RSMRST# A_CCD1# A_CCD1#
+3V A_CCD1# 24
REQ0# A_CCD2# A_CCD2#
15 REQ0# A_CCD2# 24
C283 C282 GNT0#
15 GNT0#
AD17 R189 47_4 PCM_IDSEL A_CVS1# C539 C533
A_CVS1# 24
.1U_4 .1U_4 PCIRST# R437 A_CVS2#
15,23,27 PCIRST# A_CVS2# 24
PCI_CLK_CB714
2 PCI_CLK_CB714
R572 R567 10P_4 10P_4
FRAME# 43K_4
15,23,25 FRAME#
IRDY#
15,23,25 IRDY#
PCM_SUS#
TRDY# 0_4 0_4
15,23,25 TRDY#
DEVSEL# T119 T117 T116
15,23,25 DEVSEL# T118 T115
STOP#
15,23,25 STOP#
PERR#
15,23,25 PERR#
SERR#
15,23,25 SERR#
M10
M11
M13
M12
N11
N10
N13
N12
E10
L11
L10
L12
J13
M1
M9
G4
H1
N9
C6
D9
K3
K1
B1
A1
K9
K8
A2
A4
F4
U17
L3
L2
L1
L8
J4
AD[31..0] A_CAD[31..0]
SERR#
PERR#
STOP#
DEVSEL#
TRDY#
IRDY#
FRAME#
PCICLK
PCIRST#
IDSEL
PCIGNT#
PCIREQ#
G_RST#
SUSPEND#
SPKROUT
RI_OUT#/PME#
MFUNC6
MFUNC5
MFUNC4
MFUNC3
MFUNC2
MFUNC1
MFUNC0
VCCD1#
VCCD0#
VPPD1
VPPD0
RSVD/D2
RSVD/D14
RSVD/A18
CCD1#/CD1#
CCD2#/CD2#
CVS1/VS1
CVS2/VS2
15,23,25 AD[31..0] A_CAD[31..0] 24
AD0 N8 B2 A_CAD31
AD1 AD0 CAD31/D10 A_CAD30
K7 AD1 CAD30/D9 C3
+5V +3V U18 +3V AD2 L7 B3 A_CAD29
N7 AD3 CAD28/D8 A3
VCCD0# 1 16 AD4 M7 C4 A_CAD27
VCCD1# VCCD0# SHDN# VPPD0 AD5 AD4 CAD27/D0 A_CAD26
C 2 VCCD1# VPPD0 15 N6 AD5 CAD26/A0 A6 C
3 14 VPPD1 AD6 M6 D7 A_CAD25
3.3V VPPD1 AVCC AVPP AD7 AD6 CAD25/A1 A_CAD24
4 3.3V AVCC 13 K6 AD7 CAD24/A2 C7
5 12 AD8 M5 A8 A_CAD23
5V AVCC AD9 AD8 CAD23/A3 A_CAD22
6 5V AVCC 11 L5 AD9 CAD22/A4 D8
7 10 AD10 K5 A9 A_CAD21
GND AVPP AD11 AD10 CAD21/A5 A_CAD20
8 OC# 12V 9 M4 AD11 CAD20/A6 C9
AD12 K4 A10 A_CAD19
AD13 AD12 CAD19/A25 A_CAD18
N3 AD13 CAD18/A7 B10
AD14 M3 D10 A_CAD17
ENE CP-2211 AD15 N2
AD14 CAD17/A24
E12 A_CAD16
J2 AD16 CAD15/IOWR# F10
AD17 J1 E13 A_CAD14
AVCC AVPP AVCC AD18 AD17 CAD14/A9 A_CAD13
H4 AD18 CAD13/IORD# F13
AD19 H3 F11 A_CAD12
G3 AD20 CAD11/OE# G10
AD21 G2 G11 A_CAD10
C530 C298 C285 C286 C297 C538 AD22 AD21 CAD10/CE2# A_CAD9
F1 AD22 CAD9/A10 G12
AD23 F2 H12 A_CAD8
4.7U_6 .1U_4 4.7U_6 .1U_4 .1U_4 .1U_4 AD24 AD23 CAD8/D15 A_CAD7
E2 AD24 CAD7/D7 H10
AD25 E3 J11 A_CAD6
E4 AD26 CAD5/D6 J12
AD27 D1 K13 A_CAD4
D2 AD28 CAD3/D5 J10
AD29 D4 K10 A_CAD2
+5V +3V AD30 AD29 CAD2/D11 A_CAD1
C1 AD30 CAD1/D4 K12
AD31 C2 L13 A_CAD0
AD31 CAD0/D3
CSTSCHG/BVD1/STSCHG#
C312 C313 C311 C296
CCLKRUN#/WP/IOIS16#
CBE0#
CAUDIO/BVD2/SPKR#
B N5 B
CINT#/READY/IREQ#
15,23,25 CBE0# CBE0#
4.7U_6 .1U_4 4.7U_6 .1U_4 CBE1# N1
15,23,25 CBE1# CBE1#
CBE2# A_CC/BE0#
CREQ#/INPACK#
15,23,25 CBE2# J3 CBE2# CCBE0#/CE1# H13 A_CC/BE0# 24
CSERR#/WAIT#
CDEVSEL#/A21
CBE3# A_CC/BE1#
CRST#/RESET
E1 E11
CFRAME#/A23
CBLOCK#/A19
15,23,25 CBE3# CBE3# CCBE1#/A8 A_CC/BE1# 24
CPERR#/A14
CSTOP#/A20
CTRDY#/A22
PAR A_CC/BE2#
CGNT#/WE#
M2 A11
CIRDY#/A15
15,23,25 PAR PAR CCBE2#/A12 A_CC/BE2# 24
A_CC/BE3#
CCLK/A16
CCBE3#/REG# B7 A_CC/BE3# 24
D13 A_CPAR
VCCA1
VCCA2
VCC10
CPAR/A13 A_CPAR 24
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
CB1410
D3
H2
L4
M8
K11
F12
C10
B6
F3
G1
K2
N4
L6
L9
H11
G13
A7
D12
C8
B4
B5
C5
D6
D11
C11
B8
A5
C13
C12
B13
A13
A12
B11
D5
B9
B12
+3V AVCC +3V
PCMSPK +3V
+3V C703
D41
C704
2 *0.1U/X7R-50V_6 *.1U_4
5
PCM-2 1
3 PCMSPK_DELAY
4 PCMSPK_DELAY 31
PCM-1 2
1 U41
3
*CHN217 *TC7SH08FU R577

C700 C701 D39 *10K_4 R_A_CCLK R446 10_4 A_CCLK
A_CCLK 24
C702 A_CRST#
2 A_CRST# 24
*.1U_4 *0.1U/X7R-50V_6 A_CCLKRUN#
A_CCLKRUN# 24
A *0.1U/X7R-50V_6 PCM-3 C705 A
3 A_CFRAME#
*.1U_4 A_CFRAME# 24
A_CIRDY#
1 A_CIRDY# 24
A_CTRDY#
A_CTRDY# 24
*CHN217 A_CDEVSEL# <OrgName>
A_CDEVSEL# 24
A_CSTOP#
PCM-4 R432 *200K/F_4 PCM-5 A_CPERR#
A_CSTOP# 24
<OrgAddr1> PROJECT : ZU1
A_CPERR# 24
A_CSERR# <OrgAddr2>
C706 R571 A_CREQ#
A_CSERR# 24
A_CREQ# 24
<OrgAddr3> Quanta Computer Inc.
*86.6K/F_4 A_CGNT# <OrgAddr4>
A_CGNT# 24
*0.1U/X7R-50V_6 A_CBLOCK#
A_CBLOCK# 24
A_CINT# Size Document Number Rev
A_CINT# 24
A_CSTSCHG PCMCIA (ENE CB1410) 3B
A_CSTSCHG 24
A_CAUDIO
A_CAUDIO 24
5 4 3 2 1
5 4 3 2 1
SERIRQ
16,22,28,30 SERIRQ
48MHz Clock
ID Select : AD18 INTB# SDPWREN33# +3V
15 INTB# SDPWREN33# 24 Y6
Interrupt Pin : INTB# GND_SD SDCLKI 3 4
OUT VDD
Request Indicate : REQ1# 2 1 C576
24 XDRE#/MSCLK GND OE
xDDATA3/MSDATA3 R534
xDDATA3/MSDATA3 24
Grant Indicate : GNT1# xDDATA5/MSDATA2 *TXC-48MHz-30PPM-15Pf *.01U_4
24 SDWP xDDATA5/MSDATA2 24
xDDATA2/MSDATA0 *0_4
24 SDCD# xDDATA2/MSDATA0 24
XDDATA6/MSDATA1
XDDATA6/MSDATA1 24
D XDWP# +3V D
+3V_CRVCC XDWP# 24
XDBSY#
+3V +3V XDBSY# 24
R548
PRST#
+3V_CRVCC A1A:(9/26) Add 22ohm for R490 and 10p for C839
SUSPEND#
GND_SD
SERIRQ
A1A:(9/22) no stuff R496,R522 Change Y7 from 50MHz to 48MHz
R573
R522 *0_4 XDCE#
XDCE# 24
SDCD#
T126T124 T122 43K_4 A1A:(9/28) base on EMI suggest: remove R490,C839
R496 *0_4 T127 T125 T123 T121
SDWP
SUSPEND#
GRST# should +3V
connect to Power 0_4
On reset if
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
U39 A1A:(9/22) XMDAT4B is for 8 bit MMC,remove it.
99
98
97
support S3
NC
VCC
VSS
XPMPWR_ENIZ
XPMPWR_VCC
NC
NC
XSDCDIZ
XSDWPISMWPDIZ
XMSCLKOSMREOZ
XMSDAT3BSMDAT3B
XMSDAT2BSMDAT5B
XMSDAT0BSMDAT2B
XMSDAT1BSMDAT6B
VCC_SD
XMDAT5BSMWPOZ
XMDAT6BSMBSYIZ
XMFUNC7B
GND_SD
XSUSPENDIZ
XMFUNC6B
XMFUNC5B
XMFUNC4B
XGRSTIZ
XMFUNC3B
XMFUNC2B
VCC
XMFUNC1B
XMDAT4B
XMDAT7BSMCEOZ
VSS
XPMPWR_O
AD[31..0]
15,22,25 AD[31..0]
AD0 96 XDDATA1/MSBS
MSBSOSMDAT1 XDDATA1/MSBS 24
AD1 SDPWREN33# 1 95 XDPWREN#MSPWREN#
XSDPWR33OZ MS_SMPWROZ XDPWREN#MSPWREN# 24
AD2 2 94 INTB#
C AD3 GND_SD NC MFUNC0 510_PME# R564 0_4 PCI_PME# C
3 GND_SD RIOUTZ_PMEOZ 93 PCI_PME# 15,22,25
AD4 xDCLE/SDDAT2 4 92 R563 43K_4
24 XDCLE/SDDAT2 SDDAT2SMCLE VSS +3V
AD5 xDDATA4/SDDAT35 91 AD0
24 xDDATA4/SDDAT3 SDDAT3SMDAT4 PCIAD0
AD6 xDALE/SDCMD 6 90 MSINX#
24 xDALE/SDCMD SDCMDSMALE MSINSIZ MSINX# 24
AD7 XDWE#/SDCLK 7 89 XDCD#
24 XDWE#/SDCLK SDCLKSMWEOZ SMCDIZ XDCD# 24
AD10 10 86 AD3
+3V_CRVCC VCC_SD PCIAD3
AD11 11 85 AD4
AD12 NC PCIAD4 AD5
12 NC PCIAD5 84
AD13 13 83 AD6
AD14 NC PCIAD6 AD7
14 NC PCIAD7 82
AD15 15 D3A:(2/12) 81
NC (1)no stuff 43K(CS34302JB19): VCC +3V
AD16 REQ# 16 80
15 REQ1# PCIREQOZ R562,R527,R533,R538,R539,R565,R561,R540,R498,R497,R500,R552,R555 VSS
AD17 GNT# 17 79
15 GNT1# PCIGNTIZ (2)no stuff 10k(CS31002JB28) : R560 NC
AD18 AD31 18 78
AD19 AD30 PCIAD31 (3) Change R547 from 43k (CS34302JB19) to 8.2k (CS28202JB14) NC
19 PCIAD30 NC 77
AD20 AD29 20 (4)Change R528 from 10K(CS31002JB28) to 43K(CS34302JB19) 76
AD21 PCIAD29 NC
21 VSS NC 75
AD22 AD28 22 74 C/BE0#
PCIAD28 PCICBE0Z CBE0# 15,22,25 A1A:(9/22) Add PU/PD resister
AD23 AD27 23 73 AD8
AD24 AD26 PCIAD27 PCIAD8 AD9
24 PCIAD26 PCIAD9 72
AD25 AD25 25 71 AD10 XDDATA1/MSBS R562 *43K_4
AD26 AD24 PCIAD25 PCIAD10 AD11 xDDATA3/MSDATA3 R527 *43K_4
26 PCIAD24 PCIAD11 70
B AD27 C/BE3# 27 69 xDDATA5/MSDATA2 R533 *43K_4 B
15,22,25 CBE3# PCICBE3Z VCC +3V
AD28 AD18 R503 47_4 510_IDSEL 28 68 AD12 xDDATA2/MSDATA0 R538 *43K_4
AD29 PCIIDSELI PCIAD12 AD13 XDDATA6/MSDATA1 R539 *43K_4
+3V 29 VCC PCIAD13 67
AD30 30 66 AD14
NC PCIAD14
PCIDEVSELZ
AD31 AD15 +3V
PCISERROZ
PCIFRAMEZ
31 NC PCIAD15 65
PCIPERRZ
PCISTOPZ
PCITRDYZ
A1A:(9/22) FAE suggest R value under 47 ohm.
PCICBE2Z
PCICBE1Z
PCIIRDYZ
32
PCIRSTIZ
PCIAD23
PCIAD22
PCIAD21
PCIAD20
PCIAD19
PCIAD18
PCIAD17
PCIAD16
NC
PCICLKI
PCIPAR
SDCLKI XDCD# R560 *10K_4
VCC SDCD# R565 *43K_4
VCC
VSS
VSS
SDWP R561 *43K_4
NC
NC
NC
NC
NC
NC
NC
+3V +3V_CRVCC
MR510
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
A1A:(9/26) For EMI solution
PCI_CLK_510_L
(close to MR510) XDWP# R540 *43K_4

XDCE# R556 43K_4
C599 C607 C636 C637 XDWE#/SDCLK R499 43K_4
FRAME#
C/BE2#
C/BE1#
DEVSEL#
PERR#
SERR#
TRDY#
STOP#
PRST#
PCI_CLK_510_L XDBSY# R547 8.2K_4
IRDY#
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
SDCLKI
PAR
.1U_4 .1U_4 .1U_4 .1U_4 XDRE#/MSCLK R528 43K_4
R524 XDALE/SDCMD R498 *43K_4
XDCLE/SDDAT2 R497 *43K_4
*0_4 XDDATA0/SDDAT1 R500 *43K_4
XDDATA4/SDDAT3 R552 *43K_4
1
+3V +3V C600 XDDATA7/SDDAT0 R555 *43K_4
15,22,27 PCIRST#
C577 C643 C645 C646
2 PCI_CLK_510
R529 22_4A1A:(9/26) For EMI solution *10P_4
2
A .1U_4 .1U_4 .1U_4 .1U_4 A
+3V_CRVCC 15,22,25 CBE2#
15,22,25 FRAME#
15,22,25 IRDY# PROJECT : ZU1
15,22,25 TRDY#
C615 C582 C618
15,22,25 DEVSEL#
15,22,25 STOP#
C644 C566
15,22,25 PERR#
15,22,25 SERR# Size Document Number Rev
.1U_4 .1U_4 .1U_4 .1U_4 .1U_4
15,22,25 PAR 3B
15,22,25 CBE1# Card Reader (MR510)
5 4 3 2 1
5 4 3 2 1
AVCC
R438 43K_4 A_CAD11
CN13 FOX_WZ21131-G2-8F
1 GND
A_CAD0 2
22 A_CAD0 D3 - CAD0
Main Source:TTN DFHD36MR000 22 A_CAD1
A_CAD1
A_CAD3
3
4
D4 - CAD1 GND 75
76
D 2nd Source:NorthStar DFHS36FR003 22
22
A_CAD3
A_CAD5
A_CAD5 5
D5 - CAD3
D6 - CAD5
GND
GND 77 D
A_CAD7 6 78
22 A_CAD7 D7 - CAD7 GND
A_CC/BE0# 7 79
22 A_CC/BE0# CE1- CCBE0 GND
A_CAD9 8 80
22 A_CAD9 A10- CAD9 GND
A_CAD11 9 81
22 A_CAD11 OE - CAD11 GND
A_CAD12 10 82
+3V_CRVCC 22 A_CAD12 A11- CAD12 GND
A_CAD14 11 83
22 A_CAD14 A9 - CAD14 GND
A_CC/BE1# 12 84
22 A_CC/BE1# A8 - CCBE1 GND
A_CPAR 13
22 A_CPAR A13- CPAR
CN15 A_CPERR# 14
22 A_CPERR# A14- CPERR
XDBSY# 1 A_CGNT# 15
23 XDBSY# xD-R/B 22 A_CGNT# WE/PGM - CGNT
XDRE#/MSCLK_R 2 A_CINT# 16
xD-RE 22 A_CINT# RDY/BSY,IRQ*INT
XDCE# 3 17
23 XDCE# xD-CE AVCC VCC
XDCLE/SDDAT2 4
23 XDCLE/SDDAT2 xD-CLE
XDALE/SDCMD 5 18
23 XDALE/SDCMD xD-ALE AVPP VPP1
XDWE#/SDCLK_R 6 A_CCLK 19
xD-WE 22 A_CCLK A16- CCLK
XDWP# 7 A_CIRDY# 20
23 XDWP# xD-WP 22 A_CIRDY# A15- CIRDY
XDDATA0/SDDAT1 8 A_CC/BE2# 21
23 XDDATA0/SDDAT1 xD-D0 22 A_CC/BE2# A12- CCBE2
XDDATA1/MSBS 9 A_CAD18 22
23 XDDATA1/MSBS xD-D1 22 A_CAD18 A7 - CAD18
XDCLE/SDDAT2 10 A_CAD20 23
SD-DAT2 22 A_CAD20 A6 - CAD20
XDDATA4/SDDAT3 11 A_CAD21 24
SD-DAT3 22 A_CAD21 A5 - CAD21
XDALE/SDCMD 12 A_CAD22 25
SD-CMD 22 A_CAD22 A4 - CAD22
13 A_CAD23 26
4in1-GND 22 A_CAD23 A3 - CAD23
14 A_CAD24 27
MS-VCC 22 A_CAD24 A2 - CAD24
XDRE#/MSCLK_R 15 A_CAD25 28
MS-SCLK 22 A_CAD25 A1 - CAD25
XDDATA3/MSDATA3 16 A_CAD26 29
MS-DATA3 22 A_CAD26 A0 - CAD26
MSINX# 17 A_CAD27 30
23 MSINX# MS-INS 22 A_CAD27 D0 - CAD27
XDDATA5/MSDATA2 18 22 A_CAD29
A_CAD29 31 A1A:(9/22) Change PCMCIA CONN (follow BH1)
XDDATA2/MSDATA0 MS-DATA2 A_CRSVD/D2 D1 - CAD29
19 MS-DATA0 22 A_CRSVD/D2 32 D2 - RFU
XDDATA6/MSDATA1 20 A_CCLKRUN# 33
MS-DATA1 22 A_CCLKRUN# WP,IOIS16-CKRUN
XDDATA1/MSBS 21 34
MS-BS GND
22 4in1-GND
C C
23 SD-VCC 35 GND
XDWE#/SDCLK_R 24 A_CCD1# 36
SD-CLK 22 A_CCD1# CD1- CCD1
SD-DAT0 22 A_CAD2 D11- CAD2
23 XDDATA2/MSDATA0 xD-D2 22 A_CAD4 D12- CAD4
23 XDDATA3/MSDATA3 xD-D3 22 A_CAD6 D13- CAD6
XDDATA4/SDDAT3 28 A_CRSVD/D14 40
23 XDDATA4/SDDAT3 xD-D4 22 A_CRSVD/D14 D14- RFU
SD-DAT1 22 A_CAD8 D15- CAD8
23 XDDATA5/MSDATA2 xD-D5 22 A_CAD10 CE2- CAD10
XDDATA6/MSDATA1 31 A_CVS1# 43
23 XDDATA6/MSDATA1 xD-D6 22 A_CVS1# RFSH,VS*1-CVS1
23 XDDATA7/SDDAT0 xD-D7 22 A_CAD13 IORD-CAD13
33 A_CAD15 45
xD-VCC 22 A_CAD15 IOWR-CAD15
XDCD# 34 A_CAD16 46
23 XDCD# xD-CD-SW 22 A_CAD16 A17- CAD16
SDWP 35 A_CRSVD/A18 47
23 SDWP SD-WP-SW 22 A_CRSVD/A18 A18- RFU
SDCD# 36 A_CBLOCK# 48
23 SDCD# SD-CD-SW 22 A_CBLOCK# A19- CBLOCK
37 A_CSTOP# 49
GND 22 A_CSTOP# A20- CSTOP
38 A_CDEVSEL# 50
GND 22 A_CDEVSEL# A21- CDEVSEL
AVCC 51 VCC
TTN_R015-210-LM 52
AVPP VPP2
A_CTRDY# 53
22 A_CTRDY# A22- CTRDY
A_CFRAME# 54
22 A_CFRAME# A23- CFRAME
A_CAD17 55
22 A_CAD17 A24- CAD17
A_CAD19 56
22 A_CAD19 A25- CAD19
XDWE#/SDCLK XDWE#/SDCLK_R A_CVS2# 57
23 XDWE#/SDCLK 22 A_CVS2# NC - CVS2
R493 22_4 A_CRST# 58
22 A_CRST# RESET-CRST
R488 A_CSERR# 59
A1A:(9/26) For EMI solution 22 A_CSERR# WAIT-CSERR
A_CREQ# 60
(close to socket) 22 A_CREQ# INPACK-CREQ
*0_4 A_CC/BE3# 61
22 A_CC/BE3# REG- CCBE3
A_CAUDIO 62
22 A_CAUDIO BVD2,SP-CAUDIO
1
C562 A_CSTSCHG 63
22 A_CSTSCHG BVD1,STSCHG-C*
A_CAD28 64
*10P_4 22 A_CAD28 D8 - CAD28
B A_CAD30 65 B
22 A_CAD30
2
A_CAD31 D9 - CAD30
22 A_CAD31 66 D10- CAD31
A_CCD2# 67
22 A_CCD2# CD2- CCD2
68 GND
85 HOLE1
86
N-PTH_Hole
N-PTH_Hole
XDCD# +3V HOLE2
87 HOLE3
A1A:(9/26) For EMI solution 88 HOLE4
1
C642 (close to socket)
GND
GND
GND
GND
MSINX# R523 43K_4
1
*10P_4 C598
2
69
70
71
72
73
74
*10P_4
2
XDRE#/MSCLK XDRE#/MSCLK_R A1A:(9/26) PU MSINX# to +3V

23 XDRE#/MSCLK
R515 22_4
R514
A1A:(9/26) For EMI solution
*0_4 (close to socket)
1
C581
+3V +3V +3V_CRVCC
*10P_4
2
Q32
R535 1 8
GND OUT
2 IN OUT 7
3 6 C587 C593 A1A:(9/26)Change C593 from 0.1u to 10uF
43K_4 IN OUT .1U_4 A1A:(9/28)EMI suggest add C587 0.1uF
XDPWREN#MSPWREN# R537 0_4 4 5 10U-10V_8
23 XDPWREN#MSPWREN# EN# OUTNC
A SDPWREN33# R536 0_4 A
23 SDPWREN33#
G545B2P8U
+3V
C617
PROJECT : ZU1
.1U_4

CARD Reader & PCMCIA SLOT 3B
5 4 3 2 1
5 4 3 2 1
+3V PLTRST# R518 *0_4 GNT2#
C580 C579
R516
22P-50V_4 22P-50V_4
Y5
22K_4
G_RST# C2A:(12/26) Base on vendor-FCE suggestion,

2 1 change C580/C579 from CH01206JB05 (12p) to CH02206JB08 (22p)
C588
.1U-10V_4 24.576MHZ
D D
15 INTE#
2 PCLK_1394
C549
15 GNT2#
R479 R478
15 REQ2#
1U-16V_6
15,22,23 PCI_PME#
C572 R487 56.2_4 56.2_4
15,22,23 AD[0..31]
.1U-10V_4 R554 0_6 L1394_TPA2+
R510 6.34K_4 R559 0_6 L1394_TPA2-
R553 0_6 L1394_TPB2+
R550 0_6 L1394_TPB2-
4.7K_4
+3V +3V C609 PLLVDD AVDD
FILTER1
FILTER0
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
.1U-10V_4 R285 R284
R0
R1
56.2_4 56.2_4
XO
A1A(10/24):change P/N and footprint to 1394-020115FR004SX01ZL-4P-H
XI
A1A(10/25):change footprint to 1394-020115FR004S518ZL-4P-V
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
U33 R271 C376
99
98
97
CN32
270P-25V_4 5
VDDP
PCI_PCLK
XI
PCI_AD24
PCI_AD25
REG18
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
G_RST#
PCI_INTA#
PCI_CLKRUN#
REG_EN#
XO
DVDD
DGND
PCI_AD31
PCI_PME#
PCI_REQ#
PCI_GNT#
DGND
DVDD
PLLGND
FILTER1
FILTER0
R0
R1
PLLVDD
AVDD
AGND
5.1K_4 L1394_TPB2- 1
B1C:(11/23) change R271,R306,R307 value from 56.2 to 5.1k L1394_TPA2- 3 6
L1394_TPA2+ 4
1 96 TPBIAS2 L1394_TPB2+ 2
DGND TPBIAS2 TPA2+
15,22,23 CBE3# 2 PCI_C/BE3# TPA2+ 95
AD25 R531 150_4 3 94 TPA2-
VDDP TPA2-
4 PCI_IDSEL AVDD 93
AD23 5 92 TPB2+ C378 SUY_020115FR004S518ZL
AD22 PCI_AD23 TPB2+ TPB2- R477 R476
6 PCI_AD22 TPB2- 91
7 90 1U-16V_6
AD21 DVDD AVDD 56.2_4 56.2_4
8 PCI_AD21 AGND 89
AD20 9 88 TPBIAS1
AD19 PCI_AD20 TPBIAS1 TPA1+ R281 0_6 1394TPAP1
10 PCI_AD19 TPA1+ 87 1394TPAP1 33
C AD18 11 86 TPA1- R280 0_6 1394TPAN1 C
PCI_AD18 TPA1- 1394TPAN1 33
12 85 R279 0_6 1394TPBP1
DGND AVDD 1394TPBP1 33
AD17 13 84 R278 0_6 1394TPBN1
PCI_AD17 AGND 1394TPBN1 33
AD16 14 83 TPB1+
PCI_AD16 TPB1+ TPB1-
15,22,23 CBE2# 15 PCI_C/BE2# TPB1- 82
16 VDDP AVDD 81
17 80 R295 R294
15,22,23 FRAME# PCI_FRAME# AGND
18 79 TPBIAS0
15,22,23 IRDY# PCI_IRDY# TPBIAS0
19 78 TPA0+ 56.2_4 56.2_4
DVDD TPA0+ TPA0-
15,22,23 TRDY# 20 PCI_TRDY# TPA0- 77
15,22,23 DEVSEL# 21 PCI_DEVSEL# AGND 76
22 75 TPB0+
15,22,23 STOP# PCI_STOP# TPB0+
23 74 TPB0-
DGND TPB0- R306 C389
15,22,23 PERR# 24 PCI_PERR# AGND 73
25 72 AVDD
15,22,23 SERR# PCI_SERR# AVDD
26 71 270P-25V_4
15,22,23 PAR PCI_PAR AGND
27 70 5.1K_4
15,22,23 CBE1# DVDD AVDD
28 69 R323 390K_4
AD15 PCI_C/BE1# CPS
29 PCI_AD15 PHY_TEST_MA 68
30 VDDP CNA 67
AD14 31 66
GPIO3/TEST1
GPIO2/TEST0
PCI_AD14 DGND
32 65
PCI_C/BE0#
CYCLEOUT
DGND DVDD
PCI_RST#
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
CYCLEIN
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
REG18
DGND
DGND
DGND
DVDD
DVDD
VDDP
SDA
SCL
PC2
PC1
PC0
R321 R322 C392

R293 R292
1U-16V_6
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
TSB43AB23 4.7K_4 4.7K_4 56.2_4 56.2_4
R277 0_6 1394TPAP0

1394TPAP0 33
R276 0_6 1394TPAN0
1394TPAN0 33
R275 0_6 1394TPBP0
1394TPBP0 33
SDA R274 0_6 1394TPBN0
1394TPBN0 33
SCL
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
R291 R290
B B
56.2_4 56.2_4
R517 C571
15,22,23 CBE0#
R512 R502 R494
15,16,18,21,26,27,28,30,33 PLTRST#
.1U-10V_4
4.7K_4 4.7K_4 220_4 220_4
R307 C386
+3V 270P-25V_4
5.1K_4
C383
.1U-10V_4
+3V
R297 R296
PLLVDD
2.7K_4 2.7K_4
U23 L58
1 8 BLM18PG181SN1D_6
A0 VCC C558
2 A1 NC 7
10U/10V_8
3 6 C565 C574
A3 SCL 1000p/50V_4 1000p/50V_4
4 GND SDA 5
24LC02BT AVDD
L59
BLM18PG181SN1D_6
C557 C553 C394 C561 C552 C555 C550 C551
10U/10V_8
C595
A 1000p/50V_4 1000p/50V_4 .01U_4 .01U_4 .1U-10V_4 .1U-10V_4 .1U-10V_4 A
1000p/50V_4
C556 C628 C605 C554 C578 C626 C623

10U/10V_8
C603 C625 C597 C627 C624

.01U_4 .01U_4 .01U_4 .01U_4 .01U_4 .1U-10V_4 .1U-10V_4 .1U-10V_4 .1U-10V_4 270P-25V_4 270P-25V_4 PROJECT : ZU1
1394(TSB43AB23) 3B
5 4 3 2 1
1 2 3 4
SATA HDD CN27
GND1 1
RXP 2 SATA_TXP0 14
A1A:(10/2)change footprint to SATA-C166D9-100B-22P-R 3
A1A:(10/9)change footprint to SATA-C16669-100A-22P-R RXN SATA_TXN0 14
GND2 4
5 SATA_RXN0 14
TXN
6 SATA_RXP0 14
1 2
TXP
GND3 7 2 1
RST
GND
+5V R249 0_8 HDD_VDD 8 +3.3VSATA R225 *0_8 +3V
A 3.3V A
3.3V 9
3.3V 10
GND 11
C381 12
C368 + C370 C374 GND
GND 13 20
14 HDD_VDD
.1U_4 150U_7343 .1U_4 .1U_4 5V
5V 15
5V 16 SATA HDD DOESN'T USE 3V PWR
GND 17
RSVD 18
19
GND
GND
12V 20
+3.3VSATA
X
12V 21
12V 22
43 44 44 43
C351 C350 C354
*4.7U_8 *4.7U_8 *.1U_4

AOP_C16669-12204-L
PATA ODD
B B
+3V +5V
Q24
2
DTC144EU R236
10K_4
R252 *0_4
16 RST_HDD#
R253 33_4 1 3 -IDERST
15,16,18,21,25,27,28,30,33 PLTRST#
A1A: change from 0 to 33ohm
+5V
C325 C329 C331 C324
.1U_4 .1U_4 .1U_4 .1U_4

A1A:(9/29) change footpint: CDR-C124A9-100C-50P
C
ODD Connector C
CN26
1 2
-IDERST 3 4 PDD8
PDD7 5 6 PDD9 PDD0 PDD[0..15] 14
PDD6 7 8 PDD10 PDD1
PDD5 9 10 PDD11 PDD2
PDD0 19 20 PDDREQ PDD7
21 22 PDIOR# PDD8
PDIOW# 23 24 PDD9
PIORDY 25 26 PDDACK# PDD10
IRQ14 27 28 PDD11
PDA1 29 30 -PDIAG PDD12
PDA0 31 32 PDA2 PDD13
PDCS1# 33 34 PDCS3# PDD14
ODDLED# 35 36 PDD15
29 IDELED# 37 38 PDIOR#
39 40 PDIOR# 14
+5V +5V PDIOW#
41 42 PDIOW# 14
PDDACK#
A1A:(10/30) remove D23, already add in page29 43 44 PDDACK# 14
IRQ14
45 46 IRQ14 14
RCSEL PIORDY
47 48 PIORDY 14
C344 PDDREQ
51
52
49 50 + PDDREQ 14
C327 C326
PDA[2:0] 14
51
52
R203 .1U_4 150U_7343 .1U_4 PDA0

PDA1
470_4 PDA2
D D
NC FOR SLAVE
PDCS1#
PDCS1# 14
AOP_C124A9-150A1-L PDCS3#
PDCS3# 14
A1A:(10/30) add 150uF ,0.1uF for +5V
-PDIAG R217 *10K_4 +5V

PROJECT : ZU1
R223 4.7K_4 PIORDY
A1A:(10/30) no stuff +3V
<check list & FAE>
+3V
R218 8.2K_4 IRQ14 Must be PU even when IDE device is not use Quanta Computer Inc.
SATA-HDD & PATA-ODD 3B
1 2 3 4
1 2 3 4 5 6 7 8
MINI-Card
BLUETOOTH MODULE CONNECTOR A1A: (9/25) change CONN (follow ZH3)
D3A:(2/8)EMI suggest, add common Choke, co-lay R795,R796 CN5

BT_POWER
1
2
15 USBP4+ 3
15 USBP4- 4
BT_LED
29 BT_LED 5
Q10
AO3413 ACS_88266-05001-06
A A
+3VSUS 1 3 BT_POWER_R L15 BK2125HS330_8 BT_POWER
C105 10U_8 C102
+
.01U_4
2
C101 1000P_4
A1A:(10/25) SI suggest to remove 22pF*2

BT_POWERON# 28
A1A: (9/20) Change from +3V to +3V_WL_VDD

A1A: (10/23)change +3V to +3VSUS
B1C: (10/23)change from +3VSUS to +3V
USB CONN +5V_S5

U16
2 8 USBPWR1
IN1 OUT3
3 IN2 OUT2 7
OUT1 6
+3V +1.5V 4
L28 28 USBON# EN#
1 GND
+3V_WL_VDD 9 5 R435 *6.34K_4
GND-C OC#
FBJ3216HS800_1206 +5V_S5 TPS2061DGNR
C398 C413 C414 C419 + C402 C403
10U/10V/X5R_8 .1U_4 .1U_4 .1U_4
10U_8 .1U_4
C305
.1U_4 USBPWR1
B B
POWER DECOUPLING
C279
C289
100U_3528 1000P_4
CN11
D3A:(1/21) Stuff R349,R350 for debug use +1.5V +3V_WL_VDD +3V_WL_VDD 1 5

15 USBP0- 2 6
A1A:(10/30)change form +3VSUS to +3V_WL_VDD 15 USBP0+ 3 7
4 8
A1A:9/4 Reserved for debug only 0_4 R336 +1.5V_MINI-Card
SUY_020133MB004S557ZL
U15
+ C424 C422 CM1293-04SO
15,22,23 PCIRST#
PCIRST# R349 0_4 CL_DATA1_CN 1 CH1 CH4 6 +5V_S5 A1A: (9/24)change USB CONN (follow ZC3)
PCLK_SIO R350 0_4 CL_CLK1_CN 10U_8 .1U_4
2,30 PCI_CLK_SIO
2 VN VP 5
3 CH2 CH3 4
CN28 A1A:(10/25) SI suggest to remove 22pF*2

B1C:(11/29) no stuff R353,R348,R356 51 52
R353 *0_4 CL_RST#0_CN Reserved +3.3V
16 CL_RST#1 49 Reserved GND 50
R348 *0_4 CL_DATA1_CN 47 48
16 CL_DATA1 Reserved +1.5V A1A: (9/26) Remove (CN28/Pin46)BT_LED
R356 *0_4 CL_CLK1_CN 45 46
16 CL_CLK1 Reserved LED_WPAN#
R354 0_4 KEDRON_GND_43 43 44
R351 0_6 KEDRON_VCC Reserved LED_WLAN# WIRELESS_LED# 29
41 42
A1A(10/30): +3V_WL_VDD 39
Reserved LED_WWAN#
40 B1C:(11/13) Robson ES1 to ES2 change. CN21 +5V_S5
Add (CN28/Pin39,41) to R355 0_4KEDRON_GND_37 Reserved GND PIN 37 => GND USBON#
37 Reserved USB_D+ 38 1 1 2 2
+3V_WL_VDD (follow ZO1) 35 36 A1A: (9/20) Remove USB ciucuit 3 4 +5V_S5 C45
GND USB_D- B1C:(11/20) need support BCM module 15 USBP1- 3 4
15 PCIE_TXP4 33 PETp0 GND 34 15 USBP1+ 5 5 6 6
C 31 32 MINI_DAT_SMB PIN 40 => GND 7 8 C
15 PCIE_TXN4 PETn0 SMB_DATA 7 8
29 30 MINI_CLK_SMB 9 10
GND SMB_CLK 15 USBP2- 9 10
27 28 11 12 .1U_4
GND +1.5V 15 USBP2+ 11 12
PCIE_RXP4 25 26
15 PCIE_RXP4 PERp0 GND
PCIE_RXN4 23 24 (B-B) ACS 88028-1210M
15 PCIE_RXN4 A1A:(10/20) Remove 0.1uF *2pcs PERn0 +3.3Vaux
21 GND PERST# 22 PLTRST# 15,16,18,21,25,26,28,30,33
28 uR_SOUT_CR 19 Reserved Reserved 20 RF_EN_RR R343 0_4
RF_EN 28
A1A: (10/13) change CONN (follow ZH2 Audio DB)
28 uR_SWD 17 Reserved GND 18
15 16 0_4 R337
GND Reserved LFRAME# 14,28,30
13 14 0_4 R345
+3VSUS 2 CLK_PCIE_MINI1 REFCLK+ Reserved LAD3 14,28,30
11 12 0_4 R344
2 CLK_PCIE_MINI1# REFCLK- Reserved LAD2 14,28,30
9 10 0_4 R338
GND Reserved LAD1 14,28,30
7 8 0_4 R339
CLKREQ# Reserved LAD0 14,28,30
5 Reserved +1.5V 6
3 Reserved GND 4 A1A:9/4 Reserved for debug only
Q25 1 2
WAKE# +3.3V
2
R357
*DTC144EU *4.7K_4 ACS_88911-5204
3 1 PCIE_WAKE#_MINI-Card B1D:(12/9) change from 9.0mm to 9.9mm (ME request)

16,18 PCIE_WAKE#
E3A:(3/16) Base on Acer demand, remove wake on lan for Mini PCIE function. +3V
no stuff Q25,R357
Q14
RHU002N06 R48
2
10K_4
D 3 1 MINI_DAT_SMB D
2,13,16,18,33 PDAT_SMB
+3V
Q15
RHU002N06 R58 PROJECT : ZU1
2
10K_4
2,13,16,18,33 PCLK_SMB 3 1 MINI_CLK_SMB Quanta Computer Inc.
Mini card/USB/Bluetooth 3B

1 2 3 4 5 6 7 8
5 4 3 2 1
+3VPCU
A1A: (9/25) change VBAT from +3VPCU to +A3VPCU
+A3VPCU +3V
1/13 Comfirm by vendor mail:
VDD must power up after VCC/AVCC SM BUS PU +3VPCU
MBCLK R98 4.7K_4

A1A:(9/16)Change from WPC8769 to WPC8763 L52 BLM18AG601SN1_6 +A3VPCU MBDATA
2ND_MBCLK
R99
R102
4.7K_4
4.7K_4
C474 C228 C236 1/13 Comfirm by vendor mail: 2ND_MBDATA R100 4.7K_4
C140 C476 VBAT for keep PLL power let power up can quick.
.1U_4 .1U_4 10U_8 +3V
.1U_4 10U_8 If no VBAT will switch to VCCpower.
If PLL no power will cause boot time delay. EC_GPIO42 R139 4.7K_4
CRT_SENSE# R398 4.7K_4
8769AGND 08/10 FAE:
115
102
I/O ADDRESS SETTING
C235 C139 C175 C486 C227 C141
19
46
76
88
80
0.1UF
4
10U_8 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 U14 MTEMP C149
D .1U_4 D
AVCC
VDD
VCC1
VCC2
VCC3
VCC4
VCC5
VBAT
ICMNT_L C654 I/O Address
A1A: (9/25) place the above capacitors as close to the pins as possible .1U_4
A1A: (9/26) Add it. Capacitors as close to EC as possible BADDR1-0 Index Data
LFRAME# 3 97
14,27,30 LFRAME# LFRAME AD0/GPI90 MTEMP 39
LAD0 126 98 T136 00 XOR TREE TEST MODE
14,27,30 LAD0 LAD0 AD1/GPI91
LAD1 127 99 T139
14,27,30 LAD1 LAD1 AD2/GPI92
LAD2 128 A/D 100 ICMNT_L R570 0_4 01 CORE DEFINED
14,27,30 LAD2 LAD2 AD3/GPI93 ICMNT 39
LAD3 1 108 T137
14,27,30 LAD3 LAD3 AD4/GPIO05
PCLK_591 2 96 T138 10 2Eh 2Fh
2 PCLK_591 LCLK AD5/GPIO04 E3A:(3/15) ICMNT connect to EC pin100(AD pin for power control) ,
PCLK_591 8 reserve R570 0ohm for debug use 11 164Eh 164Fh
16,30 CLKRUN# CLKRUN/GPIO11/HGPIO02
DA0/GPI94 101 CC-SET 39
14 GATEA20 121 GA20 DA1/GPI95 105 CPUFAN# 3 SHBM=0: Enable shared memory with host BIOS
D/A DA2/GPI96 106 T140
R142 122 107 T141
14 RCIN# KBRST DA3/GPI97 B1C:(10/20)SWAP GPIO1 & GPIO3 (follow EC team)
*22_4 BADDR0 CCD_POWERON# R408 10K_4
D14 BAS316 SCI#_uR 29 LPC A1A:(9/29)SWAP GPIO3 & GPIO6 (follow EC team)
16 SCI# ECSCI
64 BADDR1 SOUT_CR_DEBUG R407 *10K_4
GPIO01 ACIN 39
29 CAPSLED# 6 LDRQ/GPIO24/HGPIO01 GPIO03 95 NBSWON# 29,33
93 SHBM RF_EN R399 10K_4
A1A: (9/26) Remove LAN_WOL_EN GPIO06/HGPIO06 LID591# 16,20,29
C240 124 94
LPCPD/GPIO10/HGPIO00 GPIO07/HGPIP07 SUSB# 16
*10P_4 GPIO23 119 EC_FPBACK# 20
PLTRST# 7 109 1/13 Comfirm by vendor mail :
15,16,18,21,25,26,27,30,33 PLTRST# LREST GPIO30 SUSLED# 29
GPIO31 120 PWRLED# 29 Disabled ('1') if using FWH device on LPC.
29 NUMLED# 123 65 BATLED0# 29
PWUREQ GPIO32
66
Enabled ('0') if using SPI flash for both system BIOS and EC firmware
GPIO33 BATLED1# 29
SERIRQ 125 15
16,22,23,30 SERIRQ SERIRQ GPIO36 VRON 35
GPIO40 16 MAINON 36,37,38
08/10 FAE: SMI DOESN'T NEED DIODE 9 17 EC_GPIO42 A1A: (9/26) Remove RBAYINS#
16 KBSMI# SMI GPIO42/TCK
ACER ID
GPIO 20 A1A:(9/29) change from MBCLK/MNDATA to 2ND_MBCLK/2ND_MBDATA
GPIO43/TMS AMP_MUTE# 32
21 +3VPCU
C GPIO44/TDI PR_STS 33 U7 C
MX0 54 22
29 MX0 KBSIN0 GPIO45 SUSON 37,38
MX1 55 23 2ND_MBCLK 6 SCL
29 MX1
MX2 KBSIN1 GPIO46/TRST ENERGY_DET 18
2ND_MBDATA A0 1
29 MX2 56 KBSIN2 GPO47/JEN0 24 T130 5 SDA A1 2
MX3 57 25 D3A:(1/21) Add CableSence circuit
29 MX3
MX4 KBSIN3 GPIO50/TDO D/C# 39 A2 3
29 MX4 58 KBSIN4 GPIO51 26 S5_ON 34,38
MX5 59 27 D3A:(1/31)
29 MX5 KBSIN5 GPIO52/RDY A1A: (9/26) Remove BL/C# LOW_PWR 18 Anda inform: change LAN Low power pin from GPIO47 to GPIO527 WP VCC 8
MX6 60 28 HWPG 4
29 MX6 KBSIN6 GPIO53 GND
61 91 DNBSWON#_uR D12 BAS316
29 MX7 KBSIN7 GPIO81 DNBSWON# 16
110 24LC08 C69
GPO82/HGPIO00/TRIS BT_POWERON# 27
53 112 CCD_POWERON# .1U_4
29 MY0 KBSOUT0/JENK GPO84/HGPIO01/BADDR0 CCD_POWERON 20
29 MY1 52 KBSOUT1/TCK T16
51 CCD_POWERON ACITVE LO => HI
29 MY2 KBSOUT2/TMS 08/10 FAE: ADD TP FOR DEBUG
29 MY3 50 KBSOUT3/TDI TA1/GPIO56 31
29
29
MY4
MY5
49
48
KBSOUT4
KBSOUT5/TDO
KB TA2/GPIO20
TB1/GPIO14/HGPIO4
117
63
HIGH_LOAD 33
FANSIG 3
SPI FLASH
29 MY6 47 KBSOUT6/RDY
29 MY7 43 KBSOUT7 TIMER A_PWM0 32 CONTRAST 20 +3VPCU
29 MY8 42 KBSOUT8 A_PWM1/GPIO21 118 USBON# 27
41 62 +3VPCU
29 MY9 KBSOUT9 B_PWM0/GPIO13 SYS_CHARGE 33
40 U26
29 MY10 KBSOUT10
39 SPI_SDI_uR 2 8
29 MY11 KBSOUT11 SO VDD
38 84 CRT_SENSE# R45
29 MY12 KBSOUT12/GPIO64 SPI_DI/GPIO77 CRT_SENSE# 15,19,33
37 SPI 83 RF_EN SPI_SDO_uR_R 5 7
FOLLOW INTEL ME-EC INTERFACE SPECIFICATION,
29 MY13 KBSOUT13/GPIO63 SPI_DO/GPO76/SHBM RF_EN 27 SI HOLD
36 82 10K_4
2ND_SMB IS DEDICATED FOR ICH8 CONTROLLER LINK BUS. 29 MY14 KBSOUT14/GPIO62 SPI_SCK/GPIO75 CELL-SET 39
35 SPI_SCK_uR_R 6 3 C454
29 MY15 KBSOUT15/GPIO61/XOR_OUT SCK WP
MY16 34 .1U_4
29 MY16 KBSOUT16/GPIO60
+5V 33 75 RSMRST#_uR 0_6 R104 SPI_CS0#_uR 1 4
A1A: (9/26) Remove MY17 KBSOUT17/GPIO57/HGPIO03 IRRX1/GPIO72 RSMRST# 16 CE VSS
IRRX2_IRSL0/GPIO70 73 SUSC# 16
74 PWROK_EC_uR R103 0_4 W25X80VSSIG
IRTX/GPIO71 PWROK_EC 6,16
MBCLK 70 IR 113
39 MBCLK SCL1 SIN_CR/CIRRX/GPIO87
8
6
4
2
MBDATA 69 14 A1A: (9/26) Remove LAN_ON 1/13 Comfirm by vendor mail :

39 MBDATA SDA1 GPIO34/CIRRX2 A1A: (9/26) Remove EC_ME_ALERT
RP23 2ND_MBCLK 67 SMB 114 If the Southbridge enables 'Long Wait Abort' by default, the
B 3 2ND_MBCLK SCL2 CIRTX/GPIO16/HGPIO04 B
4.7KX4 2ND_MBDATA 68 111 SOUT_CR_DEBUG R406 0_4
3 2ND_MBDATA SDA2 SOUT_CR/GPO83/BADDR1 uR_SOUT_CR 27 flash device should be 50MHz (or faster)
7
5
3
1
BUTTON ON KEYBOARD MATRIX

72 86 SPI_SDI_uR
29 TBCLK PSCLK1 F_SDI
71 87 SPI_SDO_uR R596 22 SPI_SDO_uR_R
29 TBDATA PSDAT1 F_SDO
10 FIU 90 SPI_CS0#_uR
33 PR_KB_CLK PSCLK2/GPIO26 F_CS0
11 PS/2 92 SPI_SCK_uR R597 22 SPI_SCK_uR_R MX0
33 PR_KB_DATA PSDAT2/GPIO27 F_SCK MX0 29
12 MX1
33 PR_MS_CLK PSCLK3/GPIO25 MX1 29
13 81 SWD_DEBUG R400 0_4 MX2
33 PR_MS_DATA PSDAT3/GPIO12 SWD/GPIO66 uR_SWD 27 MX2 29
MX3
C2A:(12/12)FAE suggest add 22 Ohm dumping resistors MX3 29
8768_32KX1 77 30 uR_TP_CLKOUT T35 MX4
32KX1/32KCLKIN CLKOUT/GPIO55 on SPI flash interface F_SCK(pin92) and F_SDO(pin87) WIRELESS_SW# 29
MX5
to avoid potential EMI problem BLUETOOTH_SW# 29
85 VCC_POR# R97 4.7K_4 +3VPCU
VCC_POR MY16
VCORF
MY16 29
AGND
GND1
GND2
GND3
GND4
GND5
GND6
R101 20M_6 8768_32KX2 79 104 VREF_uR R403 0_4 +A3VPCU

32KX2 VREF
0~AVCC power for DA pin
R96 WPC8763LDG power reference
5
18
45
78
89
116
103
44
33K/F_6
1
2
VCORF_uR
08/10 FAE: 08/14 FAE:

A1A: (9/25)
FAE: PUT Y6 with EC in the same side ADD ONE GAD PAD UNDER X'TAL, Please connect VREF(uRider pin104) to
Y3
32.768KHZ AND KEEP CLEANCE. +A3VPCU instead of +3VPCU.
C130 C131
4
3
10P_4 10P_4 C181

A1A:(9/27)change C130,C131 from 6.8p to 5.6p
DEBUG PORTS
+3V L17 1U_6
1/13 Comfirm by vendor mail : HZ0603B601R-00_6
Connect to AGND
B1C:(11/28) change CN10/pin1 from +3V to +3VPCU
INTERNAL KEYBOARD STRIP SET
8769AGND R140
A C2A:(12/26) Base on vendor-FCE suggestion, +3VPCU A
change C130/C131 from CH-5606TB01 (5.6p) to CH01006JBD1 (10p)
10K_4 EC Debug Port LPC debug card
8769AGND +3VPCU MY0 R110 10K_4
A1A: (9/26) Add HWPG_CPUIO D18 BAS316 HWPG 1 A1A(10/5):Change LPC debug CONN to DFFC10FR103
38 HWPG_CPUIO 1
SOUT_CR_DEBUG 2
SWD_DEBUG 2 E3A:(3/22) confirm with BIOS-CM, no need LPC dedug CONN,
3
4
3
4
Remove CN6,R432 footprint to save space for layout. PROJECT : ZU1
D17 BAS316
36 HWPG_1.05V
CN10
37 HWPG_1.8V
D15 BAS316 *ACS_88231-04001 Quanta Computer Inc.
C2A:(12/25) Steven:D16 not necessary if 3V/5V fail, EC can't work. Size Document Number Rev
This monitor circuit is't necessary. EC (PC8763LDG)/ FLASH 3B
E3A:(3/16)PE request move D15~D18 location for FFC cable issue.Remove D16 footprint and net (HWPG_3/5VPCU) to save layout space.
5 4 3 2 1
5 4 3 2 1
INT K/B CN7 TOUCH PAD

MY15
28 MY15 1 +3VPCU
MY14 MY0
28 MY14
MY13 2 MY1 20 MIL
28 MY13 3 L23
MY12 MY2
28 MY12 4
MY11 MY3 +5V_TP C269 .1U-10V_4
28 MY11 5 +5V
MY10 MY4 RP14 uR REQUEST
28 MY10 6
MY9 MY5 10 1 MX4 BK2125HS330_8
28 MY9 7 MY DOES NOT NEED PU.
MY8 MY6 MX1 9 2 MX7
28 MY8 8
MY7 MY7 MX2 8 3 MX6 MY CAN NOT USE EMI BYPASS CAP, DUE TO FLASH.
28 MY7 9
MY6 MY8 MX3 7 4 MX5
28 MY6 10
MY5 MY9 MX0 6 5 R167 R162
28 MY5 11
MY4 MY10
D 28 MY4 12 D
MY3 MY11 10KX8 10K_4 10K_4
28 MY3 13
MX7 MY12 CONNECT TO TP/B
28 MX7 14
MX6 MY13
28 MX6 15
MY2 MY14 CN8
28 MY2 16
MX5 MY15
28 MX5 17 1
28 MX4
MX4
18
MX0
28 TBDATA
L22 LZA10-2ACB104MT_6 TP_DATA
2
BOT CONTACT
MX3 MX1 L20 TP_CLK
28 MX3 19 28 TBCLK 3 6
MX2 MX2 LZA10-2ACB104MT_6
28 MX2 20 4 5
MY1 MX3
28 MY1 21
MY0 MX4 C267 C261
28 MY0 22
28 MX1
MX1
23
MX5 A1A: (9/26) Refer to ZH3, change K/B matrix ACS_88502-0401
MX0 MX6 *.1U_4 *.1U_4
28 MX0 24 MX7
25
ACS_88502-250N
BOT CONTACT
Finger Printer
LED A1A:(9/27) Power need be confirm CN9
+3V +3V +3V +3V
+3VSUS 4
+3VPCU
R170 0_6 BUSBP1- 3 6
15 USBP6- 2
15 USBP6+ R171 0_6 BUSBP1+
1 5
R367 330_4 LED4 2 1 ACS_88266-04001-06
SUSLED# 28
LED_Y_LTST-C190KFKT R36 R37 R43 R46
R800 330_4 2 1 10K_4
PWRLED# 28
LED5 LED_G_LTST-C190KGKT 10K_4 10K_4 330_4
IDE_LED
A1A:(10/30) remove22pF*2
3
C C
D6 BAS316
R366 330_4 LED6 2 26 IDELED#
1 BATLED1# 28
LED_Y_LTST-C190KFKT D5 BAS316
2
R801 330_4 14 SATA_LED# Q11
2 1 BATLED0# 28
LED7 LED_G_LTST-C190KGKT
2N7002E
1
B1C:(11/27)Base on ME request, refer to ZH3, change LED type
B1C:(11/28)Base on ME request, change LED type
LED Board
D3A:(1/24) Base on SMT-ME request, change LED type to 2 in 1 +3VPCU
DEL LED4,LED5,LED6,LED7,R570,R571,Add LED2,LED3 +3VPCU
E3A:(3/16)Change LED2, LED3 type base on ME request, Add R800,R801 CN1
E3A:(3/30) ESD issue, change LED type (follow B stage)
MX3 1 A1A(10/5):Change Pin define (Base on Acer ID)
28 MX3 2
MY16
NBSWON# 3
PWRLED# 4 NBSWON#
NUMLED 5
CAPSLED 6 D3
IDE_LED 7
3
SUSLED# 8 DA204U
9
10
11
12
2
+3V
+3V BOT CONTACT
+3VPCU
ACS_88502-1001
R41
R40
B 330_4 B
NUMLED 330_4 A1A:(9/27) Add LED Board CONN (10pin) E3A:(3/30) change ESD protect Diode location from LED/B to MB
3
CAPSLED (Add D3)

3
A1A:(10/26) Add SUSLED#

A1A:(10/30) no stuff (ZU1 no support EMAIL LED)
2 Q8
28 NUMLED# Q7 E3A:(3/30)Remove Q27,R1 footprint to save space for layout
28 CAPSLED# 2
2N7002E ZU1 no support E-Mail LED
G2
2N7002E
28,33 NBSWON# NBSWON# 1 2
1
*SHORT_PAD
Function Board A1A: (9/24) change SW CONN (follow ZC3)

+3VPCU
CN4
D3A: (1/29) remove SW1, add G2 footprint
MX0 1
28 MX0 2
MX1 +3VPCU
28 MX1 3
MX2
28 MX2 4
MY16
28 MY16 5
MR# LED1
16,20,28 MR# 6
WIRELESS_SW# R141 330_4 ECPWRLED 2 1 PWRLED#
28 WIRELESS_SW# 7
BLUETOOTH_SW#
28 BLUETOOTH_SW# 8 A1A(10/5):Change Pin define (Base on Acer ID)
WIRELESS_LED# LED_G_LTST-C190KGKT
27 WIRELESS_LED# 9
BT_LED
27 BT_LED 10
+3V 11
BOT CONTACT
12 A1A: (10/30) Reserved LED for debug use
13
A 14 A
Keyboard Matrix Button
ACS_88502-1401
MX0/MY16 acer EAP Buttton
A1A:(9/27) Add Function Board CONN (14pin) MX1/MY16 acer EMAIL Buttton
A1A:(10/30) add +3V for Daughter Board use MX2/MY16 acer WWW Buttton PROJECT : ZU1
MX3/MY16 acer EPM Buttton
MX4/MY16 WIRELESS Button
MX5/MY16 BLUETOOTH Button SWITCH,LED,KB,Finger,TP 3B
5 4 3 2 1
5 4 3 2 1
NS SIO PC87383
U9
PCI_CLK_SIO 42 52 PD0
14,27,28 LAD0 LAD0 PD0 PPT_PD0 33
46 50 PD1
SIO_14M
14,27,28
14,27,28
LAD1
LAD2 51
LAD1
LAD2
NS PC87383 PD1
PD2 43 PD2
PPT_PD1
PPT_PD2
33
33
53 6 PD3
14,27,28 LAD3 LAD3 PD3 PPT_PD3 33
39 PD4
PD4 PPT_PD4 33
33 37 PD5
2,27 PCI_CLK_SIO LCLK PD5 PPT_PD5 33
R39 R49 34 PD6
PD6 PPT_PD6 33
*22_4 *22_4 22 30 PD7
14 LDRQ#0 LDRQ/XOR_OUT PD7/GPIO23 PPT_PD7 33
38 28 ACK#
14,27,28 LFRAME# LFRAME ACK/GPIO24 PPT_ACK# 33
D AFD# D
15,16,18,21,25,26,27,28,33 PLTRST# 35 LRESET AFD_DSTRB 57 PPT_AFD# 33
C55 C84 A1A:(9/20) PPT PU 4.7k circuit exist in Docking.
*10P_4 *10P_4 16,22,23,28 SERIRQ 36 SERIRQ BUSY_WAIT 26 BUSY
PPT_BUSY 33 remove it.
SIO_PD# 29 54 ERROR#
LPCPD/GPIO21 ERR PPT_ERR# 33
27 56 INIT#
16,28 CLKRUN# CLKRUN/GPIO22 INIT PPT_INIT# 33
58 25 PE
2 SIO_14M CLKIN PE PPT_PE 33
HOLE17 15 24 SLCT
GPIO00 SLCT PPT_SLCT 33
1 16 GPIO01
2 19 55 SLIN#
GPIO02 SLIN_ASTRB PPT_SLIN# 33
3 20 GPIO03
4 +3V 21 14 STRB#
GPIO04 STB_WRITE PPT_STB# 33
*h-c276d94p2 40
5
GPIO05
7 GPIO06
R44 41 8 IRRX R77 10K_4 +3V
C2A:(12/28) change Hole17 type to improve thermal issue, 10K_4 GPIO07 IRRX1
23 GPIO20
(change footprint to H-C276D94N-4) 10 IRMODE
IRRX2_IRSL0/GPIO17 MCTS1#
1 NC PR_CTS 33
BAS316 D7 SIO_PD# 2 9 IRTXOUT MDCD1#
16 LPC_PD# NC IRTX PR_DCD# 33
17 MDSR1#
HOLE 18
NC
NC
MDTR1#
PR_DSR#
PR_DTR#
33
33
47 3 MCTS1# MRI1 PR_RI 33
C2A:(12/12)Intel suggest:All LPC devices support LPCPD# protocol,stuff D7. NC CTS1/GPIO11 MRTS1#
48 NC PR_RTS# 33
49 59 MDCD1# MRXD1
NC DCD1/GPIO16 PR_SIN 33
HOLE28 HOLE26 HOLE29 HOLE27 +3V 64 MTXD1
NC PR_SOUT 33
*h-c236d236 *h-c236d236 *h-c236d236 *h-c236d236 60 MDSR1#
DSR1/GPIO15
45 VDD OPEN : 164Eh~164Fh
+ C64 C119 C56 C76
32 VDD DTR1_BOUT1/BADDR 4 MDTR1# R76 *10K_4
LOW : 2Eh~2Fh
11 VDD
C 10U_8 MRI1 C
RI1/GPIO10 5
.1U_4 .1U_4 .1U_4
OPEN : normal pin operation
1
44 VSS RTS1/GPIO13/TRIS 62 MRTS1# R55 *10K_4

LOW : float device pin
31 VSS
12 61 MRXD1
VSS SIN1/GPIO14
HOLE35 HOLE32 HOLE33 HOLE31
OPEN : normal Device operation
*h-c236d236 *h-c236d236 *h-c236d236 *h-c236d236 C120 .1U_4 13
VCORF SOUT1/GPIO12/TEST 63 MTXD1 R59 *10K_4
LOW : XOR pin tree
PC87383
AJ873830H22 +3V
<Description> FIR U40
6
T = 20mil
1
IRTXOUT VCC
3 TXD MODE 7
IRRX 4 C638 C640 C639
A1A:(10/19) EMI suggest :Add the VIN power shape IRMODE RXD 10U-10V_8
5 SD LED_C 2
bypass cap 0.1uF x 10pcs 8 1 .1U-10V_4 10U-10V_8
HOLE37
*h-c236d236
HOLE38
*h-c236d236
HOLE34 HOLE36
*h-c236d236 *h-c236d236
EMI Cap Add the +3VPCU power traces bypass cap 0.1uF x 3pcs
GND
VISHAY_TFDU6102_8P
LED_A
VIN VIN VIN VIN VIN
+5V_FIR
+3V +3V +3V
T = 20mil
1
R557 5.6_1206
C333 C33 C35 C116 C83 C648 C649
R551 5.6_1206
.1U-10V_4 .1U-10V_4 C641
HOLE22 HOLE14
h-c236d138p2 h-c236d138p2 10U-10V_8
E3A:(3/14)Remove PAD18 (SMT C-test open issue)
E3A:(3/14)ME request, change EMI Spring from FDTA1003014 to FDZU1002010
0.1U/X7R-50V_6 0.1U/X7R-50V_6 0.1U/X7R-50V_6 0.1U/X7R-50V_6 0.1U/X7R-50V_6 C2A:(12/22) EMI suggest to add .1u *2 to prevent noise (+3V)
B D3A:(2/14)EMI request add two of clip(FDTA1003014) in PAD17 and PAD19 for EMI issue B
VIN VIN VIN VIN VIN +3VPCU +3VPCU +3VPCU
1
PAD19 PAD17 PAD25 PAD24 PAD23
C443 C103 C32 EMIPAD EMIPAD *EMIPAD *EMIPAD *EMIPAD

HOLE25 HOLE24 C347 C349 C40 C39 C447
h-c217d59p2 h-c217d59p2 .1U-10V_4 .1U-10V_4 .1U-10V_4
1
1
0.1U/X7R-50V_6 0.1U/X7R-50V_6 0.1U/X7R-50V_6 0.1U/X7R-50V_6 0.1U/X7R-50V_6 EMIPAD157X79 EMIPAD157X79
HOLE42 C2A:(12/22) EMI suggest add three clip to contact with CPU cooler's fins
*h-o110x94d110x94n B1C:(11/27)change Hole42 footprint
B1C:(11/23)remove Hole7
ESDPad (PAD23,24,25)
Non - PTH Hole D3A:(2/8)Remove hole13

PAD15 PAD5 PAD14 PAD11 PAD13 PAD3 PAD16 PAD10 PAD2 PAD7 PAD1 PAD4 PAD8 PAD12 PAD6 PAD9 PAD20 PAD21 PAD22
*EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD *EMIPAD MEPAD MEPAD MEPAD
1
HOLE16 HOLE19 HOLE30 HOLE18 HOLE15 HOLE21 HOLE11

1
1
h-c217d122p2 h-c217d122p2 h-c217d122p2 h-c217d122p2 h-c217d122p2 h-c217d122p2 h-c217d122p2
ADOGND EMIPAD142X91
1
A A
C2A:(12/22) Add theree PAD per ME request (fix wire)
C2A:(12/1) change Hole21 from MBZU1001010 to MBZU1004010 D3A:(2/2) change PAD20.PAD21.PAD22 footprint
HOLE3 HOLE9 HOLE23 HOLE2 HOLE4 HOLE10 HOLE1 HOLE5 HOLE12 HOLE39 HOLE43 HOLE40 HOLE41 HOLE20 HOLE6 HOLE8 D3A:(2/12) Add PAD20.PAD21.PAD22 P/N (FDZU1001010)
*H-C315D177P2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276i134d94p2 *h-c276d94p2 *H-C276D122P2
PROJECT : ZU1
1

D3A:(2/2) change Hole9 footprint SUPER-IO/FIR/HOLE 3B
C2A:(12/22) change Hole20 footprint to h-c276i134d94p2
5 4 3 2 1
5 4 3 2 1
CODEC(ALC268) LINE OUT Amplifier FRONT-L_2 R352 10K_6
A1A:(9/20) Refer to ZD1, C425 47P_4

change R352,R532,R543,R358 to 10k
+5V +5V_ADO U37
L61 TI321611U480_1206 R532

FRONT-L C614 FRONT-L_1 10K_6 4 - 5 HPL
INL OUTL HPL 32
C567 C563 C620 C604 C608 C622 4.7U-6.3V_8 + 9
D
.1U-10V_4 10U-10V_8 .1U-10V_4 .1U-10V_4 .1U-10V_4 10U-10V_8 NC1 D
+3V_AVDD 3 SVDD NC2 11
MIC1-VREFO-R 15 12
MIC1-VREFO-R 32 PVDD NC3
NC4 14
D3A:(1/31) SMT B open issue: 6 2
ADOGND (1)Remove footprint for D41,D42,R525. DEL R577 (0 ohm) SVSS SGND
MIC2-VREFO 32 +NVDD 10 NVDD PGND 13
MIC2-VREFO (2) Remove net SECNTL 17
TPAD
+3V R482 0_6 MIC1-VREFO-L MUTE# 1
MIC1-VREFO-L 32 32 MUTE# SHDNR#
16 ADOGND
C2A:(12/25) solve S3 resume POP sound issue SHDNL#
R543 + 7
R483 *0_6 +AZA_VDD change C619 from CH61004M2E8 to CH5222K9A09 FRONT-R C621 FRONT-R_1 10K_6 OUTR
+1.5V 8 INR -
FRONT-L +5V_ADO
C619 2.2U/X5R-10V_8 4.7U-6.3V_8
FRONT-R
SENSEB
1 2 G1412
C2A:(12/25) no stuff R525,D41, add bypass R577 to solve pop sound issue
C560 C570
10U-10V_8 .1U-10V_4 ADOGND L62 C426 47P_4
36
35
34
33
32
31
30
29
28
27
26
25
+3V 1 2 +3V_AVDD
U34 BLM11A601S_6 FRONT-R_2 R358 10K_6 HPR
HPR 32
VREF
FRONT-R
FRONT-L
NC
GPIO1
AVSS1
AVDD1
Sense B
MIC1-VREFO-R
LINE1-VREFO
MIC1-VREFO-L
MIC2-VREFO
C575 C601 C616
*10U-10V_8 10U-10V_8 .1U-10V_4
37 24 LINE1-R
MONO-OUT LINE1-R LINE1-R 32
ADOGND ADOGND
+5V_ADO 38 23 LINE1-L C421 4.7U/6.3V_6
AVDD2 LINE1-L LINE1-L 32 A1A:(9/28) EMI suggest to change from AGND to GND
SURR-L 39 22 MIC1-R +NVDD
32 SURR-L HP-OUT-L MIC1-R MIC1-R 32
C +3V +NVDD U35 C
ADOGND R521 20K_6 40 21 MIC1-L
JDREF MIC1-L MIC1-L 32
1 VOUT C+ 6
32 SURR-R SURR-R 41 20 C602 .1U-10V_4 C606
HP-OUT-R CD-R MUTE#
4.7U/6.3V_6 2 VIN /SHDN 5
ADOGND 42 19 C594 .1U-10V_4
AVSS2 CD-GND ADOGND 3 4 A1A:(9/21)
43 NC
Acer ALC268 CD-L 18 C590 .1U-10V_4
ADOGND
C- GND
refer to ZD1,
A1A:(10/18) reserve R513 to reduce ringing
add it.
44 17 MIC2_INT_R G5930
NC MIC2-R MIC2_INT_R 32
Change C19 to 4.7u ADOGND
45 16 MIC2_INT_L
NC MIC2-L MIC2_INT_L 32
DMIC-CLK R513 100_4DMIC-CLK_R 46 15 A1A:(11/1)FAE: Docking MIC share from System MIC
DMIC-CLK NC
32 EAPD EAPD 47 14 R347 0_4 AU_JD_MIC
DMIC-1/2/GPIO0
DMIC-3/4/GPIO3
EAPD NC
33 AU_SPDIF SPDIF_OUT SPDIF_OUT_268 48
SDATA-OUT
13 SENSEA R507 20K_6 SYS / EZ MIC
SPDIFO Sense A MIC1_JD 32
R504 0_4
SDATA-IN
PCBEEP
RESET#
BIT-CLK R501 10K_6 SYS Line-in
DVDD1
DVDD2
DVSS1
DVSS2
LINEIN_JD 32,33
SYNC
AU_JD_LINEIN 32,33 EZ Line-in
1
10
11
12
R492 5.1K_6 SYS/EZ Line-out
LINEOUT_JD#_OD 32,33
SENSEB R346 *20K_6 +3V R318 10K_4
B1C: (11/24) stuff R330 for Int-SPK issue +3V AU_JD_MIC 33 EZ MIC (reserve)
+AZA_VDD
U22
5
A1A:(9/28) EMI suggest: PCMSPK_DELAY
DMIC-12
B
1 PCMSPK_DELAY 22 B
Add Additional two more bridge resistor PCBEEP C399 1U-16V_6 BEEP_1 R317 10K_4 BEEP 4
between ADDGND and GND 2 PCSPK
ACZ_SPKR 16
3
SN74LVC1G86DCKR D3A:(1/21) Change CN14/pin 2 from +3v to +3v_s5.
R330 0_6 C411 R334 Fix Modem wake from S3 fail issue.
R558 *0_6 100P-50V_6 1K_4
R530 *0_6
C564 C568 A1A:(10/30) change from +3V_S5 to +3V
10U-10V_8 .1U-10V_4 A1A: (9/20) Change DGND to AGND
ADOGND +1.5V +3V_S5
ADOGND A1A:(9/20) Refer to ZD1, +3V_S5
Tied at one point only A1A: (9/26) Remove DMIC-34 Add 0 ohm(Default:no stuff)
MDC
BIT_CLK268
ACZ_SDIN268
R491 R486
under the codec or CN14 *0_6 0_6
ACZ_RST#_AUDIO 14,32
near the codec 1 GND RSV 2+1.5V_MDC
ACZ_SDOUT_MDC 3 4 C573
14 ACZ_SDOUT_MDC AC_SDO RSV
5 6 .1U-10V_4
ACZ_SYNC_AUDIO 14 GND 3.3V
ACZ_SYNC_MDC 7 8
A1A: (9/20) Change serial R value from 22ohm to 33ohm 14 ACZ_SYNC_MDC AC_SYNC GND
R509 33_4 MDC_SDIN1 9 10
14 ACZ_SDIN1 AC_SDI GND
R485 33_4 11 12
ACZ_SDIN0 14 14 ACZ_RST#_MDC AC_RST# AC_BCLK BIT_CLK_MDC 14
R484 33_4 ACS_88018-124L
BIT_CLK_AUDIO 14 A1A:(10/13) change R598 from 22ohm to 33 ohm A1A:(9/27)change P/N (follow ZC3)
+5V +5V_ADO
C569 22P-50V_4
U24 C583 R508
R325 *0_6 4 3 *10P-50V_4 *22_4
VEN VOUT ACZ_SDOUT_AUDIO 14
5 C418
GND
VIN
ADJ
C585
A R333 *10U-25V_1206 *10P-50V_4 A
*36K_4
2
*G961-18ADJTEU(SOT89-5)
DMIC-CLK
DMIC-CLK 20
ADOGND DMIC-12
DMIC-12 20
R332 PROJECT : ZU1
Vo=1.2*(R371+R372)/R371= 4.8V *12K_4
+1.5V
A1A:(10/2) change from GND to ADOGND +1.5V 4,9,17,27,38 Quanta Computer Inc.
ADOGND AUDIO(ALC268)/AMP/MDC 3B

5 4 3 2 1
5 4 3 2 1
SYSTEM LINE OUT

Speaker Amplifier +5V_ADO
+3V_AVDD
C634 1U-16V_6
C591 C631 ADOGND

A1A(10/5):Refer to ZD1, change R604~R607 to 10K 10U-10V_8 .1U-10V_4 T129
C2A:(12/25) change R546/R520 from 10k to 9.1k

A1A:(9/29)Add net name
ADOGND
15
14
23
U36
6
8
C633 2.2U/10V_8 SURR-L-1 R546 9.1K_6 SURR-L-2 1 20 CN29
CT
VDD3
SECNTL
LVDD
RVDD
NC
D 31 SURR-L LIN1 VOL D
1 7
C596 2.2U/10V_8 SURR-R-1 R520 9.1K_6 18 HPL R363 75_4 HPL_1 L40 BK1608LL121_6 HPL_SYS 2
31 SURR-R RIN1 31 HPL
SURR-R-2 6
+5V_ADO INSPKL+ R545 10K_6 2 13 ADOGND HPR R362 75_4 HPR_1 L39 BK1608LL121_6 HPR_SYS 3
LIN2 IN1/IN2 31 HPR
C632 330P_4 17 4
RIN2 31,33 LINEOUT_JD#_OD
INSPKR+ R519 10K_6 19 INSPKR+ 8
C592 330P_4 ROUT+ INSPKR- R364 R365 C434 C433
ROUT- 12 5
24 INSPKL+ *1K_4 *1K_4 470P-50V_4 470P-50V_4 FOX_JA6033L-L3T4-7F
R359 4.7U/6.3V_6 C589 LOUT+ INSPKL-
ADOGND 16 RBYPASS LOUT- 7
100K_4 3
4.7U/6.3V_6 C635 LBYPASS
THRMPAD
1441 MUTE ADOGND
GND/HS
GND/HS
GND/HS
GND/HS
1441 MUTE R544 0_4 5 SHDN
3
Q26 R526 0_4 11 A1A(10/9):Change (D44/Pin1) from +5V to +5V_ADO

SE/BTL ADOGND
MUTE# 2 G1441
25
22
21
10
9
ADOGND +5V_ADO
2N7002 D3A:(2/5) change CN30,CN31,CN32 footprint
D31 from AUDIO-010164FR006GX53XL-C-8P to AUDIO-JA60331-X39T4-7F-8P
1
1
LINEOUT_JD#_OD D3A:(2/9) Change CN29 P/N from DFTJ06FR019 to DFTJ06FR061
ADOGND 3
ADOGND
+3V_AVDD 2
*DA204U ADOGND
1 2 R341
28 AMP_MUTE#
D26 MTW355 10K_4
1 2 MUTE#
31 EAPD MUTE# 31
D28 MTW355
14,31 ACZ_RST#_AUDIO 1 2 Docking LINE OUT/SPDIF

D27 *MTW355
C C
C2A:(12/25) STEVEN: no stuff d27

SPEAKER
HPL_SYS R360 0_4 AU_LINEOUT_L
AU_LINEOUT_L 33
HPR_SYS R361 0_4 AU_LINEOUT_R
CN16 ACS_85204-0400L AU_LINEOUT_R 33
INSPKL- L29 BK1608LL121_6 INSPKL-N
INSPKL+ L30 BK1608LL121_6 INSPKL+N 1 R549 *0_6
INSPKR- L31 BK1608LL121_6 INSPKR-N 25 R511 *0_6
INSPKR+ L32 BK1608LL121_6 INSPKR+N 36 C416 .1U-10V_4
4 C409 1000P-50V_4
C613 C612 C611 C610 C437 .1U-10V_4
A1A:(10/27) SWAP R&L channel for ME request C432 .1U-10V_4
47P-50V_4 47P-50V_4 47P-50V_4 47P-50V_4 C427 .1U-10V_4 A1A:(10/30) Add 0.1uF *4
C410 .1U-10V_4
ADOGND
ADOGND
SYSTEM LINE IN SYSTEM MIC

D3A:(2/5) change CN30,CN31,CN32 footprint
from AUDIO-010164FR006GX53XL-C-8P to AUDIO-JA60331-X39T4-7F-8P R541 2.2K_4 CN31
31 MIC1-VREFO-L
1 7
D3A:(2/9) Change CN30 P/N from DFTJ06FR017 to DFTJ06FR059 C629 2.2U_6 MIC1_L1 L38 BK1608LL121_6 MIC1_L 2
31 MIC1-L
6
R542 2.2K_4 MIC1_R1 L35 BK1608LL121_6 MIC1_R 3
31 MIC1-VREFO-R
CN30 31 MIC1_JD 4
1 7 C630 2.2U_6 8
31 MIC1-R
C417 4.7U-6.3V_8 LINE1-L_1 L33 BK1608LL121_6 LINEINL_SYS 2 5
31 LINE1-L
6 FOX_JA6033L-P3T4-7F
C423 4.7U-6.3V_8 LINE1-R_1 L34 BK1608LL121_6 LINEINR_SYS 3
B 31 LINE1-R B
4 C428 C431
31,33 LINEIN_JD
8 470P-50V_4 470P-50V_4
C436 C435 5
MIC1_L L41 BK1608LL121_6 AU_MIC_IN_L
AU_MIC_IN_L 33
470P-50V_4 470P-50V_4
FOX_JA6033L-U3T4-7F MIC1_R L42 BK1608LL121_6 AU_MIC_IN_R ADOGND
AU_MIC_IN_R 33
A1A(10/9):Change (D50/Pin1) from +5V to +5V_ADO
A1A(10/9):Change (D48/Pin1) from +5V to +5V_ADO
ADOGND A1A:(11/1)FAE: Docking MIC share from System MIC D3A:(2/5) change CN30,CN31,CN32 footprint
from AUDIO-010164FR006GX53XL-C-8P to AUDIO-JA60331-X39T4-7F-8P
+5V_ADO
D32 D3A:(2/9) Change CN31 P/N from DFTJ06FR018 to DFTJ06FR060
LINEIN_JD
1
Analog MIC
3
D29
2
31 MIC2-VREFO 2 1 MIC2-VR-R R342 *2.2K_4
*DA204U *MTW355
ADOGND C400 *2.2U_6 MIC2_INTR1
31 MIC2_INT_R
A1A(10/9):Change (D48/Pin2) from GND to ADOGND C586 *2.2U_6 MIC2_INTL1
31 MIC2_INT_L
D30
31 MIC2-VREFO 2 1 MIC2-VR-L R506 *2.2K_4
*MTW355 C584 C420
*.1U-10V_4 *.1U-10V_4
Docking LINE IN no stuff (reserve)
+5V_ADO
B1C:(11/24) Reserve circuit for Analog Mic ADOGND ADOGND
D33
C2A:(12/12)Acer change internal Mic solution to Fortemedia,
Remove CN33,D29,D30,R342,R506,C400,C586 1
MIC1_JD
LINEINL_SYS L36 BK1608LL121_6 AU_LINEIN_L 3
AU_LINEIN_L 33
LINEINR_SYS L37 BK1608LL121_6 AU_LINEIN_R 2
A A
AU_LINEIN_R 33
CN33 *DA204U
MIC2_INTR1 ADOGND
1
C429 C430 2 MIC2_INTL1
3 A1A(10/9):Change (D50/Pin2) from GND to ADOGND
*.1U-10V_4 *.1U-10V_4 4
*85204-0200L_INT_MIC
ADOGND ADOGND PROJECT : ZU1
Size
Document Number Rev
Speaker AMP / Audio JACK 3B
5 4 3 2 1
A B C D E
D46 VA1 D3A:(2/12) Base on DSC command, change CN22 P/N from DFHDF8MS000 to DFHDF4MS000
D45
DCIN VA2 2 VA1
1 2 VA1 3 VA1 VA1 VA1 VA2 VA1 VA1 VA1
1
1 C453
+3VSUS C438 C43 C34 C60 C442
SW1010C PDS1040S C21 C70
2
D3A:(2/8)The system side should have a diode (D45,D46) to block the AC adaptor power and ezDock. 10U/X6S-25V_1206
Q4 .1U-50V_6 .1U-50V_6
RHU002N06 D3A:(1/30)Acer DVR1012_Design Requirement Checklist: .1U-50V_6 .1U-50V_6 .1U-50V_6 .1U-50V_6 .1U-50V_6
2
The system side should have a diode
to block the AC adaptor power coming from ezDock. CN22 A1A:(10/27) EMI suggest add 10u*1pc, 0.1u*5pcs
3 1 EZ_DAT_SMB A1A: (9/20) Add .1uF *2 for VA 155 157
2,13,16,18,27 PDAT_SMB P1 G1 D3A:(2/2) change net name from VA to VA1
POWER DECOUPLING 156 P2 G2 158
4 E3A:(3/14)Change D46 footprint from SBM1040-3P 4
to SBM1040-3P-ZU1 for SMT C-test open issue 1 78 DET_GND# E3A:(3/21) Change C453 from CC1210 (CH61004M3E5) to CC1206 (CH61004M2E8)
+3VSUS A1 B1 Andy inform CH61004M3E5 will EOL
25 1394TPAP0 2 A2 B2 79
25 1394TPAN0 3 A3 B3 80 1394TPAP1 25
Q5 4 81
A4 B4 1394TPAN1 25
RHU002N06 5 82
25 1394TPBP0 A5 B5
2
25 1394TPBN0 6 A6 B6 83 1394TPBP1 25
7 A7 B7 84 1394TPBN1 25
3 1 EZ_CLK_SMB 8 85
2,13,16,18,27 PCLK_SMB 15 PCIE_TXP1 A8 B8
9 86 EZ_DAT_SMB
15 PCIE_TXN1 A9 B9 A1A:(9/26)Add PLTRST# for (CN22/Pin88)
10 87 EZ_CLK_SMB
R803 0_4 PCIE_RXP1_R 11 A10 B10 PCIE_RST# R208 0_6
15 PCIE_RXP1 A11 B11 88 PLTRST# 15,16,18,21,25,26,27,28,30
+2.5V E3A:(3/16)Change Q4,Q5 Pin2 from +3V to +3VSUS . R802 0_4 PCIE_RXN1_R12 89
(Docking side pull up to +3VSUS plane) 15 PCIE_RXN1 A12 B12 PCIE_CLKREQ# 2 A1A: (9/20) COPP#: reserve for ATI chipdst
13 A13 B13 90
E3A:(3/21) change C451,C452 from 0.1uF 14 91
(CH41002KB93) to 0 ohm (CS00002JB38)(R802,R803) 2 PCIE_CLK1+
15
A14 B14
92
SYS_CHARGE 28
2 PCIE_CLK1- A15 B15 HIGH_LOAD 28
R375 16 93
2.2K_4 A16 B16
17 A17 B17 94 DVI_D2+ 21
DVI_DDC_DT 18 95
A18 B18 DVI_D2- 21
DVI_DDC_CK 19 96
A19 B19
21 DVI_DET 20 A20 B20 97 DVI_CLK+ 21
DVI_DDC_DT 21 98
21 DOCK_DDC_DT A21 B21 DVI_CLK- 21
21 DVI_D0+ 22 A22 B22 99
R373 23 100
+2.5V 21 DVI_D0- A23 B23 LAN_ACTLED# 18
100K_4 24 101
A24 B24 LAN_LILED# 18
21 DVI_D1+ 25 A25 B25 102
21 DVI_D1- 26 A26 B26 103 TX2P_PR 18
A1A: (9/20) Add PL 100K for DVI_DET 27 104
A27 B27 TX2N_PR 18
R374 28 105
18 TX0P_PR A28 B28
3 2.2K_4 29 106 3
18 TX0N_PR A29 B29 TX3P_PR 18 VAUX_25 A1A: (9/20) change +VCC_LAN to VAUX_25
30 A30 B30 107 TX3N_PR 18
18 TX1P_PR 31 A31 B31 108
DVI_DDC_CK 32 109
21 DOCK_DDC_CK 18 TX1N_PR A32 B32
33 A33 B33 110
A1A:(11/1) Change LAN pin define 34 111
A34 B34 PR_MS_DATA 28
A1A: (9/20) 35 A35 B35 112 PR_MS_CLK 28
(1)Remove Level-shift circuit (already in docking side) 28 PR_KB_DATA 36 A36 B36 113
(2)change Power from +3V to +2.5V 28 PR_KB_CLK 37 A37 B37 114 PR_RTS# 30
(3)stuff 2.2k (R374,R375) 30 PR_SIN 38 A38 B38 115 PR_CTS 30
30 PR_SOUT 39 A39 B39 116 PR_DTR# 30
30 PR_DSR# 40 A40 B40 117 PR_RI 30
30 PPT_PE 41 A41 B41 118 PR_DCD# 30
30 PPT_BUSY 42 A42 B42 119 PPT_INIT# 30
+3V_S5 43 120 D3A:(1/30) Base on Safety team request
30 PPT_ACK# A43 B43 PPT_SLIN# 30 change Modem capacitor(470p-3KV_1808) to meet standard
30 PPT_ERR# 44 A44 B44 121 PPT_PD0 30
45 122 (add mark onto the capacitor surface)
30 PPT_AFD# A45 B45 PPT_PD1 30 change C37,C48 from CH147GK0I09 to CH147GK0I00
30 PPT_STB# 46 A46 B46 123 PPT_PD2 30
Q6 47 124
A47 B47 PPT_PD3 30
RHU002N06 19 DOCK_R 48 125
A48 B48 PPT_PD4 30
2
49 A49 B49 126 PPT_PD5 30

19 DOCK_G 50 A50 B50 127 PPT_PD6 30
16,18 DOCKIN# 1 3 DOCKIN#_1 R566 0_4 DOCKIN#_R 51 128 A1A:(9/28)change CONN from 2 pin to 4 pin
A51 B51 PPT_PD7 30
19 DOCK_B 52 A52 B52 129 PPT_SLCT 30
53 130 CN3
DET_GND# A53 B53 RINGL
19 DOCK_HSYNC 54 A54 B54 131 DOCK_TV_COMP 20 4
A1A:(11/1) add level shift circuit, already PU 5VA_PR in docking side. 55 132 TIPL
19 DOCK_VSYNC A55 B55 3 6
B1C:(11/20) add R566 0ohm for debug use 56 133 C37 470p-3KV_1808 RINGL
19 DOCK_DDDA A56 B56 DOCK_TV_C/R 20 2
57 134 C48 470p-3KV_1808 TIPL
2 19 DOCK_DDCK A57 B57 1 5 2
+5V 15,19,28 CRT_SENSE# 58 135
A58 B58 DOCK_TV_Y/G 20
59 A59 B59 136
32 AU_LINEIN_L 60 A60 B60 137 AU_SPDIF 31
32 AU_LINEIN_R 61 A61 B61 138 LINEOUT_JD#_OD 31,32
+3V_S5 R31 62 139
A62 B62 AU_JD_LINEIN 31,32
32 AU_LINEOUT_L 63 A63 B63 140
32 AU_LINEOUT_R 64 A64 B64 141 USBP3+ 15
10K_4 65 142 A1A:(10/2) change from USB5 to USB3
AUDIO_AGND A65 B65 USBP3- 15
R33 32 AU_MIC_IN_L 66 143
PR_INSERT_5V 19,20 A66 B66
32 AU_MIC_IN_R 67 144 PWRBTN#
A67 B67
3
31 AU_JD_MIC 68 A68 B68 145

100K_4 69 146 +5V A1A: (9/20) change 5VS to +5V
DOCKIN#_R A69 B69
70 A70 B70 147
DOCKIN# 2
+3VPCU
C47 Q28
2N7002 76 153
.1U-10V_4 TIPL A76 B76 RINGL
77 154
1
A77 B77
5
1
159 G3 G7 163 4 NBSWON# 28,29
A1A:(9/18) Refer to Acer DVR1019 160 164 PWRBTN# 2 C446
+3V_S5 G4 G8 U25
161 165
3
G5 G9 *TC7SH08FU .1U-10V_4
162 G6 G10 166
R32 R34 0_6
R35 0_6
C49 *.1U-10V_4 FOX_QL0177L-D26C02-8F
10K_4 C50 *1000P-50V_4 A1A: (9/20) refer to Acer Design Guide: R372 0_4
PR_STS 28 this signal is asserted to power on the system.
1 1
3
A buffer used for PWRBTN# on the system side

AUDIO_AGND may be necessary to prevent the signal interfered
by the contact noise.
2 C647
C2A:(12/22) EMI suggest to add .1u to prevent noise
Q29 .1U-10V_4 PROJECT : ZU1
2N7002
A1A:(9/20) Add R and C Quanta Computer Inc.
1
between AUDIO_AGND and GND

A1A:(9/20) Add Dockin circuit Size Document Number Rev
Docking(ezDockII/II+) 3B

A B C D E
5 4 3 2 1
MAIND
MAIND 38
SUSD
SUSD 38
3 SYS_SHDN# 1 2
PL20
HI0805R800R-00_8 ISL6236_3V
PR121
0_4 PL10
D VIN VIN D
PL7
VL HI0805R800R-00_8
HI0805R800R-00_8
VL
2
PC71
PR97 4.7U/X7R-10V_8
1
390K_4
1
3V_DL
PR122 PR102 PR107
39K_4 0_4 PC75 0_4 PC94 PC86
PC77 PC79 PC84 PC74 1U/10V_6 0.1U/X7R-50V_6 10U/X6S-25V_1206
1
0.1U/X7R-50V_6 2200P/X7R-50V_4 PC72 10U/X6S-25V_1206 0.1U/X7R-50V_6 PC87 PC83
2
2
D1
D1
S2
G2
10U/X6S-25V_1206 PC76 2200P/X7R-50V_4 10U/X6S-25V_1206
.01U/X7R-16V_4 PC73
0.1U/X7R-50V_6
1
3V5V_EN PQ23
2 1 FDS6900AS
2
8
7
6
5
S1/D2
2
PR95 PR103 3V_DH OCP : 6.25A
G1
Change PL11 part number from (DC-15A00036) to (DC-15A00010) *0_4 PR109
8
7
6
5
4
3
2
1
4 5V_DH 150K_4 *0_4 +3VPCU
8
PQ18 3V_DH PL12
LDOREFIN
LDO
VIN
RTC
ONLDO
VCC
TON
REF
OCP: 10A 2.5uH_7.5A
1
FDS8884 3VPCU
D3A:(2/15)Andy inform change PR116 from CS42102FB00 to CS42002FB12 PR112 3V_LX
+5VPCU 5VPCU 9 BYP 32 287K_4
PL11 REFIN2
10 OUT1 31 1 2 Change PL12 part number from (CV-2575MZ02) to (CV-2575TZ51)
1
2
3
1.5uH_10A PU7 ILIM2
C 11 FB1 OUT2 30 C
5VPCU 5V_LX 1 2 12 29
PR116 210K_4 DDPWRGD_R 13 ILIM1 ISL6236 SKIP#
28 DDPWRGD_R PC103 PC142
PGOOD1 PGOOD2
2
8
7
6
5
PR114 3V5V_EN 14 EN1 27 3V5V_EN PR118 +
*0_4 EN2
15 DH1 DH2 26 0_6
16 LX1 25 0.1U/X7R-50V_6 330U/6.3V_6X5.7
+ 5V_DL LX2
4 37 PAD
PC92 36 PAD
SECFB
1
PGND
PC95 PC143
BST1
BST2
0.1U/X7R-50V_6
GND
VDD
PAD
PAD
PAD
DL1
DL2
10U/X6S-25V_1206 PC97 PC90
1
330U/6.3V_6X5.7 0.1U/X7R-50V_6 0.1U/X7R-50V_6 PR115

PR113 PQ17 PR123 *0_6
35
34
33
17
18
19
20
21
22
23
24
0_4 PR124 1_6
1
2
3
FDS6690AS 1_6 1 2
1 2 3V_DL
2
PD6 VL
PC82 PR125 0_6 DDPWRGD_R
2 0.1U/X7R-50V_6 T144
PC99
3 1U/10V_6
3
1
OCP:10A CHN217 PC81
PD8 0.1U/X7R-50V_6 OCP:6.25A
L(ripple current) PC78
0.1U/X7R-50V_6 2
L(ripple current)
2
=(19-5)*5/(1.5u*0.4M*19)
~6A 3 PD7 =(19-3.3)*3.3/(2.5u*0.5M*19)
B B
BAT54-7-F ~2.18A
1
Iocp=10-(6/2)=7A
CHN217 Iocp=6.25-(2.18/2)=5.16A
Vth=7A*15mOhm=105mV PR117 +3VPCU
R(Ilim)=(105mV*10)/5uA +15V_ALWP 1 2 Vth=5.16A*28mOhm=145mV
15V
1
~210K R(Ilim)=(145mV*10)/5uA
PR128 PR126
22_8 PC80 200K_4 39K_4 ~294K
0.1U/X7R-50V_6 PC96
1
2
5
6
VIN 15V +5VPCU 0.1U/X7R-50V_6
SUSD 3 PQ22
+5VPCU +3VPCU +3VPCU FDC653N_NL
PR159 PR127 PC108
4
5
6
7
8
1M_6 1M_6
0.1U/X7R-50V_6 +3VSUS
PC91 PC105 PC102
S5D 4
1
2
5
6
1
2
5
6
1
2
5
6
0.1U/X7R-50V_6 0.1U/X7R-50V_6 0.1U/X7R-50V_6 PC100
3
PQ24 0.1U/X7R-50V_6
MAIND 3 PQ21 MAIND 3 PQ29 S5D 3 PQ27
2 FDC653N_NL FDC653N_NL FDC653N_NL
28,38 S5_ON
PR160 2 PQ26
1M_6
3
2
1
4
DTC144EU PQ44 FDS8884
1
2N7002E
+5V +3V +3V_S5
+5V_S5
1
A A
PC93 PC107 PC104
PC101 0.1U/X7R-50V_6 0.1U/X7R-50V_6 0.1U/X7R-50V_6
0.1U/X7R-50V_6
PROJECT : ZU1
C2A:(12/10) change S5_ON control circuit
B1C:(11/29)Change PQ26 from FDS6690AS (BAM66900022) to FDS8884 (BAM88840006)
Size Document Number
Quanta Computer Inc. Rev
SYSTEM 5V/3V (ISL6236) 3B

5 4 3 2 1
5 4 3 2 1
PL6
HI0805R800R-00_8
VIN_6262
PL5
HI0805R800R-00_8
+1.05V
VIN
1
PR138 PR139 PR140 PR141 PR142 PR143 PR144 +
*0_6 *0_6 *0_6 *0_6 *0_6 *0_6 *0_6
2
DELAY_VR_PWRGOOD 3,6,16
Merom: VCC_CORE/ 44A
5
PC49 PC132 PC48
H_VID6 H_VID5 H_VID4 H_VID3 H_VID2 H_VID1 H_VID0 10U/X6S-25V_1206 PC43 470U/25V 0.1U/X7R-50V_6
D
6262_UG1 4 10U/X6S-25V_1206 Yonah: VCC_CORE/ 36A D
PR25 4.99K_6 VCC_CORE
1
2
3
2 1 PGD_IN VIN_6262 +3V PQ36
PWR_MON
AOL1414
PL17 0.36uH
1
for ISL6262A 6262_PH1 1 2
1
PC17 PR61 A1A:(10/27) change from 10k to 1.91k
1
0.1U/X7R-50V_6 PR47
10_6 PC130
2
4
5
10_4 PR46 2200P/X7R-50V_4 + +
+5V_S5
A1A:(10/2) change from +5VSUS to +5V_S5 1.91K_4 A1A:(10/20) EMI suggest to add it A1A:(10/2) Remove PD10 for layout space issue
2
6262_LG1 4
1
3 PSI# PSI#
1
PR60 PC40 PQ35 PC53 PC50
1
2
3
10_6 0.1U/X7R-50V_6 PC33 0.1U/X7R-50V_6 AOL1412 330u_2V_7343 330u_2V_7343
2
PR76 PR75
22
20
48
2
1
PR52 0_8 PU3
PC41 0_6 0_6
VCC
VIN
PGOOD
3V3
1U/X7R-25V_8
1
PR70 3.65K_6
ISL6262A VSUM
21 GND UGATE1 35
PR69 2.2_6 PR74 10K_6
Close to Phase 1 Inductor 49 GND_T BOOT1 36 1 2
1
Throttling temp. PR72 1_6
+3VSUS PC46
105 degree C 0.22U/X5R-25V_8
2
34 PR71 *0_6 VIN_6262
PSI# PR33 0_4 PSI#_1 PHASE1 ISEN2
2 PSI#
LGATE1 32
A1A:(10/20) no stuff PR75 PR36 VR_ON PR34 *0_4 PGD_IN 3
already have PU R in CPU side PGD_IN
C PGND1 33 C
PR31 147K_6 4 RBIAS
1
*10K_4 24 ISEN1
ISEN1
3 H_PROCHOT# 5 VR_TT#
2
PR146 PR22 6 PC44
470K_4 NTC 4.02K_4 NTC
+5V_S5 0.22U/X5R-25V_6
2
ED8-B -0623-add PC26 1
2 1 PC23
15N/X7R-50V_6
7 SOFT PC45 A1A:(10/2) change from +5VSUS to +5V_S5 PC136 PC134
2
5
.01U/X7R-16V_4 31 1 2 10U/X6S-25V_1206 PC135 0.1U/X7R-50V_6
H_VID0 PVCC 10U/X6S-25V_1206
Panasonic 37 VID0
4 H_VID0 4.7U/X6S-25V_8
ERT-J0EV474J H_VID1 38 27 6262_UG2 4
4 H_VID1 VID1 UGATE2 PR73 2.2_6
H_VID2 39 26 1 2
4 H_VID2
1
2
3
VID2 BOOT2 PQ38
1
PSI#_1 H_VID3 40 AOL1414
4 H_VID3 VID3 PC47
H_VID4 41 0.22U/X5R-25V_8 A1A:(10/20) EMI suggest to add it PL18 0.36uH
4 H_VID4
2
VID4 6262_PH2
PHASE2 28 1 2
H_VID5 42
4 H_VID5 VID5
5
PR37 30 6262_LG2 PC131
4
H_VID6 LGATE2 2200P/X7R-50V_4
*0_6 4 H_VID6 43 VID6
1
PGND2 29
PR59 0_4 VR_ON 44 4 A1A:(10/2) Remove PD11 for layout space issue + +
28 VRON VR_ON
23 ISEN2
PR79 499_4 DPRSLPVR ISEN2 PQ37
6,16 PM_DPRSLPVR 45
1
2
3
2
DPRSLPVR
1
DPRSLPVR AOL1412
PR55 0_4 46 PC42
3,6,14 ICH_DPRSTP# DPRSTP# 0.22U/X5R-25V_6 PC51 PC52
2
PR53 0_4 CLKEN# 47 PR77 PR78 330u_2V_7343 330u_2V_7343
16 VR_PWRGD_CK410# CLK_EN# PC25
25 2 1 0_6 0_6
PR30 1K_4 NC
1000P/X7R-50V_4
PR26 PC20 8 PR35 13.3K_4
OCSET
B 1 2 13 VDIFF B
255_4 1000P/X7R-50V_6 19 VSUM

VSUM
PR38 ED8-B -0623-33nf to 68nf
12 PR58
FB2
1
PR57
1K_4 PC36 11K_4 2.7K_4
11
2
FB
1
68N/X7R-25V_6 PR65 3.65K_6

PC21 PC39 VSUM
PR40 97.6K_4 2 1
2
0.22U/X7R-10V_6 PR145 PR62 10K_6

470P/X7R-50V_4 10 Panasonic
PC28 COMP
2 1
ERT-J1VR103J PR67 1_6
VO 18
220P/X7R-50V_4 PR29 6.81K_4
DROOP
9 10K _6 NTC
ED8-B -0623-390p to330p VW
VSEN
ISEN1
RTN
DFB
PC27
1
1 2 PR49 PR66 *0_6

PC35 Close to Phase 1 Inductor
15
14
16
17
1000P/X7R-50V_6 1K_4 0.22U/X5R-25V_6

2
PR48
PC29 2 1 3.48K_4
ED8-B -0623-3.9k to 3.48k
.01U/X7R-16V_4
PC31
180P/NPO-50V_4
2 1 ISL6262_VO
2
PC32 PC24
.01U/X7R-16V_4 .01U/X7R-16V_4
1
Parallel
A PR41 0_4 A
VCCSENSE 4
PR43 0_4
VSSSENSE 4
PROJECT : ZU1
Custom CPU Core ( ISL6262A) 3B

5 4 3 2 1
1 2 3 4 5
A1A:(10/2) change from +5VSUS to +5V_S5 VIN-1.5V

PL14
VIN
+5V_S5 HI0805R800R-00_8
PR136
1
PC114 PC116 PC115
10_6 0.1U/X7R-50V_6 10U/X6S-25V_120610U/X6S-25V_1206
2
B1C:(11/30) T211 Power sequence issue PC126 PD10
5
6
7
8
(1)change PR134 from 0 ohm to 47k ohm. PR133 RB500V PC127
(2)stuff C448 0.1uF *.1U_6
1M_6 4.7U/Y5V-10V_8
2
A 4 A
A1A:(10/18) Reserve .1UF PU8 PC124

PQ33 Change from AOL1414 to FDS8884 (BAM88840006)
SC411MLTRT .1U/X7R-25V_8 PQ33
PR134 47K_6 15 13 FDS8884
PQ34 Change from AOL1412 to FDS6690AS (BAM66900022)
28,37,38 MAINON EN/PSV BST
+3V C448 DH-1.5V
16 12
10A
3
2
1
VIN DH PL19
.1U_6 1 11
VOUT LX +1.05V
2 10 PR8 13.7K_6 1R5UH-3.8mR
VCCA ILIM
5
6
7
8
PR137
1
*10K_6 3 9
FBK VDDP +
4 8 DL-1.5V 4 PR9
28 HWPG_1.05V PGOOD DL PC7
2
6 7 11K_6 33P/NPO-50V_6
VSSA PGND
5 17 PQ34 1.05V_FB
NC TPAD FDS6690AS
14
GND
GND
GND
GND
3
2
1
NC
1
PC125 PC123 PC120 1 PC129 PC128 PR10

0.1U/X7R-50V_6 560U/2.5V_6X5.7 10U/Y5U-10V_8 10K_6
2
18
19
20
21
PR8 Change from 6.65K(CS26653F911) to 15K(CS31503F939)
1000P/X7R-50V_6 .01U/X7R-50V_6 VOUT=(1+R2/R3)*0.5
B PR9 Change from 20K to 11K (CS31103F926) B
B1C:(11/29) Change PR8 from 20K(CS32003F933) to 6.65K ohm (CS26653F911)
C C
D D
PROJECT : ZU1
VTT 1.05V (SC411) 3B

1 2 3 4 5
5 4 3 2 1
PL9
VIN
HI0805R800R-00_8
PL16
+1.8VSUS
5
6
7
8
PR100 HI0805R800R-00_8 PC150
PC55 0.1U/X7R-50V_6
*2.2_6
10U/X6S-25V_1206 4
A1A(10/5):change net name from PU4 PQ16
+SMDDR_VTERM to SMDDR_VTERM TPS51116 C2A:(11/22) EMI suggest to add 2.2ohm BST resister in 1.8V power PC85 PC88 PC149
1 19 FDS8884 PC70 PC151 2200P/X7R-50V_6 PC89 10U/X6S-25V_1206 2200P/X7R-50V_6
VLDOIN DRVH PR153 2.2_6 *2200P/50V_6 0.1U/X7R-50V_6 10U/X6S-25V_1206 Add PC150, PC151 0.1u (CH41006K911)
2 20 1 2 PC58 0.1U/X7R-50V_6 Add PL16 HI0805R800R-00_8 (CX0R800R014)
SMDDR_VTERM VTT VBST PL8
3
2
1
PC54 PC56 4 18 +1.8VSUS
VTTSNS LL
D D
5
6
7
8
5
6
7
8
10U/X6S-25V_1206 5 17 1R5UH-3.8mR
10U/X6S-25V_1206 GND DRVL
+
MAX Current 10A
3 VTTGND PGND 16
4 4
DIS_MODE 6 11 S3_1.8V PR91 0_6
MODE S3 MAINON 28,36,38
PR88
7 12 S5_1.8V PR92 0_6
SMDDR_VREF VTTREF S5 SUSON 28,38
0_6 5VIN 8 14 5VIN C321 C322
PC60 COMP V5IN PC98 PC133 PC67
3
2
1
3
2
1
0.033U/50V_6 9 13 *.1U_6 *.1U_6 PQ19 PQ20 2200P/50V_6 560U/2.5V_6X5.7 10U/Y5V-10V_8
A1A(10/5):change net name from PR89 VDDSNS PGOOD A1A:(10/18) Reserve .1UF FDS6690AS *FDS6690AS
GND
GND
GND
GND
GND
GND
GND
+SMDDR_VREF to SMDDR_VREF 5VIN 10 15
VDDQSET CS
0_6 PR86 PR90
21
22
23
24
25
26
27
FOR DDR II PC59 +3VPCU +3VPCU
*1000P/50V_6 14K/F_6 100K/F_6
PR84 *0_6 DIS_MODE PR87 C2A:(12/28) EMI request: DEL PR120 2.2ohm(CS-2203F911), stuff PC98
5VIN
+5VPCU HWPG_1.8V 28
1
0_6 PC61
+1.8VSUS PR85 0_6 4.7U/X5R-6.3V_6
2
B1C:(11/29) Change PR86 from 12K (CS31203F911) to 8.25K (CS28253F938)
B1C:(12/11) Change PR86 from 8.25K (CS28253F938) to 14K (CS31403F919)
C C
A1A(10/5):Remove +1.8V circuit
B B
A A
PROJECT : ZU1
DDR 1.8V(TPS51116) 3B

5 4 3 2 1
5 4 3 2 1
PR12 1 GND0 VO1 5
MAINON 2 6
EN VO2 +2.5V
PQ39 FDS8884 +3VSUS
+1.8VSUS 10K_6 3 VIN1 GND1 8 0.5A
8 1 4 VIN2 GND2 9
ADJ
7 2 PR12 Change from 200K to 10K (CS31003F949)
6 3
1
PC65 PC63 5
7
0.1U/X7R-50V_6 PU1
10U/X5R-6.3V_6 AT814
4
9338DRV
D3A:(2/2) DEL PC137 footprint 1.24V R1
D VTT-ADJ D
PR147 PC10 PC8 PC13
2
+1.5V PC9 10U/Y5U-10V_8 1U/16V_6 PR28 22U/Y5U-10V_8 PC18
0_6 3A 0.1U/X7R-50V_6 10.2K_4 0.1U/X7R-50V_6
+3V PR18 R2
+1.5V 4,9,17,27,31
PR99 100K_4 10K_4
Vout=1.24*[1+(R1/R2)]
2
REV:3A MODIFY
1
3 6 PC138
28 HWPG_CPUIO PGD DRV .01U/X7R-16V_4 PR108 PC13 Change from 10U to 22U (CH6221M9A07)
1
Rg 20K_6
MAINON PR105 0_4 9338EN 4
28,36,37 MAINON EN
1
5 +
ADJ
GND
+5VPCU 1 Vout1 = (1+Rg/Rh)*0.5
2
VCC PR104
1
C339 PC69 10K_6 +5V
2
A1A:(10/18) Reserve .1UF PU6
*.1U_6 0.1U/X7R-50V_6 G9338 ADJ
Rh PC62 PU5
2
0.1U/X7R-50V_6 G966
1 2 4 VPP PGOOD 1
PC141 PR94
PC140 PC139 560U/2.5V_6X5.7 MAINON 2 6
VEN VO +1.25V
0.1U/X7R-50V_6 10U/X5R-6.3V_6
10K_6 3 2A
+1.8VSUS VIN
8 GND
ADJ
9 GND NC 5
PR82
1
PC64 PC66 C323 PC57
7
19.6K_6 10U/Y5U-10V_8
10U/X5R-6.3V_6 *.1U_6
2
0.8V
C 0.1U/X7R-50V_6 C
A1A:(10/18) Reserve .1UF
PR83
34K_6
Vout =0.8(1+R1/R2)
=1.25V
VIN SMDDR_VREF +1.8VSUS +3VSUS 15V
PR93 PR81 PR96

PR111 22_8 22_8 22_8 PR98
1M_6 1M_6
A1A:(10/25) Add +1.5V_S5 circuit (refer to ZD1)
SUS_ON_G SUSD B1C:(11/29) no stuff U38,PC144,PC146,PC147,PR149
SUSD 34
3
3
3
+3VPCU SOT23-5 +1.5V_S5

2 2 2 2 2 U38 *AT5206G-1.5V
28,37 SUSON PC68 200mA
PR110 PQ11 PQ10 PQ13 PQ12 *2200p_4 1 5
PQ15 1M_6 2N7002E 2N7002E 2N7002E 2N7002E VIN VOUT
1
2
DTC144EU
1
PC147 PC144
GND
*1U/X7R-25V_8 3 4 *1U/X7R-25V_8
1
SH BP
1
PR150
PC146 *0_4
2
B *470P/X7R-50V_4 PC145 B
2
*10U/X6S-25V_1206
28,34 S5_ON
PR149
*0_4
A1A(10/5):Remove +1.8V
A1A(10/25):Add +1.25V discharge circuit
VIN +1.05V +1.25V +2.5V +3V +5V SMDDR_VTERM +1.5V 15V
PR106 PR24 PR27 PR23 PR130 PR129 PR80 PR148

22_8 22_8 22_8 22_8 22_8 22_8 22_8 PR131
1M_6 1M_6
RUN_ON_G MAIND
A MAIND 34 A
3
3
3
2 2 2 2 2 2 2 2 PC106
28,36,37 MAINON *2200p_4
2
PR101 PQ6 PQ4 PQ28 PQ25 PQ9 PQ40 PQ30
PQ14 1M_6 2N7002E PQ5 2N7002E 2N7002E 2N7002E 2N7002E 2N7002E 2N7002E PROJECT : ZU1
1
DTC144EU 2N7002E
1
1
1

Discharge (1.5V/2.5V) 3B

5 4 3 2 1
5 4 3 2 1
3/19 Add fuse E3A:(3/14)Change PD9 footprint from SBM1040-3P 0.02_3720

VA to SBM1040-3P-ZU1 for SMT C-test open issue VA2 PR132
PJ1 HI0805R800R-00_8 PQ31 VIN PQ2
SIT_2DC-G026-I06 PL2 2 SUD45P03-15 SUD45P03-15
1 1 2 3 1 2 3 4 3 4
2 1
3 PF1 BUS-7A-1206
1
PC1 PC2 PL1 PD9 PC110 PR7
1
1P
2P
1
1
PDS1040S PC3 PR1 0.1U/X7R-50V_6
33K_6
0.1U/X7R-50V_6 220K_6
5
4
2
2
HI0805R800R-00_8
2
PD4
0.1U/X7R-50V_6
D 0.1U/X7R-50V_6 SW1010C D
PC109 PC113 1 6 PR11
1
0.1U/X7R-50V_6 0.1U/X7R-50V_6 10K_6
PR2 2 5 PR6 0_6
A1A:(9/27)change CONN (Follow ZH2) D/C# 28
220K_6
PD5 3 4
3
PR63
ACIN_1 2 1 PQ1
28 ACIN
IMD2AT108
10K_6 2
ZD12V CSIN
PR68 PQ3
PR64 2N7002E
6.8K_6 10K_6 CSIP
1
3/19 Change PR42 from 18_6 to 20_6
3/19 Add PR120 2.2_6 VIN
PC38 2.2U/X5R-10V_8
1 2 PC112 10U/X6S-25V_1206
PR120 PR42 ISL6251_VDD
2.2_6 20_6
PR15 PL13
4.7_6 PC111 0.1U/X7R-50V_6 HI0805R800R-00_8
3/19 Change PR51 from 2.2_6 to 20_6 PC30 1 2
3/19 Add PR154 20_6 0.1U/X7R-50V_6 PC11 4.7U/X5R-10V_8
3/19 Change PC34 from 1U_8 to 47N_6 ISL6251_VDDP 1 2 VA3
CSIN_1
5
6
7
8
PD3 PL15 Change from 2R2 to 4R7(DC-4775M001)
19
20
15
C C
1
RB500V PR135 Change from 0.02 to 0.03(CS+0308FL00)
4
CSIP
CSIN
VDD
VDDP
PR51 20_6 PC22 0.1U/X7R-50V_6 PQ32
CSOP CSOP_1 21 PR21 2.7_6
CSOP 6251B_2 6251B_1 FDS8884 B1C:(11/29) Change PR135 from 0.03(CS+0308FL00)
BOOT 16 1 2
PC34 to 0.02 (CS+0208GL17)
47n/X7R-25V_6 PR135
PR154 20_6 17 ISL6251_UGATE PL15 0.03_3720
3
2
1
CSON UGATE 4R7UH(PCMC063T-4R7MN)
22 CSON 6251LR
1 2 BAT-V
18 ISL6251_PHASE
PHASE
5
6
7
8
DRC 18m ohm
1P
2P
14 ISL6251_LGATE + PC148
PC37 LGATE 100U/25V_6X7.7
23 ACPRN 4
DCIN 0.1U/X7R-50V_6
PGND 13
PQ41
DCIN 24 12 VREF FDS6690AS
DCIN GND PC119 PC117
3/19 NC PR54 , PR56 CSOP 10U/X6S-25V_1206 .01U/X7R-50V_6
3
2
1
A1A:(9/27)change Pin define 11 PR19 PR13 PC118
A1A:(9/29) change footpint: BAT-250133MR007G115ZU-7P-R PR54 6251ACSET VADJ 71.5K_6 *514K_6 CSON 10U/X6S-25V_1206
2 ACSET
*130K_6
ACLIM 10
PC4
D3A:(2/2) Andy:change PR54,PR56 from NC to stuff 3 EN
VADJ Float = 4.2V / CELL
VCOMP
3/19 Add fuse
ICOMP
CELLS
CHLIM
VRFE
PR56 ACLIM
B MTEMP 28 B
ICM
*10K_6
CN20 HI0805R800R-00_8
100P/NPO-50V_4 PL4 PR14
26251ICOMP 5
9
7 MBAT+ BAT-V PU2 PR16 *514K_6
6 1 2
TEMP_MBAT ISL6251A 10K_6
5 PF2 BUS-15A-1206
4 PL3 ISL6251_VDD 6251EN VREF
3
6251VCOMP1
HI0805R800R-00_8
2 CC-SET 28
1
PC122 PC121 PC6 PR44 10K_6

1 PR5 100K/F_6 LIM = 1/R2(((0.05/VREF=2.39)VACLM)+0.050)
SUY_250133MR007G136ZL 47P/NPO-50V_4 47P/NPO-50V_4 6251CELLS_1
+3VPCU
2
0.1U/X7R-50V_6 6251CELLS_1 PC19 PC12 CURRNT LIMIT POINT = 2.908A

1
PR3 PR39 *10K_6 100P/NPO-50V_4
10mil 100_4 PR151 3.79A=1/0.02((0.05/2.365)Vaclm+0.05)
3
PR4 0_6 PR45 .01U/X7R-16V_4

PR17
100_4 MBDATA 28 *10K_6 Vaclm=0.3899V
26251VCOMP2 ICMNT 28
MBCLK 28 6251CELLS_2 2
TEMP_MBAT PR20
100_4
1
13K_4 ADP WATT monitor output

1
PQ7 3/19 Add PR17

PD1 PD2 PC5 *2N7002E 3/19 Add PC14 For 62W setting. Vicm will 1.3V
1
ZD3.6V ZD3.6V PR152 .01U/X7R-50V_6 28 CELL-SET 2 PR32 PC14

2
*100K/F_6 *100K/F_6 3300P/X7R-50V_4

2
PQ8
PR50 *2N7002E
1
*100K/F_6
1
B1C:(11/29) Change PC19 from 0.01u (CH31003KB11) to 3.9n (CH23904KB13)

A B1C:(11/29) Change PC15 from 0.01u (CH31003KB11) to 3.3n (CH23306JB16) A
PC16 PC15 B1C:(11/29) Change PR20 from 3.3K (CS23302FB12)to 18K (CS31802FB09)
Change PR5 from 10K to 100K (CS41003F932) *100P/NPO-50V_4 6.8n_4 B1D:(12/09) Change PR20 from 0402 (CS31802FB09) to 0603 (CS31803F913)
ADD PR152 and NC. Change PC19 from 3.9n to 10n (CH31003KB11)
Change PC15 from 3.3n to 6.8n (CH26804KB18) PROJECT : ZU1
Change PR20 from 18K/F to 13K/F (CS31302FB19) Quanta Computer Inc.
CELL-SET = Hi ----> Cells = VDD ---->4S
CELL-SET = Low ----> Cells = GND ---->3S Size Document Number Rev
3B
Charger (ISL6251)
5 4 3 2 1
5 4 3 2 1
ISL6262A VCC_CORE
PU3 <VRON>
D D
+5VPCU
<AC/DC Insert>
+5VPCU
FDS6690AS
+5V_S5
PQ26 <S5_ON>
FDC653N +5V
PQ21 <MAIND>
ISL6236 +3VPCU
VIN
<AC/DC Insert>
PU7
FDC653N +3V_S5
<S5D>
C PQ27 C
FDC653N +3VSUS
+3VPCU
PQ22 <SUSD>
AT814 +2.5V
PU1 <MAINON>
FDC653N +3V
ADAPTER
Charger PQ29 <MAIND>
ISL6251 VIN
AT5206G
BATTERY PU2 +1.5V_S5
U38 <S5_ON>
B
+1.8VSUS B
<SUSON>
+1.8VSUS
G966 +1.25V
PU5 <MAINON>
TPS51116
VIN
PU4
G9338
+1.5V
PU6 <MAINON>
SMDDR_VTERM
<SUSON>
SMDDR_VREF
<SUSON>
A A
SC411
+1.05V
<MAINON>
PU8
ZU1 Power Table
5 4 3 2 1
5 4 3 2 1
SLP_S3#(SUSB#):
Control non-critical power plane when system into S3(Suspend to RAM)/S4(Suspend to Disk)/S5(Soft off).
SLP_S4#(SUSC#):
Control non-critical power plane when system into S4(Suspend to Disk)/S5(Soft off).Used to control DRAM power
3
D D
NBSWON#
5
4
S5_ON +5V_S5
S5_Power
+3V_S5
2 PU26,PQ27
6
1 +3VPCU
AC Adapter RSMRST#
VIN
Charger Circuit Always System power
PU2 +5VPCU 7
PU7
Battery DNBSWON#
9
8
SUSON SUSC#
SUSB# 15 CK505
CK_PWRGD
EC SB
U19
10
MAINON
C
13 C
12
VRON 17 18
PWROK_EC
ICH_PWROK H_PWRGD CPU
U21
U30
MPWROK
U32
U14
20
13
H_CPURST#
CPU CORE VR +VCC_CORE
19
14
PLTRST#_NB
PU3
VR_PWRGD_CK410#
DELAY_VR_PWRGOOD
B B
16
10
G9338 +1.5V
HWPG_3/5VPCU
PU6
HWPG_CPUIO 11
HWPG_1.05V HWPG MPWROK

SC411 +1.05V
HWPG_1.8V
PU8
+5V
FDC653N NB
+3V
PQ21,PQ29
G966
+1.25V
PU5
A A
U29
DDR VR +1.8VSUS
SMDDR_VTERM
SMDDR_VREF
PU4
ZU1 Power Sequence
5 4 3 2 1
5 4 3 2 1
Item: Fixed Issue Modify List: Schematic Rev. Page
1 CPU Clock select issue Stuff R179,R198,R447 for CPU Clock select issue A1A 2
2 PCI Clock issue change R186 value from 33ohm to 22 ohm (refer to Intel check list 1.301) A1A 2
3 CK505 issue ICS FAE suggest to change C542,C287 from 4.7u to 10u A1A 2
D D
4 EMI issue EMI suggest to reserve R436,R199,R444 for EMI test A1A 2
5 CK505 issue Add PCIE_CLKREQ# PU to +3v A1A 2
6 CK505 issue SWAP SRC3 and SRC9 A1A 2
8 CK505 issue Remove U19/Pin48 (no use) A1A 2
10 CK505 issue remove SATACLKREQ function, change R188 value from 475ohm to 22 ohm A1A 2
11 CK505 issue FAE : (14M_ICH and SIO_14M) signals trace should be equal length A1A 3
12 CPU issue Remove XDP/ITP signals (no use) A1A 3
13 CPU issue Retain the termination resistors (R157,R150~R152) on these signals even when ITP700 not implemented. A1A 3
C C
14 Thermal Trip issue change Q19/Pin3 net name from THERM_SYS_PWR to SYS_SHDN# A1A 3
15 CPU FAN issue change CPU FAN CONN (follow ZC3) A1A 3
16 CPU FAN issue Add CPUFAN#_ON to (U28/PIN1) A1A 3
17 CPU FAN issue Add Diode D39 and PU +5V for (U28/Pin1) A1A 3
18 CPU Thermal monitor issue Add (U27/Pin6) PU to 3V A1A 3
19 CPU Thermal monitor issue remove R389, already PU in ICH8 A1A 3
20 CPU Thermal monitor issue change SMBUS from MBCLK/MNDATA to 2ND_MBCLK/2ND_MBDATA (Q30,Q31) A1A 3
21 CPU Power issue stuff C198, unstuff C217 (base on layout location) A1A 4
22 GMCH Power issue Short R115~R117,change +VCC_CFXCORE_INT to +1.05V A1A 8

B B
23 GMCH Power issue Short R122,R138, remove VCC_RXR_DMI circuit (connect to +VCC_PEG directly) A1A 9
24 GMCH Power issue INTEL CRB VCCD_QDAC Filter Modification:change L13 to R125(100ohm), change R145(*0 ohm) to C507(1uF) A1A 9
25 DDR Power issue stuff R192, no stuff R191,R193 for SMDDR_VREF_DIMM A1A 13
26 RTC BAT issue Change RTC BATTERY CONN CN12(follow to ZC3) A1A 14
27 ICH8-M Strap issue Stuff R241, no stuff R266 (Disable Internal VR powering VccLAN1_05, VccCL1_05) A1A 14
28 ICH8-M HDA issue add R283,R465,R463,R267 for MDC module (base on Intel Design Giude) A1A 14
29 ICH8-M issue PU RCIN# to +3V A1A 14
30 ICH8-M issue Remove ICH8-M GLAN/SATA1/SATA2 circuit (no use) A1A 14
31 ICH8-M issue change net name (U31/Pin2) from VR_PWRGD_CLKEN# to VR_PWRGD_CK410# A1A 16
32 ICH8-M issue Remove SATACLKREQ#(U32/Pin:AG13),RI# (U32/Pin:AF17) ;{no use} A1A 16

A A
33 ICH8-M issue no support iAMT, remove SMB_CLK_ME,SMB_DATA_ME A1A 16
34 ICH8-M issue change DOCKIN#_ICH_R PU from +3V to +3V_S5 A1A 16
PROJECT : ZU1 APPROVE BY : James Lu DRAWING BY:Barry Lee Stage: A1

PROJECT : ZU1 CHANGE LIST SHEET 1
Quanta Computer Inc. MB ASSY'S P/N : 31ZU1MB0000 PROJECT LEADER:Jack Wu DOCUMENT NO: DATE :2006/12/09
5 4 3 2 1
5 4 3 2 1
35 Power sequence issue change (U21/Pin5) from +3V to +3VSUS (refer to ZC1) A1A 16
36 ICH8-M issue Remove WOL_EN (U32/Pin:AG19) -no use A1A 16
37 ICH8-M issue Remove SUSM# (used to control power planes to the Intel AMT sub-system) A1A 16
D D
38 ICH8-M issue Remove (1)ME_EC_ALERT# (2)EC_ME_ALERT (no use) A1A 16
39 ICH8-M issue connect LAN_RST#(U32/Pin:AH20) to PLTRST# (If no use internal LAN MAC connect LAN_RST# to PLTRST#) A1A 16
40 ICH8-M issue change DOCKIN#_ICH_R PU from +3V to +3V_S5 A1A 16
41 EMI issue EMI suggest C373 from 0.1u to 10uF A1A 17
42 ICH8-M Power issue Reserve R308,R313 for +1.5V MDC module A1A 17
43 LAN Power issue change LAN power from +3V_LAN_S5 to +3V_S5 A1A 18
44 LAN Power issue BCM FAE: Pull up Vmainprsnt (U10/Pin53) to the system main power (3.3v), but not the standby power A1A 18
45 LAN Power issue BCM FAE: Change capacitance value from 47-uF to 10-uF. A1A 18
46 LAN Power issue BCM FAE:stuff R30,no stuff R47(in order to pull up C90,C86 and Q16/pin 3 to 3V_LAN rail) A1A 18
47 LAN Switch issue EMI suggest C59 from 0.1u to 10uF A1A 18
C C
48 LAN Switch issue Add Diode D4 for isolation (Dockin#) A1A 18
49 LAN Switch issue change LAN Switch from MAX4892 to PI3L500 A1A 18
50 LAN Transformer issue change TRANSFORMER GND(U3/Pin15,18,21,24) to MGND A1A 18
51 LAN CONN issue Change CONN P/N (follow ZC1) A1A 18
52 LAN CONN issue change CONN GND(CN19/Pin13,14) to MGND A1A 18
53 CRT issue change C439, C440,C7,C441 to 30~50pF(default :no stuff) A1A 19
54 CRT issue Change CRT_SENSE# from CRT CONN Pin11 to Pin5 (follow Acer define) A1A 19
55 CRT issue Change CRT CONN P/N(follow ZC1) A1A 19
56 CRT issue change R16,R17 from 2.7k to 2.2k ; R10,R12 from 39 to 0 ohm A1A 19
B B
57 CRT issue change U1 from CM2009 to IP4772 A1A 19
58 LVDS issue change CCD function from USB7 to USB8 A1A 20
59 LVDS issue Change C12 from CH6102M9900 to CH61004M3E5 (refer to ZC3) A1A 20
60 TV issue Change CN17 CONN P/N (follow ZC1) A1A 20
61 SDVO issue Change R51,R56 value from 2.2k to 4.7k (FAE suggest R value from 4K~9K) A1A 21
62 PCMCIA issue refer to BL3. Add G_RST# circuit. A1A 22
63 PCMCIA issue FAE suggest R189's value under 47 ohm. A1A 22
64 Card reader issue no stuff R496,R522 A1A 23
65 Card reader issue FAE suggest R503's value under 47 ohm. A1A 23
66 Card reader issue Remove U39/Pin99, no use (XMDAT4B is for 8 bit MMC,remove it.) A1A 23
A A
67 Card reader issue Change C593 from 0.1u to 10uF,EMI suggest add C587 0.1uF A1A 24
68 PCMCIA issue change PCMCIA CONN (follow BH1) A1A 24
PROJECT : ZU1 APPROVE BY : James Lu DRAWING BY:Barry Lee Stage: A1

5 4 3 2 1
5 4 3 2 1
69 PATA ODD issue change R253 from 0 to 33ohm A1A 26
70 PATA ODD issue Add C326,C327,C344 for +5V A1A 26
71 PATA ODD issue Remove D23, already add in page29 A1A 26

D D
72 Mini Card issue Reserve R349,R350,R337,R345,R344,R338,R339 for debug card use A1A 27
73 Mini Card issue Add (CN28/Pin39,41) to +3V_WL_VDD (follow ZO1) A1A 27
74 Mini Card issue Remove (CN28/Pin36,38) USB circuit A1A 27
75 Mini Card issue Remove (CN28/Pin46) BT LED A1A 27
76 Mini Card issue Remove 0.1uF (CN28/Pin23,25), already in WL module A1A 27
77 Bluetooth issue SI suggest to remove 22pF*2 (CN5/Pin3,4) A1A 27
78 USB CONN issue SI suggest to remove 22pF*2 (CN11/Pin2,3) A1A 27
79 EC issue Change EC from WPC8769 to WPC8763 A1A 28
80 EC issue change U7/Pin5,6 from MBCLK/MNDATA to 2ND_MBCLK/2ND_MBDATA A1A 28
81 EC issue Remove ME_EC_ALERT# A1A 28

C C
82 EC issue FAE:Change U14/Pin80 from +3VPCU to +A3VPCU A1A 28
83 EC issue change C130,C131 from 6.8p to 5.6p A1A 28
84 EC issue Add D18 for HWPG_CPUIO A1A 28
85 Finger Printer issue SI suggest to remove 22pF*2 (CN9/Pin2,3) A1A 29
86 SuperIO issue Remove PPT PU 4.7K circuit (already in docking) A1A 30
87 Audio issue Change Serial resister R484,R485 value from 22 ohm to 33 ohm A1A 31
88 Audio issue reserve R513 to reduce ringing A1A 31
89 Audio issue Refer to ZD1, change R546,R520,R545,R519 to 10k A1A 32
90 Docking issue (CN22/Pin18,Pin19):(1)Remove Level-shift circuit (2)change Power from +3V to +2.5V (3)stuff 2.2k A1A 33
B B
91 Docking Power issue Add .1u*7 , 10U*1 for VA A1A 33
92 Docking issue Reserve U25 for docking PWRBTN# A1A 33
93 Docking issue Change Docking Pin141/142 from USB5 to USB3 A1A 33
94 Docking issue PL DVI_DET 100k to GMD (CN22/Pin20) A1A 33
95 Docking issue Change LAN pin define A1A 33
96 Audio issue Change CN29,CN30,CN31 P/N (Base on Acer request) A1B 32
97 ICH8-M Strap issue Change INTVRMEN from PD to PU B1C 14
98 Leakage issue add D43,D44 to stop leakage from EC to SB B1C 16
99 ICH8-M issue change DOCKIN# from GPIO7 to GPIO12 B1C 16
100 Power sequence issue short PWROK_EC to MPWROK B1C 16

A A
101 ICH8-M issue PU GPIO10 to +3V, PD GPIO14 to GND B1C 16
102 ICH8-M issue remove R229,R233,C355 B1C 16
PROJECT : ZU1 APPROVE BY : James Lu DRAWING BY:Barry Lee Stage: A1 / A2

5 4 3 2 1
5 4 3 2 1
103 PCMCIA issue Reserve R572 for debug use B1C 22
104 1394 issue Change R271,R306,R307 from 56.2 to 5.1k ohm (fix 1394 can't detect issue) B1C 25
105 Mini Card issue no stuff R353,R348,R356 B1C 27

D D
106 Mini Card issue need support BCM WL Module, Connect CN28/Pin40 to GND B1C 27
107 EC issue SWAP GPIO1 and GPIO3 B1C 28
108 EC issue Change CN10/Pin1 from +3V to +3VPCU B1C 28
109 LED issue Base on Me request, change PWR/SUS/BAT LED type B1C 29
110 Audio issue Stuff R330 to fix Internal SPK issue (floating GND issue) B1C 27
111 Docking issue Add R566 for Debug use B1C 33
112 Mini Card issue ME request :change CN28 P/N from DFHD52MS049 to DFHS52FR082 (9.0mm to 9.9mm) B1D 27
113 GMCH Power issue Change C143 from CH71002MJC8 to CH7102MT804 (Z-limit issue,H2.9mm to H1.5mm) B1D 9
114 CPU Clock issue Set CPU Frequency to auto selection (no stuff R179,R198,R447) C2A 2
115 S5_ON issue Change S5_ON control circuit (follow ZO1/ZD1) C2A 34
C C
116 CK505 issue change CK505 VDD_IO from +1.05V to +1.25V. Because VDD_IO will drop out when high loading C2A 2
117 G995 issue Add level shift circuit (follow ZO1), remove D39,no stuff R383. C2A 3
118 BIOS EMI issue FAE suggest add 22 Ohm dumping resistors R596,R597 to avoid potential EMI problem C2A 28
119 LAN issue Base on BCM IEEE test result, change RDAC value (R42) from 1.24k to 1.18k C2A 18
120 Audio issue Acer change internal Mic solution to Fortemedia,Remove CN33,D29,D30,R342,R506,C400,C586 C2A 32
121 DVI Detect issue Intel suggest:Add hotplug circuit to DVI_DET (follow ZC1) C2A 21
122 ICH8M issue Intel Suggest :ICH8M CPIO20 should not be pulled HIGH.Remove BOARD_ID3 circuit(remove R474,R475) C2A 16
123 SDVO issue Intel Suggest :Follow Intel New Guideline(MoW 48 update) Change R51,R56 from 4.7K to 3.9K ohm C2A 21
124 GMCH Power issue Change Crestline VCC_AXM to 1.25V, reference to SR ww48 MoW.reserved 0 ohm resister (R576) C2A 8
B B
125 SuperIO issue Intel Suggest :All LPC devices support LPCPD# protocol, stuff D7 C2A 30
126 ICH8M issue no stuff R259 to prevent leakage issue C2A 16
127 EMI issue EMI suggest add C647 to prevent noise for PR_STS C2A 33
128 EMI issue EMI suggest to add .1u *2 to prevent noise (+3V) C2A 30
129 EMI issue EMI suggest to add 2.2ohm BST resister (PR153) in 1.8V power C2A 37
130 EMI issue EMI suggest add three clip to contact with CPU cooler's fins (PAD23,24,25) C2A 30
131 ME issue ME request add three pad for fix wire (PAD20,21,22) C2A 30
132 DVI issue remove the U11,R57,R52,C109 to save layout space. C2A 21
133 Power monitor issue D16 not necessary if 3V/5V fail, EC can't work. C2A 28
134 S3 resume POP sound issue change C619 from CH61004M2E8 to CH5222K9A09 to solve S3 resume POP sound issue C2A 31
A A
135 POP sound issue no stuff R525,D41, add bypass R577 to solve pop sound issue C2A 31
136 AUDIO issue no stuff D27 C2A 32
PROJECT : ZU1 APPROVE BY : King Wang DRAWING BY:Barry Lee Stage: A2 / B

5 4 3 2 1
5 4 3 2 1
137 Audio issue change R546/R520 from 10k to 9.1k C2A 32
138 GMCH POWER issue Change Crestline VCC_AXM from +1.25V to +1.05V, reserved 0 ohm resister (R578) C2A 8
139 XTAL issue Base on vendor-FCE suggestion, change C580/C579 from CH01206JB05 (12p) to CH02206JB08 (22p) C2A 25
D D
140 XTAL issue Base on vendor-FCE suggestion, change C310/C299 from CH03306JBD7 (33p) to CH02706JB06 (27p) C2A 2
141 XTAL issue Base on vendor-FCE suggestion, change C130/C131 from CH-5606TB01 (5.6p) to CH01006JBD1 (10p) C2A 28
142 EMI issue EMI request: DEL PR120 2.2ohm(CS-2203F911), stuff PC98 C2A 37
143 EMI issue EMI request: reserve .1U for (CN19/pin9,10) C2A 18
144 EMI issue EMI request: reserve L-C footprint for debug use (R52,C650) C2A 20
145 debug issue Stuff R349 , R350 for debug use D3A 27
146 Modem wake from S3 fail issue Change CN14/pin 2 from +3v to +3v_s5. D3A 31
147 CableSence circuit issue Add CableSence circuit (unstuff R78) D3A 18
148 CableSence circuit issue Add CableSence circuit (reserve R579) D3A 18
149 LED type issue Base on SMT-ME request, change LED type to 2 in 1,DEL LED4,LED5,LED6,LED7,R570,R571,Add LED2,LED3 D3A 29
C C
150 SW button issue Base on ASSEMBLY -Line request, remove SW1, add G2 footprint D3A 29
151 change Modem capacitor to meet safety standard change C37,C48 from CH147GK0I09 to CH147GK0I00 D3A 33
152 Power issue The system side should have a diode (D45,D46) to block the AC adaptor power and ezDock. D3A 33
153 EMI issue Change L4,L5,L6 from CX8BA220007 to CX8BA470003 D3A 19
154 DVI issue remove U13,R68,R75,R73,C98 for layout space issue D3A 21
155 ASF issue Connect SMLINK0 to SMBCLK and SMLINK1 to SMBDATA (Add R474,R475 for debug use) D3A 16
156 SMT B open issue (1)Remove footprint for D41,D42,R525. DEL R577 (0 ohm) (2) Remove net SECNTL D3A 31
157 CableSence circuit issue change LAN Low power pin from GPIO47 to GPIO52 D3A 28
158 LAN switch issue Change U6 from AL000500005 to AL000500030 (change to 8KV solution) D3A 18
B B
159 Change 965GM from ES sample to QS sample Change U29 P/N from AJ0QN120T37 to AJ0QP200T09 D3A 5~11
160 Change ICH8M from ES sample to QS sample Change U32 from AJ0QM740T31 to AJ0QN230T10 D3A 14~17
161 Audio Jack issue change CN30,CN31,CN32 footprint from AUDIO-010164FR006GX53XL-C-8P to AUDIO-JA60331-X39T4-7F-8P D3A 32
162 docking sometimes can't detect DVI device issue change R51,R56 from 3.9k(CS23902FB14) to 4.7k(CS24702JB38). D3A 21
163 EMI issue EMI suggest, add common Choke, co-lay R795,R796 D3A 27
164 Audio Jack issue Change CN30 P/N from DFTJ06FR017 to DFTJ06FR059 D3A 32
167 backlight control issue Follow ZO1 design,Remove R24 footprint, DEL D3(BC000316Z07).Add R73,Q36,Q37 D3A 20
168 docking CRT flicker issue Reserve C98,R525 for docking CRT flicker issue D3A 19
A A
169 EMI issue EMI suggest add C652(0.1uF) D3A 19
170 system sometimes will no backlight issue . For short term solution:change R22 from 10k(CS31002JB28) to 1K (CS21002FB24) D3A
PROJECT : ZU1 APPROVE BY : James Lu DRAWING BY:Barry Lee Stage: B/C

Quanta Computer Inc. MB ASSY'S P/N : 31ZU1MB0000 PROJECT LEADER:Kin Wang DOCUMENT NO: DATE :2006/12/09
5 4 3 2 1
5 4 3 2 1
171 Quanta DSC Team issue Base on DSC command, change CN22 P/N from DFHDF8MS000 to DFHDF4MS000 D3A 33
172 rise time of LCDVCC is >0.5ms and <=10ms. change U2 from AL004280000(AAT4280IGU-3-T1) to AL004280018(AAT4280IGU-1-T1). D3A 23
173 Card reader issue no stuff 43K(CS34302JB19):R562,R527,R533,R538,R539,R565,R561,R540,R498,R497,R500,R552,R555 D3A 23

D D
174 Card reader issue no stuff 10k(CS31002JB28) : R560 D3A 23
175 Card reader issue Change R547 from 43k (CS34302JB19) to 8.2k (CS28202JB14) D3A 23
176 Card reader issue Change R528 from 10K(CS31002JB28) to 43K(CS34302JB19) D3A 23
177 Shortage issue Change R125 from CS11003B900 (100 ohm 0.1%) to CS11003F953(100 ohm 1%) D3A 9
178 EMI issue EMI request add two of clip(FDTA1003014) in PAD17 and PAD19 for EMI issue D3A 30
179 DPST issue Acer inform no support DPST in C build, remove R15 D3A 20
180 Shortage issue Andy inform change PR116 from CS42102FB00 to CS42002FB12 D3A 34
181 ICH8M Power issue ICH8M Internal VR should not be disabled.no stuff R241, stuff R226 D3A 14
182 implement it for CPU protect in C build. Change R111 from *2.2k to 0ohm,Change R107 from 56.2(CS05622FB22) to 1k(CS21002FB24) D3A 3
183 Battery life issue. Battery life issue. Disable ICH8M Internal VR (LAN). stuff R241, no stuff R226 for C-build D3A 14
C C
184 Change EMI Spring Material ME request, change EMI Spring from FDTA1003014 to FDZU1002010 E3A 30
185 C-Test SMT open issue C-test SMT open issue, remove PAD18 E3A 30
186 ZR1 issue Change CN2 Pin define to cover production line issue(Inverter short with signal to burn system) E3A 20
187 C-Test SMT open issue Change PD9,D46 footprint from SBM1040-3P to SBM1040-3P-ZU1 for SMT C-test open issue E3A 33 & 39
188 Change NB P/N for RAMP Change U29 P/N form AJ0QP200T09 to AJSLA5T0T05 E3A 5~11
189 Change SB P/N for RAMP Change U32 P/N from AJ0QN230T10 to AJSLA5Q0T05 E3A 14~17
190 Material Lead issue Change R214 from CS02403F908 to CS02403F916 (Lead free) E3A 14
191 G995 failure rate issue Add C653 base on G995 failure rate issue E3A 3
192 Run-in auto shot down issue ICMNT connect to EC pin100 , reserve R570 0ohm for debug use, Add C654 to avoid noise E3A 28 & 39
B B
193 remove wake on lan for Mini PCIE function. Base on Acer demand, remove wake on lan for Mini PCIE function.no stuff Q25,R357 E3A 27
194 move D15~D18 location for FFC cable issue Remove footprint (D16), Remove net (HWPG_3/5VPCU),no stuff PR119 E3A 28 & 34
195 LED issue Change LED2, LED3 type base on ME request, Add R800,R801 E3A 29
196 HDD Mylar issue Change C542 from 0805(CH6102K9A01) to 0603(CH6101M9905) base on ME request(HDD Mylar issue) E3A 2
197 Docking issue Change Q4,Q5 Pin2 from +3V to +3VSUS .(Docking side pull up to +3VSUS plane) E3A 33
198 Docking issue change C451,C452 from 0.1uF (CH41002KB93) to 0 ohm (CS00002JB38)(R802,R803) E3A 33
199 Disable LAN Low Power mode Stuff R78(CS24702JB38) E3A 18
200 EOL issue Change C453 from CC1210 (CH61004M3E5) to CC1206 (CH61004M2E8) E3A 33
201 LPC CONN issue confirm with BIOS-CM, no need LPC dedug CONN,Remove CN6,R432 footprint to save space for layout. E3A 28
202 LAN_RST# issue (1)Stuff 10k for R204(2)Don't stuff R456(3)Don't stuff R247 E3A 16
A A
203 PO" sounds when insert PCMCIA card Add 0 ohm (R804) for PCMSPK E3A 22
204 ESD issue Stuff D38 for CRT port E3A 19
PROJECT : ZU1 APPROVE BY : Kin Wang DRAWING BY:Barry Lee Stage: C / Ramp
5 4 3 2 1
5 4 3 2 1
205 PCMCIA POP SOUND issue Refer to BU1, add circuit for POP sound issue E3A 24
206 GLAN issue Stuff R232 (CS02492FB29), The GLAN_COMPO/GLAN_COMPI connection to 1.5-V rail through the resistor remains E3A 14
207 ESD issue change LED type (follow B stage) DEL LED2,LED3, Add LED4~7 E3A 29
D D
208 ESD issue change ESD protect Diode from location LED/B to MB E3A 29
209 Disable LAN Low power mode Base on PM suggestion, add serial 0 ohm (R806) for debug use.(no stuff) E3A 18
210 E3A
211 E3A
212 E3A
213 E3A
214 E3A
215 E3A
216 E3A
217 E3A
C C
218 E3A
219 E3A
220 E3A
221 E3A
222 E3A
223 E3A
224 E3A
225 E3A
226 E3A
B B
227 E3A
228 E3A
229 E3A
230 E3A
231 E3A
232 E3A
233 E3A
234 E3A
235 E3A
236 E3A
A A
237 E3A
238 E3A
PROJECT : ZU1 APPROVE BY : Kin Wang DRAWING BY:Barry Lee Stage: Ramp
5 4 3 2 1

Acer TravelMate 6252 6292 - QUANTA ZU1 - REV 3B PDF

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5 4 3 2 1

ZU1 SYSTEM BLOCK DIAGRAM

DVI / 7307 CLOCK GENERATOR

S-VIDEO CONN FSB

Express Card Audio Page 36 Page 39

MDC 1.5 10/100/1G Switch 1.8V (TPS51116)

Clock Gen I2C

C2A:(12/26) Base on vendor-FCE suggestion,

C310 27P_4 CG_XIN <check list>

Clock Gen Differential IO power

C299 27P_4 CG_XOUT L26

(4)SLG8SP512 Pin 6 select Pin 17, 18 output is LCDCLK or 27 M, PD is LCDCLK, PU is 27 M ,

CPU Clock select

R440 0_4 CLK_BSEL1 0 1 1 166Mhz

R439 *0_4 0 1 0 200Mhz

+1.05V_CPU R198 *1K_4 1 1 0 400Mhz

CPU Thermal monitor

A5 C7 THERMTRIP#_PWR <check list>

Merom Ball-out Rev 1a FANPWR = 1.6*VSET

H_D#4 F23 V23 H_D#36

H_D#9 D[8]# D[40]# H_D#41 +1.05V_CPU

H_D#21 M24 AC26 H_D#53 R174

D[26]# D[58]# AE21 1 3 SYS_SHDN# 34

Merom Ball-out Rev 1a

D3A:(2/1) Change 965GM from ES sample to QS sample

Date: Tuesday, April 10, 2007 Sheet 5 of 39

MCH_RSVD1 P36 U29C +VCC_PEG

T22 CFG_8 CRT_GREEN# PEG_TX_3

11 MCH_CFG_9 C20 CFG_9 DMI_TXP_0 AJ47 DMI_RXP0 19 INT_CRT_RED

MCH_CFG_18 CFG_17 CRT_VSYNC PEG_TX_12

E35 T37 CRESTLINE_1p0

13 PM_EXTTS#1 R147 0_4 PM_EXTTS#1_R J36 E36 T41

T106 BK51 AN49 CL_RST#0 16 SDVOB_B- 21

T76 TP_MCH_NC8 BK1 .1U_4 392_6

NC_10 SDVO_CTRL_DATA SDVO_CTRLDATA 21

+1.8VSUS_GMCH R133 1K_4 SM_RCOMP_VOH

M_A_DQ33 AT13 BD20 M_A_A1 M_B_DQ33 BE11 BG28 M_B_A1

M_A_DQ46 BD7 M_B_DQ46 BJ8

Date: Tuesday, April 10, 2007 Sheet 7 of 39

VCC AXM NCTF

AC21 VCC_AXG_14 VCC_AXG_NCTF_79 AR26

AF21 BE39 VCCSM_LF3

+1.25V R120 0_6 +1.25VM_VCCA_SM AW18 B23 +1.25V_VCC_AXF .1U_4

.1U_4 22N_4 +1.05V D8 2 1 +1.05V_SD

Date: Tuesday, April 10, 2007 Sheet 10 of 39

Pin Name Strap description Configuration

CFG[2:0] FSB Frequency Select 010 = FSB 800MHz

CFG5 DMI X2 Select 0 = DMI X2

CFG7 CPU Strap 0 = Reserved

CFG8 Low power PCI Express 0 = Normal mode

CFG9 PCI Express Graphics Lane Reversal 0 = Reverse Lanes

CFG16 FSB Dynamic ODT 0 = Dynamic ODT disable

SDVO_CTRLDATA SDVO Present 0 = No SDVO Card present(Default)

CFG19 DMI Lane Reversal 0 = Normal operation(Default)

CFG20 SDVO/PCIe concurrent 0 = Only SDVO or PCIE x1 is operation(Default)

1 0 ALL-z Mode Enable

DDR2 Dual channel A/B PU

Place one cap close to every 2 pull-up resistor terminated to SMDDR_VTERM

M_A_A3 RP16 1 2 56X2 SMDDR_VTERM

M_A_A7 RP21 1 2 56X2 M_A_A8 RP20 1 2 56X2 SMDDR_VTERM

M_A_A2 RP17 1 2 56X2 RP28 1 2 56X2

M_A_A11 RP26 1 2 56X2 RP4 1 2 56X2

M_A_A12 RP24 1 2 56X2

DNBSWON# R329 10K_4 PM_LAN_ENABLE_R R456 10K_4 Q23 4.7K_4

CHN217 TC7SH08FU R577