Beruflich Dokumente
Kultur Dokumente
16-bit MCU
I/O Configuration and Functions
I/O Port Function
• Port 2: Serves as both general-purpose I/O port and reload timer I/O,
or external interrupt input
• Port 5: Serves as both general-purpose I/O port and analog input pin
• Port 2: Serves as both general-purpose I/O port and reload timer I/O, or external interrupt input
• Port 3: Serves as both general-purpose I/O port or A/D converter start trigger pin
Port Output
Pin Name Input Type Function bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Name Type
General-
P10/IN0 to
CMOS purpose I/O P17 P16 P15 P14 P13 P12 P11 P10
P13/IN3
port
Port 1
CMOS
P14/PPG0 to
high Resource PPG3 PPG2 PPG1 PPG0 IN3 IN2 IN1 IN0
P17/PPG3
current
General-
P20/TIN0 to purpose I/O P27 P26 P25 P24 P23 P22 P21 P20
Port 2 port
P27/INT7
CMOS
(hysteresis) Resource INT7 INT6 INT5 INT4 TOT1 TIN1 TOT0 TIN0
General-
P30 to p33 P36* / P35* /
purpose I/O P37 P34 P33 P32 P31 P30
Port 3 P35/X0A to X1A X0A
port
P37/ADTG
Resource ADTG − − − − − − −
CMOS General-
P40/SIN1 to purpose I/O − − − P44 P43 P42 P41 P40
Port 4 port
P44/RX
Resource − − − RX TX SOT1 SCK1 SIN1
General-
Analog/ purpose I/O P57 P56 P55 P54 P53 P52 P51 P50
P50/AN0 to port
Port 5 CMOS
P57/AN7
(hysteresis) Analog
AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
input pin
*: If the low-speed oscillation pin is selected (for MB90387 or MB90F387), P35 and P36 pins cannot be used.
Analog Input (Port 5)
R/W: Read/Write
X: Undefined value
Port 1
• Port 1 consists of the following three elements:
I/O Type
Port Circuit
Pin Name Port Function Resource
Name Type
Input Output
PDR read
Internal data bus
Output latch P ch
PDR write
Pin
Port direction register (DDR)
Direction latch N ch
DDR write
Standby control: Control of stop mode (SPL = 1), timebase timer mode (SPL = 1), and timer mode (SPL = 1)
Port
Bits of Related Registers and Corresponding Pins
Name
PDR1, DDR1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Port 1
Corresponding pin P17 P16 P15 P14 P13 P12 P11 P10
I/O Type
Port Circuit
Pin Name Port Function Resource
Name Type
Input Output
166
CHAPTER 4 I/O PORT
PDR read
Internal data bus
Output latch P ch
PDR write
Pin
Port direction register (DDR)
Direction latch N ch
DDR write
Standby control: Control of stop mode (SPL = 1), timebase timer mode (SPL = 1), and timer mode (SPL = 1)
PDR2, DDR2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Port 2
Corresponding pin P27 P26 P25 P24 P23 P22 P21 P20
Table 4.5-1 "Pin Assignment of Port 3" shows the pin assignment of port 3.
I/O Type
Port Circuit
Pin Name Port Function Resource
Name Type
Input Output
P30 P30 − −
P31 P31 − −
D
P32 P32 − −
P33 P33 General-purpose I/O − − CMOS
Port 3 CMOS
port (hysteresis)
P35/X0A P35* − − D/A
P36/X1A P36* − − D/A
External trigger input
P37/ADTG P37 ADTG D
for A/D converter
*: If the low-speed oscillation pin is selected (for MB90387 or MB90F387), P35 and P36 pins cannot be used.
171
CHAPTER 4 I/O PORT
PDR read
Internal data bus
Output latch P ch
PDR write
Pin
Port direction register (DDR)
Direction latch N ch
DDR write
Standby control: Control of stop mode (SPL = 1), timebase timer mode (SPL = 1), and timer mode (SPL = 1)
Port
Bits of Related Registers and Corresponding Pin
Name
PDR3, DDR3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Port 3
Corresponding pin P37 P36* P35* − P33 P32 P31 P30
I/O Type
Port Circuit
Pin Name Port Function Resource
Name Type
Input Output
UART1 serial
P40/SIN1 P40 SIN1
data input
UART1 serial
P41/SCK1 P41 SCK1
clock I/O
UART1 serial
P42/SOT1 P42 General- SOT1
data output CMOS
Port 4 purpose I/O CMOS D
(hysteresis)
port CAN
P43/TX P43 TX controller
send output
CAN
P44/RX P44 RX controller
receive input
176
CHAPTER 4 I/O PORT
PDR read
Internal data bus
Output latch P ch
PDR write
Pin
Port direction register (DDR)
Direction latch N ch
DDR write
Standby control: Control of stop mode (SPL = 1), timebase timer mode (SPL = 1), and timer mode (SPL = 1)
Table 4.7-1 "Pins Assignment of Port 5" shows the pin assignment of port 5.
I/O Type
Port Circuit
Pin Name Port Function Resource
Name Type
Input Output
181
CHAPTER 4 I/O PORT
Analog input
ADER
PDR read
Output latch
P ch
PDR write
Pin
DDR (port direction register)
Direction latch N ch
DDR write
Standby control: Control of stop mode (SPL = 1), timebase timer mode (SPL = 1), and timer mode (SPL = 1)
Port
Bits of Related Registers and Corresponding Pins
Name
PDR5, DDR5 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Port 5 ADER ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
Corresponding pin P57 P56 P55 P54 P53 P52 P51 P50