Department of Electrical and Computer Engineering

Abbottabad Campus

February, 2019.

Digital Logic Design

Course code: EEE-241 (3+1)

Prerequisites:

Basic Knowledge of physics and mathematics.

Course Instructor: Engr.Saima Habib.

E-mail: saimahabib@cuiatd.edu.pk

Office: DOO Office EPE

Course Catalog Description:

Introduction to Digital Computer and Systems, Number Systems, Binary Arithmetic, Boolean Algebra,
Algebraic Manipulation, Canonical and Standard Form & Conversions, Logical Operations and Gates,
Simplification of Functions, Karnaugh Map Methods, Two Level Implementations, Don’t Care Conditions,
Prime Implicants, Combinational Logic Design, Arithmetic Operations and Circuits, Analysis Procedures,
Multilevel NAND/NOR Circuits, Decoders, Encoders, Multiplexers, Demultiplexers, Memory Types, Read
Only Memory, Random Access Memory, Programmable Logic Array (PLA), Sequential Logic, Flip-Flops,
Clocked Sequential Circuits, State Machine Concept, Design of Sequential Circuits using State Machines,
Counters and their Design, Synchronous Counters, Asynchronous Counters, Shift Registers etc.

Textbook(s):

1. Digital design with an introduction to the Verilog HDL by M. Morris Mano and Michael D. Ciletti.

2. M. Morris Mano & Charles R. Kime, Logic and Computer Design Fundamentals (2nd Edition Updated,
Prentice Hall, 2000)

Reference Books
1. Thomas L. Floyd, Digital Fundamentals (7th Edition)

Course Learning Objectives:

1. The students will develop the ability to design both combinational and sequential digital logic circuits.

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Course Learning Outcomes (CLO):

After successfully completing the course, the students will be able to:

1. Describe number system, basic logic gates, Boolean algebra and basic properties of Boolean
algebra. (C1-PLO1)
2. Explain the correlation between Boolean expression and their corresponding logic diagrams. (C2-
PLO1)
3. Simplify logics using basic Boolean properties and Karnaugh Maps. (C3-PLO1)
4. Design combinational circuits (C5-PLO3)
5. Realize basic sequential circuit and perform analysis of Sequential logic circuits using different
types of flip-flops (C4-PLO2)
6. Illustrate and design sequential components used in typical digital Systems: Registers,
Shifters, counters, RAM, ROM etc. (C5-PLO3)
Learning Outcomes Assessment plan
Sr. Course Learning Outcomes [CLOs] Assessment
#
1. CLO1, CLO2 Assignment No. 1
2. CLO1, CLO2 Quiz No. 1
3. CLO1, CLO2, CLO3 Sessional No. 1
4. CLO4 Assignment No. 2
5. CLO4 Quiz No. 2
6. CLO5 Assignment No. 3
7. CLO5 Quiz No. 3
8. CLO4, CLO5 Sessional No. 2
9. CLO6 Assignment No. 4
10. CLO6 Quiz No. 4
11. CLO1-CLO6 Terminal Examination
Table 1 - Assessment Plan for Learning Objectives

Course Learning Outcomes mapped to Standard Program Learning Outcomes:

CLOs\PLOs
PLO10

PLO11

PLO12
PLO1

PLO2

PLO3

PLO4

PLO5

PLO6

PLO7

PLO8

PLO9

CLOs
CLO1 C1

CLO2 C2
CLOs C3
CLO3

CLO4 C5

CLO5 C4

CLO6 C5

Table 2: Mapping CLOs to PLOs

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Assessment Plan:

Theory Quizzes (4) 15%

Homework assignments 10%
2 Sessional exams (in class, 60-80 minutes each, 25%
(10%+15%)
Terminal exam (3 hours) 50%
Total (theory) 100
%
Lab work Lab reports (12) 25%
2 Lab sessionals 25%
Lab project and terminal exam 50%
Total (lab) 100
%
Final marks Theory marks * 0.75 + Lab marks * 0.25

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Course Outline: Tentative Lecture breakdown (32 Lectures)

Topics No. of
Week
Lectures
Digital Computers and Information

 Digital computers and Binary Numbers

1  Other base numbers (base-8, base-16 etc.) 2
 Number base conversions
 1’s and 2’s Complements
 Unsigned and Signed numbers and Arithmetic operations (Addition,
subtraction, Multiplication and Division)
COMBINATIONAL LOGIC CIRCUITS

 Binary Logic and Introduction to Logic Gates

 Timing Diagrams
 Introduction to Boolean Algebra
2,3,4  Standard forms
 Boolean Functions and their implementation
6
 Canonical and Standard Forms (Minterms, Maxterms, Conversions)
 Minimization of Boolean functions using K-Map
 Don't Care States
 Universal gates and implementation of Boolean functions using
universal gates
COMBINATIONAL LOGIC DESIGN

 Combinational Circuits
5,6,7  Design Procedure
 Decoders
6
 Encoders
 Multiplexers / Demultiplexer
 Binary Adders (Half Adder, Full Adders, Binary Ripple Carry Adder.
COMBINATIONAL LOGIC DESIGN

8  Binary Subtractor
 Binary Adder/Subtractor 2
 Code Conversion
 Magnitude Comparator
 Parity Generators/ Checkers
SEQUENTIAL CIRCUITS

 Introduction to Sequential Circuits

 Introduction to Latches
 Introduction to Flip Flops
9,10,11,12 8
 Type of Flip Flops
 Analysis of Sequential Circuits
 Design Procedures
 Introduction to develop state diagram and state table
 State reduction excitation tables

REGISTERS AND COUNTERS

13,14,15  Registers 4
 Counters
 Synchronous/Asynchronous
 Shift Registers

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 MEMORY AND PROGRAMMABLE LOGIC DEVICES

 Read-Only Memories
16  Programmable Logic Array Devices 2
 Random Access Memory
 Static and Dynamic RAM
 Memory construction using RAM Integrated Circuits