CPU....

Instruction set Architecture

ISA Based on instruction type
 Reduced Instruction Set Computer
>> Uses simple instructions
>>Operands are assumed to be in processor
registers
- Not in memory
-Simplifies design
>> Only load/store instructions can access memory
- Fixed instruction size
 Complex Instruction Set Computer
>>Uses complex instructions
>>Many different addressing modes
>>Operands can be in registers or memory
 Instruction size varies

 Typically uses a microprogram

 Cont'd..
.
 Cont'd..
 Variations of the ISA-level can be implemented by changing the
microprogram
 RISC vs CISC
CISC -- High Code Density
Fewer instructions needed to specify the algorithm
RISC -- Simpler to Design & Faster to Silicon
Higher Performance -- smaller die size
Lower power consumption
Easier to develop compilers to take advantage of all
features
 Examples

.
Intel: 80x86
CISC
Motorola: 680x0
Sun : Sparc
Silicon Graphics :MIPS
HP : PA-RISC
IBM: Power PC
Compaq: Alpha RISC
 Why CISC still lives?

 Why are there still CISC CPUs being developed?

 Why is Intel spending time and money to manufacture the Pentium III
and Pentium 4?

Answer

The answer is simple, backward compatibility.

The IBM compatible PC is the most common computer in the world. Intel
wanted a CPU that would run all the applications that are in the hands of
more than 100 million users.
 Hybrid CISC-RISC
Up till the mid 1990s, processor designers were split into two
opposing camps.
One side supported CISC designs due to its low burden on
compiler developers and wide availability of existing software.
The other camp supported RISC designs because of its
simplicity and efficiency.
However, the CISC vs. RISC debate has now died down as
contemporary processor designers realize that RISC designs
might benefit from the addition of some CISC characteristics
and vice-versa.
 Hybrid CISC-RISC ...
.
 Today, most CISC processors are based on hybrid CISC-RISC
architecture.
 These designs use a decoder to convert CISC instructions into
RISC instructions before execution. They are then processed
by a RISC core, which performs a few basic instructions very
quickly.
 Having a RISC core is advantageous because it allows
performance enhancing features, such as pipelining and
branch prediction.
 Popular examples of hybrid designs include the Pentium and
Athlon family of processors. These processors are
compatible with software written for their CISC predecessors
yet perform competitively against processors based on RISC
designs.
 Hybrid CISC-RISC ...
RISC and CISC: The Best Of Both Worlds

(AltiVec unit adds 162 new instructions to the existing RISC architecture)