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Digital System Design

Lecture 3: ASIC Design

Amir Masoud Gharehbaghi


amgh@mehr.sharif.edu
Table of Contents

{ Microelectronic Industry
{ Rapid Prototyping
{ ASIC Design

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Microelectronics Market

{ Primary Market
z Information Systems
z Telecommunications
z Consumer
{ Secondary Market
z Systems (e.g. Transportation)
z Manufacturing (e.g. Robots)

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Electronic Market
Systems

Electronic Sub-Systems

Integrates Circuits

EDA

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Trends in Microelectronics

{ Improvement in Device Technology


z Smaller Circuits
z Higher Performance
z More Devices on a Chip
{ Higher Degree of Integration
z More Complex Systems
z Lower Cost
z Higher Reliability

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Moore’s Law
{ Every 18 Months:
z Gate Count Doubles
z Frequency Increases 50%

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Integration-Scale Limitations

{ Intrinsic physical scaling limits


{ Capital investment for fabrication
z Use of appropriate design styles
{ Large-scale design management
z Use of CAD tools for design

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Microelectronic Design Problems

{ Use most recent technologies


z Higher performance
{ Reduce design cost
z Lower price
{ Speedup design time
z Shorten time-to-market

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Rapid Prototyping

{ Prototype:
z The original or model on which
something is based or formed
z Something that serves as an example
of its kind
{ Rapid:
z Occurring within a short time
z Happening Speedily

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Why Rapid Prototyping?
{ Avoid high non-recurring engineering (NRE) costs
{ Avoid long construction time for "real" system
{ Reduced time allowed from concept to product
{ Can quickly react to changing customer
environment or requirements
{ Systems are too complex to simulate real-world
operation in "bounded" time (need to build to
test)
{ Customers won’t put up with unreliable products
{ Sometimes the prototype is the product

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Why Not Rapid Prototyping?
{ Not the same performance as final
product (slower)
{ Not the same size as final product
(bigger or more ICs required)
{ Prototype more expensive than final
production unit
{ More design time required to complete
engineering of both prototype and final
system

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VLSI Market

ASIC
Application Specific
Integrated Circuits
ASSP
Application Specific
Standard Part
Standard (Commodity) Part

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Implementation Technologies

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ASIC
{ Dedicated to single function, or limited
range of functions
{ Not ASIC:
z CPUs, Microprocessors
z Memories: DRAM, SRAM, ROM, …
z Standard Components (e.g. 74 Series)
{ ASIC:
z Toy Chips
z Mpeg Decoder/Encoder ICs
z DSP Processors

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Design Aspects
{ Shorter product life-time
z Shorter time-to-market
z More parallel design flow
z Better communication between
different design groups

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Design Aspects (cont.)
{ More complex systems
z More efficient design methods need to
be used
z Design automation is a necessity
z More tool-dependant design and
optimization
z More difficult to ensure correct functionality

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Design Aspects (cont.)
{ Not fixed system specification when
starting the design entry
z More emphasis on high level design aspects
z Flexible and very rapid design flow
z Easy testability through the whole design
flow

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Structures ASIC Design
{ Hierarchy: Subdivide the design into
many levels of sub-modules
{ Regularity: Subdivide to max number of
similar sub-modules at each level
{ Modularity: Define sub-modules
unambiguously & well defined interfaces
{ Locality: Max local connections, keeping
critical paths within module boundaries

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ASIC vs. Standard IC
Standard IC ASIC
{ Typically low { Good security of intellectual
component cost property
{ Parts available off the { Optimum system design
shelf { Relatively efficient use of board
{ Low or insignificant IC space (smaller systems)
design cost { Reliability enhanced at system level
{ Proven component (fewer components)
reliability { Performance may be better than
{ Multiple sourcing comparable standard ICs (unique
{ System house not features and lower power
required to have in- consumption)
house experts in chip { Possibility to optimize component cost
design { Design cost is high and design cycle
is long

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ASICs
Advantages Disadvantages
{ Efficient use of board { Potential for design
space (lower final failure
system cost) { Not off-the-shelf
{ Product security available
{ Unique features and (specification, design,
fine-tuning the testing and
product documentation phases
{ Optimized system are needed)
performance { High unit cost of IC
(higher initial costs of
development)

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Types of ASIC

{ Full Custom
{ Semi Custom
z Cell based
z Gate Array
{ Programmable Logic
z FPGA (Field Programmable Gate Array)
z PLD (Programmable Logic Device)

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Full Custom ASICs
{ Some (or all) logic cells are customized
z Demands longer design cycle
{ All mask layers are customized
{ Involves an implementation of a
completely new chip
{ Designer must be an expert in VLSI
design
{ It is used when:
z existing cell libraries are not fast enough
z logic cells not small enough or consume too
much power
z technology migration (mixed-mode design)

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Examples of Full Custom ICs

{ Analog (e.g. Sensor, Actuator)


{ Mixed Analog/Digital (e.g.
Telecommunication)
{ High Voltage (e.g. Automobile)
{ Low Power (e.g. PDA, Mobile)

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Cell Based ASICs
{ Use predesigned logic cells (standard
cells) in combination with larger cells
(megacells)
{ Standard Cells
z Primitive Gates (and, or, …)
z Multiplexers
z Registers
{ Mega cells (full-custom blocks, system-
level macros, fixed blocks, cores,
functional standard blocks, or IP)
z Microcontrollers, Microprocessor, MPEG
decoder
z RAM, ROM

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Cell Based ASICs (cont.)

{ Designers save time, money, and


reduce risk
{ Each standard cell can be optimized
individually
{ All mask layers are customized
{ Custom blocks can be embedded

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Gate Array Based ASICs
{ Gate array (or prediffused array)
z Transistors are predefined on the silicon wafer
z Base array: the predefined pattern of transistors
z Base cell: the smallest element that is replicated to
make the base array
{ Masked gate array (MGA)
z Only the top few layers of metal are defined by the
designer using custom masks
z The designer chooses from a gate-array library of
predesigned logic cells (macros)
{ Types of MGA ASICs
z Channeled gate arrays
z Channel-less gate arrays
z Structured gate arrays

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Channeled Gate Array
{ Only the
interconnect is
customized
{ The interconnect
uses predefined
spaces between
rows of base cells

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Channel-less Gate Arrays

{ Also known as
sea-of-gate
(SOG)
{ only some mask
layers are
customized- the
interconnect

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Structured Gate Array
{ Combine some of
the features of
CBICs (Cell-Based
ICs) and MGAs
{ Only the
interconnect is
customized
{ Custom blocks can
be embedded

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