SR FLIPFLOP

module srff(s,r,q,clk,reset );
input s,r,clk,reset;
output reg q=0;
always@(posedge clk)
begin
if(reset)
q=0;
else if(s==1)
q=1;
else if(s==0)
q=0;
else if(s==0 && r==0)
q=q;
else if(s==1 && r==1)
q=1'bz;
end
endmodule

testbench:
module tb_srff;

// Inputs
reg s;
reg r;
reg clk=0;
reg reset=0;

// Outputs
wire q;

// Instantiate the Unit Under Test (UUT)

srff uut (
.s(s),
.r(r),
.q(q),
.clk(clk),
.reset(reset)
);

initial begin
// Initialize Inputs
s = 0;
r = 0;

// Wait 100 ns for global reset to finish

#100;
s = 1;
r = 0;

// Wait 100 ns for global reset to finish

#100;
s = 1;
r = 1;

// Wait 100 ns for global reset to finish

 #100;
s = 0;
r = 1;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

end
always begin
#50 clk=~clk;
end
endmodule

T FLIPFLOP
module tff(q,t,reset,clk );
input t,clk,reset;
output reg q=0;
always@(posedge clk or posedge reset)
begin
if (reset)
q=0;
else if(t==1)
q=~q;
else if(t==0)
q=q;
end
endmodule

testbench:

module tb_tff;

// Inputs
reg t;
reg reset=0;
reg clk=0;

// Outputs
wire q;

// Instantiate the Unit Under Test (UUT)

tff uut (
.q(q),
.t(t),
.reset(reset),
.clk(clk)
);

initial begin
// Initialize Inputs
t <= 0;

// Wait 100 ns for global reset to finish

#100;
 t <= 1;
// Wait 100 ns for global reset to finish
#100;
t <= 0;

// Wait 100 ns for global reset to finish

#100;
// Add stimulus here
t <= 1;
// Wait 100 ns for global reset to finish
#100;
end
always begin
#50 clk=~clk; end;
endmodule

JK FLIPFLOP
module jkff(q,j,k,clk,reset);
output reg q=0;
input j,k,reset,clk;
always@(posedge clk or posedge reset)
begin
if(reset)
q=0;
else if(j==0&&k==0)
q=q;
else if(j==1&&k==1)
q=~q;
else if(j==1)
q=1;
else if(j==0)
q=0;
end
endmodule

testbench:
module tb_jkff;

// Inputs
reg j;
reg k;
reg clk=0;
reg reset=0;

// Outputs
wire q;

// Instantiate the Unit Under Test (UUT)

jkff uut (
.q(q),
.j(j),
.k(k),
.clk(clk),
.reset(reset)
);
initial begin
// Initialize Inputs
j <= 0;
k <= 0;
 // Wait 100 ns for global reset to finish
#100;
j <= 1;
k <= 1;

// Wait 100 ns for global reset to finish

#100;
j <= 0;
k<= 1;

// Wait 100 ns for global reset to finish

#100;
j <= 1;
k <= 0;

// Wait 100 ns for global reset to finish

#100;
// Add stimulus here
end
always begin
#50; clk=~clk; end;

endmodule

D FLIPFLOP
module dff(d,q,clk,reset);
input d,clk,reset;
output reg q;
initial q=0;
always@(posedge clk or reset)
if(reset)
q=0;
else
casex(d)
0: q=1'b0;
1: q=1'b1;
default : q=1'bz;
endcase

endmodule

testbench:
module tb_dff;

// Inputs
reg d;
reg clk=0;
reg reset=0;

// Outputs
wire q;

// Instantiate the Unit Under Test (UUT)

dff uut (
 .d(d),
.q(q),
.clk(clk),
.reset(reset)
);

initial begin
// Initialize Inputs
d = 0;
reset=0;
#100;
d=1;
#10;
reset=0;
#100;

d=1;
reset=1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here

end
always begin
#20 clk=~clk; end
endmodule

UNIVERSAL SHIFT REGISTER

module usr(in,out,clk,reset,r,l,s );
input reset, r, l,clk;
input [3:0]in;
input [1:0]s;
output reg[3:0]out;
always@(posedge clk)
if(reset)
out<=4'b0000;
else
casex(s)
2'b01: out<={r,in[3:1]};
2'b10: out<={in[2:0],l};
2'b11: out<=in;
default: out<=4'bxxxx;
endcase
endmodule

testbench:
module tb_usr;

// Inputs
reg [3:0] in;
reg clk=0;
reg reset=0;
reg r;
reg l;
reg [1:0] s;
 // Outputs
wire [3:0] out;

// Instantiate the Unit Under Test (UUT)

usr uut (
.in(in),
.out(out),
.clk(clk),
.reset(reset),
.r(r),
.l(l),
.s(s)
);

initial begin
// Initialize Inputs
in =4'b1011 ;
r = 0;
l = 0;
// Wait 100 ns for global reset to finish
#100;
in =4'b1111 ;
r = 0;
l = 0;
s = 2;

// Wait 100 ns for global reset to finish

#100;

in =4'b1111 ;
r = 0;
l = 0;
s = 1;

// Wait 100 ns for global reset to finish

#100;
in =4'b1111 ;
reset=1;

// Wait 100 ns for global reset to finish

#100;
// Add stimulus here

end
always begin
#5 clk=~clk;
end
endmodule

PRIORITY ENCODER
module pencoder(a,b );
input [7:0]a;
output reg[2:0]b;
always@(*)
casex(a)
8'b00000001: b=3'b000;
8'b0000001x: b=3'b001;
8'b000001xx: b=3'b010;
8'b00001xxx: b=3'b011;
8'b0001xxxx: b=3'b100;
8'b001xxxxx: b=3'b101;
8'b01xxxxxx: b=3'b110;
8'b1xxxxxxx: b=3'b111;
default b=2'bzz;
endcase
endmodule

____PRIORITY ENCODER TESTBENCH

module tb_pencoder;

// Inputs
reg [7:0] a;

// Outputs
wire [2:0] b;

// Instantiate the Unit Under Test (UUT)

pencoder uut (
.a(a),
.b(b)
);

initial begin
// Initialize Inputs
a = 11001001;

// Wait 100 ns for global reset to finish

#100;
a = 11000100;

// Wait 100 ns for global reset to finish

#100;a = 11001010;

// Wait 100 ns for global reset to finish

#100;a = 11010000;

// Wait 100 ns for global reset to finish

#100;
// Add stimulus here

end

endmodule

4BIT UPDOWN COUNTER

module counter_4bit_updown(in,out,c,reset,clk);
input c,reset,clk;
input [3:0]in;
output reg[3:0]out;
initial out<=4'b0000;
always@(posedge clk)
if(reset)
out<=4'b0000;
else if(!c)
out<=out+1;
else if(c)
out<=out-1;
endmodule

_____4BIT UPDOWN TESTBENCH

module tb_counter_4bit_updown;

// Inputs
reg [3:0] in;
reg c;
reg reset=0;
reg clk=0;

// Outputs
wire [3:0] out;

// Instantiate the Unit Under Test (UUT)

counter_4bit_updown uut (
.in(in),
.out(out),
.c(c),
.reset(reset),

.clk(clk)
);

initial begin
// Initialize Inputs
in = 0;
c = 0;
// Wait 100 ns for global reset to finish
#96;
in=0;
c=1;
#96 $stop;
// Add stimulus here

end
always begin
#3 clk=~clk;
end
endmodule