Beruflich Dokumente
Kultur Dokumente
3 MOSFET Model
Users’Manual
Copyright © 2005
The Regents of the University of California
All Rights Reserved
Developers:
Technical Support:
Dr. Xuemei (Jane) Xi: janexi@eecs.berkeley.edu
Acknowledgment:
Special acknowledgment goes to Dr. Josef Watts, chair of CMC, Dr. Keith
Green, former Chairman of the Technical Issue Subcommittee of CMC;
and Bhaskar Gadepally, Britt Brooks, former chairs of CMC.
• Chapter 2 discusses the physical basis used to derive the I-V model.
• Chapter 3 highlights a single-equation I-V model for all operating regimes.
• Chapter 4 presents C-V modeling and focuses on the charge thickness model.
• Chapter 5 describes in detail the restrutured NQS (Non-Quasi-Static) Model.
• Chapter 6 discusses model parameter extraction.
• Chapter 7 provides some benchmark test results to demonstrate the accuracy
and performance of the model.
First, if the gate voltage is greater than the threshold voltage, the inversion charge
density is larger than the substrate doping concentration and MOSFET is operating
in the strong inversion region and drift current is dominant. Second, if the gate
voltage is smaller than Vth, the inversion charge density is smaller than the
substrate doping concentration. The transistor is considered to be operating in the
weak inversion (or subthreshold) region. Diffusion current is now dominant [2].
Lastly, if the gate voltage is very close to Vth , the inversion charge density is close
to the doping concentration and the MOSFET is operating in the transition region.
In such a case, diffusion and drift currents are both important.
For MOSFET’s with long channel length/width and uniform substrate doping
concentration, Vth is given by [2]:
(2.1.1)
(
Vth =VFB + Φs +γ Φs −Vbs =VTideal +γ Φs −Vbs − Φs )
where VFB is the flat band voltage, VTideal is the threshold voltage of the long
channel device at zero substrate bias, and γ is the body bias coefficient and is given
by:
(2.1.2)
2ε siqN a
γ =
Cox
where Na is the substrate doping concentration. The surface potential is given by:
(2.1.3)
k BT N a
Φs = 2 ln
q ni
Equation (2.1.1) assumes that the channel is uniform and makes use of the one
dimensional Poisson equation in the vertical direction of the channel. This model
is valid only when the substrate doping concentration is constant and the channel
length is long. Under these conditions, the potential is uniform along the channel.
Modifications have to be made when the substrate doping concentration is not
uniform and/or when the channel length is short, narrow, or both.
Nch
Nsub
In order to take into account such non-uniform substrate doping profile, the
following Vth model is proposed:
(2.1.4)
(
Vth = VTideal + K1 Φ s − Vbs − Φ s − K 2Vbs )
For a zero substrate bias, Eqs. (2.1.1) and (2.1.4) give the same result. K1
and K2 can be determined by the criteria that Vth and its derivative versus
Vbs should be the same at Vbm , where Vbm is the maximum substrate bias
voltage. Therefore, using equations (2.1.1) and (2.1.4), K1 and K2 [3] will
be given by the following:
(2.1.5)
K 1 = γ 2 − 2 K 2 Φ s − Vbm
(2.1.6)
(γ 1 − γ 2 )( Φ s − Vbx − Φ s )
K2 =
2 Φs ( )
Φ s − Vbm − Φ s + Vbm
where γ1 and γ2 are body bias coefficients when the substrate doping
concentration are equal to Nch and Nsub , respectively:
(2.1.7)
2qε si N ch
γ1 =
Cox
(2.1.8)
2qε si N sub
γ2 =
Cox
Vbx is the body bias when the depletion width is equal to Xt. Therefore, Vbx
satisfies:
(2.1.9)
2
qN ch X t
= Φ s − Vbx
2ε si
(2.1.10)
Na ( L − 2Lx ) + Npocket⋅ 2Lx 2L Npocket− Na
N eff = = Na 1+ x ⋅
L L Na
Nlx
≡ Na ⋅ 1+
L
(2.1.11)
Vth = Vth 0 + K1 ( )
Φ s − V bs − Φ s − K 2Vbs
Nlx
+ K1 1 + − 1 Φ s
Leff
Eq. (2.1.11) can be derived by setting Vbs = 0, and using K1 ∝ (Neff) 0.5. The
fourth term in Eq. (2.1.11) is used to model the body bias dependence of
the lateral non-uniform doping effect. This effect gets stronger at a lower
body bias. Examination of Eq. (2.1.11) shows that the threshold voltage
will increase as channel length decreases [3].
Npocket Npocket
N(x)
Na
Lx Lx
(2.1.12)
( )
Vth = Vth 0 + K1 Φ s − V bs − Φ s − K 2Vbs
Nlx
+ K1 1 + − 1 Φ s − ∆V th
Leff
where ∆Vth is the threshold voltage reduction due to the short channel
effect. Many models have been developed to calculate ∆Vth. They used
either numerical solutions [4], a two-dimensional charge sharing approach
[5,6], or a simplified Poisson's equation in the depletion region [7-9]. A
simple, accurate, and physical model was developed by Z. H. Liu et al.
[10]. Th is model was derived by solving the quasi 2D Poisson equation
along the channel. This quasi-2D model concluded that:
(2.1.13)
∆Vth = θ th ( L)(2(Vbi − Φ s ) + Vds )
where Vbi is the built-in voltage of the PN junction between the source and
the substrate and is given by
(2.1.14)
K T N N
Vbi = B ln( ch 2 d )
q ni
(2.1.15)
θ th ( L ) = [exp ( − L 2lt ) + 2 exp ( − L lt )]
(2.1.16)
ε si Tox X dep
lt =
ε ox η
(2.1.17)
2ε si (Φ s − Vbs )
X dep =
qN ch
Xdep is larger near the drain than in the middle of the channel due to the
drain voltage. Xdep / η represents the average depletion width along the
channel.
Dsub, Eta0 and Etab are introduced, and the following modes are used to
account for charge sharing and DIBL effects separately.
(2.1.18)
θ th ( L ) = Dvt 0 [exp( − D vt 1 L / 2l t ) + 2 exp( − Dvt 1 L / l t )]
(2.1.19)
∆Vth (L) = θ th (L)(Vbi − Φ s )
(2.1.20)
ε si Tox X dep
lt = (1 + Dvt 2Vbs )
ε ox
(2.1.21)
θ dibl ( L ) = [exp( − Dsub L / 2 lt 0 ) + 2 exp( − D sub L / lt 0 )]
(2.1.22)
∆Vth(Vds) = θdibl ( L)(Eta0 + EtabVbs)Vds
As channel length L decreases, ∆Vth will increase, and in turn Vth will
decrease. If a MOSFET has a LDD structure, Nd in Eq. (2.1.14) is the
doping concentration in the lightly doped region. Vbi in a LDD-MOSFET
will be smaller as compared to conventional MOSFET’s; therefore the
threshold voltage reduction due to the short channel effect will be smaller
in LDD-MOSFET’s.
As the body bias becomes more negative, the depletion width will increase
as shown in Eq. (2.1.17). Hence ∆Vth will increase due to the increase in lt.
The term:
will also increase as Vbs becomes more negative (for NMOS). Therefore,
the changes in
and in ∆Vth will compensate for each other and make Vth less sensitive to
Vbs. This compensation is more significant as the channel length is
shortened. Hence, the Vth of short channel MOSFET’s is less sensitive to
body bias as compared to a long channel MOSFET. For the same reason,
the DIBL effect and the channel length dependence of Vth are stronger as
Vbs is made more negative. This was verified by experimental data shown
in Figure 2-3 and Figure 2-4. Although Liu et al. found an accelerated Vth
roll-off and non-linear drain voltage dependence [10] as the channel
became very short, a linear dependence of Vth on Vd s is nevertheless a good
approximation for circuit simulation as shown in Figure 2-4. This figure
shows that Eq. (2.1.13) can fit the experimental data very well.
Furthermore, Figure 2-5 shows how this Vth model can fit various channel
lengths under various bias conditions.
Figure 2-3. Threshold voltage versus the drain voltage at different body biases.
The actual depletion region in the channel is always larger than what is
usually assumed under the one-dimensional analysis due to the existence of
fringing fields [2]. This effect becomes very substantial as the channel
width decreases and the depletion region underneath the fringing field
becomes comparable to the "classical" depletion layer formed from the
vertical field. The net result is an increase in Vth. It is shown in [2] that this
increase can be modeled as:
(2.1.23)
πqN a X d max 2 T
= 3π o x Φ s
2 Co xW W
The right hand side of Eq. (2.1.23) represents the additional voltage
increase. This change in Vth is modeled by Eq. (2.1.24a). This formulation
includes but is not limited to the inverse of channel width due to the fact
that the overall narrow width effect is dependent on process (i.e. isolation
technology) as well. Hence, parameters K3 , K3b , and W 0 are introduced as
(2.1.24a)
Tox
( K3 + K 3bVbs ) Φs
Weff '+W0
Weff ’is the effective channel width (with no bias dependencies), which
will be defined in Section 2.8. In addition, we must consider the narrow
width effect for small channel lengths. To do this we introduce the
following:
(2.1.24b)
'
Weff Leff Weff Leff
'
When all of the above considerations for non-uniform doping, short and
narrow channel effects on threshold voltage are considered, the final
complete Vth expression implemented in SPICE is as follows:
(2.1.25)
Vth = Vth0ox + K1ox ⋅ Φs −Vbseff − K2oxVbseff
Nlx
−1 Φs + (K3 + K3bVbseff) ox Φ s
T
+ K1ox 1 +
Leff Weff '+W0
Weff ' Leff W ' L
− DV T0w exp − DV T1w + 2 exp− DV T1w eff eff (Vbi − Φs )
2ltw ltw
L L
− DV T0 exp − DV T1 eff + 2exp− DV T1 eff (Vbi − Φs )
lt
2lt
Leff Leff
− exp− Dsub + 2exp− Dsub (Etao + EtabVbseff )Vds
2lto lto
Vth0ox =Vth0 − K1 ⋅ Φs
and
Tox
K1ox = K1 ⋅
Toxm
Tox
K2 ox = K2 ⋅
Toxm
Toxm is the gate oxide thickness at which parameters are extracted with a
default value of Tox .
In Eq. (2.1.25), all Vbs terms have been substituted with a Vbseff expression
as shown in Eq. (2.1.26). This is done in order to set an upper bound for the
body bias value during simulations since unreasonable values can occur if
this expression is not introduced (see Section 3.8 for details).
(2.1.26)
Vbseff = Vbc + 0.5[Vbs − Vbc − δ 1 + (Vbs − Vbc − δ 1) − 4δ 1Vbc ]
2
(2.2.1)
Q + ( Qn 2 )
Eeff = B
ε si
The physical meaning of Eeff can be interpreted as the average electrical field
experienced by the carriers in the inversion layer [14]. The unified formulation of
mobility is then given by
(2.2.2)
µ0
µ eff =
1 + ( Eeff E0 ) ν
Values for µ 0, E0 , and ν were reported by Liang et al. [15] and Toh et al. [16] to be
the following for electrons and holes
For an NMOS transistor with n-type poly-silicon gate, Eq. (2.2.1) can be rewritten
in a more useful form that explicitly relates Eeff to the device parameters [14]
(2.2.3)
Vgs + Vth
Eeff ≅
6 Tox
Eq. (2.2.2) fits experimental data very well [15], but it involves a very time
consuming power function in SPICE simulation. Taylor expansion Eq. (2.2.2) is
used, and the coefficients are left to be determined by experimental data or to be
obtained by fitting the unified formulation. Thus, we have
(mobMod=1) (2.2.4)
µo
µeff = Vgst + 2Vth
gsteff gsteff + 2V th 2
VVgst
1 + (U a + U c Vbseff )( ) + U b( )
TOX TOX
(mobMod=2) (2.2.5)
µo
µeff =
Vgsteff V gsteff
1 + (U a + UcVbseff )( gst ) + U b ( gst ) 2
TOX TOX
The unified mobility expressions in subthreshold and strong inversion regions will
be discussed in Section 3.2.
To consider the body bias dependence of Eq. 2.2.4 further, we have introduced the
following expression:
(2.3.1)
µ eff E
v= , E < Esat
1 + ( E Esat )
= vsat , E > Esat
The parameter Esat corresponds to the critical electrical field at which the carrier
velocity becomes saturated. In order to have a continuous velocity model at E =
Esat, Esat must satisfy:
(2.3.2)
2 vsat
Esat =
µ eff
The parameter, Abulk, is used to take into account the bulk charge effect. Several
extracted parameters such as A0, B0, B1 are introduced to account for the channel
length and width dependences of the bulk charge effect. In addition, the parameter
Keta is introduced to model the change in bulk charge effect under high substrate
bias conditions. It should be pointed out that narrow width effects have been
considered in the formulation of Eq. (2.4.1). The Abulk expression is given by
(2.4.1)
2
K1ox A0Leff Leff B0 1
Abulk = 1 + 1 − AgsVgsteff W '+B ⋅ 1 + KetaV
+
Φ − + +
2 Vbseff eff
L 2 X X L
eff 2 X X dep 1
eff bseff
s J dep J
where A0, Ags , B0, B1 and Keta are determined by experimental data. Eq. (2.4.1)
shows that Abulk is very close to unity if the channel length is small, and Abulk
increases as channel length increases.
In the strong inversion region, the general current equation at any point y
along the channel is given by
(2.5.1)
I ds = WC ox (Vgst − AbulkV ( y )) v ( y )
The parameter Vgst = (Vgs - V th), W is the device channel width, Cox is the
gate capacitance per unit area, V(y) is the potential difference between
minority-carrier quasi-Fermi potential and the equilibrium Fermi potential
in the bulk at point y, v(y) is the velocity of carriers at point y.
With Eq. (2.3.1) (i.e. before carrier velocity saturates), the drain current
can be expressed as
(2.5.2)
µ eff E ( y )
I ds = WC ox (V gs − Vth − AbulkV ( y ))
1 + E ( y ) E sat
(2.5.3)
I ds dV ( y )
E (y) = =
µ eff WC ox (V − AbulkV ( y ) ) − I ds E sat dy
gst
(2.5.4)
W 1
I ds = µ eff Cox (V gs − Vth − Abulk Vds 2)Vds
L 1 + Vds E sat L
The drain current model in Eq. (2.5.4) is valid before velocity saturates.
For instances when the drain voltage is high (and thus the lateral electrical
field is high at the drain side), the carrier velocity near the drain saturates.
The channel region can now be divided into two portions: one adjacent to
the source where the carrier velocity is field-dependent and the second
where the velocity saturates. At the boundary between these two portions,
the channel voltage is the saturation voltage (Vdsat) and the lateral
electrical is equal to Esat . After the onset of saturation, we can substitute v
= vsat and Vds = Vdsat into Eq. (2.5.1) to get the saturation current:
(2.5.5)
I ds = WC ox (V gst − AbulkVdsat ) v sat
By equating eqs. (2.5.4) and (2.5.5) at E = Esat and Vds = Vdsat , we can
solve for saturation voltage Vdsat
(2.5.6)
E sat L(Vgs − Vth )
Vdsat =
AbulkE sat L + (Vgs − Vth )
(2.5.9)
V ds V ds
I ds = =
R tot R ch + R ds
W 1 ( V gst − A bulk V ds 2 ) V ds
= µ eff C ox
L 1 + V ds ( E sat L ) W ( V gst − A bulk V ds 2 )
1 + R ds µ eff C ox
L 1 + V ds ( E sat L )
Due to the parasitic resistance, the saturation voltage Vdsat will be larger
than that predicted by Eq. (2.5.6). Let Eq. (2.5.5) be equal to Eq. (2.5.9).
Vdsat with parasitic resistance Rds becomes
(2.5.10)
− b − b2 − 4 ac
Vdsat =
2a
(2.5.11)
1
a = Abulk
2
Rds C ox Wvsat + ( − 1) A bulk
λ
2
b = −(Vgst ( − 1) + Abulk Esat L + 3 Abulk Rds Cox Wvsat Vgst )
λ
c = Esat LVgst + 2 Rds Cox Wvsat Vgst 2
λ = A1V gst + A 2
(2.5.11)
Rds =
( (
Rdsw 1 + PrwgVgsteff + Prwb Φ s − Vbseff − Φ s ))
(10 W ')
6
eff
Wr
The variable Rdsw is the resistance per unit width, Wr is a fitting parameter,
Prwb and Prwg are the body bias and the gate bias coeffecients, repectively.
curve can be clearly divided into four regions with distinct Rout vs. Vds
dependences.
The first region is the triode (or linear) region in which carrier velocity is not
saturated. The output resistance is very small because the drain current has a strong
dependence on the drain voltage. The other three regions belong to the saturation
region. As will be discussed later, there are three physical mechanisms which
affect the output resistance in the saturation region: channel length modulation
(CLM) [4, 14], drain-induced barrier lowering (DIBL) [4, 6, 14], and the substrate
current induced body effect (SCBE) [14, 18, 19]. All three mechanisms affect the
output resistance in the saturation range, but each of them dominates in only a
single region. It will be shown next that channel length modulation (CLM)
dominates in the second region, DIBL in the third region, and SCBE in the fourth
region.
3.0 14
10
Rout (KOhms)
2.0
8
Ids (mA)
1.5
6
1.0
4
0.5
2
0.0 0
0 1 2 3 4
V ds (V)
Generally, drain current is a function of the gate voltage and the drain voltage. But
the drain current depends on the drain voltage very weakly in the saturation region.
A Taylor series can be used to expand the drain current in the saturation region [3].
(2.6.1)
∂I ds (Vgs , Vds )
Ids ( Vgs , Vds ) = Ids ( Vgs , Vdsat ) + ( Vds − Vdsat )
∂Vds
V − Vdsat
≡ I dsat (1 + ds )
VA
where
(2.6.2)
Idsat = Ids ( Vgs, Vdsat ) = Wv satCox (Vgst − AbulkVdsat )
and
(2.6.3)
∂ Ids − 1
VA = I dsat ( )
∂ Vds
The parameter VA is called the Early voltage and is introduced for the analysis of
the output resistance in the saturation region. Only the first order term is kept in the
Taylor series. We also assume that the contributions to the Early voltage from all
three mechanisms are independent and can be calculated separately.
(2.6.4)
∂I ∂ L −1 Abulk Esat L + Vgst ∂ ∆L −1
VACLM = I dsat ( ds ) = ( )
∂ L ∂ Vds Abulk Esat ∂ Vds
(2.6.5)
Abulk Esat L + Vgst
VACLM = (Vds − Vdsat )
Abulk Esatl
The parameter Pclm is introduced into the VACLM expression not only to
compensate for the error caused by the Taylor expansion in the Early
voltage model, but also to compensate for the error in XJ since l ∝ XJ
and the junction depth XJ can not generally be determined very accurately.
Thus, the VACLM became
(2.6.6)
1 Abulk Esat L + Vgst
VACLM = ( Vds − Vdsat )
Pclm Abulk Esat l
(2.6.7)
∂ I ds ∂ Vth −1 1 1
VADIBLC= I dsat ( ) = (Vgst − ( +
∂ Vth ∂ Vds θ th ( L ) Abulk Vdsat V
(2.6.8)
θ rout ( L) = Pdiblc1 [exp( − Drout L / 2l t ) + 2 exp( − Drout L / l t )] + Pdiblc2
Parameters Pdiblc 1 , Pdiblc 2 , Pdiblcb and Drout are introduced to correct for
DIBL effect in the strong inversion region. The reason why Dvt0 is not
equal to Pdiblc 1 and Dvt 1 is not equal to Drout is because the gate voltage
modulates the DIBL effect. When the threshold voltage is determined, the
gate voltage is equal to the threshold voltage. But in the saturation region
where the output resistance is modeled, the gate voltage is much larger than
the threshold voltage. Drain induced barrier lowering may not be the same
at different gate bias. Pdiblc 2 is usually very small (may be as small as
8.0E-3). If Pdiblc 2 is placed into the threshold voltage model, it will not
cause any significant change. However it is an important parameter in
VADIBL for long channel devices, because Pdiblc 2 will be dominant in Eq.
(2.6.8) if the channel is long.
(2.6.9)
Esat L + Vdsat + 2 Rdsv satC oxW ( Vgst − AbulkVds / 2)
VAsat =
1 + Abulk Rds vsat Cox W
(2.6.10)
1 1
VA = VAsat + ( + ) −1
VACLM VADIBL
(2.6.11)
V − Vdsat
Idso = Wvsat Cox (Vgst − Abulk Vdsat )(1 + ds )
VA
(2.6.12)
PvagVgs 1 1
) −1
gsteff
VA = VAsat + (1 + )( +
E satL eff VACLM VADIBLC
When the electrical field near the drain is very large (> 0.1MV/cm), some
electrons coming from the source will be energetic (hot) enough to cause
impact ionization. This creates electron-hole pairs when they collide with
silicon atoms. The substrate current Isub thus created during impact
ionization will increase exponentially with the drain voltage. A well known
Isub model [20] is given as:
(2.6.13)
Ai Bi l
I sub = I ds (Vds − Vdsat )exp −
Bi Vds − Vdsat
The parameters Ai and Bi are determined from extraction. I sub will affect
the drain current in two ways. The total drain current will change because it
is the sum of the channel current from the source as well as the substrate
current. The total drain current can now be expressed [21] as follows
(2.6.14)
I ds = I dso + I sub
(Vds − Vdsat )
= Idso 1 +
Bi Bil
exp( )
Ai Vds − Vdsat
The total drain current, including CLM, DIBL and SCBE, can be written as
(2.6.15)
Vds − Vdsat Vds − Vdsat
I ds = Wv sat Cox ( Vgst − Abulk Vdsat )(1 + )(1 + )
VA VASCBE
where VASCBE can also be called as the Early voltage due to the substrate
current induced body effect. Its expression is the following
(2.6.16)
Bi Bi l
VASCBE = exp( )
Ai Vds − Vdsat
From Eq. (2.6.16), we can see that VASCBE is a strong function of Vds . In
addition, we also observe that VASCBE is small only when Vds is large. This
is why SCBE is important for devices with high drain voltage bias. The
channel length and gate oxide dependence of VASCBE comes from Vdsat and
l. We replace Bi with PSCBE2 and Ai/Bi with PSCBE1/L to yield the
following expression for VASCBE
(2.6.17)
1 P P l
= SCBE 2 exp( − SCBE1 )
VASCBE L Vds − Vdsat
(2.7.1)
Vds Vgs − Vth − Voff
I ds = I s0 (1 − exp( − )) exp( )
vt nv
nvt tm
(2.7.2)
W qε si N ch 2
I s0 = µ 0 vt
L 2φ s
Here the parameter vt is the thermal voltage and is given by KBT/q. V off is the
offset voltage, as discussed in Jeng's dissertation [18]. Voff is an important
parameter which determines the drain current at Vgs = 0. In Eq. (2.7.1), the
parameter n is the subthreshold swing parameter. Experimental data shows that the
subthreshold swing is a function of channel length and the interface state density.
These two mechanisms are modeled by the following
(2.7.3)
Leff Leff
(Cdsc + CdscdVds + CdscbVbseff )exp(−DVT1 ) + 2 exp(− DVT1 )
Cd 2lt lt Cit
n = 1+ Nfactor + +
Cox Cox Cox
L eff Leff
( Cdsc + CdscdVds + C dscb Vbseff ) exp( − DVT 1 ) + 2 exp( − DVT1 )
2l t lt
+
represents the coupling capacitance between the drain or source to the channel.
The parameters Cdsc , Cdscd and Cdscb are extracted. The parameter Cit in Eq. (2.7.3)
is the capacitance due to interface states. From Eq. (2.7.3), it can be seen that
subthreshold swing shares the same exponential dependence on channel length as
the DIBL effect. The parameter Nfactor is introduced to compensate for errors in
the depletion width capacitance calculation. Nfactor is determined experimentally
and is usually very close to 1.
(2.8.1)
L eff = Ldrawn − 2dL
(2.8.2a)
Weff = Wdrawn − 2 dW
(2.8.2b)
W eff = Wdrawn − 2 dW
The only difference between Eq. (2.8.2a) and (2.8.2b) is that the former includes
bias dependencies. The parameters dW and dL are modeled by the following
(2.8.3)
(2.8.4)
Ll Lw L
dL = Lint + L ln
+ Lwn + L ln wl Lwn
L W L W
These complicated formulations require some explanation. From Eq. (2.8.3), the
variable W int models represents the tradition manner from which "delta W" is
extracted (from the intercepts of straights lines on a 1/Rds vs. Wdrawn plot). The
parameters dWg and dWb have been added to account for the contribution of both
front gate and back side (substrate) biasing effects. For dL, the parameter Lint
represents the traditional manner from which "delta L" is extracted (mainly from
the intercepts of lines from a Rds vs. Ldrawn plot).
The remaining terms in both dW and dL are included for the convenience of the
user. They are meant to allow the user to model each parameter as a function of
Wdrawn , Ldrawn and their associated product terms. In addition, the freedom to
model these dependencies as other than just simple inverse functions of W and L is
also provided for the user. For dW, they are Wln and Wwn. For dL they are Lln and
Lwn.
By default all of the above geometrical dependencies for both dW and dL are
turned off. Again, these equations are provided for the convenience of the user. As
such, it is up to the user to adopt the correct extraction strategy to ensure proper
use.
In reality, the doping concentration is, of course, finite. The positive charge near
the interface of the poly-silicon gate and the gate oxide is distributed over a finite
depletion region with thickness Xp. In the presence of the depletion region, the
voltage drop across the gate oxide and the substrate will be reduced, because part
of the gate voltage will be dropped across the depletion region in the gate. That
means the effective gate voltage will be reduced.
Ngate
Figure 2-7. Charge distribution in a MOSFET with the poly gate depletion effect.
The device is in the strong inversion region.
The effective gate voltage can be calculated in the following manner. Assume the
doping concentration in the poly gate is uniform. The voltage drop in the poly gate
(Vpoly ) can be calculated as
(2.9.1)
Ngate 2
1 qN poly X poly
V poly = X poly E poly =
2 2 ε si
where Epoly is the maximum electrical field in the poly gate. The boundary
condition at the interface of poly gate and the gate oxide is
(2.9.2)
ε ox Eox = ε si E poly = 2qε si Ngate
polyV poly
where Eox is the electrical field in the gate oxide. The gate voltage satisfies
(2.9.3)
Vgs − VFB − Φs = V poly + Vox
where Vox is the voltage drop across the gate oxide and satisfies Vox = Eox Tox .
(2.9.4)
where (2.9.5)
ε ox
2
a=
2 qε si N gateTox
2
By solving the equation (2.9.4), we get the effective gate voltage (Vgs_eff) which is
equal to:
(2.9.6)
qε siN gateTox 2εox (Vgs −VFB − Φs )
2 2
Figure 2-8 shows Vgs_eff / Vg s versus the gate voltage. The threshold voltage is
assumed to be 0.4V. If Tox = 40 Å, the effective gate voltage can be reduced by 6%
due to the poly gate depletion effect as the applied gate voltage is equal to 3.5V.
1.00
80
Vgs_eff / Vgs
60
0.95
0.90
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Figure 2-8. The effective gate voltage versus applied gate voltage at different gate
oxide thickness.
The drain current reduction in the linear region as a function of the gate voltage
can now be determined. Assume the drain voltage is very small, e.g. 50mV. Then
the linear drain current is proportional to Cox(Vgs - Vth). The ratio of the linear drain
current with and without poly gate depletion is equal to:
(2.9.7)
Figure 2-9 shows I d s(Vgs_eff ) / Ids(Vg s) versus the gate voltage using Eq. (2.9.7). The
drain current can be reduced by several percent due to gate depletion.
The development of separate model expressions for such device operation regimes as
subthreshold and strong inversion were discussed in Chapter 2. Although these
expressions can accurately describe device behavior within their own respective region of
operation, problems are likely to occur between two well-described regions or within
transition regions. In order to circumvent this issue, a unified model should be synthesized
to not only preserve region-specific expressions but also to ensure the continuities of
current and conductance and their derivatives in all transition regions as well. Such high
standards are kept in BSIM3v3.2.1 . As a result, convergence and simulation efficiency
are much improved.
This chapter will describe the unified I-V model equations. While most of the parameter
symbols in this chapter are explained in the following text, a complete description of all I-
V model parameters can be found in Appendix A.
(3.1.1a)
Vgs − Vth
Q chsubs 0 = Q 0 exp( )
nvt
where Q0 is
(3.1.1b)
qεsiNch Voff
Q0 = vt exp( − )
2φs nvt
(3.1.2)
Qchs 0 = Cox( Vgs − Vth)
In both Eqs. (3.1.1a) and (3.1.2), the parameters Qchsubs0 and Qchs0 are the channel
charge densities at the source for very small Vds. To form a unified expression, an
effective (Vgs-Vth) function named Vgsteff is introduced to describe the channel
charge characteristics from subthreshold to strong inversion
(3.1.3)
Vgs − Vth
2 n vt ln1 + exp( )
2 n vt
Vgsteff =
2Φs Vgs − Vth − 2Voff
1 + 2 n COX exp( − )
qεsiN ch 2 n vt
The unified channel charge density at the source end for both subthreshold and
inversion region can therefore be written as
(3.1.4)
Qchs0 = CoxVgsteff
Figures 3-1 and 3-2 show the smoothness of Eq. (3.1.4) from subthreshold to
strong inversion regions. The Vgsteff expression will be used again in subsequent
sections of this chapter to model the drain current.
Vgs-Vth (V)
Vgs-V th (V)
Eq. (3.1.4) serves as the cornerstone of the unified channel charge expression at
the source for small Vds. To account for the influence of Vds , the Vgsteff function
must keep track of the change in channel potential from the source to the drain. In
other words, Eq. (3.1.4) will have to include a y dependence. To initiate this
formulation, consider first the re-formulation of channel charge density for the
case of strong inversion
(3.1.5)
Qchs(y) = Cox(Vgs − Vth − AbulkVF(y))
The parameter VF(y) stands for the quasi-Fermi potential at any given point y,
along the channel with respect to the source. This equation can also be written as
(3.1.6)
Qchs ( y ) = Qchs 0 + ∆Qchs ( y )
The term ∆Qchs(y) is the incremental channel charge density induced by the drain
voltage at point y. It can be expressed as
(3.1.7)
∆Qchs( y ) = − CoxAbulkVF ( y )
For the subthreshold region (Vgs<<Vth), the channel charge density along the
channel from source to drain can be written as
(3.1.8)
Vgs − Vth − AbulkVF ( y)
Qchsubs( y) = Q0 exp( )
nvt
AbulkVF ( y)
= Qchsubs0 exp(− )
nvt
A Taylor series expansion of the right-hand side of Eq. (3.1.8) yields the following
(keeping only the first two terms)
(3.1.9)
AbulkVF ( y)
Qchsubs (y) = Qchsubs 0(1 − )
nvt
(3.1.10)
Qchsubs( y) = Qchsubs0 + ∆Qchsubs( y)
(3.1.11)
AbulkVF ( y )
∆Qchsubs( y) = − Qchsubs0
nvt
Note that Eq. (3.1.9) is valid only when VF (y) is very small, which is maintained
fortunately, due to the fact that Eq. (3.1.9) is only used in the linear regime (i.e. Vds
≤2vt).
Eqs. (3.1.6) and (3.1.10) both have drain voltage dependencies. However, they are
decupled and a unified expression for Qch (y) is needed. To obtain a unified
expression along the channel, we first assume
(3.1.12)
∆Qchs( y ) ∆Qchsubs( y )
∆Qch( y ) =
∆Qchs ( y ) + ∆Qchsubs ( y )
Here, ∆Qch (y) is the incremental channel charge density induced by the drain
voltage. Substituting Eq. (3.1.7) and (3.1.11) into Eq. (3.1.12), we obtain
(3.1.13)
VF ( y )
∆Q ch( y ) = Qchs 0
Vb
where Vb = (Vgsteff + n*vt )/Abulk . In order to remove any association between the
variable n and bias dependencies (Vgsteff) as well as to ensure more precise
modeling of Eq. (3.1.8) for linear regimes (under subthreshold conditions), n is
replaced by 2. The expression for Vb now becomes
(3.1.14)
Vgsteff + 2 vt
Vb =
Abulk
A unified expression for Qch (y) from subthreshold to strong inversion regimes is
now at hand
(3.1.15)
VF ( y )
Qch ( y ) = Qchs0(1 − )
Vb
(mobMod = 1) (3.2.1)
µo
µeff =
+ 2Vth
Vgsteff Vgsteff + 2Vth 2
1 + (U a + U c Vbseff )( ) + U b( )
TOX TOX
To account for depletion mode devices, another mobility model option is given by
the following
(mobMod = 2) (3.2.2)
µo
µeff =
Vgsteff Vgsteff 2
1 + (U a + UcVbseff )( ) + Ub ( )
TOX TOX
To consider the body bias dependence of Eq. 3.2.1 further, we have introduced the
following expression
µo
µeff =
Vgsteff + 2 Vth Vgsteff + 2Vth 2
1 + [U a ( ) + U b( ) ](1 + UcVbseff )
TOX TOX
Generally, the following expression [2] is used to account for both drift and
diffusion current
(3.3.1)
dVF( y )
Id ( y ) = WQc h( y ) µne ( y )
dy
(3.3.2)
µeff
µne ( y ) =
Ey
1+
Esat
(3.3.3)
VF ( y ) µeff dVF ( y )
Id ( y ) = WQchso (1 − )
Vb 1 + Ey dy
Esat
Eq. (3.3.3) resembles the equation used to model drain current in the strong
inversion regime. However, it can now be used to describe the current
characteristics in the subthreshold regime when Vds is very small ( Vds<2vt ).
Eq. (3.3.3) can now be integrated from the source to drain to get the
expression for linear drain current in the channel. This expression is valid
from the subthreshold regime to the strong inversion regime
(3.3.4)
V
W µ eff Q chs0V ds 1 − ds
2Vb
I ds 0 =
V
L 1 + ds
E sat L
The current expression when Rds > 0 can be obtained based on Eq. (2.5.9)
and Eq. (3.3.4). The expression for linear drain current from subthreshold
to strong inversion is:
(3.3.5)
Idso
Ids =
RdsIdso
1+
Vds
(3.4.1)
I dso
Ey =
Idso 2 2 Ids 0WQchs 0µ eff y
( WQchs0 µeff − ) −
Esat Vb
(3.4.2)
Wµeff Qchs0 Esat LVb
Idsat =
2 L( Esat L + Vb)
Let Vds=Vdsat in Eq. (3.3.4) and set this equal to Eq. (3.4.2), we get the
following expression for Vdsat
(3.4.3)
EsatL( Vgsteff + 2vt )
Vdsat =
AbulkEsatL + Vgsteff + 2vt
The Vdsat expression for the extrinsic case is formulated from Eq. (3.4.3)
and Eq. (2.5.10) to be the following
(3.4.4a)
− b − b − 4 ac
2
Vdsat =
2a
where
(3.4.4b)
1
a = A bulk 2Weff νsatCoxR DS + ( − 1) A bulk
λ
(3.4.4c)
2
b = − (Vgsteff + 2 vt )( − 1) + A bulk EsatLeff + 3 A bulk (Vgsteff + 2 v t)WeffνsatCoxR DS
λ
(3.4.4d)
c = (Vgsteff + 2vt ) E satLeff + 2(Vgsteff + 2vt ) WeffνsatCoxRDS
2
(3.4.4e)
λ = A1Vgsteff + A2
(3.5.1)
Ids =
Idso( Vdsat ) 1 + V ds − V dsat 1 + Vds − V dsat
RdsIdso( Vdsat ) VA VASCBE
1+
Vdsat
where
(3.5.2)
Pvag Vgsteff 1 1
VA = VAsat + (1 + )( + ) −1
EsatLeff VACLM VADIBLC
(3.5.3)
AbulkVdsat
EsatLeff + Vdsat + 2 RDSνsatCox WeffVgsteff [1 − ]
2(Vgsteff + 2vt )
VAsat =
2 / λ − 1 + RDSνsatCoxWeffAbulk
(3.5.4)
AbulkEsatLeff + Vgsteff
VACLM = (Vds − Vdsat )
PCLM AbulkEsat litl
(3.5.5)
(Vgsteff + 2 vt) AbulkVdsat
VADIBLC = 1 −
θ rout (1 + PDIBLCB Vbseff ) AbulkVdsat + Vgsteff + 2vt
(3.5.6)
L eff L eff
θrout = PDIBLC 1 exp( − DROUT ) + 2 exp( − DROUT ) + PDIBLC 2
2l t 0 l t0
(3.5.7)
− Pscbe 1 litl
exp
1 P scbe 2
=
VASCBE Leff Vds − Vdsat
(3.6.1)
Ids =
Idso( Vdseff ) 1 + Vds − V dseff 1 + V ds − V dseff
RdsIdso( Vdseff ) VA V ASCBE
1+
Vdseff
Most of the previous equations which contain Vds and Vdsat dependencies are now
substituted with the Vdseff function. For example, Eq. (3.5.4) now becomes
(3.6.2)
AbulkEsatLeff + Vgsteff
VACLM = (Vds − Vdseff )
PCLMAbulkEsat litl
(3.6.3)
1 Pscbe 2 − Pscbe1 litl
= exp
VASCBE Leff Vds − Vdseff
(3.6.4)
Vdseff = Vdsat −
1
2
(Vdsat − Vds − δ + (Vdsat − Vds − δ)2 + 4δVdsat )
The expression for Vdsat is that given under Section 3.4. The parameter δ in the
unit of volts can be extracted. The dependence of Vdseff on Vds is given in Figure 3-
3. The Vdseff function follows Vds in the linear region and tends to Vdsat in the
saturation region. Figure 3-4 shows the effect of δ on the transition region between
linear and saturation regimes.
Figure 3-3. Vdseff vs. Vds for δ=0.01 and different Vgs.
Figure 3-4. Vdseff vs. Vds for Vgs =3V and different δ values.
(3.7.1)
α 0 + α1 ⋅ Leff β0 Vds − Vdseff
I sub = (V ds − Vdseff )exp −
Vds − Vdseff
I ds0
1 +
Leff 1 + Rds I ds0 VA
Vdseff
(3.8.1)
Vbseff = Vbc + 0.5[Vbs − Vbc − δ 1 + (Vbs − Vbc − δ1) 2 − 4δ 1Vbc ]
where δ1 =0.001V.
Parameter Vbc is the maximum allowable Vbs value and is obtained based on the
condition of dVth/dVbs = 0 for the Vth expression of 2.1.4.
Accurate modeling of MOSFET capacitance plays equally important role as that of the
DC model. This chapter describes the methodology and device physics considered in both
intrinsic and extrinsic capacitance modeling in BSIM3v3.3. Detailed model equations are
given in Appendix B. One of the important features of BSIM3v3.2 is introduction of a
new intrinsic capacitance model (capMod=3 as the default model), considering the finite
charge thickness determined by quantum effect, which becomes more important for
thinner Tox CMOS technologies. This model is smooth, continuous and accurate
throughout all operating regions.
• Separate effective channel length and width are used for capacitance models.
• The intrinsic capacitance models, capMod=0 and 1, use piece-wise equations.
capMod=2 and 3 are smooth and single equation models; therefore both charge and
capacitance are continous and smooth over all regions.
• Threshold voltage is consistent with DC part except for capMod=0, where a long-
channel V th is used. Therefore, those effects such as body bias, short/narrow channel
and DIBL effects are explicitly considered in capMod=1, 2, and 3.
• Overlap capacitance comprises two parts: (1) a bias-independent component which
models the effective overlap capacitance between the gate and the heavily doped
source/drain; (2) a gate-bias dependent component between the gate and the lightly
doped source/drain region.
• Bias-independent fringing capacitances are added between the gate and source as well
as the gate and drain.
acde Exponential coefficient for XDC for accumulation and deple- 1 (m/V)
tion regions
cgso Non-LDD region G/S overlap C per channel length Calculated F/m
cgdo Non-LDD region G/D overlap C per channel length Calculated F/m
(Lactive) and width (W active ) when the gate to S/D region is at flat band voltage.
Lactive and Wactive are defined by Eqs. (4.2.1) through (4.2.4).
(4.2.1)
Lactive = Ldrawn − 2δLeff
(4.2.2)
Wactive = Wdrawn − 2δWeff
(4.2.3)
Llc Lwc Lwlc
δLeff = DLC + L ln
+ Lwn + Lln Lwn
L W L W
(4.2.4)
Wlc Wwc Wwlc
δWeff = DWC+ W ln
+ Wwn + W ln Wwn
L W L W
The meanings of DWC and DLC are different from those of Wint and Lint in the I-
V model. Lactive and Wactive are the effective length and width of the intrinsic
device for capacitance calculations. Unlike the case with I-V, we assumed that
these dimensions have no voltage bias dependence. The parameter δLeff is equal to
the source/drain to gate overlap length plus the difference between drawn and
actual POLY CD due to processing (gate printing, etching and oxidation) on one
side. Overall, a distinction should be made between the effective channel length
extracted from the capacitance measurement and from the I-V measurement.
Traditionally, the Leff extracted during I-V model characterization is used to gauge
a technology. However this Leff does not necessarily carry a physical meaning. It is
just a parameter used in the I-V formulation. This Leff is therefore very sensitive to
the I-V equations used and also to the conduction characteristics of the LDD
region relative to the channel region. A device with a large Leff and a small
parasitic resistance can have a similar current drive as another with a smaller Leff
but larger Rds. In some cases Leff can be larger than the polysilicon gate length
giving Leff a dubious physical meaning.
The accumulation charge and the substrate charge are associated with the
substrate while the channel charge comes from the source and drain
terminals
(4.3.1)
Qg = −( Qsub + Qinv + Qacc )
Qb = Qacc + Qsub
Q = Q + Q
inv s d
The substrate charge can be divided into two components - the substrate
charge at zero source-drain bias (Qsub0 ), which is a function of gate to
substrate bias, and the additional non-uniform substrate charge in the
presence of a drain bias (δQsub). Qg now becomes
(4.3.2)
Q g = −(Qinv + Qacc + Q sub0 + δQsub )
The total charge is computed by integrating the charge along the channel.
The threshold voltage along the channel is modified due to the non-
uniform substrate charge by
(4.3.3)
Vth ( y ) = Vth (0) + ( Abulk −1)Vy
(4.3.4)
Lactive L active
dV y
dy =
εy
and
(4.3.5)
Wactiveµeff Cox
Vgt − bulk Vds Vds = Wactiveµeff Cox (Vgt − AbulkVy )E y
A
I ds =
Lactive 2
(4.3.6)
2 2
Q c = −W active L active C ox V gt − A bulk
V ds +
A bulk V ds
2 A bulk
12 V gt − V ds
2
2
V ds Abulk V ds
Q g = − Q sub 0 + W active Lactive C ox V gt − +
2 A
12 V gt − bulk V ds
2
Q b = − Q g − Q c = Q sub + Q sub 0 + Q acc
where
(4.3.7)
The inversion charges are supplied from the source and drain electrodes
such that Qinv = Qs + Qd. The ratio of Qd and Qs is the charge partitioning
ratio. Existing charge partitioning schemes are 0/100, 50/50 and 40/60
(XPART = 0, 0.5 and 1) which are the ratios of Qd to Qs in the saturation
region. We will revisit charge partitioning in Section 4.3.4.
(4.3.8)
∂Qi
Ci j =
∂V j
∑Ci
ij = ∑C
j
ij =0
(4.3.9)
V gsteff ,cv
Vdsat ,iv < Vdsat ,cv < Vdsat ,iv Lactive →∞
=
Abulk
(4.3.10a)
V gsteff ,cv
cdsat ,cv =
Vdsat,cv
CLC
CLE
Abulk 1 +
L active
(4.3.10b)
Parameters noff and voffcv are introduced to better fit measured data above
subthreshold regions. The parameter Abulk is substituted Abulk0 in the long
channel equation by
(4.3.11)
CLC CLE
Abulk ' = Abulk 0 1 +
L active
(4.3.11a)
A0 Leff B0
Abulk = 1 +
K1o x 1
+ ⋅
2 Φ −V L + 2 X X
Weff '+B1 1 + KetaVbseff
s bseff eff J dep
(4.3.12)
Q(Vgt ) = Q(Vgsteff,CV )
(4.3.13)
∂Vgsteff,CV
C(Vgt ) = C(Vgsteff,CV )
Vgs,ds,bs
(4.3.14)
{
VFBeff = vfb − 0.5 V3 + V3 + 4δ 3 vfb
2
} where V3 = vfb − Vgs + Vbseff − δ 3 ; δ 3 = 0.02V
(4.3.15)
vfb = Vth − Φs − K1ox Φs −Vbseff
(4.3.16)
(
Qacc = −WactiveLactive Cox VFBeff − vfb )
(4.3.17)
K 2 ( )
4 Vgs −VFBeff −Vgsteff,CV −Vbseff
Qsub0 = −WactiveLactiveCox ⋅ 1ox −1+ 1+
2 K1ox2
An effective Vds , Vcveff, is used to smooth out the transition between linear
and saturation regions. It affects the inversion charge.
(4.3.18)
{
Vcveff = Vdsat,cv − 0.5 V4 + V4 + 4δ4Vdsat, cv
2
} whereV = V 4 dsat, cv − Vds − δ 4; δ4 = 0.02V
(4.3.19)
2 2
A ' Abulk ' Vcveff
Qinv = −Wactive Lactive Cox Vgsteff ,cv− bulk Vcveff +
2 Abulk '
12Vgsteff ,cv− V
2 cveff
(4.3.20)
2
1 − Abulk ' (1 − A ' ) A ' V
δQsub = Wactive LactiveCox Vcveff −
bulk bulk cveff
2 A '
−
12Vgsteff ,cv bulk
Vcveff
2
Below is a list of all the three partitioning schemes for the inversion
charge:
(4.3.21)
Abulk ' 2 Vcveff 2
Wactive Lactive Cox Abulk '
Qs = Qd = 0 .5Qinv = − Vgsteff,cv− Vcveff +
2 2 Abulk '
12Vgsteff,cv− Vcveff
2
This is the most physical model of the three partitioning schemes in which
the channel charges are allocated to the source and drain terminals by
assuming a linear dependence on the position y.
(4.3.22)
Lactive
y
Q s = Wactive
∫ qc 1 −
L
dy
0 active
Lactive
Q = W y
d active ∫ q c L active dy
0
(4.3.23)
2
A ' 3 3 15
2VgsteffCV − bulk Vcveff
2
(4.3.24)
( ) (
V 3 − 5V cv2 A ' V + V cv A ' V 2 − 1 A ' V 3
) ( )
WactiveLactiveCox
Qd = − 2 gsteffcv bulk cveff
gsteff bulk cveff gsteff bulk cveff
Abulk' 3 5
2Vgsteffcv − Vcveff
2
charges in the saturation region to the source electrode. Notice that this
charge partitioning scheme will still give drain current spikes in the linear
region and aggravate the source current spike problem.
(4.3.25)
V ( )
2
Abulk ' Vcveff Abulk ' Vcveff
Qs = −Wactive Lactive Cox
gsteff,c
+ −
gstefcvf
2 4 Abulk '
24 Vgsteff,c − Vcveff
gsteffcv 2
(4.3.26)
V ( )
2
3 Abulk ' Vcveff Abulk ' Vcveff
Qd = − Wactive LactiveC ox gsteff,c
− +
gsteffcv
2 4 V Abulk '
8 − V
cveff
gsteff,c
gsteffcv
2
This section describes the concepts used in the charge-thichness model (CTM).
Appendix B lists all charge equations. A full report and anaylsis of the CTM model
can be found in [32].
Normalized Charge Distribution
1.0
E E
0.15 0.8 A
Cgg (µF/cm )
2
B D
0.6
D
0.4 C
0.2
0.10
C -4 -3 -2 -1 0 1 2 3
Vgs (V)
A Tox=30A
0.05 Nsub=5e17cm
-3
0.00
0 20 40 60
Depth (A)
Figure 4-1. Charge distribution from numerical quantum simulations show significant
charge thickness at various bias conditions shown in the inset.
CTM is a charge-based model and therefore starts with the DC charge thicknss,
XDC . The charge thicknss introduces a capacitance in series with Cox as illustrated
in Figure 4-2, resulting in an effective Cox , Coxeff. Based on numerical self-
consistent solution of Shrodinger, Poisson and Fermi-Dirac equations, universal
and analytical XDC models have been developed. Coxeff can be expressed as
(4.4.1)
C oxC cen
C oxeff =
C ox + C cen
where
Ccen = ε si X
DC
Vgs
Figure 4-2. Charge-thickness capacitance concept in CTM. Vgse accounts for the poly
depletion effect.
(4.4.2)
1 N sub
−0.25
Vgs −Vbs −Vfb
X DC = Ldebyeexpacde⋅ ⋅
2 ×10
16
3 Tox
where XDC is in the unit of cm and (Vgs - Vbs - vfb) / Tox has a unit of MV/cm. The
model parameter acde is introduced for better fitting with a default value of 1. For
numerical statbility, (4.4.2) is replaced by (4.4.3)
(4.4.3)
X DC = X max −
1
2
(
X0 + X 02 + 4δ x X max )
where
X 0 = X max − X DC − δ x
(4.4.4)
−7
1.9×10
XDC = [cm]
V + 4(Vth − vfb−2ΦB )
0.7
1 + gsteff
2Tox
represents the boundary conditions (the average of the electric fields at the top and
the bottom of the charge layers) of the Schrodinger and the Poisson equations.
30 Model
20
10
Figure 4-3. For all T ox and Nsub , modeled inversion charge thickness agrees with numerical
quantum simulations.
(4.4.5)
V ⋅V
Φδ = Φs − 2ΦB =νt ln gsteff,cv gsteff,cv
+ 2K1ox 2ΦB
+1
( )
moin ⋅ K ν 2
1ox t
where the model parameter moin (defaulting to 15) is introduced for better fit to
different technologies. The inversion channel charge density is therefore derived
as
(4.4.6)
qinv = −Coxeff ⋅ (Vgsteff,cv − Φδ )
Figure 4-4 illustrates the universality of CTM model by compariing Cgg of a SiON/
Ta2O5 /TiN gate stack structure with an equivalent Tox of 1.8nm between data,
numerical quantum simulation and modeling [32].
10.0
Measured Q.M. simulation CTM
18A equivalent SiO2 thickness
7.5
Cgg (pF)
5.0 TiN
60A Ta2O5
2.5
8A SiON
p-Si
0.0
-2 -1 0 1 2 3
Vgs (V)
(4.5.1)
2ε ox t poly
CF = ln1 +
π Tox
(4.5.2)
Qoverlap, s CKAPPA 4V
= CGS 0 ⋅ Vgs + CGS 1Vgs − Vgs ,overlap − − 1 + 1 − gs ,overlap
Wactive 2 CKAPPA
(4.5.3)
2
2ε si qN LDD
CKAPPA = 2
C ox
17
The typical value for NLDD is 5 × 10 cm-3 .
(4.5.4)
(4.5.5)
V gd , overlap =
1
V gd + δ 1 −
2
(V gd + δ 1 ) + 4δ 1 , δ 1 = 0. 02V
2
(4.5.6)
Qoverlap, g = − (Qoverlap, d + Qoverlap, s + (CGB 0 ⋅ Lactive ) ⋅V gb )
CGD0 = (DLC*Cox ) - CGD1 (if DLC is given and DLC > CGD1/Cox)
(5.3.1)
Q def
icheq(t) Vdef R
C=1 ×Cfact
dominates. τ is expressed by
(5.3.2)
1 1 1
= +
τ τdiff τdrift
(5.3.3)
2 2
Leff Leff
Relm = ≈
elm⋅ µ0Qch elm⋅ µ0Qcheq
(5.3.4)
3
CoxWeff Leff
τ drift ≈ Relm ⋅ CoxWeff Leff ≈
elm⋅ µ0Qcheq
(5.3.5)
2
qLeff
τ diff =
16 ⋅ µ 0 kT
Considering both the transport and charging component, the total current
related to the terminals D, G and S can be written as
(5.3.6)
∂Qd , g, s (t )
iD,G ,S (t ) = I D ,G,S (DC) +
∂t
(5.3.7)
Qdef (t ) = Qcheq (t ) − Q ch (t )
and
(5.3.8a)
∂Qdef (t ) ∂Qcheq (t ) Qdef (t )
= −
∂t ∂t τ
(5.3.8b)
∂Qd , g ,s (t ) Q def (t )
= D , G, S xpart
∂t τ
where D,G,Sxpart are the NQS channel charge partitioning number for
terminals D, G and S, respectively; Dxpart + Sxpart = 1 and Gxpart = -1. It is
important for Dxpart and Sxpart to be consistent with the quasi-static charge
partitioning number XPART and to be equal (Dxpart = Sxpart) at Vds =0 (which
is not the case in the previous version), where the transistor operation mode
changes (between forward and reverse modes). Based on this
consideration, Dxpart is now formulated as
(5.3.9)
Qd Q
Dxpart = = d
Qd + Qs Qcheq
which is now bias dependent. For example, the derivities of Dxpart can be
easily obtained based on the quasi-static results:
(5.3.10)
dDxpart
=
1
(Sxpart ⋅Cdi − Dxpart ⋅Csi )
dVi Qcheq
where i represents the four terminals and Cdi and Csi are the intrinsic
capacitances calculated from the quasi-static analysis. The corresponding
values for Sxpart can be derived from the fact that Dxpart + Sxpart = 1.
This section gives some examples of how to derive the nodal conductances
related to NQS for transient analysis. By noting that τ = RC, Gtau can be
derived as
(5.3.11)
C fact
Gtau =
τ
(5.3.12)
(5.3.13)
Dxpart ⋅ Gtau
(5.3.14)
∆Qcheq (t )
∆Qch (t ) =
1 + jωτ
(5.3.15)
G m0 G ⋅ ωτ
Gm = + j − m0 2 2
1+ω τ2 2
1+ ω τ
and
(5.3.16)
Cdg0 Cdg 0 ⋅ ωτ
Cdg = + j −
1 +ω τ2 2
1+ω τ
2 2
Those quantities with sub “0”in the above two equations are known from
OP (operating point) analysis.
device performance quite well. Values extracted in this manner will now have
some physical relevance.
BSIM3v3 uses group device extraction strategy. This requires measured data from
devices with different geometries. All devices are measured under the same bias
conditions. The resulting fit might not be absolutely perfect for any single device
but will be better for the group of devices under consideration.
One large size device and two sets of smaller-sized devices are needed to
extract parameters, as shown in Figure 6-1.
W Large W and L
Wmin
L
Lmin
6.3.2 Optimization
(6.3.1)
Initial Guess of
Parameters P i
Model Equations
∆P
i
+ ∆P
(m+1) (m)
P =P
i i i
∆P no
< δ
i
(m)
P
i
yes
STOP
To change Eq. (6.3.1) into a form that a linear least-squares fit routine can
be used (i.e. in a form of y = a + bx 1 + cx2), both sides of the Eq. (6.3.1)
are divided by ∂fsim / ∂P1. This gives the change in P1 , ∆P1(m) , for the next
iteration such that:
(6.3.2)
( m + 1)
Pi = Pi( m ) + ∆ Pi( m )
where i=1, 2, 3 for this example. The (m+1) parameter values for P2 and P3
are obtained in an identical fashion. This process is repeated until the
incremental parameter change in parameter values ∆Pi (m) are smaller than
a pre-determined value. At this point, the parameters P1, P2 , and P3 have
been extracted.
Step 1
Step 2
Step 3
Step 4
Step 5
Step 6
Step 7
Step 8
Step 9
Step 10
Step 11
Step 12
Step 13
Step 14
Step 15
Step 16
Pclm , θ(Drout , Pdiblc1 , Pdiblc2 , L), Pavg One Set of Devices (Large and Fixed W &
Different L).
Fitting Target Exp. Data: Rout(Vgs, Vds ) I ds vs. Vds @ Vbs = 0V at Different Vgs
Step 17
Step 18
Step 19
θdibl(Eta0, Etab, Dsub, L) One Set of Devices (Large and Fixed W &
Different L).
Fitting Target Exp. Data: Subthreshold I ds vs. Vgs @ Vds = Vdd at Different Vbs
region Ids(Vgs, Vbs)
Step 20
Step 21
Step 22
Below is a list of model parameters which have special notes for parameter
extraction.
Vth0 Threshold voltage for large W and L device @ 0.7 (NMOS) V nI-1
Vbs=0V -0.7 (PMOS)
K1 First order body effect coefficient 0.5 V 1/2 nI-2
Vth0 = VFB + Φ s + K1 Φ s
VFB = Vth0 − Φs − K1 Φs
K 1 = γ 2 − 2 K 2 Φ s − Vbm
(γ 1 −γ 2 )( Φs −Vbx − Φs )
K2 =
(
2 Φs Φs −Vbm − Φs +Vbm )
where Φ s is calculated by
N
Φ s = 2Vtm0 ln ch
ni
k BTnom
Vtm0 =
q
Eg 0
1.5
Tnom
ni = 1. 45 × 10 exp 21. 5565981−
10
300. 15 2Vtm 0
γ 1 C ox
2 2
N ch =
2 qε si
If both γ 1 and Nch are not given, Nch defaults to 1.7e23 m-3 and γ 1 is
calculated from Nch.
2 qε si Nch
γ1 =
Cox
2qε si N sub
γ2 =
Cox
2
qN ch X t
= Φ s − Vbx
2ε si
2 ε ox 4 × 10 −7
CF = ln 1 +
π Tox
A series of benchmark tests [26] have been performed to check the model robustness,
accuracy and performance. Although not all the benchmark test results are included in this
chapter, the most important ones are demonstrated.
Figure
Device Size Bias Conditions Notes Number
W/L=20/5 Ids vs. Vgs @ Vbs=0V; Vds=0.05, 3.3V Log scale 7-1
W/L=20/5 Ids vs. Vgs @ Vbs=0V; Vds=0.05, 3.3V Linear scale 7-2
W/L=20/0.5 Ids vs. Vgs @ Vbs=0V; Vds=0.05, 3.3V Log scale 7-3
W/L=20/0.5 Ids vs. Vgs @ Vbs=0V; Vds=0.05, 3.3V Linear scale 7-4
W/L=20/5 Ids vs. Vgs @ Vds=0.05V; Vbs=0 to -3.3V Log scale 7-5
W/L=20/5 Ids vs. Vgs @ Vds=0.05V; Vbs=0 to -3.3V; W/ Linear scale 7-6
L=20/5
W/L=20/0.5 Ids vs. Vgs @ Vds=0.05V; Vbs=0 to -3.3V Log scale 7-7
W/L=20/0.5 Ids vs. Vgs @ Vds=0.05V; Vbs=0 to -3.3V Linear scale 7-8
W/L=20/5 Gm/Ids vs. Vgs @ Vds=0.05V, 3-3V; Vbs=0V Linear scale 7-9
Figure
Device Size Bias Conditions Notes Number
W/L=20/0.5 Gm/Ids vs. Vgs @ Vds=0.05V, 3-3V; Vbs=0V Linear scale 7-10
Figure 7-3. Same as Figure 7-1 but for a short channel device.
Figure 7-4. Same as Figure 7-2 but for a short channel device.
Figure 7-7. Same as Figure 7-5 but for a short channel device.
Figure 7-8. Same as Figure 7-6 but for a short channel device.
Figure 7-10. Same as Figure 7-9 but for a short channel device.
Figure 7-12. Same as Figure 7-11 but for a short channel device.
Figure 7-15. Same as Figure 7-14 but for a short channel device.
8.1.1 Parameters
There exist two models for flicker noise modeling. One is called SPICE2
flicker noise model; the other is BSIM3 flicker noise model [35-36]. The
flicker noise model parameters are listed in Table 8-1.
Symbols Symbols
used in used in Description Default Unit
equation SPICE
Noia noia Noise parameter A (NMOS) 1e20 none
(PMOS) 9.9e18
Noib noib Noise parameter B (NMOS) 5e4 none
(PMOS) 2.4e3
Noic noic Noise parameter C (NMOS) -1.4e-12 none
(PMOS) 1.4e-12
Em em Saturation field 4.1e7 V/m
Af af Flick noise exponent 1 none
Ef ef Flicker noise frequency 1 none
exponent
Kf kf Flicker noise coefficient 0 none
LINTNOI lintnoi Length Reduction Parameter Off- 0.0 m
set
8.1.2 Formulations
(8.2)
kB Tq µeff I ds N + 2 × 1014
( )
2
+ NOIB⋅ ( N 0 − N l ) +
NOIC 2
S id,inv( f ) = NOIA⋅ log 0 N0 − Nl
2
+ ⋅
Weff ⋅ ( Leff − 2 ⋅ LINTNOI) 2 f ef ⋅108 (
Nl + N*
2
)
where Vtm is the thermal voltage, µeff is the effective mobiity at the given
bias condition, and Leff and Weff are the effective channel length and width,
respectively. The parameter N0 is the charge density at the source side
given by
(8.3)
Co x (Vgs − Vth )
N0 =
q
(8.4)
∆Lclm is the channel length reduction due to channel length modulation and
given by
(8.5)
Vds −Vdsat
+ Em
Litl ⋅ log Litl (for Vds > Vdsat)
∆Lclm = Esat
0 (otherwise)
2× vsat
Esat =
µeff
where
Litl = 3 X jTox
Otherwise
(8.6)
Slimit × Swi
Noisedensity=
Slimit + Swi
Where, Slimit is the flicker noise calculated at Vgs = Vth + 0.1 and Swi is given
by
(8.7)
Noia ⋅ Vtm ⋅ I ds
2
Swi =
Weff Leff ⋅ f ef ⋅ 4×1036
Qinv is the inversion channel charge computed from the capacitance models
(capMod = 0, 1, 2 or 3).
3 min( Vds,Vdsat )
kT ( g m + g ds + g mbs ) −
8
3 2 2Vdsat
If the S/B saturation current Isbs is larger than zero, the following equations
is used to calculate the S/B diode current Ibs.
(9.1)
V
Ibs = Isbs exp bs − 1 + GminVbs
NVtm
(9.2)
V
Ibs = Isbs exp bs −1 + GminVbs
NVtm
otherwise
(9.3)
ijth+ Isbs
Ibs = ijth+ (Vbs −Vjsm) + GminVbs
NVtm
(9.4)
I sbs = As J s + Ps J ssw
(9.5)
Eg 0 Eg T
− + XTI ln
Vtm0 Vtm Tnom
J s = J s0 exp
NJ
(9.6)
Eg0 Eg T
− + XTI ln
Vtm0 Vtm nom
T
J ssw = J s0sw exp
NJ
The energy band-gap Eg0 and Eg at the nominal and operating temperatures
are expressed by (9.7a) and (9.7b), repectively:
(9.7a)
7 .02 × 10 −4 Tnom
2
Eg 0 = 1.16 −
Tnom + 1108
(9.7b)
−4
7 .02 × 10 T 2
E g = 1.16 −
T + 1108
In the above derivatoins, Js0 is the saturation current density at Tnom. If Js0 is
–4
not given, J s0 = 1 × 10 A/m2. Js0sw is the sidewall saturation current density
at Tnom , with a default value of zero.
(9.8)
I bs = Gmin ⋅ Vbs
If the D/B saturation current Isbd is larger than zero, the following equations
is used to calculate the D/B diode current I bd.
(9.9)
V
Ibd = I sbd exp bd −1 + GminVbd
NVtm
V
Ibd = I sbd exp bd − 1 + GminVbd
NVtm
otherwise
(9.11)
ijth + I sbd
Ibd = ijth + (Vbd − Vjdm) + GminVbd
NVtm
ijth
Vjdm = NVtm ln + 1
sbd
I
(9.12)
I sbd = Ad J s + Pd J ssw
where Ad is the drain junction area and Pd is the perimeter of the drain
junction. If Isbd is not positive, Ibd is calculated by
(9.13)
I bd = Gmin ⋅ Vbd
Symbols Symbols
used in used in Description Default Unit
equation SPICE
Js0 js Saturation current density 1e-4 A/m2
Js0sw jssw Side wall saturation current density 0 A/m
NJ nj Emission coefficient 1 none
XTI xti Junction current temperature expo- 3.0 none
nent coefficient
ijth ijth Limiting current 0.1 A
If Ps > Weff
(9.14)
Capbs = As C jbs + (Ps − Weff )C jbssw + Weff C jbsswg
Otherwise
(9.15)
Capbs = As C jbs + Ps C jbsswg
where Cjbs is the unit bottom area capacitance of the S/B junction,
Cjbssw is the periphery capacitance of the S/B junction along the
field oxide side, and Cjbsswg is the periphery capacitance of the S/B
junction along the gate oxide side.
if Vbs < 0
(9.16)
−M j
V
Cjbs = C j 1− bs
Pb
otherwise
(9.17)
V
C jbs = C j 1 + M j bs
Pb
if Vb s < 0
(9.18)
− M jsw
V
C jbssw = C jsw1− bs
Pbsw
otherwise
(9.19)
V
Cjbssw = C jsw1 + M jsw bs
Pbsw
if Vb s < 0
(9.20)
− M jswg
V
C jbsswg = C jswg1 − bs
Pbswg
otherwise
(9.21)
V
Cjbsswg = C jswg 1 + M jswg bs
Pbswg
If Pd > W eff
(9.22)
Capbd = Ad C jbd + (Pd − Weff )C jbdsw + WeffC jbdswg
Otherwise
(9.23)
Capbd = Ad C jbd + PdC jbdswg
where Cjbd is the unit bottom area capacitance of the D/B junction,
Cjbdsw is the periphery capacitance of the D/B junction along the
field oxide side, and Cjbdswg is the periphery capacitance of the D/B
junction along the gate oxide side.
if Vbd < 0
(9.24)
−M
V
j
C jbd = C j 1 − bd
Pb
otherwise
(9.25)
V
C jbd = C j 1+ M j bd
Pb
if Vbd < 0
(9.26)
− M jsw
V
C jbdsw = C jsw1 − bd
Pbsw
otherwise
(9.27)
V
C jbdsw = C jsw1 + M jsw bd
Pbsw
if Vbd < 0
(9.28)
− M jswg
V
Cjbdswg = Cjswg1 − bd
Pbswg
otherwise
(9.29)
V
C jbdswg = C jswg1 + M jswg bd
Pbswg
(9.30a)
C j (T ) = C j (Tnom ) ⋅ (1 + tcj ⋅ ∆T )
(9.30b)
(9.30c)
(9.31a)
Pb (T ) = Pb (Tnom ) − tpb ⋅ ∆T
(9.31b)
Pbsw(T ) = Pbsw(Tnom ) − tpbsw⋅ ∆T
(9.31c)
Pbswg(T ) = Pbswg(Tnom) − tpbswg⋅ ∆T
(9.32)
∆T = T −Tnom
The six new model parameters in the above equations are described
in Table 9-2.
Symbols Symbols
used in used in Description Default Unit
equation SPICE
Cj cj Bottom junction capacitance per 5e-4 F/m2
unit area at zero bias
Mj mj Bottom junction capacitance grad- 0.5 none
ing coefficient
Pb pb Bottom junction built-in potential 1.0 V
Cjsw cjsw Source/drain sidewall junction 5e-10 F/m
capacitance per unit length at zero
bias
Mjsw mjsw Source/drain sidewall junction 0.33 none
capacitance grading coefficient
Pbsw pbsw Source/drain side wall junction 1.0 V
built-in potential
Cjswg cjswg Source/drain gate side wall junc- Cjsw F/m
tion capacitance per unit length at
zero bias
Mjswg mjswg Source/drain gate side wall junc- Mjsw none
tion capacitance grading coeffi-
cient
Pbswg pbswg Source/drain gate side wall junc- Pbsw V
tion built-in potential
tpb tpb Temperature coefficient of Pb 0.0 V/K
tpbsw tpbsw Temperature coefficient of Pbsw 0.0 V/K
Symbols Symbols
used in used in Description Default Unit
equation SPICE
tpbswg tpbswg Temperature coefficient of Pbswg 0.0 V/K
tcj tcj Temperature coefficient of Cj 0.0 1/K
tcjsw tcjsw Temperature coefficient of Cjsw 0.0 1/K
tcjswg tcjswg Temperature coefficient of Cjswg 0.0 1/K
A.2 DC Parameters
Symbols Symbols
used in used in Description Default Unit Note
equation SPICE
Vth0 vth0 Threshold voltage @Vbs=0 for 0.7 V nI-1
Large L. (NMOS)
-0.7
(PMOS)
VFB vfb Flat-band voltage Calculated V nI-1
K1 k1 First order body effect coeffi- 0.5 V1/2 nI-2
cient
K2 k2 Second order body effect coef- 0.0 none nI-2
ficient
K3 k3 Narrow width coefficient 80.0 none
K3b k3b Body effect coefficient of k3 0.0 1/V
W0 w0 Narrow width parameter 2.5e-6 m
Nlx nlx Lateral non-uniform doping 1.74e-7 m
parameter
Vbm vbm Maximum applied body bias in -3.0 V
Vth calculation
Dvt0 dvt0 first coefficient of short-chan- 2.2 none
nel effect on Vth
Dvt1 dvt1 Second coefficient of short- 0.53 none
channel effect on Vth
Dvt2 dvt2 Body-bias coefficient of short- -0.032 1/V
channel effect on Vth
Dvt0w dvt0w First coefficient of narrow 0 1/m
width effect on Vth for small
channel length
Dvt1w dvtw1 Second coefficient of narrow 5.3e6 1/m
width effect on Vth for small
channel length
Symbols Symbols
used in used in Description Default Unit Note
equation SPICE
Dvt2w dvt2w Body-bias coefficient of narrow -0.032 1/V
width effect for small channel
length
µ0 u0 Mobility at Temp = Tnom
NMOSFET 670.0 cm2/Vs
PMOSFET 250.0
Ua ua First-order mobility degrada- 2.25E-9 m/V
tion coefficient
Ub ub Second-order mobility degrada- 5.87E-19 (m/V)2
tion coefficient
Uc uc Body-effect of mobility degra- mobMod m/V2
dation coefficient =1, 2:
-4.65e-11
mobMod
=3:
-0.046 1/V
Symbols Symbols
used in used in Description Default Unit Note
equation SPICE
Rdsw rdsw Parasitic resistance per unit 0.0 Ω-µmWr
width
Prwb prwb Body effect coefficient of Rdsw 0 V-1/2
Prwg prwg Gate bias effect coefficient of 0 1/V
Rdsw
Wr wr Width Offset from Weff for Rds 1.0 none
calculation
Wint wint Width offset fitting parameter 0.0 m
from I-V without bias
Lint lint Length offset fitting parameter 0.0 m
from I-V without bias
dWg dwg Coefficient of Weff’s gate 0.0 m/V
dependence
dWb dwb Coefficient of Weff’s substrate 0.0 m/V1/2
body bias dependence
Voff voff Offset voltage in the subthresh- -0.08 V
old region at large W and L
Nfactor nfactor Subthreshold swing factor 1.0 none
Eta0 eta0 DIBL coefficient in subthresh- 0.08 none
old region
Etab etab Body-bias coefficient for the -0.07 1/V
subthreshold DIBL effect
Dsub dsub DIBL coefficient exponent in drout none
subthreshold region
Cit cit Interface trap capacitance 0.0 F/m2
Cdsc cdsc Drain/Source to channel cou- 2.4E-4 F/m2
pling capacitance
Symbols Symbols
used in used in Description Default Unit Note
equation SPICE
Cdscb cdscb Body-bias sensitivity of Cdsc 0.0 F/Vm2
Cdscd cdscd Drain-bias sensitivity of Cdsc 0.0 F/Vm2
Pclm pclm Channel length modulation 1.3 none
parameter
Pdiblc1 pdiblc1 First output resistance DIBL 0.39 none
effect correction parameter
Pdiblc2 pdiblc2 Second output resistance DIBL 0.0086 none
effect correction parameter
Pdiblcb pdiblcb Body effect coefficient of 0 1/V
DIBL correction parameters
Drout drout L dependence coefficient of the 0.56 none
DIBL correction parameter in
Rout
Pscbe1 pscbe1 First substrate current body- 4.24E8 V/m
effect parameter
Pscbe2 pscbe2 Second substrate current body- 1.0E-5 m/V nI-3
effect parameter
Pvag pvag Gate dependence of Early volt- 0.0 none
age
δ delta Effective Vds parameter 0.01 V
Ngate ngate poly gate doping concentration 0 cm-3
α0 alpha0 The first parameter of impact 0 m/V
ionization current
α1 alpha1 Isub parameter for length scal- 0.0 1/V
ing
β0 beta0 The second parameter of impact 30 V
ionization current
Symbols Symbols
used in used in Description Default Unit Note
equation SPICE
Rsh rsh Source drain sheet resistance in 0.0 Ω/
ohm per square square
Js0sw jssw Side wall saturation current 0.0 A/m
density
Js0 js Source drain junction saturation 1.0E-4 A/m2
current per unit area
ijth ijth Diode limiting current 0.1 A nI-3
Symbols Symbols
used in used in Description
equation SPICE Default Unit Note
Xpart xpart Charge partitioning flag 0.0 none
CGS0 cgso Non LDD region source-gate calculated F/m nC-1
overlap capacitance per
channel length
CGD0 cgdo Non LDD region drain-gate calculated F/m nC-2
overlap capacitance per
channel length
CGB0 cgbo Gate bulk overlap capaci- 0.0 F/m
tance per unit channel length
Cj cj Bottom junction capacitance 5.0e-4 F/m2
per unit area at zero bias
Symbols Symbols
used in used in Description
equation SPICE Default Unit Note
Mj mj Bottom junction capacitance 0.5
grating coefficient
Mjsw mjsw Source/Drain side wall junc- 0.33 none
tion capacitance grading coef-
ficient
Cjsw cjsw Source/Drain side wall junc- 5.E-10 F/m
tion capacitance per unit area
Cjswg cjswg Source/drain gate side wall Cjsw F/m
junction capacitance grading
coefficient
Mjswg mjswg Source/drain gate side wall Mjsw none
junction capacitance grading
coefficient
Pbsw pbsw Source/drain side wall junc- 1.0 V
tion built-in potential
Pb pb Bottom built-in potential 1.0 V
Pbswg pbswg Source/Drain gate side wall Pbsw V
junction built-in potential
CGS1 cgs1 Light doped source-gate 0.0 F/m
region overlap capacitance
CGD1 cgd1 Light doped drain-gate region 0.0 F/m
overlap capacitance
CKAPPA ckappa Coefficient for lightly doped 0.6 V
region overlap
capacitance Fringing field
capacitance
Cf cf fringing field capacitance calculated F/m nC-3
CLC clc Constant term for the short 0.1E-6 m
channel model
CLE cle Exponential term for the short 0.6 none
channel model
Symbols Symbols
used in used in Description
equation SPICE Default Unit Note
DLC dlc Length offset fitting parame- lint m
ter from C-V
DWC dwc Width offset fitting parameter wint m
from C-V
Vfbcv vfbcv Flat-band voltage parameter -1 V
(for capMod=0 only)
noff noff CV parameter in Vgsteff,CV 1.0 none nC-4
for weak to strong inversion
voffcv voffcv CV parameter in Vgsteff,CV 0.0 V nC-4
for week to strong inversion
acde acde Exponential coefficient for 1.0 m/V nC-4
charge thickness in capMod=3
for accumulation and deple-
tion regions
moin moin Coefficient for the gate-bias 15.0 none nC-4
dependent surface potential
Symbols Symbols
used in used in Description Default Unit Note
equation SPICE
Elm elm Elmore constant of the channel 5 none
Symbols Symbols
used in used in Description Default Unit Note
equation SPICE
Wl wl Coefficient of length depen- 0.0 mWln
dence for width offset
Symbols Symbols
used in used in Description Default Unit Note
equation SPICE
Symbols Symbols
used in used in Description Default Unit Note
equation SPICE
oC
Tnom tnom Temperature at which parame- 27
ters are extracted
Symbols Symbols
used in used in Description Default Unit Note
equation SPICE
Symbols Symbols
used in used in Description Default Unit Note
equation SPICE
tpb tpb Temperature coefficient of Pb 0.0 V/K
tpbsw tpbsw Temperature coefficient of 0.0 V/K
Pbsw
tpbswg tpbswg Temperature coefficient of 0.0 V/K
Pbswg
tcj tcj Temperature coefficient of Cj 0.0 1/K
tcjsw tcjsw Temperature coefficient of 0.0 1/K
Cjsw
tcjswg tcjswg Temperature coefficient of 0.0 1/K
Cjswg
Symbols Symbols
used in used in Description Default Unit Note
equation SPICE
Noia noia Noise parameter A (NMOS) 1e20 none
(PMOS) 9.9e18
Noib noib Noise parameter B (NMOS) 5e4 none
(PMOS) 2.4e3
Noic noic Noise parameter C (NMOS) -1.4e- none
12
(PMOS) 1.4e-12
Em em Saturation field 4.1e7 V/m
Symbols Symbols
used in used in Description Default Unit Note
equation SPICE
Af af Flicker noise exponent 1 none
Ef ef Flicker noise frequency 1 none
exponent
Kf kf Flicker noise coefficient 0 none
LINTNOI lintnoi Length Reduction Parameter 0.0 m
Offset
Symbols Symbols
used in used in Description Default Unit Note
equation SPICE
Tox tox Gate oxide thickness 1.5e-8 m
Toxm toxm Tox at which parameters are Tox m nI-3
extracted
Xj xj Junction Depth 1.5e-7 m
Symbols Symbols
used in used in Description Default Unit Note
equation SPICE
Lmin lmin Minimum channel length 0.0 m
Vth 0 = VFB + Φ s + K1 Φ s
VFB = Vth0 − Φs − K1 Φs
K1 = γ 2 − 2 K 2 Φ s − Vbm
(γ1 − γ 2 )( Φs −Vbx − Φs )
K2 =
(
2 Φs Φs −Vbm − Φs + Vbm )
where Φ s is calculated by
Nch
Φ s = 2Vtm0 ln
ni
k BTnom
Vtm 0 =
q
1 .5
Tnom Eg 0
ni = 1.45 × 10 10
exp 21 .5565981 −
300 .15 2Vtm 0
2
7.02 × 10−4 Tnom
Eg 0 = 1.16 −
Tnom + 1108
nI-3.
γ 1 2 C ox 2
N ch =
2 q ε si
If both γ and Nch are not given, Nch defaults to 1.7e23 m-3 and γ is
calculated from Nch.
2qε si N ch
γ1 =
Cox
2qε si N sub
γ2 =
Cox
2
qN ch X t
= Φ s − Vbx
2ε si
2ε ox 4 × 10 −7
CF = ln 1 +
π Tox
nC-4.
If (acde < 0.4) or (acde > 1.6), a warning message will be given.
If (moin < 5.0) or (moin > 25.0), a warning message will be given.
If (noff < 0.1) or (noff > 4.0), a warning message will be given.
If (voffcv < -0.5) or (voffcv > 0.5), a warning message will be given.
Vth0ox = Vth0 − K1 ⋅ Φ s
Tox
K 1ox = K 1 ⋅
Toxm
Tox
K2ox = K 2 ⋅
Toxm
2ε si( Φs − Vbseff )
Xdep =
qN ch
2 εsi Φs
Xdep 0 =
qNch
(δ1=0.001)
Vbseff = Vbc + 0.5[Vbs − Vbc − δ 1 + (Vbs − Vbc − δ1) 2 − 4δ1Vbc ]
K
2
Vbc = 0. 9 Φ s − 1 2
4K 2
NchNDS
Vbi = vt ln( 2
)
ni
Vgs − Vth
2 n v t ln 1 + exp(
2 n vt
)
Vgsteff =
2Φs Vgs − Vth − 2 Voff
1 + 2 n COX exp( − )
qεsiNch 2 n vt
εsi
Cd =
Xdep
B.1.3 Mobility
For mobMod=1
µo
µeff =
Vgsteff + 2Vth Vgsteff + 2Vth 2
1 + (Ua + Uc Vbseff )( ) + U b( )
TOX TOX
For mobMod=2
µo
µeff =
Vgsteff Vgsteff 2
1 + (U a + UcVbseff )( ) + Ub ( )
TOX TOX
For mobMod=3
µo
µeff =
Vgsteff + 2 Vth Vgsteff + 2Vth 2
1 + [Ua ( ) + U b( ) ](1 + UcVbseff )
TOX TOX
− b − b 2 − 4 ac
Vdsat =
2a
1
a = A bulk 2Weff νsatCoxR DS + ( − 1) A bulk
λ
2
b = − (V gsteff + 2 v t )( − 1) + A bulkE satL eff + 3 Abulk (Vgsteff + 2 vt )WeffνsatC oxR D S
λ
λ = A1Vgsteff + A2
2
K1ox A0Leff Leff B0 1
Abulk = 1+ 1− AgsVgsteff + ⋅
2 Φs −Vbseff Leff + 2 XJ Xdep L + 2 X J Xdep Weff '+B1 1+ KetaV
eff
bseff
2νsat
E sat =
µeff
B.1.5 Effective V ds
1
(
Vdseff = Vdsat − Vdsat −Vds − δ + (Vdsat −Vds − δ )2 + 4δVdsat
2 )
B.1.6 Drain Current Expression
Ids =
Idso( Vdseff ) 1 + Vds − V dseff 1 + V ds − V dseff
RdsIdso( Vdseff ) VA V ASCBE
1+
Vdseff
Vdseff
WeffµeffCoxVgsteff (1 − Abulk )Vdseff
2 (Vgsteff + 2 v t )
Idso =
Leff [1 + Vdseff / ( EsatLeff )]
PvagVgsteff 1 1
VA = VAsat + (1 + )( + ) −1
E satL eff VACLM VADIBLC
Leff Leff
θrout = PDIBLC 1 exp( − DROUT ) + 2 exp( − DROUT ) + P DIBLC 2
2lt 0 l t 0
AbulkVdsat
EsatLeff + Vdsat + 2 RDSνsatCox WeffVgsteff [1 − ]
2(Vgsteff + 2vt )
VAsat =
2 / λ − 1 + RDSνsatCoxWeffAbulk
ε si Tox X j
litl =
ε ox
α 0 + α 1 ⋅ L eff β0 V ds − V dseff
I sub = (V ds − V dseff )exp −
Vds − Vdseff
I ds 0
1 +
L eff 1 + R ds I ds0 VA
Vdseff
2
1 Ngate
qN poly X poly
V poly = X poly E poly =
2 2 ε si
a (V gs − V FB − Φ s − V poly ) − V poly = 0
2
ε ox
2
a=
2qε si N gateTox
2
L eff = L drawn − 2 dL
(
dW = dW '+dWgVgsteff + dWb Φ s −Vbseff − Φ s )
Wl Ww W
dW ' = Wint + W ln
+ Wwn + W ln wl Wwn
L W L W
Ll Lw L
dL = Lint + L ln
+ Lwn + L ln wl Lwn
L W L W
B.1.10Source/Drain Resistance
Rds =
( (
Rdsw 1 + PrwgVgsteff + Prwb Φ s − Vbseff − Φ s ))
(10 W ')
6
eff
Wr
B.1.11Temperature Effects
T µte
µo(T ) = µo(Tnorm)( )
Tnorm
T
R dsw( T ) = Rdsw( Tnorm) + Pr t ( − 1)
Tnorm
Qoverlap,s
= CGS0Vgs
Wactive
If Vgs < 0
Else
Qoverlap ,s
= (CGS 0 + CKAPPA⋅ CGS1) ⋅ V gs
Wactive
2
Qoverlap , d
= CGD0Vgd
Wactive
If Vgd < 0
Else
Qoverlap ,d
= (CGD 0 + CKAPPA ⋅ CGD1) ⋅ V gd
W active
2
(
Q overlap,g = − Qoverlap,s + Qoverlap, d )
(1) capMod = 0
Qsub = −Qg
Qinv = 0
Qg = −Qb
Qinv = 0
Vgs − Vth
Vdsat,cv =
Abulk '
CLC CLE
Abulk ' = Abulk 0 1 +
Leff
A0 Leff B0
Abulk0 = 1 +
K1ox 1
+ ⋅
2 Φ s − Vbseff L +2 X X Weff '+B1 1 + KetaVbseff
eff J dep
2
Vds
Qg = CoxWactiveLactive Vgs − Vfbcv − Φs − +
Abulk'Vds
2 Abulk'Vds
12Vgs −Vth −
2
otherwise
Vdsat
Qg = Wactive Lactive Cox (Vgs − Vfb − Φs − )
3
1
Qs = Qd = − Wactive Lactive Cox (Vgs − Vth )
3
Qd = −WactiveLactive Cox
(Vgs − Vth)2 Abulk ' Vds(Vgs − Vth ) ( Abulk ' Vds) 2
Vgs − Vth Abulk ' Abulk ' Vds [ − +
− Vds + 6 8 40
2 2 A '
(Vgs − Vth − bulk Vds )2
2
Q s = −( Qg + Q b + Qd )
otherwise
Vdsat
Qg = Wactive Lactive Cox (Vgs − Vfb − Φs − )
3
4
Qd = − W L Cox (Vgs − Vth )
15 active active
Qs = − ( Qg + Qb + Qd )
if Vd s < Vdsat
Vgs − Vth Abulk ' ( Abulk ' Vds) 2
Qd = −Wactive Lactive Cox + Vds −
2 4 A '
24(Vgs − Vth − bulk Vds )
2
Q s = −( Qg + Q b + Qd )
otherwise
Vdsat
Qg = Wactive Lactive Cox (Vgs − Vfb − Φs − )
3
Qd = 0
Qs = − (Qg + Qb )
(2) capMod = 1
where the bias dependences of Vth given in Section B.1.1 are not
considered in calculating Vfb for capMod = 1.
else
Qg 1 = WactiveLactiveCox ⋅
K1ox
2
(
4 V − V fb − Vgsteff, CV − Vbseff
− 1 + 1 + gs
)
2
2
K1 ox
Qb 1 = −Qg 1
Vgsteffcv
Vdsat,cv =
Abulk '
CLC CLE
A bulk '= A bulk0 1 +
L eff
A0 Leff B0
Abulk 0 = 1 +
K1ox 1
+ ⋅
2 Φs − Vbseff L +2 X X Weff '+B1 1 + KetaVbseff
eff J dep
V − V th − voffcv
V gsteff,cv = noff ⋅ nvt ln 1 + exp gs
noff ⋅ nvt
if (Vds <=Vdsat)
Vds Abulk ' Vds 2
Qg = Qg 1 + Wactive Lactive Cox Vgsteff cv − +
2 Abulk '
12 Vgsteff cv − Vds
2
1− A ' 2
(1 − Abulk ' ) Abulk ' Vds
Qb = Qb 1 + Wactive Lactive Cox bulk
Vds −
12 Vgsteffcv − bulk Vds
2 A '
2
W active L active C ox A bulk ' A bulk ' 2 V ds 2
Qs = Qd = − V gsteff cv − V ds +
2 2 A bulk '
1 2 V gsteffcv − Vd s
2
Qd = −( Qg + Qb + Qs)
V
( bulk ds )
2
Abulk ' Vds A ' V
Qs = −Wactive Lactive Cox gstefcv
+ −
2 4 Abulk '
24 Vgsteffcv − Vds
2
Qd = −( Qg + Qb + Qs)
Vdsat
Qg = Q g 1 + Wactive Lactive C ox Vgsteff cv −
3
2Wactive LactiveCox
Qs = − Vgsteffcv
5
Qd = −( Qg + Qb + Qs)
2Vgstefcv
Qs = −Wactive Lactive Cox
3
Qd = −( Qg + Qb + Qs)
(3) capMod = 2
where the bias dependences of Vth given in Section B.1.1 are not
considered in calculating Vfb for capMod = 2.
Q inv = Q s + Q d
VFBeff = vfb − 05 {
. V3 + V32 + 4δ 3vfb } where V3 = vfb − Vgb − δ 3 ; δ 3 = 0.02
(
Qacc = −Wactive Lactive Cox VFBeff − vfb )
K1ox
2
4(V gs − V FBeff − V gsteff,CV − Vbseff )
Qsub0 = −WactiveL activeC ox ⋅ −1 + 1 +
2 K 1ox
2
Vgsteff,cv
V dsat , cv =
gstefcvf
A bulk '
CLC CLE
Abulk ' = Abulk 0 1 +
L active
A0 Leff B0
Abulk 0 = 1 +
K1ox 1
+ ⋅ 1 + KetaV
2 Φs − Vbseff L + 2 X X W '+ B
eff J dep eff 1
bseff
{
Vcveff = Vdsat, cv − 0.5 V4 + V42 + 4δ 4Vdsat, cv } where V4 = Vdsat,cv − Vds − δ 4 ; δ 4 = 0.02
2 2
Qinv = −Wactive Lactive Cox Vgsteff cv −
Abulk '
V +
A bulk ' Vcveff
2 cveff Abulk '
12Vgsteff cv − Vcveff
2
( − ) 2
1 − A ' 1 A ' A ' V
δQsub = Wactive L active C ox Vcveff −
bulk bulk bulk cveff
2 Abulk '
12 Vgsteffcv − Vcveff
2
2
Abulk ' Vcveff 2
Wactive Lactive Cox Abulk '
Qs = Qd = 05
. Qinv = − V cv − Vcveff +
2 gsteff 2 A
12Vgsteffcv − bulk Vcveff
2
( ) ( ) ( )
Wactive LactiveCox 4 2 2 2 3
Qs = − 2Vgsteffcv 3 − Vgsteffc
gstefcvf Abulk ' Vcveff + Vgsteff Abulk ' Vcveff
2
− Abulk' Vcveff
A ' 3 3 15
2Vgsteff cv − bulk Vcveff
2
3
WactiveLactiveCox 5
( ) ( ) 1
( )
2
Qd = − 2 Vgsteffcv − Vgsteffc
3
gsteff cv Abulk ' Vcveff + Vgsteff cv Abulk ' Vcveff
2
− Abulk ' Vcveff
A ' 3 5
2Vgsteffcv − bulk Vcveff
2
Vgsteffcv A ' V
Qs = −Wactive Lactive Cox
gstefcvf
+
bulk cveff
−
A bulk ' Vcveff
2
(
)
2 4 Abulk '
24 Vgsteffcv − Vcveff
2
V ( )
2
3A ' V A ' V
Qd = − Wactive Lactive Cox gsteffcv
−
bulk cveff
+
bulk cveff
2 4 Abulk '
8 Vgsteffcv − Vcveff
2
V gbacc =
1
2
[
⋅ V0 + V 02 + 4δ 3 V fb ]
V0 = V fb + Vbseff − Vgs − δ 3
{
VFBeff = vfb − 05
. V3 + V32 + 4δ 3vfb } where V3 = vfb − Vgb − δ 3; δ 3 = 0.02
Cox Ccen
Coxeff =
Cox + Ccen
Ccen = ε si X
DC
K1ox
2 4(Vgs − VFBeff − Vbseffs− Vgsteff,cv )
Qsub0 = −WLCoxeff ⋅ ⋅ -1 + 1 +
2 K1ox2
V cveff = Vdsat −
1
2
(
⋅ V1 + V12 + 4δ 3V dsat )
V1 = Vdsat − Vds − δ 3
V gsteff , cv − ϕ δ
V dsat =
Abulk '
1
2 2
Abulk' Vcveff
Qinv = −WLCoxeff ⋅ Vgsteff,cv − ϕδ − Abulk'Vcveff +
2 Abulk'Vcveff
12 ⋅ Vgsteff,cv − ϕδ −
2
1 − A ' (1 − Abulk ') ⋅ Abulk 'Vcveff
2
δQ sub = WLC oxeff ⋅ bulk
Vcveff −
2 Abulk ' Vcveff
12 ⋅ V gsteff ,cv − ϕ δ −
2
1 WLC 1 A ' 2 2
V
QS = QD = Qinv = −
oxeff
Vgsteff,cv −ϕδ − Abulk'Vcveff + bulk cveff
2 2 2 Abulk'Vcveff
12⋅ Vgsteff,cv −ϕδ −
2
WLCoxeff 1
2 2
Abulk' Vcveff
QS = − ⋅ Vgsteff,cv −ϕδ + Abulk'Vcveff −
2 2 Abulk'Vcveff
12⋅ Vgsteff,cv −ϕδ −
2
WLCoxeff 3
2 2
Abulk' Vcveff
QD = − ⋅ Vgsteff, cv − ϕδ − Abulk 'Vcveff +
2 2 Abulk'Vdveff
4 ⋅ Vgsteff,cv − ϕδ −
2
[1] G.S. Gildenblat, VLSI Electronics: Microstructure Science, p.11, vol. 18, 1989.
[2] Muller and Kamins, Devices Electronics for Integrated Circuits, Second Edition.
[4] J.A. Greenfield and R.W. Dutton, "Nonplanar VLSI Device Analysis Using the
Solution of Poisson's Equation," IEEE Trans. Electron Devices, vol. ED-27, p.1520,
1980.
[5] H.S. Lee. "An Analysis of the Threshold Voltage for Short-Channel IGFET's," Solid-
State Electronics, vol.16, p.1407, 1973.
[7] T. Toyabe and S. Asai, "Analytical Models of Threshold Voltage and Breakdown
Voltage of Short-Channel MOSFET's Derived from Two-Dimensional Analysis,"
IEEE J. Solid-State Circuits, vol. SC-14, p.375, 1979.
[8] D.R. Poole and D.L. Kwong, "Two-Dimensional Analysis Modeling of Threshold
Voltage of Short-Channel MOSFET's," IEEE Electron Device Letter, vol. ED-5,
p.443, 1984.
[10] Z.H. Liu, C. Hu, J.H. Huang, T.Y. Chan, M.C. Jeng, P.K. Ko, and Y.C. Cheng,
"Threshold Voltage Model For Deep-Submicrometer MOSFETs," IEEE Tran.
Electron Devices, vol. 40, pp. 86-95, Jan., 1993.
[11] Y.C. Cheng and E.A. Sullivan, "Effect of Coulombic Scattering on Silicon Surface
Mobility," J. Appl. Phys. 45, 187 (1974).
[12] Y.C. Cheng and E.A. Sullivan, Surf. Sci. 34, 717 (1973).
[13] A.G. Sabnis and J.T. Clemens, "Characterization of Electron Velocity in the Inverted
<100> Si Surface," Tech. Dig.- Int. Electron Devices Meet., pp. 18-21 (1979).
[14] G.S. Gildenblat, VLSI Electronics: Microstructure Science, p. 11, vol. 18, 1989.
[15] M.S. Liang, J.Y. Choi, P.K. Ko, and C. Hu, "Inversion-Layer Capacitance and
Mobility of Very Thin Gate-Oxide MOSFET's," IEEE Trans. Electron Devices, ED-
33, 409, 1986.
[16] F. Fang and X. Fowler, "Hot-electron Effects and Saturation velocity in Silicon
Inversion Layer," J. Appl. Phys., 41, 1825, 1969.
[19] K.Y. Toh, P.K. Ko and R.G. Meyer, "An Engineering Model for Short-channel MOS
Devices," IEEE Jour. of Solid-State Circuits, vol. 23, No. 4, Aug. 1988.
[20] C. Hu, S. Tam, F.C. Hsu, P.K. Ko, T.Y. Chan and K.W. Kyle, "Hot-Electron Induced
MOSFET Degradation - Model, Monitor, Improvement," IEEE Tran. on Electron
Devices, Vol. 32, pp. 375-385, Feb. 1985.
[21] F.C. Hsu, P.K. Ko, S. Tam, C. Hu and R.S. Muller, "An Analytical Breakdown
Model for Short-Channel MOSFET's," IEEE Trans. on Electron Devices, Vol.ED-
29, pp. 1735, Nov. 1982
[23] M. Shur, T.A. Fjeldly, T. Ytterdal, and K. Lee, “A Unified MOSFET Model,”Solid-
State Electron., 35, pp. 1795-1802, 1992.
[25] C. F. Machala, P. C. Pattnaik and P. Yang, "An Efficient Algorithms for the
Extraction of Parameters with High Confidence from Nonlinear Models," IEEE
Electron Device Letters, Vol. EDL-7, no. 4, pp. 214-218, 1986.
[26] Y. Tsividis and K. Suyama, “MOSFET Modeling for Analog Circuit CAD: Problems
and Prospects,”Tech. Dig. vol. CICC-93, pp. 14.1.1-14.1.6, 1993.
[28] D. S. Jeon, et al, IEEE Tran. on Electron Devices, vol. ED-36, no. 8, pp1456-1463,
1989.
[30] P. Gray and R. Meyer, Analysis and Design of Analog Integrated Circuits, Second
Edition.
[31] R. Rios, N. D. Arora, C.-L. Huang, N. Khalil, J. Faricelli, and L. Gruber, “A physical
compact MOSFET model, including quantum mechanical effects, for statistical
circuit design applications”, IEDM Tech. Dig., pp. 937-940, 1995.
[32] Weidong Liu, Xiaodong Jin, Ya-Chin King, and Chenming Hu, “An efficient and
accurate compact model for thin-oxide-MOSFET intrinsic capacitance considering
the finite charge layer thickness”, IEEE Trans. on Electron Devices, vol. ED-46,
May, 1999.
[33] Mansun Chan, et al, "A Relaxation time Approach to Model the Non-Quasi-Static
Transient Effects in MOSFETs," IEDM, 1994 Technical Digest, pp. 169-172, Dec.
1994.
[36] K.K. Hung et al, “A Unified Model for the Flicker Noise in Metal-Oxide
Semiconductor Field-Effect Transistors,” IEEE Transactions on Electron Devices,
vol. 37, no. 3, March 1990.
[37] T.P. Tsividis, Operation and Modeling of the MOS Transistor, McGraw-Hill,
New York, 1987.
Below is the information on parameter binning regarding which model parameters can or
cannot be binned. All those parameters which can be binned follow this implementation:
PL P PP
P = P0 + + W +
Leff Weff Leff ×Weff
For example, for the parameter k1: P0 = k1, PL = lk1, PW = wk1, PP = pk1. binUnit is a
bining unit selector. If binUnit = 1, the units of Leff and W eff used in the binning equation
above have the units of microns; therwise in meters.
For example, for a device with Leff = 0.5µm and W eff = 10µm. If binUnit = 1, the parameter
values for vsat are 1e5, 1e4, 2e4, and 3e4 for vsat, lvsat, wvsat, and pvsat, respectively.
Therefore, the effective value of vsat for this device is
To get the same effective value of vsat for binUnit = 0, the values of vsat, lvsat, wvsat, and
pvsat would be 1e5, 1e-2, 2e-2, 3e-8, respectively. Thus,
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
None level The model selector NO
None version Model version selector NO
None binUnit Bining unit selector NO
None param- Parameter value check NO
Chk
mobMod mobMod Mobility model selector NO
capMod capMod Flag for the short channel NO
capacitance model
nqsMod nqsMod Flag for NQS model NO
noiMod noiMod Flag for Noise model NO
D.2 DC Parameters
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
Vth0 vth0 Threshold voltage @Vbs =0 for YES
Large L.
VFB vfb Flat band voltage YES
K1 k1 First order body effect coeffi- YES
cient
K2 k2 Second order body effect coef- YES
ficient
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
K3 k3 Narrow width coefficient YES
K3b k3b Body effect coefficient of k3 YES
W0 w0 Narrow width parameter YES
Nlx nlx Lateral non-uniform doping YES
parameter
Dvt0 dvt0 first coefficient of short-chan- YES
nel effect on Vth
Dvt1 dvt1 Second coefficient of short- YES
channel effect on Vth
Dvt2 dvt2 Body-bias coefficient of short- YES
channel effect on Vth
Dvt0w dvt0w First coefficient of narrow YES
width effect on Vth for small
channel length
Dvt1w dvtw1 Second coefficient of narrow YES
width effect on Vth for small
channel length
Dvt2w dvt2w Body-bias coefficient of narrow YES
width effect for small channel
length
µ0 u0 Mobility at Temp = Tnom
NMOSFET YES
PMOSFET
Ua ua First-order mobility degrada- YES
tion coefficient
Ub ub Second-order mobility degrada- YES
tion coefficient
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
Uc uc Body-effect of mobility degra- YES
dation coefficient
νsat vsat Saturation velocity at Temp = YES
Tnom
A0 a0 Bulk charge effect coefficient YES
for channel length
Ags ags gate bias coefficient of Abulk YES
B0 b0 Bulk charge effect coefficient YES
for channel width
B1 b1 Bulk charge effect width offset YES
Keta keta Body-bias coefficient of bulk YES
charge effect
A1 a1 First non0saturation effect YES
parameter
A2 a2 Second non-saturation factor YES
Rdsw rdsw Parasitic resistance per unit YES
width
Prwb prwb Body effect coefficient of Rdsw YES
Prwg prwg Gate bias effect coefficient of YES
Rdsw
Wr wr Width Offset from Weff for YES
Rds calculation
Wint wint Width offset fitting parameter NO
from I-V without bias
Lint lint Length offset fitting parameter NO
from I-V without bias
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
dWg dwg Coefficient of Weff’s gate YES
dependence
dWb dwb Coefficient of Weff’s substrate YES
body bias dependence
Voff voff Offset voltage in the subthresh- YES
old region for large W and L
Nfactor nfactor Subthreshold swing factor YES
Eta0 eta0 DIBL coefficient in subthresh- YES
old region
Etab etab Body-bias coefficient for the YES
subthreshold DIBL effect
Dsub dsub DIBL coefficient exponent in YES
subthreshold region
Cit cit Interface trap capacitance YES
Cdsc cdsc Drain/Source to channel cou- YES
pling capacitance
Cdscb cdscb Body-bias sensitivity of Cdsc YES
Cdscd cdscd Drain-bias sensitivity of Cdsc YES
Pclm pclm Channel length modulation YES
parameter
Pdiblc1 pdiblc1 First output resistance DIBL YES
effect correction parameter
Pdiblc2 pdiblc2 Second output resistance DIBL YES
effect correction parameter
Pdiblcb pdiblcb Body effect coefficient of YES
DIBL correction parameters
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
Drout drout L dependence coefficient of the YES
DIBL correction parameter in
Rout
Pscbe1 pscbe1 First substrate current body- YES
effect parameter
Pscbe2 pscbe2 Second substrate current body- YES
effect parameter
Pvag pvag Gate dependence of Early volt- YES
age
δ delta Effective Vds parameter YES
Ngate ngate poly gate doping concentration YES
α0 alpha0 The first parameter of impact YES
ionization current
α1 alpha1 Isub parameter for length scal- YES
ing
β0 beta0 The second parameter of impact YES
ionization current
Rsh rsh Source drain sheet resistance in NO
ohm per square
Js0 js Source drain junction saturation NO
current per unit area
ijth ijth Diode limiting current NO
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
Xpart xpart Charge partitioning rate flag NO
CGS0 cgso Non LDD region source-gate NO
overlap capacitance per
channel length
CGD0 cgdo Non LDD region drain-gate NO
overlap capacitance per
channel length
CGB0 cgbo Gate bulk overlap capaci- NO
tance per unit channel length
Cj cj Bottom junction per unit area NO
Mj mj Bottom junction capacitance NO
grating coefficient
Mjsw mjsw Source/Drain side junction NO
capacitance grading coeffi-
cient
Cjsw cjsw Source/Drain side junction NO
capacitance per unit area
Pb pb Bottom built-in potential NO
Pbsw pbsw Source/Drain side junction NO
built-in potential
CGS1 cgs1 Light doped source-gate YES
region overlap capacitance
CGD1 cgd1 Light doped drain-gate region YES
overlap capacitance
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
CKAPPA ckappa Coefficient for lightly doped YES
region overlap
capacitance Fringing field
capacitance
Cf cf fringing field capacitance YES
CLC clc Constant term for the short YES
channel model
CLE cle Exponential term for the short YES
channel model
DLC dlc Length offset fitting parame- YES
ter from C-V
DWC dwc Width offset fitting parameter YES
from C-V
Vfbcv vfbcv Flat-band voltage parameter YES
(for capMod = 0 only)
noff noff CV parameter in Vgsteff,CV YES
for weak to strong inversion
voffcv voffcv CV parameter in Vgsteff,CV YES
for weak to strong inversion
acde acde Exponential coefficient for YES
charge thickness in capMod=3
for accumulation and deple-
tion regions
moin moin Coefficient for the gate-bias YES
dependent surface potential
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
Elm elm Elmore constant of the channel YES
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
Wl wl Coefficient of length depen- NO
dence for width offset
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
Tnom tnom Temperature at which param- NO
eters are extracted
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
tpb tpb Temperature coefficient of Pb NO
tpbsw tpbsw Temperature coefficient of NO
Pbsw
tpbswg tpbswg Temperature coefficient of NO
Pbswg
tcj tcj Temperature coefficient of Cj NO
tcjsw tcjsw Temperature coefficient of NO
Cjsw
tcjswg tcjswg Temperature coefficient of NO
Cjswg
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
Noia noia Noise parameter A NO
Noib noib Noise parameter B NO
Noic noic Noise parameter C NO
Em em Saturation field NO
Af af Flicker noise exponent NO
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
Ef ef Flicker noise frequency NO
exponent
Kf kf Flicker noise parameter NO
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
Tox tox Gate oxide thickness NO
Toxm toxm Tox at which parameters are NO
extracted
Xj xj Junction Depth YES
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
Lmin lmin Minimum channel length NO