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Code No: D5504


R09
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JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M.Tech II SEMESTER EXAMINATIONS, APRIL/MAY-2013
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CPLD AND FPGA ARCHITECTURES AND APPLICATIONS
(EMBEDDED SYSTEMS)
Time: 3hours Max.Marks:60
Answer any five questions
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All questions carry equal marks
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1. Design a 4-bit Majority function generator and implement it with a suitable PAL.

2. With block diagram explain the Macro Cell of Altera 7000 CPLD.
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3.
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Explain, in detail, every block of FLEX 10000 Device.
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4.

5.
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Write down the behavioural model for XC4000 CLB

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Explain the alternative realizations for SM charts using microprogramming with
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suitable examples.

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6. Demonstrate the one-hot state assignment and discuss its advantages using an
example.

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8.
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Discuss the features of Mentor Graphics EDA tool.
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A 4×4 array multiplier is to be implemented using an XC4000 family FPGA.
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Without using the built-in-carry logic, partition the logic so that it fits in a
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required.

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minimum number of logic cells. Draw loops around each set of components that
will fit in a single logic cell. Find the total number of F and G function generators
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