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Applications of Xilinx FPGAs in Space

H. Michalik, B. Fiethe

Institute of Computer and Communication Network Engineering


TU Braunschweig
Data Processing Unit (DPU)

Requirements:
• Mission specific
• Operational radiation tolerance
control
• Specific data
• Adequate reliability
processing • Low volume and mass
• S/C TM/TC • Low power
handling
• Sufficient computing
• Autonomous
sequences power
• Real-time
requirements for high
sensor data rates
• Moderate unit costs

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System-on-Chip Design Approach
Integration of all interfaces and special functions together
with processor system on radiation tolerant qualified FPGA

+ Reduced parts count, reusable


+ No extensive parts qualification, off-the-shelf available
+ Low mass and power
+ Very flexible, re-programmable
+ Common modules, standardized interfaces
+ Very short development time

– SRAM based FPGA configuration is sensible to SEU

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Basic SEU Mitigation
Configuration RAM, logic and memory prone to SEU’s
Reduction of SEU rates to negligible or tolerable values:
• Triple Modular Redundancy (TMR)
• Removal of half-latches in design
• Configuration memory scrubbing
• Error detection in configuration data stream
• Functional testing
• Detection of bus contention
• Cyclic reconfiguration to avoid persistent errors
• Processor watchdog

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Advanced SEU Tolerance

Not only SEU mitigation by additional (external)


measures, but avoid SEU effects by internal design
provisions to increase reliability:
• No dead-time for reconfiguration
• Built-in error correction for configuration, BRAM
(Virtex-4)
• Intelligent TMR
• Processor fault-tolerance

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VMC DPU Parameter
Processor • LEON-2 core (SPARC compatible) in XilinX-1
• 20 MIPS
Memory • 1 Gbit image mass memory (SDRAM) incl. DMA controller
• 16 Mbit SRAM
• 16 Mbit EEPROM (Program memory)
• 64 kbit PROM (Bootloader)
Error Correction • System Supervisor by rad-hard Actel FPGA
• Zero wait state Reed-Solomon single symbol correction for
program and image memory
Interface to S/C RTU & 1355 Spacewire I/F, main & redundant

Volume 250cm3

Power < 3.5 W secondary

Mass 280g

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VMC DPU

Venus Monitoring Camera DPU

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Venus Monitoring Camera

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VMC Verified in Space
• Routine science
operations started
• VMC switched on
>400h
• Only few single
errors in
SRAM/SDRAM
detected
• No indication of
any SEU effect in
FPGA’s

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Application Roadmap

Institute of Computer and Communication Network Engineering


TU Braunschweig
SoC DPU Design Variants
Very high capacity needed, dedicated MCM or ASIC not useful
→ Xilinx Virtex FPGA selected
Approach Fully Embedded Combined
Programmable Cores Hard-wired
Device Virtex Virtex-II Virtex-II Pro Virtex 4
(XC2VP40) (XC4VFX60)
Logic Cells 27,648 76,032 43,632 56,880
On-chip Devices 128kbit BlockRAM 2.5Mbit BlockRAM 3.4Mbit BlockRAM 4Mbit BlockRAM
144 MULTs 192 MULTs 128 XtremeDSP
2 PowerPC 2 PowerPC
12 RocketIO 16 RocketIO
Size [cm2] 18.5 12.3 12.3 12.3
TID [kRad] 100 200 N/A >200 (TBC)
SEL [MeV cm2/mg] 125 160 N/A TBD
Configuration SEU: Testing by IDA in Build-in ECC for
LETth [MeV cm2/mg] 1.2 1 progress configuration and
Cross sec. [cm2/bit] 8E-8 4.4E-8 BlockRAM

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Roadmap (1): Use of Xilinx1
The SoC Approach has been proven by VMC project to
be highly advantageous for space applications
Already implemented further applications are:
- Dawn Framing Camera (Nasa Satellite)
Camera DPU (similiar to VMC but Class S Parts)
- KompSat 2: Korean Earth Observation Satellite
Implementation of high speed CCSDS
communication processor (channel coding +
encyption) within Xilinx 1
- SarLupe: German SAR Satellite:
+ high speed CCSDS communication processor
+ Crypto Coprocessor for authentication

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DAWN FC DPU

Venus Monitoring Camera DPU

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KompSat 2 Communication Processor

Venus Monitoring Camera DPU

© OHB/DSI

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Roadmap (2) Future DPU: Virtex-II/IV with
Embedded Cores
Detector Spacewire
VIRTEX FPGA
I/F Drivers I/F Drivers
Ser. I/F Online
14 14 Pre-Processing Data Mux/ Space DATA
/ / & JPEG2000 Formatting Wire
Data Compression Core Core
Core
S/C
Detector On Chip
Bus System CMD
Supervisor RTU-I/F
Ser. I/F I/F CPU Core (ACTEL FPGA) TLM
Logic (Leon 3)
CTRL

I/F Config. PROM


Logic + EEPROM

Local Bus

Image Memory
Local Memory HK Interface
Buffer
128 Mbit SDRAM (Digital + Analog)
4 Gbit DRAM
8 Mbit EEPROM
(Error Corrected)

Detector Power Conv.


HK HK

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JPEG2000 Compression Core
• Tile size of 128x128 pixels, 14 bits resolution
• 5-level lossless DWT, Tier-1 encoding
• 125MHz on Virtex-II
• Scalable to needed data rate (250 Mbit/s)

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Roadmap (2): Design Drivers for advanced
DPUs (Solar Orbiter)

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Virtex-II Pro DPU Design
Spacewire
VIRTEX-II PRO FPGA
Detector I/F Drivers
or VIRTEX-4
I/F Drivers
Data
Online Online RTE S/C-I/F
Compression Space
Detector Image Pre- Inversion
Core
and Wire
Data I/F Summation Processing
or FPGA Formatting Core
Core Core Core

On Chip
Bus
CPU
Supervisor
Dual PowerPC Core (ACTEL FPGA)
ISS, I/F - real-time processing control
MPM, Logic
CTRL - instrument control
etc.

I/F Config. PROM


Logic + EEPROM

Local Bus

Image Memory
Helioseismic Local Memory
Buffer Thermal Control
Data Storage 256 Mbit SDRAM
8 Gbit DRAM + HK Interface
(EEPROM) 8 Mbit EEPROM
(Error Corrected)

HK Heaters

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Advanced Scalable PDH Architecture
Ultra High Rate Interfaces

Ultra High PDH Generic


Mass
Rate Post-
Memory
Pre-Processing Processing
Sensor Unit
SFU's SFU's

Down Link Transmitter


Data B
... ...
Instruments

internal High Rate network / bus


... ...

High / Medium Dedicated


PDH
Rate Post-
Controller B
Pre-Processing Processing
Unit
SFU's SFU's
Sensor Down Link
Data ... Data

external High Rate network / bus

external Command & Control network / bus

OBDH

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Virtex based Processor Module

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Roadmap (3): Mass Memory Modules
Example TerraSar-X SSMM Module (UFM)
High Speed (up to 2 Gbit/s)
and High Capacity (64/128
Gbit),
• G-Link serial input
interfaces and parallel
output interface
• 64/128 Gbit/Board
(256/512 Mbit SDR-SDRAM
devices)
• appr. 1.6 Gbit/s input
data rate
• appr. 300 Mbit/s output
data rate
• appr. double Eurocard
board size

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Memory Module functional groups
Data Input
16 16
Data I/F Control Memory
Data Drivers
Clk Sync. 32
Logic Array
FIFO
Enable Write
/FF

Sync.
36 36 Error 72 72
FIFO
Correction
Scrub
Data Output
16 16
Data
Clk Sync. Memory Array of
32 64 Gbit User Data
FIFO
Enable
Read
/EF 256 Mbit SDRAM
in 8 high Stacks
Cmd/Status
8 8 CMD I/F 2 Latch-Up Protected
Address
/Data
Memory Partitions
5 5 Address 15 15
ModCtrl
Generator
/Int

+3,3V Power
+5V
Fast 18 18
Distribution Timing &
3 Power
PCmd
Switch Control
PE
PStat FPGA

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Summary
• SRAM based FPGAs are needed for implementation of
advanced applications in space
• Future applications of Virtex II, Virtex IV, Virtex V (?) are in
– SoC DPUs and on Board Processors
– Communication Processors (Digital Radio)
– Mass Memory Control
– etc.
• Main efforts:
– coping with single event effects, failure tolerant design
– radiation characterisation of FPGAs (complex)

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