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Fig. 2. Gate-level schematic of the novel LG_C DET flip-flop using (a) non-
inverting and (b) inverting C-elements.
Fig. 5. Operational waveforms for a generic Latch-MUX flip-flop.
LAPSHEV AND HASAN: NEW LOW GLITCH AND LOW POWER DET FLIP-FLOPS USING MULTIPLE C-ELEMENTS 3
Fig. 11. Gate-level schematic of the FN_C DET flip-flop shown in Fig. 8 with
2 inner 3-input weak C-elements exhibiting a floating-node behavior.
Fig. 12. Simulated signal levels of the FN_C flip-flop implemented in the GF
28HPP technology. The figure illustrates the behavior of the FN_C flip-flop.
Floating states are denoted as “∼”.
LAPSHEV AND HASAN: NEW LOW GLITCH AND LOW POWER DET FLIP-FLOPS USING MULTIPLE C-ELEMENTS 5
Fig. 16. Transistor-level schematic diagrams of the six previous DET flip-flop designs that are considered in this paper for comparison with the presented novel
DET flip-flops. All circuits include input, output, and clock buffering. The flip-flops are (a) LM [9], (b) EP [4], (c) LM_C [7], (d) TSP [10], (e) CP [1], and
(f) IP [3].
is also known as the relative standard deviation (RSD) which The power is measured from the calculated E(t) curve of
is defined as the ratio between standard deviation (SD) and the total dissipated energy versus simulation time. This curve is
mean. In this technology, simulation models make somewhat computed by integrating simulated power supply, data input,
conservative assumptions about sources of variation when per- and clock input currents for each simulated flip-flop in the
forming Monte Carlo analysis on schematic designs. Variations following way:
in physical implementations are expected to be lower than the
ones reported from these simulations. E(t) = VDD
The following parameters were evaluated from Monte Carlo
simulations: 1
× IDD + (ID + |ID | + ICK_in + |ICK_in |) dt. (1)
2
• Power at 10%, 50%, and 100% switching activities P0.1 ,
P0.5 , and P1 respectively. In (1), the power supply current is integrated along with
• Power-delay products PDP0.1 , PDP0.5 , and PDP1 for each the positive currents flowing into the flip-flop’s D and CK_in
of the three power values with the delay being the D-Q inputs. Currents flowing out of the flip-flop’s inputs are dis-
delay. carded. These negative currents are either the result of a weak-
• Maximum CK-Q delay tcq . feedback inverter working against the D input driver, in which
• Worst-case minimum D-Q delay tdq . case the current is supplied by the flip-flop and is thus already
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
LAPSHEV AND HASAN: NEW LOW GLITCH AND LOW POWER DET FLIP-FLOPS USING MULTIPLE C-ELEMENTS 7
TABLE I
S IMULATION R ESULTS OF N OVEL AND P REVIOUSLY R EPORTED DET F LIP -F LOPS IN THE GF 28HPP CMOS T ECHNOLOGY
fewer such transistors because it uses a C-element to perform Considering variations in CK-Q delays, 7 out of 12 DET
the function of the MUX. flip-flops show practically the same CV of 7.7%. Although the
Considering energy dissipation due to glitches, the four worst absolute values of SDs for these flip-flops are quite different,
performing flip-flops are the LM, LM_C, TSP, and IP designs. the fact that these work out to the same RSD shows that these
In these four flip-flops, every change at the input leads to differences have less to do with particular circuit topologies and
switching within internal circuits. The measured G1 and G3 more to do with the technology itself. Monte Carlo simulations
glitch energies for these flip-flops are such that the presence of show a clear trend that higher mean values have higher absolute
multiple glitches at the input leads to glitch energies dominating variations. This trend is also evident in a previous Monte Carlo
the overall power consumption. All five novel flip-flops have analysis of DET flip-flops in [14]. The work in [14] judged the
significantly lower glitch energies. EP design as the best in terms of parameter variations, but it
The novel LG_C and FN_C flip-flops are the only surveyed only considered absolute variations. While it is true that the
flip-flops that have both low P0.1 and low G1 and G3 . The absolute value of the EP’s SD for the D-Q delay is the lowest,
FN_C’s glitch energies are lower than that of LG_C due to its RSD is actually one of the highest.
the absence of static latches at nodes A and B. Energies due to The hold time was found to be positive for all novel flip-
the first glitch in both LG_C and FN_C are high due to switch- flops with the CTF_C achieving the lowest value among them.
ing at one of A or B, yet the energies of subsequent glitches The hold time was also found to be positive for most of the
in the same cycle are considerably lower due to the flip-flops’ previously reported DET flip-flop designs except the TSP as
internal states staying unchanged. This behavior distinguishes shown in Table I.
the proposed LG_C and FN_C flip-flops from Latch-MUX The results of voltage scaling simulations are shown in
flip-flops. Fig. 18. The CK-Q delays of all flip-flops scale in a very similar
Of the three LG_C, IP_C, and FN_C designs, IP_C is the way. The only two flip-flops that scale slightly differently from
fastest while FN_C shows the best overall performance: FN_C others are the CT_C and CTF_C flip-flops. The CK-Q delays
and FN_C (sym) designs show the lowest power, PDP0.5 , of these two flip-flops increase faster with decreased supply
variations, and glitch energies. Comparing the FN_C and FN_C voltage when compared to other flip-flops. The opposite is true
(sym) designs, the latter shows reduced power and reduced as well: Increasing the supply voltage decreases delays in these
delays. The PDP values of FN_C (sym) are 10% better than that flip-flops faster than in other designs. Had the traces of these
of FN_C, which is attributable to the symmetric implementation two flip-flops not been plotted, there would have been no line
of the output C-element having a lower PDP in itself when com- crossings on the plot.
pared to the weak-feedback implementation [15]. Although not
shown in Table I, similar performance gains are also seen when
V. C ONCLUSION
using symmetric C-elements in LG_C and IP_C flip-flops.
Considering the Monte Carlo analysis, LM and FN_C (sym) Five novel DET flip-flop designs have been presented. The
are the two flip-flops that exhibit the lowest variation in their new designs were compared to previous DET flip-flops using
parameters. Relative variations in the CT_C design are the simulation in the 28 nm GF 28HPP CMOS technology. The
highest, which is due to its weak transistors playing a key role in novel LG_C design and its derivatives were shown to signif-
its energy and timing performance parameters. Generally, per- icantly improve on Latch-MUX DET flip-flop designs in the
formance of weak transistors is more susceptible to variations area of energy dissipation due to glitches at the input, which
than that of stronger and wider transistors. makes them useful for designs with large logic depth that are
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
LAPSHEV AND HASAN: NEW LOW GLITCH AND LOW POWER DET FLIP-FLOPS USING MULTIPLE C-ELEMENTS 9
prone to glitching. The novel CT_C and CTF_C designs can Stepan Lapshev received the B.Eng. (Hons) degree
be used in high-performance scenarios as they were found to in mechatronics from Massey University, Auckland,
New Zealand, in 2013. He is currently working to-
have superior power and power-delay products during periods ward the Ph.D. degree in electronics engineering at
of high switching activity. Massey University. His current research interests in-
Extensive Monte Carlo simulations were carried out to clude integrated circuit design, VLSI, and computer
architecture.
demonstrate that the novel flip-flops are robust under process
variations. The new FN_C design was found to be one of
designs least susceptible to process variations. Voltage scaling
simulations were performed that show that the performance of
the presented flip-flops scales very similarly to that of previous
DET flip-flops. S. M. Rezaul Hasan (SM’02) received the Ph.D.
degree in electronics engineering from the Univer-
R EFERENCES sity of California, Los Angeles, CA, USA, in 1985.
From 1983 to 1986, he was a VLSI design engi-
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and clocking strategy for low-power systems,” IEEE Trans. Very Large USA, where he worked in the design of CMOS
Scale Integr. (VLSI) Syst., vol. 13, no. 5, pp. 577–590, May 2005. VLSI microprocessors. In 1986 he moved to the
[2] A. G. M. Strollo, E. Napoli, and C. Cimino, “Analysis of power dissipation Asia-Pacific region and served several institu-
in double edge-triggered flip-flops,” IEEE Trans. Very Large Scale Integr. tions including Nanyang Technological University,
(VLSI) Syst., vol. 8, no. 5, pp. 624–629, Oct. 2000. Singapore (1986–1988), Curtin University of Tech-
[3] P. Zhao, J. McNeely, P. Golconda, M. A. Bayoumi, R. A. Barcenas, and nology, Australia (1990–1991), and Universiti Sains
W. Kuang, “Low-power clock branch sharing double-edge triggered flip- Malaysia, Malaysia (1992–2000). At University Sains Malaysia he held the
flop,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 15, no. 3, position of Associate Professor and was the coordinator of the analog and
pp. 338–345, Mar. 2007. VLSI research laboratory. He spent the next four years (2000–June 2004)
[4] J. Tschanz, S. Narendra, C. Zhanping, S. Borkar, M. Sachdev, and V. De, in the United Arab Emirates where he served as an Associate Professor of
“Comparative delay and energy of single edge-triggered and dual edge- Microelectronics, Integrated Circuit Design & VLSI Design in the Department
triggered pulsed flip-flops for high-performance microprocessors,” Proc. of Electrical & Computer Engineering at the University of Sharjah. While in
Int. Symp. Low Power Electron. Des., 2001, pp. 147–152. Sharjah he received the Sharjah Award for outstanding publication in Integrated
[5] D. E. Muller, “Theory of asynchronous circuits,” Internal Rep. no. 66, Circuit Design. Presently he leads the Analog & VLSI Design Research Group
Digit. Comput. Lab., Univ. Illinois at Urbana-Champaign, 1955. at Massey University, New Zealand, where he is serving as a Senior Faculty
[6] K. van Berkel, “Beware the isochronic fork,” Integr., VLSI J., vol. 13, Member in electronic and computer engineering. He has so far published
pp. 103–128, Jun. 1992. 63 journal and around 100 conference papers in the areas of analog, digital,
[7] S. V. Devarapalli, P. Zarkesh-Ha, and S. C. Suddarth, “A robust and low RF and mixed-signal IC design, and VLSI design, as well as in gene circuit
power dual data rate (DDR) flip-flop using C-elements,” in Proc. 11th Int. design. His present areas of interest include integrated circuit and VLSI design,
Symp. Quality Electron. Des. (ISQED), Mar. 22–24 2010, pp. 147–150. microsystem design, CMOS MEMS, and biological circuit design.