COMPUTER STRUCTURE I – WORKSHOP 03

STUDENT: HASSLER ISAAC ACOSTA

PROFESSOR: EDUARDO ZUREK, PH.D.

SISTEMS ENGINEERING (COMPUTER SCIENCES) DPT. -

UNIVERSIDAD DEL NORTE
SEPTEMBER 07TH – 2017
BARRANQUILLA-COLOMBIA.
General objective:
Implement:
-A RAM memory with 256 8-bit words.

-The inputs have to be taken from the set of switches on the Altera DE2 board. The outputs have to
be shown using the 7-segment displays on the Altera DE2 board.

1) List the variables and/or signals that are related with the solution. Include a description of
the Pin Planner assignments.
The program was run in an Altera DE2-115. CYCLONE IV E-EP4CE115F29C7.

In the pinplanner, the assignments to the input type variables are in the pin type switches and the
output type variables are in the pin type Displays.

The assignments are as follows:

INPUTS DATA_IN SW(4)----------------- RW_Addr(4)

SW(17)----------------- Data_in(7) SW(3)----------------- RW_Addr(3)

SW(16)----------------- Data_in(6) SW(2)----------------- RW_Addr(2)

SW(15)----------------- Data_in(5) SW(1)----------------- RW_Addr(1)

SW(14)----------------- Data_in(4) SW(0)----------------- RW_Addr(0)

SW(13)----------------- Data_in(3) INPUT SW

SW(12)----------------- Data_in(2) SW(8)----------------- Sw (1 to write or 0 to

read)
SW(11)----------------- Data_in(1)
OUTPUTS DISPLAYS
SW(10)----------------- Data_in(0)
HEX5-------------------HEX1(6 downto 0)
INPUTS RW_Addr
HEX4-------------------HEX1(6 downto 0)
SW(7)----------------- RW_Addr(7)
CLOCK INPUT
SW(6)----------------- RW_Addr(6)
Clock-------------------KEY3 button
SW(5)----------------- RW_Addr(5)
2) Explain the VHD code of the solution that generate the expected results. Include comments in
your VHDL code.

library ieee;

use ieee.std_logic_1164.all; libreries

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

--------------------------------------------------------------

entity taller3 is Declaration of variables

port( Clock: in std_logic; Clock variable

Sw: in std_logic; Logical type variable (sw)

RW_Addr: in std_logic_vector(7 downto 0); Vector input 8 bits (rw_addr)

Data_in: in std_logic_vector(7 downto 0); Vector input 8 bits (data_in)

Data_out: out std_logic_vector(7 downto 0); Vector input 8 bits (data_out)

HEX1: out std_logic_vector(6 downto 0); Logic Variable (HEX1)

HEX2: out std_logic_vector(6 downto 0) Logic Variable (HEX2)

);

end taller3;

--------------------------------------------------------------

architecture behav of taller3 is

type ram_type is array (0 to 255) of

std_logic_vector(7 downto 0); Re-declaration of variables in the architecture.

signal tmp_ram: ram_type;

signal sg: std_logic_vector(7 downto 0);

signal sg2: std_logic_vector(7 downto 0);

begin

process(Clock)

begin

if (Clock'event and Clock='1') then IF CLOCK IS ACTIVE

if Sw='0' then IF SW = 0, THEN IT WILL BE READ.

sg <= tmp_ram(conv_integer(RW_Addr)); DATA_OUT VALUE IS ASSIGNED TO A SIGNAL

sg2 <= tmp_ram(conv_integer(RW_Addr)); DATA_OUT VALUE IS ASSIGNED TO A SIGNAL

data_out<= sg;

case sg(7 downto 4) is THE FIRST 4 BITS ARE TAKEN.

when "0000" => HEX1 <= not"0111111";

when "0001" => HEX1 <= not"0000110";

when "0010" => HEX1 <= not"1101101";

when "0011" => HEX1 <= not"1011011";

when "0100" => HEX1 <= not"1100110";

when "0101" => HEX1 <= not"1101101";

when "0110" => HEX1 <= not"1111101";

when "0111" => HEX1 <= not"0000111"; DEPENDING ON THE VALUE OF THE 4 BITS

when "1000" => HEX1 <= not"1111111"; HEX1 IS ASSIGNED IN HEXADECIMAL

when "1001" => HEX1 <= not"1101111";

when "1010" => HEX1 <= not"1110111";

when "1011" => HEX1 <= not"1111100";

when "1100" => HEX1 <= not"0111001";

when "1101" => HEX1 <= not"1011110";

when "1110" => HEX1 <= not"1111001";

when "1111" => HEX1 <= not"1110001";

end case;
case sg2(3 downto 0) is THE LAST 4 BITS ARE TAKEN.

when "0000" => HEX2 <= not"0111111";

when "0001" => HEX2 <= not"0000110";

when "0010" => HEX2 <= not"1101101";

when "0011" => HEX2 <= not"1011011";

when "0100" => HEX2 <= not"1100110";

when "0101" => HEX2 <= not"1101101";

when "0110" => HEX2 <= not"1111101"; DEPENDING ON THE VALUE OF THE 4 BITS

when "0111" => HEX2 <= not"0000111"; HEX2 IS ASSIGNED IN HEXADECIMAL

when "1000" => HEX2 <= not"1111111";

when "1001" => HEX2 <= not"1101111";

when "1010" => HEX2 <= not"1110111";

when "1011" => HEX2 <= not"1111100";

when "1100" => HEX2 <= not"0111001";

when "1101" => HEX2 <= not"1011110";

when "1110" => HEX2 <= not"1111001";

when "1111" => HEX2 <= not"1110001";

end case;

end if;

end if;

end process;

process(Clock)

begin

if (Clock'event and Clock='1') theN IF CLOCK IS ACTIVE

if Sw='1' then IF SW = 1, THEN YOU WILL WRITTE

tmp_ram(conv_integer(RW_Addr)) <= Data_in; INPUT VALUE IS ASSIGNED (8BITS)

end if; TO A DIGITED ADDRESS (8 BITS).

end if;
 end process;

end behav;

3) Simulate the solution using ModelSim.

I can’t simulate the solution with modelSim, I get this error:

4) implement the solution and test it.

EXAMPLE:

In all these examples, I used the direction “0000000”.

Data_in= 11111111, HEX1=1111, HEX2=1111, DISPLAYS=FF.

 Data_in= 11111110, HEX1=1111, HEX2=1110, DISPLAYS=FE.

Data_in= 11111010, HEX1=1111, HEX2=1010, DISPLAYS=FA.

Conclusion: Thanks to this work we can learn more about the uses of the Memory RAM, in addition
to learning how to handle "when" or "case" conditionals, it is likely to serve us in future works.
Bibliographic references:
[1]"DE2-115 board User Manual", ee ryerson, 2011. [Online]. Available:
http://www.ee.ryerson.ca/~courses/coe608/labs/DE2_115_User_Manual.pdf. [Accessed: 11- Aug-
2017].

[2]"CASE Statement", Vhdl-online.de, 2017. [Online]. Available: https://www.vhdl-

online.de/courses/system_design/vhdl_language_and_syntax/sequential_statements/case_state
ment. [Accessed: 25- Aug- 2017].

[3]"VHDL Tutorial: Learn by Example", RAM MODULE, 2017. [Online]. Available:

http://esd.cs.ucr.edu/labs/tutorial/. [Accessed: 7- SEPT- 2017].