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Frequency Response of a Common-Emitter

BJT Amplifier

1 Circuit Topology

The schematic of a typical common-emitter amplifier is shown in figure 1. Capacitors CB and CC are
used to block the amplifier DC bias point from the input and output (AC coupling). Capacitor CE is an
AC bypass capacitor used to establish a low frequency AC ground at the emitter of Q1. Miller capacitor
CF is a small capacitance that will be used to control the high frequency 3-dB response of the amplifier.

Figure 1: Common-emitter BJT amplifier.

1.1 DC Biasing and Mid-band Frequency Response

For this section, assume that CB = CC = CE = 1 Farad and CF = CΠ = Cµ = 0. You can find the DC
collector current (IC) and the resistor values following the analysis provided in your text book. Since
the topology and the requirements might be slightly different than in the text, you will need to make
minor modifications to the design procedure and equations.

1.2 Low Frequency Response

Figure 2 shows the low-frequency small-signal equivalent circuit of the amplifier. Note that CF is

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ignored since it is assumed that its impedance at these frequencies is very high. RB is the parallel
combination of RB1 and RB2.

Figure 2: Low-frequency equivalent circuit.

Using short-circuit time constant analysis, the lower 3-dB frequency (?L) can be found as:

Where

1.3 High Frequency Response

Figure 3 shows the high-frequency small-signal equivalent circuit of the amplifier. At high frequencies,
CB, CC and CE can be replaced with short circuits since their impedance becomes very small compared
to RS, RL and RE.

Figure 3: High-frequency equivalent circuit.

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The higher 3-dB frequency (?H) can be derived as:

Where

Thus, if we assume that the common-emitter amplifier is properly characterized by these dominant
low and high frequency poles, then the frequency response of the amplifier can be approximated by:

2 Pre-Lab

Assuming CB = CC = CE = 1 Farad and CF = CΠ = Cµ = 0, and using a 2N3904 transistor, design a

common-emitter amplifier with the following specifications:

VCC = 5 V
RS = 50?
RL = 1 k?
RIN > 250
Isupply < 8mA
AV > 50
peak-to-peak unclipped output swing > 3 V

1. Show all your calculations, design procedure, and final component values.
2. Verify your results using a circuit simulator (TINA, QUCS, PSpice). Submit all necessary simulation
plots showing that the specifications are satisfied. Also provide the circuit schematic with DC bias
points annotated.
3. Using the simulator, find the higher 3-dB frequency (fH) while CF = 0.
4. Determine Cp, Cµ and rb of the transistor from the simulated operating point data, (refer to your
simulator's documentation on how to obtain operating point data). Calculate fH using the equation
from section 1.3 and compare it with the simulation result obtained in Step 3. Remember that the
equation gives you the radian frequency and you need to convert to Hz.
5. Calculate the value of CF to have fH = 50 kHz. Simulate the circuit to verify your result, and adjust
the value of CF if necessary.
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6. Calculate CB, CC, CE to have fL = 500 Hz. Simulate the circuit to verify your result, and adjust the
values of capacitors if necessary.
7. Be prepared to discuss your design at the beginning of the lab period with your TA.

3 Lab Procedure

Objective:

The objective of this section of the Lab Activity is to validate your pre-Lab design values by building
the actual circuit and measuring its frequency response performance.

Materials:

Analog Discovery Lab hardware\ Solder-less breadboard

6 - Resistors various values from the Analog Parts Kit
4 - Capacitors various values from the Analog Parts Kit
1 - small signal NPN transistor (2N3904)

Note on the source resistor RS and the AWG output in Discovery. The AWG output has a relatively low
output resistance and you will need to include an equivalent external resistance in series with its
output. Also because of the relatively high gain of your design you will need an input signal with a
small amplitude of around 50mV (3 V / 50). Rather than turning down the AWG in software is would be
better from a noise point of view to insert a resistor voltage divider between the AWG output and your
circuit input to attenuate the signal. Using something like that shown in figure 4 will provide both an
attenuation factor of 1/8 and a 60Ω equivalent source resistance. Other combinations of resistor
values are of course also possible based on what you have available.

Figure 4 Signal attenuator with 60Ω source resistance

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Directions:

1. Construct the amplifier, based on the schematic in figure 1, you designed in the pre-lab. Based on
your design values from the pre-Lab, use the closest standard value from your kit. Remember that
you can combine the standard values in series or parallel to get a combined value closer to your
design number.
2. Check your DC operating point by measuring IC, VE, VC and VB. If any DC bias value is significantly
different than the one obtained from simulation, modify your circuit to get the desired DC bias before
moving onto the next step.
3. Measure Isupply.
4. Use the Network analyzer instrument in the Waveforms software to obtain the magnitude of the
frequency response of the amplifier from 10 Hz to as high as 5 MHz and determine the lower and
upper 3-dB frequencies fL and fH.
5. At mid-band frequencies, measure AV, RIN, and ROUT.
6. Measure the maximum un-clipped output signal amplitude.
7. Prepare a data sheet showing your simulated and measured values.
8. Be prepared to discuss your experiment with your TA. Have your lab data sheet checked off by your
TA before submitting the lab report.

For further experimentation replace each capacitor with ones that are factors of 2 and 10 larger and
smaller than your design values and re-measure the response curve with the Network Analyzer
instrument. Do this to only one capacitor at a time to observe its individual effect on the response.
Explain the changes in the response that you see.

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