DEVELOPMENT OF EPICS ENABLED ALARM ANNINCIATION SYSTEM
Anindya Roy†, Partha Pratim Nandy, R. B. Bhole, Sarbajit Pal, Amitava Roy
Variable Energy Cyclotron Centre, Kolkata, India
Abstract
Alarm annunciation system plays a crucial role in the
control systems of large-scale experiments like accelera-
tors, telescopes, superconducting tokamak, etc. It pro-
vides discrete state information of important machine
parameters to the operators as audio-visual alarms. The
time-stamped log of these alarms is a useful tool for fault
analysis in large machines during commissioning and
day-to-day operation. In VECC, an Alarm annunciation
system with embedded EPICS is developed for logging
the time-stamped alarms into control system data archiv-
er. The system is designed as an ARM based master mod-
ule with embedded EPICS IOC connected with multiple
microcontroller based slave modules. The master and
slave modules are connected over SPI bus. The field
alarm signals are connected with slave modules for gene-
rating audio-visual alarms. The communication between
master and slaves are driven by the events generated by
hardware interrupts e.g. field alarm signal, acknowledge
button, reset button. The embedded EPICS IOC is de-
signed for event driven acquisition of alarm states e.g.
FAULT, ACK, OK and RESET from slave modules and to
broadcast the same to the channel access clients e.g. oper-
ator interface, data archiver etc. The detail design and
functional testing of the system is described in this paper.
INTRODUCTION
There are two cyclotrons in VECC i.e. Room Tempera-
ture Cyclotron (K=130) (RTC) and Superconducting
Cyclotron (K=500) (SCC). RTC is being operated round-
the-clock for delivering Alpha and Proton beams at pre-
sent. SCC is under commissioning.
The supervisory control systems of these cyclotrons are
developed using EPICS [1], a standard open-source dual
layer software tool for designing distributed control sys-
tem. The in-house developed control data archiver [2] is
used for logging time stamped data of various control
parameters. An E-Log system is also developed in-house
for time-stamped logging of operators’ messages into the
data archiver. A NTP server is installed to synchronize all
control nodes and data archiver. In this present setup, it is
now possible to extract time correlations among various
events while operating the machines. This information is
a useful tool for fault analysis in a complex machine like
cyclotron. There is also an objective to implement an
Auto inference engine to enhance the fault analysis capa-
bility of the system. However, the above system requires
logging of time stamped sequence of machine faults i.e.
audio-visual alarms in addition to above logs. The alarm
annunciation systems of the cyclotrons are third party
systems. These systems are not equipped for event based
___________________________________________
† r_ani@vecc.gov.in
remote logging of alarms. Hence an alarm annunciation
system with embedded EPICS is designed and developed
in VECC for this purpose.
HARDWARE DESIGN
A modular architecture is adopted for designing the
hardware. The annunciation system consists of one master
module and upto six pluggable slave modules. The master
module communicates over SPI protocol with slave mod-
ules sitting on a common backplane. Each slave module is
designed to acquire 16 alarm signals. Hence, the system is
capable to handle maximum 96 alarms. The novelty of the
design is the use of hardware interrupts for exchanging
alarm data between master and slave modules. This archi-
tecture is adopted to minimise the latency between time of
occurrence and logging of alarm states. The hardware
architecture of the system is shown in Figure 1.
Table 1: Specifications of ARM based SBC
CPU 1 GHz Quad core ARM CPU
OS Debian Linux, Kernel 4.1.15
Memory
DDR-RAM 2 GB
eMMC Flash 4 GB
Micro SD Card 4 GB
Peripherals
USB 2.0 Host (4) / Device (1)
Ethernet 10 / 100 Mbit (1)
Serial SPI and I2C interface
DIO 24 configurable as interrupts
Power 600 mA @ 5 VDC
The master module is developed using ARMv7-A based
Single Board Computer (SBC). The SBC is based on 1
Ghz Quad core NXP i.MX6 Cortex-A9 ARM CPU. Its
detailed specifications are listed in Table 1. The SBC is
configured to boot SD card based full featured Debian
Linux (version Jessie Arm, kernel version 4.1.15) distri-
bution including a complete GNU C/C++ embedded de-
velopment environment. There are six dedicated hardware
interrupt inputs assigned to six slave modules. Acknowl-
edge and reset buttons of the annunciation system are also
interfaced with master module through hardware interrupt
inputs.
The slave module is developed using 8-bit AVR micro-
controller. Each module has sixteen discrete inputs to be
interfaced with potential free contacts. On change in in-
put, the slave module interrupts the master and communi-
cates alarm states over SPI to master module. There are
sixteen discrete type latched outputs with buffer for driv-
ing the alarm windows. A jumper based selection is pro-
vided on the slave module for assigning to a particular
master interrupt.
 Figure 1: Hardware configuration of the alarm annunciation system
ducted to measure the processing delay of the annuncia-
SOFTWARE tion system. For this purpose, alarm sequences are simu-
The embedded EPICS Soft-IOC running on master lated simultaneously among the channels of same slave
module is designed to run dedicated thread for handling module and different slave modules. The time stamped
individual interrupt. On interrupt, EPICS IOC callback data is logged into file using EPICS camonitor utility.
task is used to process device support routine for acquir-
ing data from slave. Subsequently, the alarm states of RESULT
individual channels are updated into dedicated EPICS Initially the slave module is designed to send the alarm
process variables using forward link feature. EPICS status of individual channel using 16 bytes over SPI. The
Mutex is used to overcome SPI bus contention due to response time of the system is measured 200 msec for
parallel processing of interrupts. The interrupt based broadcasting the alarms for logging. Consequent investi-
asynchronous processing of records ensures logging of gation reveals that the processing time of interrupt from
alarm state into data archiver with minimum delay. the slave is measured to around 1 msec on master module.
The firmware of slave module is designed to poll its in- Hence, the communication of status bytes over SPI is
puts and generate interrupt to master on any change in responsible for the delay. So the firmware of slave is
state. Individual input can acquire either faulty state or modified to send 4 bytes to master using 2 bits for indi-
healthy state. The output of the module will have either of vidual channel. The response time of the system is re-
four states i.e. fault, acknowledged, reset and healthy duced to 50 msec which is acceptable for cyclotron con-
depending on the condition of input signal and operator trol system.
action. The module is configured to operate in Ringback
sequence as per ISA S18.1 1979(R2004) standard. CONCLUSION
The system is developed and tested in lab, however is
FUNCTIONAL TESTNG not deployed yet. The logging of time-stamped sequence
A dedicated test setup is developed to evaluate the per- of alarms along with operators’ messages and other pa-
formance of the annunciation system. The setup is com- rameters will be a useful tool for regular operation and
prised of a microcontroller based fault simulator and a PC commissioning of the cyclotrons in VECC. The system
for logging time-stamped alarm states using EPICS chan- will also provide necessary information for implementing
nel access interface. The fault simulator is designed to Auto inference engine for fault finding in future.
simulate sixteen field signals, acknowledge and reset
actions. It is programmed to introduce predefined delays REFERENCES
among the channels during testing. [1] EPICS, http://www.aps.anl.gov/epics/
The functional testing is conducted by simulating mul-
tiple faults catering to several slave modules. The system [2] Anindya Roy et.al., “Implementation of EPICS based va-
cuum control system for variable energy cyclotron centre,
is put on for continuous seventy two hours to detect any
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