Digital Circuit Design

ECE 344
Fall 2018

Topic 2
CMOS Inverter

Sameh A. Ibrahim
Ain Shams University
ICL
(Courtesy of H. F. Ragai, Ain Shams University,
J. M. Rabaey, UC Berkeley, A. Chandrakasan, MIT
& B. NiKolic, UC Berkeley )
 Outline

⚫ The CMOS Inverter Noise Margin and Threshold

Voltage
⚫ The CMOS Inverter Propagation Delay and Switching
Speed
⚫ The CMOS Inverter Power Consumption
⚫ Sizing of the CMOS Inverter

CMOS Inverter
2
 The Ideal Inverter

Transfer Function
Gain = 0
Switching waveforms

Gain = ∞

Gain = 0

CMOS Inverter
3
 Noise in Digital Circuits

Power and Ground

Inductive Coupling Capacitive Coupling
Noise

CMOS Inverter
4
 The Real Inverter Transfer Function

VOH
NML
❑ VM = gate threshold voltage (mid-swing)
❑ Noise margins = NML and NMH

Regenerative
NMH

VOL VIL VIH VOH

CMOS Inverter
5
The Real Inverter Switching Waveforms

tPLH , tPHL , tP , tr, tf

VDD =

VSS = 0 V =

VDD =

VSS = 0 V =

Propagation time (or propagation delay time or simply delay time):

tP = (tPLH + tPHL)/2

CMOS Inverter
6
 The CMOS Inverter

N Well VDD

VDD PMOS 2l

Contacts
PMOS
In Out
In Out
Metal 1
Polysilicon
NMOS

NMOS
GND

CMOS Inverter
7
 CMOS Inverter Static Operation (1)

+ +
0 pull-up
VDD
to VDD
_ _

+ +
pull-down
to GND 0
VDD _
_

vI = VDD, QN  ON, QP  OFF, vO = 0 (pull-down)

vI = 0, QN  OFF, QP  ON, vO = VDD (pull-up) vO = vI
CMOS Inverter
8
 CMOS Inverter Static Operation (2)

Notice:
Transistor threshold = Vtn or Vtp
Inverter threshold = VM
Normally VM = VDD/2 for symmetric NMs

CMOS Inverter
9
 CMOS Inverter Static Operation (3)

ON OFF
LIN SAT

SAT SAT

Notice: SAT LIN OFF ON

Transistor threshold = Vtn or Vtp
Inverter threshold = VM
Normally VM = VDD/2 for symmetric NMs

CMOS Inverter
10
 CMOS Inverter Static Operation (4)

Region 1: vI<Vtn
ON OFF

vO = VDD

CMOS Inverter
11
 CMOS Inverter Static Operation (5)

Region 5: vI > VDD-Vtp 

ON OFF
LIN SAT

SAT SAT

SAT LIN OFF ON

vO = 0

CMOS Inverter
12
 CMOS Inverter Static Operation (6)

Region 3: vI ≈VM
ON OFF
LIN SAT

SAT SAT

To get an expression
for VM, equate
the PMOS sat current
to the NMOS sat current

CMOS Inverter
13
 CMOS Inverter Static Operation (7)

Region 3: vI ≈VM
2 2
k p (VDD − vI − Vtp ) = k n (vI − Vtn )
where k p ,n = k p ,n ' (W / L) p ,n
vI = VM
VDD
One gets VM =
2
iff k p = kn
and Vtn = Vtp
CMOS Inverter
14
CMOS Inverter Static Operation (8)

Otherwise the inverter threshold voltage is given by:

VDD − Vtp + kn / k pVtn

VM =
1 + kn / k p

CMOS Inverter
15
 CMOS Inverter Static Operation (9)

Region 2: VM>vI>Vtn
ON OFF
LIN SAT

To get an expression
for vO vs. vI, equate
the PMOS linear current
to the NMOS sat current

CMOS Inverter
16
CMOS Inverter Static Operation (10)

Region 4: VM< vI< VDD-Vtp 

ON OFF
LIN SAT

SAT SAT

To get an expression SAT LIN

for vO vs. vI, equate
the PMOS sat current
to the NMOS linear current
kp
(vI − VDD − Vtp ) = k n  
1 2
2
(vI − Vtn )vO − vO
2 CMOS Inverter 2
17
 MOSFET Switch Model

How is a MOS transistor different from an ideal switch ?

⚫ Non-zero switch ON resistance

⚫ Parasitic capacitances

G G
CG
S D S D
CS RON CD
Ideal switch One possible model of the
MOS transistor as a switch

CMOS Inverter
18
 MOS ON Resistance

600
• The switch ON resistance RON ≠ 0
500 • RON is a non-linear resistor
• it changes with VDS
400
Ids (mA) • region of MOS operation matters
300
• Suppose switch turns ON suddenly
200 • i.e. VGS jumps from 0 to VDD
• RON varies (as slope–1 of the red curve)
100
• A simple estimate of average RON
0
0 0.5 1 1.5 2 2.5 • RON ≈ slope–1 of blue line
Vds
Vo=2.5 G 𝑉𝐷𝑆 𝐿
𝑅𝑂𝑁 = = 𝑅□
𝐼𝐷𝑆 𝑊
S D
The R□ of a MOSFET is inversely
proportional to the gate overdrive, VGS -VT
CMOS Inverter
19
RON During Transition

CMOS Inverter
20
 MOS Capacitance

• Parasitic (undesirable) elements are everywhere

• Devices are small enough such that inductive effects are negligible.
• Capacitances dominate; and there are MANY
1. Cchannel – since channel connects S/D, it is split
2. Coverlap – gate overlaps S/D, and there is fringe cap from Gate
3. Cjunction – S/D form reverse-biased PN junctions with the body
4. Cj_sidewall – S/D different doping to the bottom and side
5. Cbody – from channel to body, quite small b/c of small L
Gate
C2 C2
C1

C4 Source Drain C4
C5
C3 C3

CMOS Inverter
21
 Gate Capacitance

Channel cap characteristics Gate

• Split between S/D
• Varies with region of operation C1A C1B
Source Drain
Off MOSFET
• Cch = CGB

Cov = Cox*W*Lov*k, where k is a

On MOSFET constant accounting for fringing
• Cch = W*Lch*eox/tox
• Triode region Removing technology dependence
– C1A = C1B = Cch/2 and assuming minimum channel
• Saturated region length
– C1A = 2/3Cch, C1B = 0 Cgate = CG * W

CMOS Inverter
22
 Self-Loading Capacitance

• A transistor pulls current from its S/D,

so the S/D junction is often called the
Self-Loading Capacitance.
• CS/D = Cj_area + Cj_sidewall
Ldiff
• Cj_area = W*Ldiff*CJ(VS/D)

• Cj_sidewall = (W+2Ldiff)*CJSW(VS/D) W
CJ = CO /(1 + VRB / VO ) M
• Note that CJ and CJSW are
Where CO, VO, and M are
– layout dependent
junction dependent constants
– voltage dependent
Can also be simplified as
– Ldiff is typically 5l (unshared and
Cjunction = CD,S * W
contacted)

CMOS Inverter
23
CMOS Inverter: Transient Response

VDD VDD
VDD

Rp tpHLtpHL
= f(R=on
f(R
.Con .C )
L) L
= 0.69
= 0.69 RonR CLon CL
Vout
Vout
Vout
CL Vout ln(0.5)
C
C L
L
Ron Rn 1 VDD

0.5
0.36

Vin = V DD
(a) Low-to-high (b) High-to-low
t
RonCL
CMOS Inverter
24
 CMOS Inverter: Propagation Delay

2.5
?
2
tp = 0.69 CL (Rn+Rp)/2
1.5
Vout(V)

tpHL tpLH
1

3 𝑉𝐷𝐷
0.5
𝑅𝑒𝑞 ≅ (neglecting
4 𝐼𝐷𝑆𝐴𝑇
0 channel length mod.)
-0.5
0 0.5 1 1.5 2 2.5
t (sec) x 10
-10

CMOS Inverter
25
 Choosing Wp/Wn Ratio
⚫ For symmetric inverter VM = VDD/2 and tPHL = tPLH, β
=Wp/Wn should be equal to r=µn/µp=Reqp/Reqn.
⚫ However, this does not guarantee minimum delay.
⚫ tPLH decreases with β whereas tPHL increases with β.

CMOS Inverter
26
 Power Consumption

• Static (leakage) (low for low transistor count and perfected technology)
• Dynamic (to charge and discharge CL at a certain frequency : appreciable)
• Short-Circuit (when both PMOS and NMOS are ON : reduced in fast transitions)

Ptotal = Pstatic + Pdynamic + Pshort−circuit

may be the most important

CMOS Inverter
27
 Static Power

Gate-leakage current
sub-threshold current

Pstatic = VDD I leakage

CMOS Inverter
28
 Dynamic Power

During
output
transition

* An equal energy is needed to discharge CL (in the next half cycle)

* Therefore in one switching cycle we need an energy of CLVDD2
2
CV
= L DD = C LVDD f activity
2
Pdynamic
T
CMOS Inverter
29
 Short-Circuit Power

During
input
transition

• This average short-circuit current drawn from VDD results in Pshort-circuit

• Fast rise and fall times of input waveform reduce short-circuit power

CMOS Inverter
30
 Power-Delay & Energy-Delay Product
⚫ Used as quality measure of logic gates.

⚫ PDP is energy, so not so useful.

CMOS Inverter
31
 Outline

⚫ The CMOS Inverter Noise Margin and Threshold

Voltage
⚫ The CMOS Inverter Propagation Delay and Switching
Speed
⚫ The CMOS Inverter Power Consumption
⚫ Sizing of the CMOS Inverter

CMOS Inverter
32
 Inverter with Load

Delay

Req

CL
Req Load (CL)
tp = k ReqCL

k is a constant, equal to 0.69 (note ln (2) =0.69)

Assumptions: no load -> zero delay

CMOS Inverter
33
 Layout-Aware Inverter with Load (1)

2W

Intrinsic or internal or self-loading cap

W
Cint CL
External loading cap

Delay = kReq(Cint + CL) = kReqCint + kReqCL = kReq Cint(1+ CL /Cint)

= Delay (Internal) + Delay (Load)

CMOS Inverter
34
 Layout-Aware Inverter with Load (2)

Delay
2W

W
Cint CL kREQCint

Load

Delay = kReq(Cint + CL) = kReqCint + kReqCL = kReq Cint(1+ CL /Cint)

= Delay (Internal) + Delay (Load)

CMOS Inverter
35
 Cg vs. Cint

Cgp = 2Ccgn Delay = tp

2W
Cint  Cg = Cg
Cg
W
Cint CL tpo CL
Load
Cgn

Delay = tp = kReq Cint(1+ CL /Cint) = tpo(1+ CL /Cgin)

CMOS Inverter
36
 Delay Formula

Delay = tp = kReq Cint(1+ CL /Cint) = tpo(1+ CL /Cg)

= tpo(1+ f /)

Cint = Cg ( for simplicity one assumes   1, it is indeed close

to 1 for most submicron processes)

f = CL/Cg = effective fanout (also called “electrical effort”)

tpo = 0.69ReqCint (zero-load delay or intrinsic delay)

Relative (Normalized) Delay d = tp /tpo = (1+ f /)

CMOS Inverter
37
Size of a Single Inverter for a Given CL (1)

Delay = tp = kReq Cint(1+ CL /Cint) = tpo(1+ CL /SCg)

Scaling W by a factor S: Req  Req/S and Cint  SCint tpo = k(Req/S) (SCint)  f(S) = kReqCint

Req/S

Req/S SCint

CMOS Inverter
38
Size of a Single Inverter for a Given CL (2)

large area and

wasted effort
[Ex. 5.7 Rabaey]

SCint>>CL

CMOS Inverter
39
 Sizing an Inverter Chain

In Out

1 2 N CL

tp = tp1 + tp2 + …+ tpN

 C g , j +1 
t pj = t po 1 + 
 C 
Small load cap
 g, j 
as if a gate N+1 exists

N N  C g , j +1 
t p =  t p , j = t p 0  1 + , C g , N +1 = CL
 C 
i =1 
j =1 g, j 

CMOS Inverter
40
Driving Large CL

CMOS Inverter
41
Growing Stages for Driving Large CL

Small Cg
Large current

stage 2 acts
as a (single-stage) buffer
between
load and 1st stage

CMOS Inverter
42
 The Tapered Buffer

Cint fCint f2Cint fN-1Cint

CMOS Inverter
43
Optimum Delay and Number of Stages

When each stage is sized by f and has same eff. fanout f:

f N = F = CL / C g1

Effective fanout of each stage:

f =NF
f
Path (N-stages) delay

(
t p = Nt p 0 1 + N F /  )
CMOS Inverter
44
 Optimum Number of Stages

For a given load, CL and given input capacitance Cin

Find optimal sizing f
ln F
C L = F  C g1 = f C g1N
with N =
ln f

t p 0 ln F  f  
(
t p = Nt p 0 F /  + 1 =
1/ N
)  +
  ln f ln f


t p t p 0 ln F ln f − 1 −  f
=  =0
f  ln f 2

f = exp(1 +  f )  Special case: no self loading: For  = 0, f = e, N = ln F

Exponential Buffer

CMOS Inverter
45
 Optimum 𝒇 vs. 𝜸 in Tapered Buffers

3.6 ( 4)
tapered buff
(self-loading at  = 1)

Exponential buff
(no self-loading)
Cint =  Cg

CMOS Inverter
46
 Buffer Design

N f tp
1 64 1 64 65

1 8 64
2 8 18

1 4 16 64 3 4 15
(Typical instead of 3.6)

1 64 4 2.8 15.3
2.8 8 22.6 (≈ exponential)

CMOS Inverter
47
 FO4 Delay
⚫ Want a way to characterize the delay of a circuit
(roughly) independent of technology
⚫ Most common metric:
▪ Delay of an inverter driving four copies of itself (tFO4)

CMOS Inverter
48