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Air Washington Electronics – Intro.

To Digital

06 Encoders/Decoders

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Air Washington Electronics – Intro. To Digital

Contents
06 Encoders/Decoders .................................................................................................................... 1
Data Representation ....................................................................................................................... 3
Data Coding Systems ................................................................................................................... 3

American Standard Code for Information Interchange (ASCII) .................................................. 3

Data Storage Concepts.................................................................................................................... 5


Knowledge Check ........................................................................................................................ 5

Optoelectronic Devices ................................................................................................................... 5


Knowledge Check ........................................................................................................................ 8

Encoders.......................................................................................................................................... 8
74147 Encoder ............................................................................................................................ 8

Decoders ......................................................................................................................................... 8
7447A – BCD to seven segment decoder/driver ......................................................................... 9

74HC4543 BCD to seven segment latch/decoder/driver ............................................................ 9

Answers to Knowledge Checks ..................................................................................................... 10


Data Representation ................................................................................................................. 10

Optoelectronic Devices ............................................................................................................. 10

Additional Resources .................................................................................................................... 11


Physics Resources...................................................................................................................... 11

Web Resources .......................................................................................................................... 11

References .................................................................................................................................... 12
Attributions ................................................................................................................................... 13
Table of Figures ............................................................................................................................. 14

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Air Washington Electronics – Intro. To Digital

Data Representation
Data is represented by symbols. Symbols convey meaning only when understood. The symbol
itself is not the information, but merely a representation of it. Symbol meaning is one of
convention. Symbols may convey one meaning to you and me, another meaning to others, and
no meaning at all to those that do not know their significance. Data must be reduced to a set of
symbols that the computer can read and interpret before there can be any communication with
the computer. The first computers were designed to manipulate numbers to solve arithmetic
problems. We create, use, and manipulate many other symbols to represent facts in the world
in which we live. We are fortunate that early computer experts soon realized the need to
manipulate nonnumerical symbols as well. Manipulating these symbols is possible if an
identifying code or coded number is assigned to the symbol to be stored and processed. Thus,
the letters in a name such as ALBERT or CAROL can be represented by different codes, as can all
special characters, such as #, (,), &, $, @, and yes, even the comma. The data to be represented
is called source data.

Data Coding Systems

To represent numeric, alphabetic, and special characters in a computer's internal storage and
on magnetic media, we must use some sort of coding system. In computers, the code is made
up of fixed size groups of binary positions. Each binary position in a group is assigned a specific
value; for example 8, 4, 2, or 1. In this way, every character can be represented by a
combination of bits that is different from any other combination.

American Standard Code for Information Interchange (ASCII)

American Standard Code for Information Interchange (ASCII) (pronounced ASS-KEY), was
originally designed as a 7-bit code. Several computer manufacturers cooperated to develop this
code for transmitting and processing data. The purpose was to standardize a binary code to
give the computer user the capability of using several machines to process data regardless of
the manufacturer. ASCII is commonly used in the transmission of data through data
communications and is used almost exclusively to represent data internally in microcomputers.
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Air Washington Electronics – Intro. To Digital

In ASCII uppercase letters are assigned codes beginning with hexadecimal value 41 and
continuing sequentially through hexadecimal value 5A. Similarly, lowercase letters are assigned
hexadecimal values of 61 through 7A. The decimal values 1 through 9 are assigned the zone
code 0011 in ASCII. Figure 1 is the ASCII coding chart showing uppercase and lowercase
alphabetic characters and numeric digits 0 through 9.

Figure 1: Eight-bit ASCII coding chart (including Hex equivalents).

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Air Washington Electronics – Intro. To Digital

Data Storage Concepts


A bit is a single binary digit. It represents the smallest unit of data. However, computers usually
do not operate on single bits, rather they store and manipulate a fixed number of bits. Most
often, the smallest unit or number of bits a computer works with is eight bits. These eight bits
make up a byte. You just learned that ASCII codes use eight bits, and that eight bits represent a
single character, such as the letter A or the number 7. Thus, the computer can store and
manipulate an individual byte (a single character) or a group of bytes (several characters, a
word) at a time. These individual bytes, or groups of bytes, form the basic unit of memory.

Bit single binary digit


(either a 0 or a 1)
Nibble 4 bits
Byte 8 bits
Half-word 16 bits
2 Bytes
Word 32 bits
4 Bytes
Double-word 64 bits
8 bytes

Knowledge Check

1. What is a bit?

2. How many bits make up a byte?

Optoelectronic Devices
Optoelectronic devices either produce light or use light in their operation. The first of these,
the light-emitting diode (LED), was developed to replace the fragile, short-life incandescent
light bulbs used to indicate on/off conditions on panels. A light-emitting diode is a diode which,
when forward biased, produces visible light. The light may be red, green, or amber, depending
upon the material used to make the diode.

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Air Washington Electronics – Intro. To Digital

Figure 1 shows an LED and its schematic symbol. The LED is designated by a standard diode
symbol with two arrows pointing away from the cathode. The arrows indicate light leaving the
diode. The circuit symbols for all optoelectronic devices have arrows pointing either toward
them, if they use light, or away from them, if they produce light. The LED operating voltage is
small, about 1.6 volts forward bias and generally about 10 milliamperes. The life expectancy of
the LED is very long, over 100,000 hours of operation.

Figure 2: LED

LEDs are used widely as "power on" indicators of current and as displays for pocket calculators,
digital voltmeters, frequency counters, etc. For use in calculators and similar devices, LEDs are
typically placed together in seven-segment displays, as shown in Figure 2 (view A and view B).
This display uses seven LED segments, or bars (labeled A through G in the figure), which can be
lit in different combinations to form any number from "0" through "9." The schematic, view A,
shows a common-anode display. All anodes in a display are internally connected. When a
negative voltage is applied to the proper cathodes, a number is formed. For example, if
negative voltage is applied to all cathodes except that of LED "E," the number "9" is produced,
as shown in view A of Figure 3. If the negative voltage is changed and applied to all cathodes
except LED "B," the number "9" changes to "6" as shown in view B.

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Air Washington Electronics – Intro. To Digital

Figure 3: Seven-segment LED display.

Figure 4: Seven-segment LED display examples.

Seven-segment displays are also available in common-cathode form, in which all cathodes are
at the same potential. When replacing LED displays, you must ensure the replacement display is

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Air Washington Electronics – Intro. To Digital

the same type as the faulty display. Since both types look alike, you should always check the
manufacturer's number.

LED seven-segment displays range from the very small, often not much larger than standard
typewritten numbers, to about an inch. Several displays may be combined in a package to show
a series of numbers, such as the one shown in Figure 4.

Figure 5: Stacked seven-segment display.

Knowledge Check

1. What type of bias is required to cause an LED to produce light?

2. When compared to incandescent lamps, what is the power requirement of an LED?

3. In a common anode, seven-segment LED display, an individual LED will light if a negative
voltage is applied to what element?

Encoders
Use of the data sheet for a 74147 will be sufficient to teach encoders. Instructors may use
preferred brands or types.

74147 Encoder

See Appendix A.

Decoders
Use of the datasheets for the following decoders will be sufficient. Instructors may use
preferred brands or types.

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Air Washington Electronics – Intro. To Digital

7447A – BCD to seven segment decoder/driver

See Appendix A.

74HC4543 BCD to seven segment latch/decoder/driver

See Appendix A.

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Air Washington Electronics – Intro. To Digital

Answers to Knowledge Checks

Data Representation

1. A single binary bit.

2. Eight (8).

Optoelectronic Devices

1. Forward bias.

2. Very low.

3. The cathode.

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Air Washington Electronics – Intro. To Digital

Additional Resources

Physics Resources

Georgia State University – HyperPhysics: http://hyperphysics.phy-


astr.gsu.edu/hbase/hframe.html

Web Resources

All About Circuits

• Volume IV, Digital: http://www.allaboutcircuits.com/vol_4/index.html

Bucknell University – Welcome to Electrical Engineering

• Digital Signals and Logic Chapter, Gates:


http://www.facstaff.bucknell.edu/mastascu/elessonshtml/Logic/Logic1.html

Natiional Instituted of Standards and Technology (NIST)

• Dictionary of Algorithms and Data Structures: http://xlinux.nist.gov/dads/

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Air Washington Electronics – Intro. To Digital

References
United States Navy. (1998). Module 13 - Introduction to Number Systems and Logic. In Navy
Electricity and Electronics Training Series (NEETS). Pensacola, FL: Naval Education and
Training Professional Development and Technology Center.

United States Navy. (1998). Module 22 - Introduction to Digital Computers. In Navy Electricity
and Electronics Training Series (NEETS). Pensacola, FL: Naval Education and Training
Professional Development and Technology Center.

United States Navy. (2003). Module 7 - Introduction to Solid-State Devices and Power Supplies.
In Navy Electricity and Electronics Training Series (NEETS). Pensacola, FL: Naval
Education and Training Professional Development and Technology Center.

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Air Washington Electronics – Intro. To Digital

Attributions
United States Navy. Navy Electricity and Electronics Training Series (NEETS). Public Domain per
Distribution Statement A
http://www.dtic.mil/dtic/submit/guidance/distribstatement.html

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Air Washington Electronics – Intro. To Digital

Table of Figures
Source of figures: United States Navy.

Figure 1: Eight-bit ASCII coding chart (including Hex equivalents). ............................................... 4


Figure 2: LED .................................................................................................................................. 6
Figure 3: Seven-segment LED display. ........................................................................................... 7
Figure 4: Seven-segment LED display examples. ........................................................................... 7
Figure 5: Stacked seven-segment display. ..................................................................................... 8

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Air Washington Electronics – Intro. To Digital

Appendix A

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Air Washington Electronics – Intro. To Digital

Page 16 of 16
     
 
    
              
SDLS053B − OCTOBER 1976 − REVISED MAY 2004

’147, ’LS147 ’148, ’LS148


D Encode 10-Line Decimal to 4-Line BCD D Encode 8 Data Lines to 3-Line Binary
D Applications Include: (Octal)
− Keyboard Encoding D Applications Include:
− Range Selection − n-Bit Encoding
− Code Converters and Generators
SN54147, SN54LS147 . . . J OR W PACKAGE SN54148, SN54LS148 . . . J OR W PACKAGE
SN74147, SN74LS147 . . . D OR N PACKAGE SN74148, SN74LS148 . . . D, N, OR NS PACKAGE
(TOP VIEW) (TOP VIEW)

4 1 16 VCC 4 1 16 VCC
5 2 15 NC 5 2 15 E0
6 3 14 D 6 3 14 GS
7 4 13 3 7 4 13 3
8 5 12 2 EI 5 12 2
C 6 11 1 A2 6 11 1
B 7 10 9 A1 7 10 0
GND 8 9 A GND 8 9 A0

SN54LS147 . . . FK PACKAGE SN54LS148 . . . FK PACKAGE


(TOP VIEW) (TOP VIEW)
VCC

VCC
NC

NC

NC

E0
5
4

5
4
3 2 1 20 19 3 2 1 20 19
6 4 18 D 6 4 18 GS
7 5 17 3 7 5 17 3
NC 6 16 NC NC 6 16 NC
8 7 15 2 EI 7 15 2
C 8 14 1 A2 8 14 1
9 10 11 12 13 9 10 11 12 13
9

A1

A0
0
B
GND

GND
NC

NC

NC − No internal connection

TYPICAL TYPICAL
TYPE DATA POWER
DELAY DISSIPATION
’147 10 ns 225 mW
’148 10 ns 190 mW
’LS147 15 ns 60 mW
’LS148 15 ns 60 mW

NOTE: The SN54147, SN54LS147, SN54148, SN74147, SN74LS147, and SN74148 are obsolete and are no longer supplied.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

    !"#$ % &'!!($ #%  )'*+&#$ ,#$(- Copyright  2004, Texas Instruments Incorporated
!,'&$% &!" $ %)(&&#$% )(! $.( $(!"%  (/#% %$!'"($%  )!,'&$% &")+#$ $ 3 #++ )#!#"($(!% #!( $(%$(,
%$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',( '+(%% $.(!0%( $(,-  #++ $.(! )!,'&$% )!,'&$
$(%$2  #++ )#!#"($(!%- )!&(%%2 ,(% $ (&(%%#!+1 &+',( $(%$2  #++ )#!#"($(!%-

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1


     
 
    
              
SDLS053B − OCTOBER 1976 − REVISED MAY 2004

description/ordering information
These TTL encoders feature priority decoding of the inputs to ensure that only the highest-order data line is
encoded. The ’147 and ’LS147 devices encode nine data lines to four-line (8-4-2-1) BCD. The implied decimal
zero condition requires no input condition, as zero is encoded when all nine data lines are at a high logic level.
The ’148 and ’LS148 devices encode eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry
(enable input EI and enable output EO) has been provided to allow octal expansion without the need for external
circuitry. For all types, data inputs and outputs are active at the low logic level. All inputs are buffered to represent
one normalized Series 54/74 or 54/74LS load, respectively.

ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
PDIP − N Tube SN74LS148N SN74LS148N
Tube SN74LS148D
0°C to 70°C SOIC − D LS148
Tape and reel SN74LS148DR
SOP − NS Tape and reel SN74LS148NSR 74LS148
CDIP − J Tube SNJ54LS148J SNJ54LS148J
−55°C
−55 C to 125
125°C
C CFP − W Tube SNJ54LS148W SNJ54LS148W
LCCC − FK Tube SNJ54LS148FK SNJ54LS148FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.

FUNCTION TABLE − ’147, ’LS147


INPUTS OUTPUTS
1 2 3 4 5 6 7 8 9 D C B A
H H H H H H H H H H H H H
X X X X X X X X L L H H L
X X X X X X X L H L H H H
X X X X X X L H H H L L L
X X X X X L H H H H L L H
X X X X L H H H H H L H L
X X X L H H H H H H L H H
X X L H H H H H H H H L L
X L H H H H H H H H H L H
L H H H H H H H H H H H L
H = high logic level, L = low logic level, X = irrelevant

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265


     
 
    
              
SDLS053B − OCTOBER 1976 − REVISED MAY 2004

FUNCTION TABLE − ’148, ’LS148


INPUTS OUTPUTS
EI 0 1 2 3 4 5 6 7 A2 A1 A0 GS EO
H X X X X X X X X H H H H H
L H H H H H H H H H H H H L
L X X X X X X X L L L L L H
L X X X X X X L H L L H L H
L X X X X X L H H L H L L H
L X X X X L H H H L H H L H
L X X X L H H H H H L L L H
L X X L H H H H H H L H L H
L X L H H H H H H H H L L H
L L H H H H H H H H H H L H
H = high logic level, L = low logic level, X = irrelevant

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3


     
 
    
              
SDLS053B − OCTOBER 1976 − REVISED MAY 2004

’147, ’LS147 logic diagram (positive logic)


(11)
1

(12)
2 (9)
A

(13)
3

(1)
4

(7)
B
(2)
5

(3)
6

(4) (6)
7 C

(5)
8

(14)
(10) D
9

Pin numbers shown are for D, J, N, and W packages.

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265


     
 
    
              
SDLS053B − OCTOBER 1976 − REVISED MAY 2004

’148, ’LS148 logic diagram (positive logic)


(10)
0
(15)
EO

(14)
(11) G5
1

(12)
2

(9)
A0

(13)
3

(1)
4

(7)
A1
(2)
5

(3)
6

(4) (6)
7 A2

(5)
EI

Pin numbers shown are for D, J, N, NS, and W packages.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5


     
 
    
              
SDLS053B − OCTOBER 1976 − REVISED MAY 2004

schematics of inputs and outputs


’147, ’148

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS


VCC VCC

 Ω NOM
Req

Input

Output

0 input (’148): Req = 2 kΩ NOM


All other inputs: Req = 4 kΩ NOM

’LS147, ’LS148

EQUIVALENT OF ALL INPUTS TYPICAL OF ALL OUTPUTS

VCC
VCC
120 Ω NOM
Req

Input

Output

’LS148 inputs 1–7: Req = 9 kΩ NOM


All other inputs: Req = 18 kΩ NOM

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265


     
 
    
              
SDLS053B − OCTOBER 1976 − REVISED MAY 2004

absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI: ’147, ’148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
’LS147, ’LS148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Inter-emitter voltage: ’148 only (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Package thermal impedance θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values, except inter-emitter voltage, are with respect to the network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. For ’148 circuits, this rating applies between any two of the
eight data lines, 0 through 7.
3. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 4)


SN54’ SN74’ SN54LS’ SN74LS’
UNIT
MIN NOM MAX MIN NOM MAX MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 4.5 5 5.5 4.75 5 5.25 V
IOH High-level output current −800 −800 −400 −400 µA
IOL Low-level output current 16 16 4 8 mA
TA Operating free-air temperature −55 125 0 70 −55 125 0 70 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7


     
 
    
              
SDLS053B − OCTOBER 1976 − REVISED MAY 2004

electrical characteristics over recommended operating free-air temperature range (unless


otherwise noted)
’147 ’148
PARAMETER TEST CONDITIONS† UNIT
MIN TYP‡ MAX MIN TYP‡ MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIK Input clamp voltage VCC = MIN, II = −12 mA −1.5 −1.5 V
VCC = MIN, VIH = 2 V,
VOH High-level output voltage 2.4 3.3 2.4 3.3 V
VIL = 0.8 V, IOH = −800 µA
VCC = MIN, VIH = 2 V,
VOL Low-level output voltage 0.2 0.4 0.2 0.4 V
VIL = 0.8 V, IOL = 16 mA
Input current at maximum input
II VCC = MIN, VI = 5.5 V 1 1 mA
voltage
High-level input 0 input 40
IIH VCC = MAX, VI = 2.4 V µA
A
current Any input except 0 40 80
Low-level input 0 input −1.6
IIL VCC = MAX, VI = 0.4 V mA
current Any input except 0 −1.6 −3.2
IOS Short-circuit output current§ VCC = MAX −35 −85 −35 −85 mA
VCC = MAX Condition 1 50 70 40 60
ICC Supply current mA
(See Note 5) Condition 2 42 62 35 55
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time.
NOTE 5: For ’147, ICC (Condition 1) is measured with input 7 grounded, other inputs and outputs open; ICC (Condition 2) is measured with all
inputs and outputs open. For ’148, ICC (Condition 1) is measured with inputs 7 and EI grounded, other inputs and outputs open; ICC
(Condition 2) is measured with all inputs and outputs open.

SN54147, SN74147 switching characteristics, VCC = 5 V, TA = 255C (see Figure 1)


FROM TO TEST
PARAMETER WAVEFORM MIN TYP MAX UNIT
(INPUT) (OUTPUT) CONDITIONS
tPLH 9 14
Any Any In-phase output ns
tPHL CL = 15 pF, 7 11
tPLH RL = 400 Ω 13 19
Any Any Out-of-phase output ns
tPHL 12 19

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265


     
 
    
              
SDLS053B − OCTOBER 1976 − REVISED MAY 2004

SN54148, SN74148 switching characteristics, VCC = 5 V, TA = 255C (see Figure 1)


FROM TO TEST
PARAMETER† WAVEFORM MIN TYP MAX UNIT
(INPUT) (OUTPUT) CONDITIONS
tPLH 10 15
1–7 A0, A1, or A2 In-phase output ns
tPHL 9 14
tPLH 13 19
1–7 A0, A1, or A2 Out-of-phase output ns
tPHL 12 19
tPLH 6 10
0–7 EO Out-of-phase output ns
tPHL 14 25
tPLH CL = 15 pF, 18 30
0–7 GS In-phase output ns
tPHL RL = 400 Ω 14 25
tPLH 10 15
EI A0, A1, or A2 In-phase output ns
tPHL 10 15
tPLH 8 12
EI GS In-phase output ns
tPHL 10 15
tPLH 10 15
EI EO In-phase output ns
tPHL 17 30
† tPLH = propagation delay time, low-to-high-level output.
tPHL = propagation delay time, high-to-low-level output.

electrical characteristics over recommended operating free-air temperature range (unless


otherwise noted)
SN54LS’ SN74LS’
PARAMETER TEST CONDITIONS† UNIT
MIN TYP‡ MAX MIN TYP‡ MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage VCC = MIN, II = −18 mA −1.5 −1.5 V
VCC = MIN, VIH = 2 V,
VOH High-level output voltage 2.5 3.4 2.7 3.4 V
VIL = 0.8 V, IOH = −400 µA
VCC = MIN, IOL = 4 mA 0.25 0.4 0.25 0.4
VOL Low-level output voltage VIH = 2 V, V
VIL = VIL MAX IOL = 8 mA 0.35 0.5

Input current at ’LS148 inputs 1–7 0.2 0.2


II maximum input VCC = MAX, VI = 7 V mA
voltage All other inputs 0.1 0.1

High-level input ’LS148 inputs 1–7 40 40


IIH VCC = MAX, VI = 2.7 V µA
A
current All other inputs 20 20
Low-level input ’LS148 inputs 1–7 −0.8 −0.8
IIL VCC = MAX, VI = 0.4 V mA
current All other inputs −0.4 −0.4
IOS Short-circuit output current§ VCC = MAX −20 −100 −20 −100 mA
VCC = MAX Condition 1 12 20 12 20
ICC Supply current mA
(See Note 6) Condition 2 10 17 10 17
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time.
NOTE 6: For ’LS147, ICC (Condition 1) is measured with input 7 grounded, other inputs and outputs open; ICC (Condition 2) is measured with
all inputs and outputs open. For ’LS148, ICC (Condition 1) is measured with inputs 7 and EI grounded, other inputs and outputs open;
ICC (Condition 2) is measured with all inputs and outputs open.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9


     
 
    
              
SDLS053B − OCTOBER 1976 − REVISED MAY 2004

SN54LS147, SN74LS147 switching characteristics, VCC = 5 V, TA = 255C (see Figure 2)


FROM TO TEST
PARAMETER WAVEFORM MIN TYP MAX UNIT
(INPUT) (OUTPUT) CONDITIONS
tPLH 12 18
Any Any In-phase output ns
tPHL CL = 15 pF, 12 18
tPLH RL = 2 kkΩ 21 33
Any Any Out-of-phase output ns
tPHL 15 23

SN54LS148, SN74LS148 switching characteristics, VCC = 5 V, TA = 255C (see Figure 2)


FROM TO TEST
PARAMETER† WAVEFORM MIN TYP MAX UNIT
(INPUT) (OUTPUT) CONDITIONS
tPLH 14 18
1–7 A0, A1, or A2 In-phase output ns
tPHL 15 25
tPLH 20 36
1–7 A0, A1, or A2 Out-of-phase output ns
tPHL 16 29
tPLH 7 18
0–7 EO Out-of-phase output ns
tPHL 25 40
tPLH CL = 15 pF, 35 55
0–7 GS In-phase output ns
tPHL RL = 2 kΩ
k 9 21
tPLH 16 25
EI A0, A1, or A2 In-phase output ns
tPHL 12 25
tPLH 12 17
EI GS In-phase output ns
tPHL 14 36
tPLH 12 21
EI EO In-phase output ns
tPHL 23 35
† tPLH = propagation delay time, low-to-high-level output
tPHL = propagation delay time, high-to-low-level output

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265


     
 
    
              
SDLS053B − OCTOBER 1976 − REVISED MAY 2004

PARAMETER MEASUREMENT INFORMATION


SERIES 54/74 DEVICES
VCC
Test RL
Test Point S1
Point VCC
From Output
VCC Under Test (see Note B)
RL CL
From Output RL (see Note A) 1 kΩ
Under Test (see Note B) From Output Test
CL Under Test Point
(see Note A) CL
(see Note A) S2

LOAD CIRCUIT LOAD CIRCUIT LOAD CIRCUIT


FOR 2-STATE TOTEM-POLE OUTPUTS FOR OPEN-COLLECTOR OUTPUTS FOR 3-STATE OUTPUTS

3V
High-Level Timing
Pulse 1.5 V 1.5 V Input 1.5 V
0V
tw th
tsu
3V
Low-Level 1.5 V 1.5 V Data
1.5 V 1.5 V
Pulse Input
0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATIONS SETUP AND HOLD TIMES

Output 3V
Control
(low-level 1.5 V 1.5 V
3V
Input 1.5 V 1.5 V enabling) 0V
0V tPZL tPLZ

tPLH tPHL
Waveform 1 ≈1.5 V
In-Phase VOH (see Notes C 1.5 V
Output 1.5 V 1.5 V and D) VOL + 0.5 V
(see Note D) VOL
VOL
tPZH tPHZ
tPHL tPLH
VOH
Out-of-Phase VOH Waveform 2 VOH − 0.5 V
(see Notes C 1.5 V
Output 1.5 V 1.5 V ≈1.5 V
(see Note D) and D)
VOL
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance.


B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open, and S2 is closed for tPZH; S1 is closed, and S2 is open for tPZL.
E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Series
54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices.
F. The outputs are measured one at a time, with one input transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11


     
 
    
              
SDLS053B − OCTOBER 1976 − REVISED MAY 2004

PARAMETER MEASUREMENT INFORMATION


SERIES 54LS/74LS DEVICES
VCC
Test RL
Test Point S1
Point VCC
From Output
VCC Under Test (see Note B)
RL CL
From Output RL (see Note A) 5 kΩ
Under Test (see Note B) From Output Test
CL Under Test Point
(see Note A) CL
(see Note A) S2

LOAD CIRCUIT LOAD CIRCUIT LOAD CIRCUIT


FOR 2-STATE TOTEM-POLE OUTPUTS FOR OPEN-COLLECTOR OUTPUTS FOR 3-STATE OUTPUTS

3V
High-Level Timing
Pulse 1.3 V 1.3 V Input 1.3 V
0V
tw th
tsu
3V
Low-Level 1.3 V 1.3 V Data
1.3 V 1.3 V
Pulse Input
0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATIONS SETUP AND HOLD TIMES

Output 3V
Control
(low-level 1.3 V 1.3 V
3V
Input enabling)
1.3 V 1.3 V 0V
0V tPZL tPLZ

tPLH tPHL
Waveform 1 ≈1.5 V
In-Phase VOH 1.3 V
(see Notes C
Output 1.3 V 1.3 V VOL + 0.5 V
and D)
(see Note D) VOL VOL
tPZH tPHZ
tPHL tPLH
VOH
Out-of-Phase Waveform 2 VOH − 0.5 V
VOH
Output (see Notes C 1.3 V
1.3 V 1.3 V
and D) ≈1.5 V
(see Note D) VOL
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open, and S2 is closed for tPZH; S1 is closed, and S2 is open for tPZL.
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns.
G. The outputs are measured one at a time, with one input transition per measurement.

Figure 2. Load Circuits and Voltage Waveforms

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265


     
 
    
              
SDLS053B − OCTOBER 1976 − REVISED MAY 2004

APPLICATION INFORMATION
16-Line Data (active low)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Enable
(active low)

0 1 2 3 4 5 6 7 EI 0 1 2 3 4 5 6 7 EI

’148/’LS148 ’148/LS148

EO A0 A1 A2 GS EO A0 A1 A2 GS

’08/’LS08

0 1 2 3 Priority Flag
(active low)
Encoded Data (active low)

16-Line Data (active low)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Enable
(active low)

0 1 2 3 4 5 6 7 EI 0 1 2 3 4 5 6 7 EI

’148/’LS148 ’148/’LS148

EO A0 A1 A2 GS EO A0 A1 A2 GS

’HC00

0 1 2 3 Priority Flag
(active high)
Encoded Data (active high)

Figure 3. Priority Encoder for 16 Bits

Because the ’147/’LS147 and ’148/’LS148 devices are combinational logic circuits, wrong addresses can appear
during input transients. Moreover, for the ’148/’LS148 devices, a change from high to low at EI can cause a transient
low on GS when all inputs are high. This must be considered when strobing the outputs.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13


PACKAGE OPTION ADDENDUM

www.ti.com 31-May-2014

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

78027012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 78027012A
SNJ54LS
148FK
7802701EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 7802701EA
SNJ54LS148J
7802701FA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 7802701FA
SNJ54LS148W
JM38510/36001B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/
36001B2A
JM38510/36001BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
36001BEA
JM38510/36001BFA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
36001BFA
M38510/36001B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/
36001B2A
M38510/36001BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
36001BEA
M38510/36001BFA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
36001BFA
SN54148J OBSOLETE CDIP J 16 TBD Call TI Call TI -55 to 125
SN54LS148J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 SN54LS148J

SN74147N OBSOLETE PDIP N 16 TBD Call TI Call TI 0 to 70


SN74148J OBSOLETE CDIP J 16 TBD Call TI Call TI 0 to 70
SN74148N OBSOLETE PDIP N 16 TBD Call TI Call TI 0 to 70
SN74148N3 OBSOLETE PDIP N 16 TBD Call TI Call TI 0 to 70
SN74LS147DR OBSOLETE SOIC D 16 TBD Call TI Call TI 0 to 70
SN74LS147N OBSOLETE PDIP N 16 TBD Call TI Call TI 0 to 70
SN74LS148D ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS148
& no Sb/Br)
SN74LS148DE4 ACTIVE SOIC D 16 TBD Call TI Call TI 0 to 70

SN74LS148DG4 ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS148


& no Sb/Br)

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 31-May-2014

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

SN74LS148DR ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS148


& no Sb/Br)
SN74LS148DRE4 ACTIVE SOIC D 16 TBD Call TI Call TI 0 to 70

SN74LS148DRG4 ACTIVE SOIC D 16 TBD Call TI Call TI 0 to 70

SN74LS148J OBSOLETE CDIP J 16 TBD Call TI Call TI 0 to 70


SN74LS148N ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type 0 to 70 SN74LS148N
(RoHS)
SN74LS148N3 OBSOLETE PDIP N 16 TBD Call TI Call TI 0 to 70
SN74LS148NE4 ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type 0 to 70 SN74LS148N
(RoHS)
SN74LS148NSR ACTIVE SO NS 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS148
& no Sb/Br)
SN74LS148NSRE4 ACTIVE SO NS 16 TBD Call TI Call TI 0 to 70

SN74LS148NSRG4 ACTIVE SO NS 16 TBD Call TI Call TI 0 to 70

SNJ54148J OBSOLETE CDIP J 16 TBD Call TI Call TI -55 to 125


SNJ54148W OBSOLETE CFP W 16 TBD Call TI Call TI -55 to 125
SNJ54LS148FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 78027012A
SNJ54LS
148FK
SNJ54LS148J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 7802701EA
SNJ54LS148J
SNJ54LS148W ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 7802701FA
SNJ54LS148W

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.

Addendum-Page 2
PACKAGE OPTION ADDENDUM

www.ti.com 31-May-2014

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54147, SN54148, SN54LS147, SN54LS148, SN74147, SN74148, SN74LS147, SN74LS148 :

• Catalog: SN74147, SN74148, SN74LS147, SN74LS148


• Military: SN54147, SN54148, SN54LS147, SN54LS148

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product


• Military - QML certified for Military and Defense Applications

Addendum-Page 3
PACKAGE MATERIALS INFORMATION

www.ti.com 8-Apr-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal


Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LS148DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 8-Apr-2013

*All dimensions are nominal


Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LS148DR SOIC D 16 2500 333.2 345.9 28.6

Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products Applications
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Wireless Connectivity www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2014, Texas Instruments Incorporated
SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49
SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
SDLS111 – MARCH 1974 – REVISED MARCH 1988

PRODUCTION DATA information is current as of publication date. Copyright  1988, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1


SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49
SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
SDLS111 – MARCH 1974 – REVISED MARCH 1988

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265


SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49
SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
SDLS111 – MARCH 1974 – REVISED MARCH 1988

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3


SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49
SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
SDLS111 – MARCH 1974 – REVISED MARCH 1988

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265


SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49
SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
SDLS111 – MARCH 1974 – REVISED MARCH 1988

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5


SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49
SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
SDLS111 – MARCH 1974 – REVISED MARCH 1988

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265


SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49
SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
SDLS111 – MARCH 1974 – REVISED MARCH 1988

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7


SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49
SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
SDLS111 – MARCH 1974 – REVISED MARCH 1988

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265


SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49
SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
SDLS111 – MARCH 1974 – REVISED MARCH 1988

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9


SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49
SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
SDLS111 – MARCH 1974 – REVISED MARCH 1988

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265


SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49
SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
SDLS111 – MARCH 1974 – REVISED MARCH 1988

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11


SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49
SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
SDLS111 – MARCH 1974 – REVISED MARCH 1988

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265


SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49
SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
SDLS111 – MARCH 1974 – REVISED MARCH 1988

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13


IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
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Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
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Latch/Decoder/Driver for Liquid Crystal Displays
MM54HC4543/MM74HC4543 BCD-to-7 Segment
January 1988

MM54HC4543/MM74HC4543
BCD-to-7 Segment Latch/Decoder/Driver
for Liquid Crystal Displays
General Description
The MM54HC4543/MM74HC4543 BCD-to-7 segment The MM54HC4543/MM74HC4543 are functionally and pin-
latch/decoder/driver utilize advanced silicon-gate CMOS out equivalent to the CD4543BC/CD4543BM and the
technology, and can be used either as a high speed decod- MC14543BA/MC14543BC. All inputs are protected from
er or as a display driver. This circuit contains a 4-bit latch, damage due to static discharge by diodes to VCC and
BCD-to-7 segment decoder, and 7 output drivers. Data on ground.
the input pins flow through to the output when the LATCH
ENABLE (LE) is high and is latched on the high to low tran- Features
sition of the LE input. The PHASE input (PH) controls the Y Typical propagation delay: 60 ns
polarity of the 7 segment outputs. When PH is low the out- Y Supply voltage range: 2 – 6V
puts are true 7 segment, and when PH is high the outputs Y Maximum input current: 1 mA
are inverted 7 segment. When the PHASE input is driven by
a liquid crystal display (LCD) backplane waveform the seg-
Y Maximum quiescent supply current: 80 mA (74HC)
ment pins output the correct segment waveform for proper Y Display blanking
LCD AC drive voltages. Y Low dynamic power consumption
In addition a BLANKING INPUT (Bl) is provided, which will
blank the display.

Connection Diagram Truth Table


Dual-In-Line Package Inputs Outputs
LE Bl Ph* D C B A a b c d e f g Display
X H L X X X X L L L L L L L Blank
H L L L L L L H H H H H H L 0
H L L L L L H L H H L L L L 1
H L L L L H L H H L H H L H 2
H L L L L H H H H H H L L H 3
H L L L H L L L H H L L H H 4
H L L L H L H H L H H L H H 5
TL/F/5128 – 1 H L L L H H L H L H H H H H 6
Top View H L L L H H H H H H L L L L 7
Order Number MM54HC4543 or MM74HC4543 H L L H L L L H H H H H H H 8
H L L H L L H H H H H L H H 9
H L L H L H L L L L L L L L Blank
H L L H L H H L L L L L L L Blank
Display Format
H L L H H L L L L L L L L L Blank
H L L H H L H L L L L L L L Blank
H L L H H H L L L L L L L L Blank
H L L H H H H L L L L L L L Blank
L L L X X X X ** **
Inverse of Output Display
² ² H ² Combinations as
TL/F/5128 – 2
Above above
X Ð don’t care
² e same as above combinations
* e for liquid crystal readouts, apply a square wave to Ph.
** e depends upon the BCD code previously applied when LEÐH

C1995 National Semiconductor Corporation TL/F/5128 RRD-B30M105/Printed in U. S. A.


Absolute Maximum Ratings (Notes 1 & 2) Operating Conditions
If Military/Aerospace specified devices are required, Min Max Units
please contact the National Semiconductor Sales Supply Voltage (VCC) 2 6 V
Office/Distributors for availability and specifications. DC Input or Output Voltage 0 VCC V
Supply Voltage (VCC) b 0.5 to a 7.0V (VIN, VOUT)
DC Input Voltage (VIN) b 1.5 to VCC a 1.5V Operating Temp. Range (TA)
DC Output Voltage (VOUT) b 0.5 to VCC a 0.5V MM74HC b 40 a 85 §C
MM54HC b 55 a 125 §C
Clamp Diode Current (IIK, IOK) g 20 mA
Input Rise or Fall Times
DC Output Current, per pin (IOUT) g 25 mA
(tr, tf) VCC e 2.0V 1000 ns
DC VCC or GND Current, per pin (ICC) g 50 mA VCC e 4.5V 500 ns
Storage Temperature Range (TSTG) b 65§ C to a 150§ C VCC e 6.0V 400 ns
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temp. (TL) (Soldering 10 seconds) 260§ C

DC Electrical Characteristics (Note 4)


74HC 54HC
TA e 25§ C
Symbol Parameter Conditions VCC TA eb40 to 85§ C TA eb55 to 125§ C Units
Typ Guaranteed Limits
VIH Minimum High Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
VIL Maximum Low Level 2.0V 0.5 0.5 0.5 V
Input Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
VOH Minimum High Level VIN e VIH or VIL
Output Voltage lIOUTl s20 mA 2.0V 2.0 1.9 1.9 1.9 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
VIN e VIH or VIL
lIOUTl s0.4 mA 4.5V 4.2 3.98 3.84 3.7 V
lIOUTl s0.52 mA 6.0V 5.7 5.48 5.34 5.2 V
VOL Maximum Low Level VIN e VIH or VIL
Output Voltage lIOUTl s20 mA 2.0V 0 0.1 0.1 0.1 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
VIN e VIH or VIL
lIOUTl s0.4 mA 4.5V 0.2 0.26 0.33 0.4 V
lIOUTl s0.52 mA 6.0V 0.2 0.26 0.33 0.4 V
IIN Maximum Input VIN e VCC or GND 6.0V g 0.1 g 1.0 g 1.0 mA
Current
ICC Maximum Quiescent VIN e VCC or GND 6.0V 8.0 80 160 mA
Supply Current IOUT e 0 mA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C.
Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN,
ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
**VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89.

2
AC Electrical Characteristics VCC e 5V, TA e 25§ C, CL e 15 pF, tr e tf e 6 ns
Guaranteed
Symbol Parameter Conditions Typ Units
Limit
tPHL, tPLH Maximum Propagation 60 100 ns
Delay Data LE, BI, Ph to Output
ts Minimum Setup Time 20 ns
LE to Data
tH Minimum Hold Time 10 ns
Data to LE
tW Minimum LE Pulse Width 16 ns

AC Electrical Characteristics CL e 50 pF, tr e tf e 6 ns (unless otherwise specified)


74HC 54HC
TA e 25§ C
Symbol Parameter Conditions VCC TA eb40 to 85§ C TA eb55 to 125§ C Units
Typ Guaranteed Limits
tPHL, tPLH Maximum Propagation 2.0V 300 600 760 895 ns
Delay Data LE, Ph, BI to Output 4.5V 60 120 151 179 ns
6.0V 51 102 129 152 ns
ts Minimum Setup Time 2.0V 100 125 150 ns
LE to Data 4.5V 20 25 30 ns
6.0V 17 21 25 ns
tH Minimum Hold Time 2.0V 50 63 75 ns
Data to LE 4.5V 10 13 15 ns
6.0V 9 11 13 ns
tW Minimum LE Pulse Width 2.0V 80 100 120 ns
4.5V 16 20 24 ns
6.0V 14 17 20 ns
CPD Power Dissipation pF
Capacitance (Note 5)
CIN Maximum Input 5 10 10 10 pF
Capacitance
Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC.

3
Logic Diagram

TL/F/5128 – 3

Typical Applications
4 Digit LCD Display

TL/F/5128 – 4

4
Physical Dimensions inches (millimeters)

Dual-In-Line Package
Order Number MM54HC4543J or MM74HC4543J
NS Package J16A

5
MM54HC4543/MM74HC4543 BCD-to-7 Segment
Latch/Decoder/Driver for Liquid Crystal Displays
Physical Dimensions inches (millimeters) (Continued)

Order Number MM74HC4543N


NS Package N16E

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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:

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systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.

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