06 Advanced MOSFET PDF

Chap 6 Advanced MOSFET Development
poly-Si,
Gate fin metal Gate
silicon thickness
oxide
oxide
w silicon
Source Drain
silicon
channel length
Dr.-Ing. J.Biba
Advanced MOSFETs and Novel Devices
AdMOS, 6-1
6.1 Overview
Feature size, pitch, node
6.2 State of the Art MOSFETs

Electrical and geometrical parameters
6.3 Mobility-Enhanced MOSFETs

Strain, SiGe, Liners, Directed Channels, Gate-Last
6.4 High-k Metal-Gate MOSFETs

Poly-Depletion, FuSi
6.5 Vertical MOSFETs
6.6 Halo MOSFETs
6.7 SOI MOSFETs
6.8 Double-Gate and Multi-Gate MOSFETs

Fully-depleted MOSFETs, FinFETs, Nanowire FETs
6.9 Advanced Memory Devices
Advanced MOSFETs and Novel Devices Prof.Dr. W. Hansch , Dr.J.Biba

Institut für Physik AdMOS, 6-2
6 Future MOSFETs
6.1 Overview
Advanced MOSFET Development – Forecast and Alternatives
Planar MOSFET
Extensions + Halo Immersion Double + Multi Gate
-> scaling lithography -> scaling
180 nm node 130 nm node 100/90 nm node 70/65 nm node 50/45 nm node 35/32 nm node 22 nm node
140nm – 100nm 90nm – 70nm 65nm – 50nm 45nm – 35nm 30nm – 25nm 20nm – 17nm 14nm – 10nm
1999 - 2001 2002 - 2004 2004 - 2006 2006 - 2008 2008 - 2010 2010 - 2012 2012 - 2014
CMP + Cu + low-k SiGe + strain high-k + metal gate

-> lower RC -> higher mobility -> scaling
FinFET
Lateral GAA 450mm Wafer Monolithic 3D
3xNWs stacked Integration
16/14 nm node 11/10 nm node 8/7 nm node 6/5 nm node 4/3 nm node 3/2.5 nm node 2/1.5 nm node
24nm 18nm 14nm 10nm 10nm 10nm 10nm
2014 - 2016 2016 - 2018 2019 - 2020 2021 - 2023 2024 - 2026 2027 - 2029 2030 -
EUV-lithography Vertical GAA

3xNWs stacked
Emerging devices
TFETs, NanoCarbonTube, New materials

6 Future MOSFETs
6.1 Overview
Advanced MOSFET Development - Shrinking
From economic view the shrinking of devices reduces fabrication costs dramatically (see chapter 2, economics).
(if shrinking can be done using the same equipment.

If new equipment is neccessary after some shrinking the fabrication costs rise)
In addition, shrinked devices offer the advantage of:
* better dynamic performance (faster, less power consumption)

* new applications -> new markets -> more need for chips -> more money
MOSFETs are best suited for shrinking, because:
MOSFETs are Field-Effect devices -> easy scaling

MOSFETs allow CMOS-circuits -> lowest power consumption up today -> best suited for ULSI and mobile
Moore´s Law:
Industry is able to shrink the dimensions of MOSFETs
a factor S  1  0.7 every 3 years (one generation)
2
Using this shrinking factor S = 0.7 / generation a forecast

can be done relating time and properties of MOSFETs.
This is done in so-called roadmaps.

6 Future MOSFETs
6.1 Overview
Advanced MOSFET Development - Forecast by Roadmaps
historical US National Roadmaps 1992, 1994, 1997

1st International Roadmap ITRS
yearly updates
DRAM-complexity 1k 4k 16k 64k 256k 1M 4M 16M 64M 256M 1G 1G * 4G 16G 64G 256G Scaling S
Year 1970/71 1973 1976/77 1979/80 1982 1985 1988 1993 1995 1997 1999 2001 2003 2006 2009 2012 All 3 years
Process p-chan n-chan n-chan n-chanl forecast: ITRS-roadmap 1997
Si-gate Si-gate 2-poly 2-poly
DRAM cell structure 3T 1T 1T 1T 1T 1T 1T 1T 1T 1T 1T 1T 1T
Min.Feature [µm] 8 - 10 7-8 6-7 3.5 2.0 1.0 0.7 0.5 0.35 0.25 0.18 150 130 100 70 50 S=1/2=0.7
(channel length) 3-4 2-2.5 1.5 0.8 0.5 0.3
junction depth [nm] 2500 2000 1000 700 450 250 150 150 100-50 72-36 60-30 52-26 40-20 30-15 20-10
gate oxide thick [nm] 120 120 100 70, 70 45 30-20 15-10 15-10 5-4 4-3 3-2 3-2 2-1.5 < 1.5 < 1.0
gate width µm 5-7 3-4 2 1.2 0.5 0.5
interconnect width µm 5 4 3 2 1 1
interconnect thick µm 1 1 0.9 0.75 0.6 0.6
cell area [µm²] 3700 900 450 170 30 10 3.9 1.5 0.56 0.22 0.14 0.09 0.036 0.014 0.006 S²/1.3
Chip size [mm²] 13 19 18 21 38 55 80 145 190 280 400 445 560 790 1120 1580 1 / 1.5
Udd [V] 18/12 12 12,5 5, 5 5 5 5-3.3 3.3 2.5- 1.8 1.8-1.5 1.5 1.2 1.2-0.9 0.9-0.6 0.6-0.5
Power dissipation [W] 0.2 70 90 110 130 160 170 175
comments HMOS HMOS HMOS
II
! All properties listed in the ITRS are only calculated with a working MOSFET,
there exists no prediction how to achieve these values !
As an indicator, whether the technology exists

to fabricate future devices, colors are used:
no problem
existing technology, but

development neccessary
no imagination, how to do

6 Future MOSFETs
6.1 Overview
Advanced MOSFET Development - Forecast by Roadmaps
Have a look at:
http://www.itrs.net/
http://www.itrs2.net/
"New way" Higher performance

-> "more than Moore" by better systems
"Old way"
-> "More Moore"
Higher performance
by higher integration
-> shrinking
Minimum Feature size F

6 Future MOSFETs Advanced MOSFET Development
6.1 Overview - Minimum Feature Size and Pitch
1) Generations were characterized by the so-called "minimum feature size F", which can be fabricated.
According to the fabrication process of MOSFETs, this minimum feature size was identically with the channel length.
Minimum Feature
Size 1 F pitch
MOSFET 1 MOSFET 3
MOSFET 2
2F plug
plug
Iso Gate
Gate Gate 1F
1F Iso 1F 1F
1F D 1F
Iso S Iso Iso Iso
4F 5F 5F
* all-over Isolation * fill in Isolation * open S/D plugs with 1F
* open 4F in Isolation with distance 2F
* put in 1F Gate (misalignment not critical) channel
* selfaligned S/D Implantation
* MOSFETs in INTEL-PIII MPU (IEDM2000)

Process flow (test-pattern of MOSFETs, not real circuit-design)
* here: pitch 5F, but missing isolation -> 6F
In the first International Technology Roadmap (2001) two things were recognized: * channel length < 1F, but 1F is pattern size (litho)
2) Some structures cannot be scaled with F to ensure proper working,

e.g. shallow Source/Drain with 1F² will result in too high series resistance
3) On chips not single devices are fabricated, but functional structures (DRAM, inverter).
Therefore, to describe the number of functional blocks, not the channel length is important, but the density of blocks.
This is described by the "pitch" (distance between
Advanced repeating
MOSFETs structures).
and Novel Devices Prof.Dr. W. Hansch , Dr.J.Biba
- printed gate length

Resist trimming - physical gate length
- electrical channel length

Starting in 2002 the terminus "node" was used

to characterize the smallest "half-pitch" in devices
(mainly the DRAM Gate half-pitch and Metal-1 in MPUs)
Starting in 2012 the terminus "node" was used more generalized to

characterize the principle smallest functional dimensions in devices
(mainly the FinFET electrical channel length )

6.1 Overview - Minimum Feature Size, Pitch and Node
http://www.itrs2.net/
Note the different dimensions for node, pitch, channel length

6.1 Overview - Application dependent MOSFETs
History (1960- 2000): multi-purpose MOSFETs were designed according the scaling laws
Trend( since ~2000): scaling limits for several structures reached (e.g.: gate oxide -> tunneling -> no high-k available)
-> depending due to the application different performance is needed
high performance
History year Future (MPU)
~2000
Long-channel MOSFETs Short-channel MOSFETs Nano-MOSFETs general purpose
(ASIC)
low power low stand-by power

(mobil, DRAM) (battery)
low operational power
(Laptop)
Example:
System on Chip (SoC) with all needs
DRAM: leakage current must be avoided

(will change stored information)
-> thick gate oxide (-> high Vt and no tunneling)
Logic: should be fast, leakage not so important

-> thin gate oxide
Source: Toshiba, IEDM 2002

6.1 Overview



6.6 Halo MOSFETs
6.7 SOI MOSFETs


6 Future MOSFETs
6.2 State of Art
A Year 2000 State-of Art MOSFET
• LG =70nm defined by lithography (printed)

(KrF 248nm, ArF 193 nm with phase shift masks)
• SDEs self-aligned to gate
• High-quality gate oxide (1.7-1.5nm)
• Small parasitic capacitances
Typical values from INTEL, FUJITSU, Toshiba, ... :
Usually dual VT (by 2 oxide thicknesses) is used:

- high Vt (thick gate oxide) -> low leakage, slowly -> low power
- low Vt (thin gate oxide)-> high speed, high leakage -> high performance

6 Future MOSFETs
6.2 State of Art
Year 2000 / 2009 State-of Art MOSFETs
Typical performance values from INTEL, IBM, FUJITSU, Motorola, Hitachi:
2000 Node: 130 nm 2009 Node: 32 nm
• LG =70 nm defined by lithography (printed)

• LG =32 nm defined by lithography (printed)
(KrF 248 nm, ArF 193 nm with phase shift masks)
(ArF 193 nm immersion with phase shift masks)
• High-quality gate oxide (1.7-1.5 nm)
• High-k (EOT = 0.9 nm) + metal gate
• Small parasitic capacitances

6 Future MOSFETs
6.2 State of Art
Year 2015 State-of Art MOSFET (FinFET)
2014 Node (FinFET): 14 nm
INTEL, IEDM 2014
• Fin width 8 nm
• Fin pitch 42 nm
• Replacement Gate
• High-k + Metal Gate

6 Future MOSFETs
6.2 State of Art
Year 2017 State-of Art MOSFET (FinFET)
2016 Node (FinFET): 10 nm Samsung 2016
S: ~ 65mV/dec
DIBL: ~ 30mV/V
https://news.samsung.com/global/samsung-starts-industrys-first-mass-
production-of-system-on-chip-with-10-nanometer-finfet-technology
• Fin width: ?
• Fin pitch: ?
• High-k + Metal Gate
• Triple patterning
04.01.2017: Snapdragon 835 (Qualcomm) is the first chipset to be made

on the 10nm FinFET process node of Samsung. Samsung 14 nm FinFET
Source: TechInsights
6 Future MOSFETs
6.2 State of Art
Typical performance values from INTEL, FUJITSU, Motorola, Hitachi:

2009 Node: 32 nm
2000 Node: 130 nm L: ~ 32 nm, EOT: ~ 0.9 nm high-k HfSiON

VDD: ~ 1.0 V, Vt:~ 0.4 V
Lgate: ~ 70nm, tox: ~ 1.5nm
VDD: ~ 1.2 V, Vt:~ 0.5 -0.4 V
0.25 A/mm
/0.1 Vg
S: ~ 90mV/dec
DIBL: ~ 100mV/V
Ioff: 10-100nA/µm
Ion: ~ 1mA/µm gm: ~2500 mS/mm
0.2 A/mm
Ioff: ~ nA/µm
INTEL, IEDM 2008
/0.2 Vg Ion: ~ 1mA/µm
gm: ~1000 mS/mm S: ~ 100mV/dec

DIBL: ~ 130mV/V

6 Future MOSFETs
6.2 State of Art
2009 Node: 32 nm INTEL, IEDM 2008 2014 Node (FinFET): 14 nm INTEL, IEDM 2014
L: ~ 32 nm, EOT: ~ 0.9 nm high-k HfSiON L: ~ 20 nm, high-k HfSiON

VDD: ~ 1.0 V, Vt:~ 0.4 V VDD: ~ 0.7 V, Vt:~ 0.3 V
Ioff: ~ 10nA/µm
Ioff: ~ 100nA/µm Ion: ~ 1mA/µm
Ion: ~ 1mA/µm
S: ~ 65mV/dec
S: ~ 100mV/dec DIBL: ~ 70mV/V
DIBL: ~ 130mV/V
0.3 A/mm
/0.1 Vg
gm: ~3000 mS/mm
gm: ~2500 mS/mm

6 Future MOSFETs
6.2 State of Art
Year 2015 / 2017 State-of Art MOSFETs (FinFET)
2014 Node (FinFET): 14 nm 2016 Node (FinFET): 10 nm Samsung 2016

INTEL, IEDM 2014
L: ~ 20 nm, high-k HfSiON L: ~ nm, high-k
VDD: ~ 0.7 V, Vt:~ 0.3 V VDD: ~ 0.75 V, Vt:~ 0.3 V
Ioff: ~ 10nA/µm Ioff: ~ 50nA/µm

Ion: ~ 1mA/µm Ion: ~ 1mA/µm
S: ~ 65mV/dec S: ~ 65mV/dec
DIBL: ~ 70mV/V DIBL: ~ 30mV/V
Samsung Intel
10 nm 10 nm
0.3 A/mm xxx 34 nm
/0.1 Vg
64 nm 54 nm
48 nm 36 nm
gm: ~3000 mS/mm
0.04 um² ? um²
https://www.extremetech.com/computing/221532-tsmc-will-begin-10nm-production-this-year-claims-5nm-
by-2020

6 Future MOSFETs
6.2 State of Art
2000 Node: 130 nm 2008 Node: 45 nm
Vt roll-off: good above L > 70nm Vt roll-off: good above L > 35nm
high fluctuations -> challenge for circuit design
stage delay: ~7psec

6 Future MOSFETs A Year 2000 vs 2009 vs 2015 State-of Art MOSFET
6.2 State of Art – SRAM Performance
SRAM: For demonstration of design improvement 6T-SRAM cells are used (usually embedded in MPU):
- regular structure
- easy to evaluate density and yield (like DRAM, DRAM-pitch)
2000 Node: 130 nm 2009 Node: 32 nm
STI Typical cell size:

(1.3 x 1.7) µm² = 2.2 µm²
! Make a test:
2000 -> 2009 = 3 generations
-> does scaling work ?
Gate etch Metallization
! Make a test:
0.059µm²
2009 -> 2014 = 2 generations
-> does scaling work ?
Schmoo-plot (fmax =f(VDD) of SRAM performance

6 Future MOSFETs
6.2 State of Art
A Year 2015 State-of Art MOSFET– SRAM Performance
SRAM:
2014 Node (FinFET): 14 nm Intel's 6T SRAM options in their SoC technology, including
high density / low leakage (HDC), low voltage (LVC), and high
performance (HPC) [1
BL VDD VSS T1 T4 T5
WL T1 T4 T5
BL VDD VSS M1
T1 T4 T5
T2 T3 T6 WL Gate pitch
WL M1
VDD VSS BL = 70 nm
T2 T3 T6
VDD VSS BL M1
T2 T3 T6
fin pitch = 42 nm
poly-Gate
poly-Gate
courtesy: A.B.Kahng; "The ITRS Design ...",

Design Automation Conference, 2013

6 Future MOSFETs A Year 2000 vs 2009 State-of Art MOSFET
6.2 State of Art – Interconnects
2000 Node: 130 nm 2009 Node: 32 nm
Interconnects limit the RC delay

of faster devices
AR ~ 1.6 -> more metallization layers -> lower R

-> higher aspect ratios/ low-k ILD -> lower C
Typically:
# 6-8 layers of interconnects
# Cu + ILD
# every layer separately optimized
Minimum pitch on device layer

(isolation, gate, contact, metal1)

2009 Node: 32 nm 2014 Node (FinFET): 14 nm
Interconnects limit the RC delay

of faster devices
-> more metallization layers -> lower R

-> higher aspect ratios/ low-k ILD -> lower C
Minimum pitch on device layer

(isolation, gate, contact, metal1)

2000 Node: 130 nm
2009 Node: 32 nm
pitch-dependent sheet resistance
RC delay for 1mm wire length, line capacity: ~ 250fF/mm for M1-M5

6 Future MOSFETs
6.2 State of Art
State-of Art MOSFET – Processor Development
- Willamette (2000)
180nm, channel: 90nm, 217mm², < 2 GHz, L2 =256kB, 42 Mill. T
- Northwood (2002)
130nm, channel: 65 nm, 146mm², < 3GHz, L2=512kB, 55 Mill. T
- Prescott (2004)
90nm, low-k, metal: 7 levels Cu, channel: 45 nm, 112mm², < 3.4GHz, INTEL Broadwell
L2=1024kB, 125 Mill. T
- Cedar Mill (2006) [tick]

65nm, strain channels with SiGe S/D &Si3N4, 2 cores, 596mm², 1.7 Bill. T
- Penryn (2008) [tick]

45nm, high-k + metal gate, 6 cores, 503mm² up to 1.9 Bill. T.
- Westmere (2010) [tick]

32nm, high-k + metal gate, 10 cores, 512mm² up to 2.6 Bill. T.
- Ivy Bridge (2012) [tick]

22nm, FinFET, 15 cores, 541mm² up to 4.3 Bill. T
- Haswell (2013) [tock]
22nm, FinFET, 18 cores, 661mm² up to 5.5 Bill. T
- Broadwell (2014) [process]

14nm, FinFET, 22 cores, 456mm² up to 7.2 Bill.T
- Skylake (2015) [architecture]
14nm, FinFET, 28 cores, ? mm² up to ? Bill. T
- Kaby Lake (2016) [optimization]
14nm, FinFET, ?? cores, ? mm² up to ? Bill. T http://arstechnica.co.uk/gadgets/2015/06/intel-launches-long-delayed-quad-core-broadwell-cpus-and-the-iris-pro-6200-gpu//
- Cannonlake (2017?) [process]

10nm, FinFET,

6 Future MOSFETs Intel Always a Step Ahead ?
6.2 State of Art
INTEL, 2017
In history INTEL wanted to be the most innovative semiconductor manufacturer

6 Future MOSFETs Intel: News about 10 nm FinFET (29.03.2017)
6.2 State of Art
Logic Transistor Density

Transistor
Density
MTr/mm²
• Fin pitch 34 nm
• Fin height 53 nm
Samsung Intel
10 nm 10 nm
xxx 34 nm
INTEL, 2017
64 nm 53 nm
48 nm 36 nm
0.04 um² xx um²
INTEL claims to be 3 years ahead of the other companies

6 Future MOSFETs Intel: News about 10 nm FinFET (29.03.2017)
6.2 State of Art
INTEL, 2017
Through clever technological design (hyper scaling) INTEL seems to achieve a higher
transistor density
Foundries do a hybrid scaling and not a full node scaling

6.1 Overview



6.6 Halo MOSFETs
6.7 SOI MOSFETs


6 Future MOSFETs
6.3 Mobility Enhanced MOSFETs
Mobility Enhanced Channels - The Problem !
The Ion current of a MOSFET w  2


I D    C   VGS  VT  VDS 
´´ VDS
is given by: ox 
L  2 
mobility increases/decreases drive current and therefore High-Frequency performance
The problem: Mobility decreases in high Electric Fields
Electric Fields in Nano-MOSFETs
Estimation:
If channel length: 100nm (Linear) Electric Field:
VDrain = 1 V 1V/100nm = 105 V/cm
v=µ*E
bulk mobility is reduced
Sze, Irvin: RESISTIVITY, MOBILITY AND IMPURITY LEVELS IN GaAs,

Challenge for sub-100nm CMOS: increase mobility in high electric fields
Ge, AND Si AT 300°K, Solid-State Electronics, 11(1968)599 introduction of strain techniques for 90 nm node
6 Future MOSFETs Mobility Enhanced Channels - Overview
* carrier scattering events

  e   
Field-effect mobility is basically dependent on: vdrift    E   E
2m * -> non-periodic atoms (doping, surface roughness)
-> lattice vibrations (temperature)
* carrier mass -> bandstructure -> transport (ballistics, tunneling)
d 2 (k ) 1

dk 2 m*
flat bands -> high masses
->low mobility
steep bands -> low masses
-> high mobility
bandstructure dependent on:
* material
wave vector k * crystal orientation
L <111>  <100> X  * strain
Material Strain Crystal Orientation

with higher bulk mobilities inside the channel from surroundings surface direction
Ge, SiGe -> material -> liner (100), (110), ... <110>, <100>, ...
(SiGe, ..) -> S/D
and combinations
6 Future MOSFETs
6.3 Mobility Enhanced MOSFETs Mobility Enhanced Channels - New Channel Materials
Due to interface states Dit from 1960 (first working MOSFET) until ~ 2007 the only possibility to create a proper working MOSFET
was using Si(100) and thermal oxidation for the Gate oxide
Energetic Distribution in the Band Gap Dependence on Surface Orientation
NV =1019
=1018 cm-3
Dit ~ 1010cm-2
This explains why (100) substrates

are used for MOS Technology
WV
historical measurement:
Arnold et al., CRYSTALLOGRAPHIC SYMMETRY OF SURFACE STATE DENSITY
IN THERMALLY OXIDIZED SILICON, Appl.Phys.Lett 13(1968)413

6 Future MOSFETs
Why we need an interface state density Dit ~ 1010cm-2 or lower ?

Let´s make an estimation:
1) How many charges are in a switched-on channel ?
Estimation 1) a conducting channel acts as a metallic layer
-> for silicon this is the case, if the Fermi level is within the bands -> this needs dopings above ND >1019 at/cm³ = ne
because the thickness of the channel is only a few nanometer, the (volume) charge carrier density ne can be expressed as
area charge density ne" (carrier/cm²).
-> to calculate the area charge density ne" we can multiply the volume charge density ne by the thickness of the channel (~5nm)
-> 1019 at/cm³ * 5 nm = 1019 at/cm³ * 5*10-7 cm = 5*1012 e/cm2
Estimation 2)
The Gate capacity is about: C"=0ox/tox, -> C"~10-13*4/4nm = 10-6 F/cm².
This results in a charge of: Q=C*U = 10-6 F/cm² * 1 V = 10-6 Cb/cm²
=> number of electrons: ne" = 10-6 Cb/cm²/ 1.6*e-19 Cb/e -> 6*1012 e/cm² ne" ~ 5*1012 at/cm2
SOURCE DRAIN
In a switched-on MOSFET-channel around 1012 - 1013 electrons/cm² are existing
2) How are the channel charges created ? How many in a 32nm MOSFET ?
GATE metal Non-ideal case:

+ + + + + GATE metal
+ + - oxide charges may create channel charges
E oxide
+E + + oxide
without external Gate voltage or are screening
the external voltage
channel channel -> no channel charge control, if oxide charges (Dit)
Ideal case: reach same amount as desired channel charges
- perfect (charge-free dielectrics)
for good channel control the Dit should be less 1% of the channel charge
-> each metal gate charge creates a channel charge
-> Dit ≤ 1010 cm-2
6 Future MOSFETs
Due to interface states Dit from 1960 (first working MOSFET) until ~ 2007 the only possibility to create a proper working MOSFET
was using Si(100) and thermal oxidation for the Gate oxide
1) Using Germanium in old days (1948-1954) -> the oxidation of Ge delivers a very hygroscopic thermal Gate oxide
-> no long-term stable MOSFET
-> standard technology with Ge is bipolar
2) Using Compound Semiconductors (GaAs, InP, ...) -> delivers inhomogeneous thermal Gate oxides
(because one element is oxidizing faster than the other)
-> inhomogeneous oxide thickness along channel
with different materials (work functions are changing)
-> no reproducible Vt for devices
Oxidfilme auf AIIIBV-Halbleitern
-> standard technology with III-V is bipolar
K. Löschkea, G. Kühna, H.-J. Bilz Unda and G. Leonhardta
Abstract
Thermal oxidation of GaP, InP, GaAs, GaSb and InSb was carried out at room temperature and at 300 °C in air. The optical constants and film thicknesses were measured ellipsometrically and the
same samples, including oxidized GaSb, were investigated by photoelectron spectroscopy. The concentration profiles of the elements in the films and their binding state were determined. It is shown
that the elements in oxide films of GaP are oxidezed perfectly, whereas films of the other compounds exhibit a very inhomogeneous structure. The thicknesses of the oxide films increase in the order
GaP ≈ InP < GaAs < GaSb, InSb. The interpretation of the ellipsometric measurements is complicated by the presence of a non-oxidized BV component, especially in the case of arsenides and
antimonides.
3) For deposited Gate dielectrics the interface state density is for all materials close to 1012 /cm²
GaAs metal-oxide-semiconductor devices with a complex gate oxide composed of SiO2 and GaAs oxide grown using a photoelectrochemical oxidation method
Hsin-Ying Lee et al 2010 Semicond. Sci. Technol. 25 015005 (4pp)
Abstract. In this study, a SiO2/GaAs oxide bi-layer layer was used as the gate oxide in GaAs-based metal-oxide-semiconductor (MOS) devices.
The GaAs oxide layer of the bi-layer layer was directly formed on the GaAs surface by using the photoelectrochemical (PEC) oxidation method.
Some samples were thermally treated at 200 °C and 300 °C in O2 ambience for 30 min.
The surface state density of the oxide/GaAs interface with and without GaAs oxide thermal treatment was 7.2 × 1011 and 7.9 × 1011 cm−2 eV−1, respectively.
The GaAs MOS field effect transistors (MOSFETs) with the PEC-deposited GaAs oxide thermally treated showed an output current of 152 mA mm−1 at VDS = 2.4 V and VGS = 0 V
and an extrinsic transconductance of 89 mS mm−1.

6 Future MOSFETs
But why we use deposited high-k today ?
INTEL, IEDM 2007 INTEL, 2012
Solution:
We use silicon substrate

and create a thin interface layer
of SiOx to achieve good Dit
courtesy: AMD, Ph.D. thesis Kelwing 2014

6 Future MOSFETs

6 Future MOSFETs
Egap (Si) = 1.1 eV
Silicon cubic fcc lattice

lattice constant: aSi = 0.54 nm
Egap (Ge) = 0.67 eV
Mobility of electrons and holes 2 times higher in Ge

Germanium
cubic fcc lattice
lattice constant: aGe = 0.56 nm
Ge lattice is about 4.2% larger than Si So let´s try to use Ge in the channel

6 Future MOSFETs
Mobility Enhanced Channels - SiGe
For defectfree devices the Ge must be grown epitaxially on Si-substrate.

-> No problem, since both elements have the same cubic lattice,
but Ge lattice is 4.2 % larger
Ge or mixtures of Si-Ge -> because Ge lattice is larger, with epitaxial growth strain is induced
can be grown epitaxially on Si
Mixing Si (Egap = 1.1 eV) and Ge (Egap = 0.67 eV) results in an

intermediate bandgap of the mixture (Vegard´s rule)
Dependent on the Ge-fraction a critical thickness

limits the pseudomorphic growth of SiGe on Si -> for 10 % Ge the bandgap is changed only 10 %
-> experiments show, that the step in band is only in the valence band
-> for a 10nm thick channel only 10 % Ge can be used -> technology shows, on Ge or SiGe, no oxide with MOS-quality can be grown
-> only 10-20 % improvement of mobility using Ge in the channel an additional Si-cap is necessary to form MOS-oxide

6 Future MOSFETs
Looking around: SiGe – HBT
In a Si bipolar transistor the current gain is determined by the thickness and doping of the base layer.
A trade-off has to be found for the thickness and doping to optimize the current gain:
- as thinner the base as higher the current gain, but as higher the resistance (decreasing current gain)
- as higher the doping as lower the resistance, but as higher the leakage current (tunneling)
In the SiGe Hetero-Bipolar Transistor (HBT), Ge is selectively introduced into the base region of a Si-bipolar transistor
The bandgap of the SiGe-base arranges linearly between the bandgap of pure Si (1.12eV) and pure Ge (0.67eV) (called Vegard´s law).
The band-offset is almost in the valence band.
SiGe (HBT) technology: Transistor HF-performance: Frequency divider: Low Noise Amplifier (LNA):
(digital application) (analogue application)
Input
Output
80mV
Source: Infineon, IEDM2000 fmax: 128 GHz, 88 GHz input, at 12 GHz:

FT : 85 GHz at 2mA consumes 100mA at 6V noise: 1.9 dB, gain: 25dB
The smaller base bandgap enhances electron injection, producing a higher current gain compared to Si for the same base doping level.
In addition with varying vertical Ge-content in the base an intrinsic drift-field can be incorporated to improve the transistor frequency
SiGe is standard high performance Bipolar technology

6 Future MOSFETs
Mobility Enhanced Channels - SiGe – MOSFET
The band offset in SiGe is used to improve mobility
but Si-cap needed for MOS
Band offset for SiGe is almost in the valence band

-> for p-MOSFET most holes in the channel are confined to SiGe
-> for n-MOSFET a fraction of channel electrons move in SiGe
Band offset and strain properties improve performance
n-MOSFET p-MOSFET
CMOS with 100nm gate length (University research)
Source:UCLA, IEDM2000
Selective epitaxy with UHV-CVD

for Si 0.76 Ge 0.24 the critical thickness is 10nm
S/D recrystallization: 950°C, 30sec
Epitaxy in CVD-reactors is standard CMOS technology.
Introducing Ge in Si-CMOS improves performance

for nearly no cost rise

6 Future MOSFETs
Mobility Enhanced Channels - SiGe – MOSFET
Electrical properties of SiGe-MOSFETs (experimental state): Source:UCLA, IEDM2000
!!! x
Ioff < 0.1nA/µm S: ~100mV Threshold voltage is shifted to positive values for SiGe
DIBL: <10mV
Ion increased by 25% ín p-MOSFETs with SiGe channel
-> Fabricating defectfree SiGe with additional Si-cap is not easy

-> Performance increase in mobility larger as expected just from Ge content
An additional increase in mobility is induced by strain

6 Future MOSFETs
Mobility Enhanced Channels - Strained Channels
How can strain increases mobility ?
Not easy to answer, not completely understood
Holes Electrons
Silicon (no strain) SiGe under biaxial strain
The six-fold degeneracy for electron masses

is decoupled in 4 in-plane lower energy valleys
and 2 perpendicular transport, higher states
-> higher mobility
The biaxial stress (lateral and vertical) breaks down the existing
cubic lattice symmetry. To create strain different approaches exist
For holes in strained Si the top-most heavy hole mass is reduced

-> higher mobility

6 Future MOSFETs
Creation/Measurement of strain
Depending on wafer and pit orientation
tensile or comressive stress, and also
uniaxial and biaxial stress can be created
wafer with devices on top
tensile stress
Example of measurement
compressive stress
uniaxial stress biaxial stress

6 Future MOSFETs
Strain is induced on special fabricated Si substrates with relaxed SiGe-buffer
Advantage:
50 % current gain !
Disadvantage:
high sophisticated process

for buffer growth
takes a long time > 3h
very expensive
Courtesy: AMD
presented at Analyst Meeting 2002
6 Future MOSFETs

6 Future MOSFETs
Other concepts: Induce strain from surroundings, not from substrate
n-MOSFET INTEL CMOS: p-MOSFET

65 nm node
* introduce tensile strain in the channel L = 35 nm
* introduce compressive strain in the channel
tox (SiON) = 1.2nm
FUSI: NiSi
4 layers of nitride
metal
from Liner gate from Liner from Liner from Liner
spacer
tensile stress
compressive stress
tensile strain introduced by: compressive strain introduced by:

* 4 layers of nitride + NiSi2 - S/D * SiGe
nitride: strain can be adjusted by process Ge: larger atom than Si + advantage of higher doping
NiSi: volume reduction during formation
INTEL: IEDM 2005
http://www.intel.com/technology/itj/2008/v12i2/1-transistors/6-stressenhancement.htm
6 Future MOSFETs

6 Future MOSFETs
INTEL CMOS:
65 nm node
L = 35 nm
tox (SiON) = 1.2nm
FUSI: NiSi
n-MOSFET p-MOSFET
complexe technology
-> more fluctuations ! best Ion / Ioff ratio as reported
highest reported drive current Ion in industrial devices !

(but with the help of metal gate) -> see later

6 Future MOSFETs
Mobility Enhanced Channels - Strain Memorization
higher strain

6 Future MOSFETs

6 Future MOSFETs
Jan 2010 Gate-first
Sep 2010: problems with Gate-first

6 Future MOSFETs
Since the 20 nm technology node all companies

are using Gate-Last/Replacement-Gate
6 Future MOSFETs
Mobility Enhanced Channels - Directed Channels
Silicon exhibits a cubic lattice

Orientation of crystal planes and directions can be defined by intersection points with the unit cell axis
(111) plane (100) plane (110) plane
Historically, for CMOS-Technology all wafers are fabricated with:

<100> <110>
- (100) surface <110>
(best interface Si/SiO2 with (100)
<100> (100)
lowest interface state density) surface
<110> (100)
<110> (110)
- <110> channel direction
- closest package of devices rectangular flat
- best lithography rectangular flat
- best orientation for electron and hole topview
arrangement of devices on a wafer
mobility

6 Future MOSFETs
6.3 Mobility Enhanced MOSFETs New Technologies
Rotated wafer New surface orientation
<100> <110>
(100)
<110> (100)
surface
(110)
in <110> direction
flat
arrangement of devices on a wafer
Since ~2004 various companies (INTEL, AMD, IBM,..), which are

fabricating high-performance MPUs, are using (100)-wafers, but
with notch in <100> direction ( = rotated wafers) to use existing equipment.
Arranging device channels in <100> direction may increase hole mobility
of about 15% without decreasing electron mobility.
in <110> direction
Combined technology
+ strain
We need to have detailed knowledge of bandstructure

6 Future MOSFETs Mobility Enhanced Channels
6.3 Mobility Enhanced MOSFETs - Hybrid Orientated Channels
Hybrid Orientation Technology (HOT)

Due to higher mobilities of holes (p-MOSFET) on (110)-surface, but higher mobility of electrons (N-MOSFETs) on (100)-surface,
each type of MOSFET should have its own surface orientation on the same substrate (handling wafer).
first proposed by IBM at IEDM 2003
Both types of handling wafers are possible, but today best developed wafers (with 300mm) are (100)-wafers
Advantage: Advantage:
+ well established (100)-wafer in 300mm (cheap)
+ low temperature wafer fabrication + better performance with n-FET on SOI
+ well established (100) selective epitaxy and p-FET in substrate
Disadvantage: Disadvantage:
- non-established (110)-wafer bonding - high-temperature wafer bonding
- n-Fet in substrate requires additional - difficult (110) selective epitaxy
technology steps (halo) to avoid SCE

Usual fabrication of SOI-wafer Wafer Bonding
Smart Cut
SIMOX (Separation by implanted oxygen)

Basic technology steps:
1. wafer bonding (100) and (110)

2. reduce SOI thickness to ~50nm (CMP)
3. open BOX down to handling wafer
4. selective epitaxy
5. conventional CMOS fabrication


6 Future MOSFETs
Mobility Enhanced Channels - Putting all together
Depending on company´s technology experience and risk willingness various combinations of the mobility enhancement techniques
are possible:
Using liners Using SiGe and liners
Using HOT and liners
See research for vertical

stacked hybrid channel
devices chapter 6.8

6.1 Overview



6.6 Halo MOSFETs
6.7 SOI MOSFETs


6 Future MOSFETs
6.4 Metal Gate MOSFETs
Metal Gate MOSFETs
In contacts of materials always a contact potential exists which depends more or less on the workfunction of the various materials
This contact potential causes a depletion zone depending on charge carrier density
Conventional CMOS: Highly doped Poly-Silicon is used as Gate electrode metallization
Advantages: Technological: * self-adjust S/D formation because of high temperature stability (1100°C), no reaction with SiO2
Electrical: using p+ and n+ poly gates symmetrical VT on doped Si (P-MOS and n-MOS) can be realized
important for good CMOS-inverter characteristics
Disadvantages 1) high resistivity of gate electrode even with silicide on -> additional design and technological effort on Gate lines
in connection with thin gate oxides (3-1)nm as required from scaling roadmap
2) penetration of boron doping atoms from poly-Si Gate in/through oxide causes shift in threshold voltage VT
3) because poly-Si is just high doped (1020 cm-3) and not a metal (1022 cm-3) a depletion width exist of about 1 nm
at the interface of poly-Si to SiO2.
With scaling to tox ~1nm this depletion zone contributes in Gate capacitor to electrical oxide thickness,
this reduces gate capacitance and therefore drive current Ion
Possible solutions: 1) extremely high doping (ev.Ge) -> but creating charged defects -> mobility in channel and Ion decreases
-> no help for boron diffusion
2) opposite doping of poly-Gate -> poly-Si in accumulation, if MOS is in inversion
-> but additional processes are needed (increasing cost, decreasing yield)
3) new Gate material -> Metal -> what about adjustment of VT ?
-> what about manufacturing ?
these solutions are addressed in this section

6 Future MOSFETs
Metal Gate MOSFETs - The poly-Si Process
Conventional CMOS: Poly-Si Gate allows selfadjusting process with nanometer resolution: S/D extensions doping,
spacer formation,
S/D doping,
Various processes for poly-Gate are possible: Halo doping
n-doping p-doping
Standard process (1970 - 2007):
1) deposit undoped poly-Si for all devices
isolation
2) Gate patterning (1 mask)
Si 3) S/D doping for n-MOSFETs and p-MOSFETs (2 masks)
n-doped
Sometimes used:
1) deposit single-doped poly-Si for all devices
Si 3) S/D doping for n-MOSFETs and p-MOSFETs (2 masks)
Not used yet:

1) deposit opposite doped poly-Si for n-Gates and p-Gates (2 masks)
Si
3) S/D doping for n-MOSFETs and p-MOSFETs (2 masks)

6 Future MOSFETs
Metal Gate MOSFETs - A view on poly-Si Gates
Poly crystalline Si-gate
poly-Si
amorphous Gate oxide
c-Si

Single crystalline Si-wafer

6 Future MOSFETs
Metal Gate MOSFETs - Electrical Oxide Thickness
Gate Capacitance involves 3 capacitors: E

Ec
+ EF
++
Gate highly doped poly-Si + EV
electrode + VG ++
EF ++
Cpolydep n+-doped
Gate Cox
dielectrics depth into substrate [nm]
Cqm
Year 2005 2006 2007 2010 2013 2016
Node [nm] 80 70 65 45 32 22
Silicon Printed Gate 45 40 35 25 18 13
substrate Leff [nm] 32 28 25 18 13 9
EOT [nm] 1.1 1.0 0.9 0.7 0.6 0.5
Ec
all contribute about 1 nm to the total Gate capacitor

classical charge distribution
 SiO2 
* poly depletion tox,el  tox   w polydepl  SiO2  wqm quantum charge distribution
* oxide  poly  Si Ec
* quantum mechanical
tox,el  tox  0.33  w polydepl  0.33nm
1
cancelled out by metal nm
depth into substrate [nm]
6 Future MOSFETs
Metal Gate MOSFETs - Effects of poly-Si Depletion
Gate Depletion Effects (GDE) are:
Reduction of Gate capacitance in On-state (inversion) Voltage drop in Gate depletion zone
-> increase of Short Channel effects (SCE) -> lower Gate voltage on channel -> lower drive current Ion
These effects are increased with

thinner oxides
Metal Gate favorable at 65 nm node

(2007, EOT < 1 nm)

6 Future MOSFETs
Metal Gate MOSFETs - Experimental results
INTEL: IEDM 2005
20 % Capacity Gain
INTEL CMOS: with Fully Silizided (FUSI)
65 nm node Gate metal (NiSi)
L = 35 nm
tox (SiON) = 1.2nm 15 % Current Gain n-MOS
FUSI: NiSi
with Fully Silizided (FUSI)
Gate metal (NiSi)
Texas Instruments CMOS:

65 nm node
L = 35 nm Yu et al., TI, IEDM 2005
EOT (SiON) = 1.7 nm
FUSI: NiSi
as measured VT normalized
* better S
* lower Ioff
higher VT for NiSi
Yu et al., TI, IEDM 2005 Yu et al., TI, IEDM 2005
Metal Gate works ! But: What about VT ?

6 Future MOSFETs
Metal Gate MOSFETs - Adjusting VT
What metals can be used to achieve symmetrical VT ?
To overcome the problem of doping fluctuations and to achieve better gate control undoped channels will be needed.
Therefore the barrier must be created by the workfunction of the gate metal.
Basic value of work function may be choosen from reported bulk values
but: 1) scaling VT will need different metal MS every future node -> no chance for technology try to adjust workfunction
2) measured workfunction may be dependent on process, charges (doping) and dielectrics with one metal

6 Future MOSFETs
Workfunction may be adjusted with:
metal doping Si channel doping oxide thickness

Example: NiSi
not
shown
here
published data for NiSi, exact values are very sensitive to fabrication process
frequently used process:
doping poly-Si and then silicidation which results in rearrangement of doping Source: Hosoi et al., RCNS, 2004
Ni but basically fixed due to scaling rules

NiSi
VT can be adjusted symmetrically
for n- and p-MOSFETs
1) formation of poly-Gate 4) formation of silicide but values are

2) poly doping incl. rearrangement of very sensitive to fabrication process
3) metal deposition doping atoms -> shift of workfunction

6 Future MOSFETs
Tunable Mo Gate Technology
Molybdenium: * compatibility with CMOS processing

Source: Michaelson, J.Appl.Phys. 48(1977)4729 * low resistivity
* thermal expansion like Si
workfunction of Mo very sensitive to structural variations

introduce structural
modifications by
implant and anneal
Low energy implant

of Nitrogen
shift in workfunction IV-characteristics for a Mo gated PMOS FinFET

from 4.9 - 4.4 eV
Implantation shifts the curve to more negative biases,

indicating a lowering of gate work function

6 Future MOSFETs
Metal Gate MOSFETs
Fully Silizide Gate in production
Texas Instruments CMOS:

INTEL CMOS:
65 nm node
65 nm node
L = 35 nm
L = 35 nm
EOT (SiON) = 1.7 nm
tox (SiON) = 1.2nm
FUSI: NiSi
FUSI: NiSi

6 Future MOSFETs
The workfunction values of the fully silicide gates are very sensitive to fabrication process.
The workfunction of the metal gate is tailored by engineering the metal/dielectric interface. This leads to the usage of capping
layers.
Capping layer is a metal, around 1 nm thick
Different capping layer for NMOS and PMOS
courtesy: AMD, Ph.D. thesis Kelwing 2014

Typical gate stack: SiO2, High-k, capping layer, TiN,
polysilicon or metal
Used for Gate-First and Replacement-Gate
In production since 45 nm technology node (INTEL)
All companies are using capping layers to adjust the

workfunction

6 Future MOSFETs
Applied Physics 2008
• AlN is amorphous a) No AlN layer • Workfunction is shifting

• Annealing b) With AlN layer with the capping layer
Capping layer AlN is shifting the workfunction depending on the gate dielectric
AlN is making the workfunction more positive
Promising candidate for the p-channel MOSFET

6 Future MOSFETs
Various capping layers
n+-Si p+-Si
 [V] ~ 4.1 ~ 5.2
Source:H.N. Alshareef et all, Work function engineering using

lanthanum oxide interfacial layers, Applied Physics 89, 2006
Source: J.A. Carraveo-Frescas et all, Experimental and theoretical investigation of the effect of SiO2 content in gate
dielectrics on work function shift induced by nanoscale capping layers, Applied Physics 101, 2012
• Workfunction is shifting due to • Lanthanum causes a negative VFB

different capping layers
• Depending on the gate dielectric
Capping layer AlN/Al2O3 are suitable for PMOS Capping layer La2O3 is suitable for NMOS
Why is the capping layer shifting the workfunktion?

6 Future MOSFETs
Different high-k materials on SiO2 Oxygen atoms per unit area
Source: Koji Kita et all,Intrinsic Origin of Electric Dipoles Formed at High-k/SiO2 Interface, IEDM 2008 Koji Kita et all,Intrinsic Origin of Electric Dipoles Formed at High-k/SiO2 Interface, IEDM 2008
• For some oxides there is a positive VFB shift • Al2O3 and HfO2 have a higher density of O2 than SiO2
• For some oxides there is a negative VFB shift • Y2O3 and La2O3 have a lower density of O2 than SiO2
VFB shift due to the formation of a dipole layer To adjust the oxygen atom density at the interface,
at high-k/SiO2 interface oxygen atoms move from higher density material to
lower density material
Voltage drop at the interface layer for HfO2 leads to higher workfunction
Voltage drop at the interface layer for La2O3 leads to smaller workfunction

6 Future MOSFETs
High-k materials as capping layer
Source:H.N. Alshareef et all, Work function engineering using Source:H.N. Alshareef et all, Work function engineering using
AlN interfacial layers, Applied Physics 89, 2006 lanthanum oxide interfacial layers, Applied Physics 89, 2006
Source: J.A. Carraveo-Frescas et all, Experimental and theoretical investigation of the effect of SiO2 content in
gate dielectrics on work function shift induced by nanoscale capping layers, Applied Physics 101, 2012
Through annealing, the capping metal reaches the SiO2 /HfO2 interface layer creating the dipole
The higher the amount of oxygen at the interface is the higher is the influence of the dipole
Disadvantage is a low mobility of the carriers due to higher scattering caused through the dipole (especially for PMOS)
No knowledge about the reliability of lanthanum What is industry doing?

6 Future MOSFETs
Gatestack Intel 14 nm 2014

PMOS NMOS
• TiN is used as capping layer • TiAl/TiAlN is used as capping layer

• TiN:  [V] = 5.1 - 4.7 eV ; (p+-Si:  [V] = 5.1 eV) • TiAlN:  [V] = 4.3 – 5.1 eV ; (n+-Si:  [V] = 4.1 eV)
• No aluminum as capping layer needed • Aluminum is reducing the workfunction of TiN
• TiN has a high thermo stability to HfO2 • Strong dependence on the process
No mobility degradation CMOS compatible
But very critical process window and high sophisticated process

6 Future MOSFETs
FGA
• HfO2, TiN, Al ,TiN are deposited • To high N in TiAlN leads to positive VFB
• Forminggas annealing (450°C) diffusion • To high amount of aluminum leads to
of Al towards the interface of TiN and HfO2 positive VFB
 Dipole • Annealing with O2 => Al2O3 which leads to
 Shift to negative Flatband Voltage positive VFB
TiN is suitable as capping layer
NMOS aluminum has to diffuse to the interface high-k/TiN to become a negative shift of VFB
Small changes in technology can lead to different workfunctions

6 Future MOSFETs
Is the threshold voltage still symmetrical with the new capping layers?
For a quick calculation we take the values of exercise 3 and change the workfunction accordingly.
TiN TiAlN
 [V] ~ 4.8 ~ 4.4
NMOS TiAlN Exercise 3

𝐸𝑔
ΦMS = Φ𝑀 − Χ𝑠𝑖 + + |Ψ𝐵 | = 4.4V – 4.05V – 0.56V – 0.45V = -0.66V
2𝑞
Exercise 3
′′
𝑄𝐷𝑒𝑝𝑙
𝑉𝑇𝑛 = ′′ + |2Ψ𝐵 | + Φ𝑀𝑆 = 0.34V + 2*0.45V – 0.66V = 0.58V
𝐶𝑜𝑥
PMOS TiN
Exercise 3
𝐸𝑔
ΦMS = Φ𝑀 − Χ𝑠𝑖 + − |Ψ𝐵 | = 4.8V – 4.05V – 0.56V + 0.45V = 0.64V
2𝑞
Exercise 3
′′
𝑄𝐷𝑒𝑝𝑙
𝑉𝑇𝑝 = − ′′ − |2Ψ𝐵 | + Φ𝑀𝑆 = -0.34V – 2*0.45V + 0.64V = -0.6V
𝐶𝑜𝑥
New metal gate stack leads to symmetrical threshold voltage

6 Future MOSFETs
Metal Gate MOSFETs - Summary
Channel doping must be eliminated to avoid dopant fluctuations and increase drive current Ion
Poly-Si Gate depletion must be eliminated to avoid lowering of Gate capacitance and increasing short channel effects
Gatestack TSMC 20 nm 2012 Gatestack Samsung 20 nm 2012

NMOS Metal Gate is needed NMOS
PMOS PMOS
Samsung/TSMC/Intel are using TiN for PMOS and TiAlN for NMOS as workfunction layer/capping layer
Workfunction is very sensitive to fabrication and test chips have to be fabricated
Most companies used until 20nm technology node gate-first with fully silicide gate and capping layers
Since the 20 nm, technology node all companies are using replacement-gate and capping layers

6 Future MOSFETs
Metal Gate MOSFETs
Since the 20 nm technology node all companies

are using Gate-Last/Replacement-Gate
6.1 Overview



6.6 Halo MOSFETs
6.7 SOI MOSFETs


6 Future MOSFETs
Vertical MOSFETs
Vertical MOSFETs offer the possibility Stacking devices results in 3-dim integration
to extremely reduce channel length without Vgate and further reduces the footprint.
sophisticated lithography: Vdd
Vsd The difficulties with vertical interconnects increase
GATE
SOURCE Stromkanal DRAIN SOURCE
n out
wafer
Vsd Vgate DRAIN
SOURCE
DRAIN
DRAIN
Vgate
channel length defined by layer deposition p
(nm-resolution), not by optical lithography
SOURCE SOURCE
Single MOSFET
Vdd
1F
Vdd
p-MOSFET
5F
Using wraped gates the MOSFETs Vin
8F
Vin Vout Vout

have about factor 2 smaller footprints
3F
n-MOSFET Vss
5F
Vss
Planar: 40F2 Vertical: 16.5 F 2
Planar Inverter Vertical Inverter
Reduction by ~2
Reduction by ~5

6 Future MOSFETs
Vertical MOSFETs
Historical:
Anisotropic etched VMOS, ~ 1974 example: Perera et al., IEDM´94, 851

MOTOROLA
1µm channel length, TTL-logic, 4kB-SRAM
Source: Hansch et al, IEDM1997 wrapped gate

50-nm VMOS

6 Future MOSFETs
Vertical MOSFETs - Technology
A Vertical Replacement Gate (VRG)-MOSFET
Gate replacement must be done,

if temperature sensitive gate stacks Si epitaxy
(most high-k) will be used
Si Chemical-Mechanical Polishing
PSG
SiO2
PSG
n+ Drain
p- epi
spacer formation open gate

poly-Si
deposition poly-Source
deposition nitride
grown gate oxide patterning

poly-deposition SD-extension drive-in
Gate Gate Gate Gate
Drain
Source: BELL-LABS, IEDM 1999

6 Future MOSFETs
Vertical MOSFETs - Performance
1E-3
VDS = 1.5 V 0.25
tox = 2.8nm
1E-4
0.1 V 1
1E-5 Planar
ID / WC (A/µm)
0.20 VGS = 1.8 V
ID / WC (mA/µm)
0.1
1E-6 25 Å Oxide
0.01
IG (A/cm )
1E-7 0.15 1.6 V
2
1E-3
1E-8 DIBL = 90 mV 1E-4
1.4 V
1E-9 S = 105 mV/dec 0.10 1E-5
1E-10 1.2 V 1E-6
1E-11 0.05 Planar
1.0 V 1E-7
32 Å Oxide
1E-12 0.8 V 1E-8
0.0 0.5 1.0 1.5 0 1 2 3 4
0.00
VGS (V) 0.0 0.5 1.0 1.5 VG (V)
VDS (V)
•All critical dimensions controlled without lithography

•Gate length = film thickness
•Gate oxide grown on Si
•Self-aligned SDEs formed by solid source diffusion
•Two sides of pillar drive in parallel
•Replacement-gate approach - enables alternative gate stacks
•Small parasitic capacitances should allow high-frequency operation
•Uses current manufacturing methods, materials, and tools

6 Future MOSFETs
Vertical MOSFETs - Design
CMOS-Layout NAND gatter:
VRG vs Planar:
• Similar packing density
• Up to double drive
• Parallel more dense
• Series less dense
p-well + BSG n-well + PSG

Planar Layout VRG Layout
STI
(from 0.25 µm (using similar 0.25 µm
ASIC library) design rules)
Overlap Capacitance
• Dominated by true overlap and local fringing
• Doubled width compensated by doubled drive current
Substrate Capacitance
• Source: minimal
• Drain: reduced coefficient
An estimation shows that the parasitics are similar to SOI

6 Future MOSFETs
Vertical MOSFETs – Status 2017
IEEE 2008
LG = 150 nm
D = 25 nm
Up to now no vertical MOSFETs are used in industry,

mainly because planar MOSFETs could fulfill Moore‘s Law
Anyhow vertical MOSFETs are still under investigation.

6.1 Overview



6.6 Halo MOSFETs
6.7 SOI MOSFETs


6 Future MOSFETs
6.6 Halo MOSFETs
Halo Doping to reduce SCE
In 1997, when the first "Roadmap" was created, the companies started to look several years in the future
It was recognized:
1) because of leakage current the gate oxide can not be scaled,

2) the Vdd cannot be lowered, the electric fields will increase
-> this will result in short channel effects
-> the increase of S/D depletion zones under the gate must
be stopped
First investigations (simulation) were given by:
Taur et al. (IBM): "CMOS devices below 0.1µm: How high will performance go ?",
IEDM 1997, p.215-218
Introduction of high oppositely doped regions before Source/Drain
Halo Doping or Pocket Doping

6 Future MOSFETs
6.6 Halo MOSFETs
25 nm planar bulk MOSFET with Halo
Halo or pocket doping:

tilted p-implant high, sharp bulk doping in front of Source/Drain
to reduce Short Channel Effects
- stopping the width of Source/Drain depletion zones
classical long channel limit: wSD < 1/5 L
very abrupt implant profiles (~2nm)
very sensitive high temperature treatment (-> diffusion)
flash heating (-> 1000°C in 1 sec) for implant recrystallization
Source: IBM, IEDM2000
- decoupling of VDD, threshold voltage Vth and Ioff
- problem: n+/p+ band-band tunneling starts -> additional Ioff
vertically and laterally nonuniform channel doping profile
- optimization only via simulations

- classical scaling rules are overruled
(see tox=1.5nm, VDD=1.0V at 25 nm channel length)

6 Future MOSFETs
6.6 Halo MOSFETs
25 nm planar bulk MOSFET with Halo (1998)
Electrical properties:
Advantage: important:
with HALO-doping the depth of Source/Drain sharp doping profiles (nm/dec) are needed
-S ~ 200mV/dec
junctions is not very critical
- -> for Ion/Ioff ~ 105 1V swing is needed
-questionable from implant process
--> VDD=1V and Vth=0.2 V
- leaving scaling rules (statistics in range straggling, under-implant)
- Source/Drain resistance keeps low -flash heating (1000°C for a few sec is needed)
- S/D extensions (if any) with low resistance (recrystallization of implant damage, but no diffusion)
- decoupling of Vdd and Vth
Feasibility of 25nm channel length (proposed for year 2012) planar bulk MOSFETs was shown in 1998
Halo doping is used till 22/20 nm technology node (Samsung/TSMC planar technology)
For fully depleted channels like FinFET Halo doping not necessary

6.1 Overview



6.6 Halo MOSFETs
6.7 SOI MOSFETs


6 Future MOSFETs
6.8 SOI-MOSFETs
Classical SOI- MOSFETs
Advantage of SOI:
easy lateral isolation
radiation tolerance
lower leakage current -> lower power consumption
lower parasitic capacitance -> higher speed
Classical SOI-MOSFETs show various advantages in performance compared to classical bulk-MOSFET, but are more expensive

6 Future MOSFETs
6.8 SOI-MOSFETs
SOI Techniques
Several techniques are established to fabricate SOI-wafers:
1) SIMOX: Separation by Implanted Oxygen
~1400°C, 2h SiO2 = buried oxide
1018 O2/cm²
100keV
T ~ 500°C
2) BESOI: Bonded etch-back silicon on insulator MOSFETs fabricated on SOI
3) other separation techniques, like Nanocleave, Smartcut,....
Wafer costs are 10 x standard wafer
Silicon layers down to 10nm are demonstrated

6 Future MOSFETs
6.8 SOI - MOSFETs
SOI-MOSFETs for scaling
 N doping  EF
The position of Fermi-Level can be
calculated (chap. 3.13):
bulk  kT  ln   Ei = 0
 ni 
wdep
The barrier in a pn-junction can be calculated:
Vbi
Ei = 0
kT   N D   N A   kT  N A  N D  p
Vbi  n  p    ln    ln     ln  2  EF
q   ni   ni   q  ni 
n
2 0 Si  Vbi  Vext 
and the width of the (one-side abrupt) w
depletion zone will be: qN dop
 Drain  VDS
Short-channel
Calculating the threshold voltage, we receive:
 Drain  Vbi
2 0 Si  qN dop   Drain  Vext    0 Si  Drain  VDS  

Vt  VFB  2bulk   1   
"
Cox  qN L 2  Long-channel
 dop eff 

6 Future MOSFETs
6.8 SOI - MOSFETs
We receive for the threshold voltage: Vt  Vt ,long  SCE  DIBL
  x 2j  tox ,el wdep

SCE  0.64  0 Si   1  2      drain SCE  2  EI   drain
 ox  Lel  Lel Lel
  x 2j  tox ,el wdep
DIBL  0.80  0 Si   1  2     VDS DIBL  2.5  EI VDS
 ox  Lel 
L el
Lel
 x 2j  tox ,el wdep

The geometrical factors we define as Electrical Integrity EI: EI   1  2   
 Lel  Lel Lel
From EI-equation we can follow:
SCE and DIBL will be small, if: Lel ->large of course, because we have a long channel device
tox -> small better gate control -> less reduction of threshold voltage
xj and wdep -> small we already learned from scaling (chap.4)
Around the year 2000 it was recognized:
see next page

If we use thin Si on insulator (SOI), then the thickness of xj and wdep will be defined by silicon thickness

6 Future MOSFETs
6.8 SOI - MOSFETs
fully depleted
tSi tSi tSi

xj wdep xj wdep tBOX
buried oxide (BOX)
p-Si
p-Si remaining
non-depleted
oxide
bulk Partially depleted Fully depleted Ground-plane Double-Gate

SOI SOI Double-Gate
remaining contribution
EI  EI  EI  of partially depleted BOX EI  EI  0.5 
 x 2j  tox,el wdep  x 2j  tox,el wdep  t Si2  tox,el t Si    t BOX  t Si2  tox,el t Si  t BOX  t Si2  t
1    1    1  2    1  2      tox,el Si 2
 L2  L  L2  L  Lel  elL Lel  Lel  elL L 1  2
4
 
 el  el Lel  el  el Lel el
 Lel  el Lel
L
 
From roadmap small SCE and DIBL

are requested
Double-Gate
Requirement: (FinFET)
EI < 10% -> DIBL < 25% since 2012 (22nm)
(see eq. DIBL)
Only Double-Gate can fulfill

requirements

6 Future MOSFETs
6.8 SOI - MOSFETs
Scaling Calculations for State-of Art MOSFET (FinFET)
2014 Node (FinFET): 14 nm Calculation of the Electrical Integrity
 tSi2  t
• Fin width 8 nm   tox ,el Si 2
• Fin pitch 42 nm EI  0.5   1  24  
 Lel  el Lel
L
 
• Assumption:
• Lel = 14 nm  ( 8 nm )²  8 nm
 4  0.8 nm 2
• tox,el = 0.8 nm EI  0.5   1    14 nm  14 nm  0.0088
 ( 14 nm )² 
 
Calculation of DIBL
INTEL, IEDM 2014
S: ~ 65mV/dec
DIBL: ~ 70mV/V DIBL  2.5  EI  VDS
DIBL  2.5  0.0088  0.7V  15.4 mV / V
State-of Art FinFET is suppressing Short-channel-effects
The actual DIBL value is in the range of the theory value

6 Future MOSFETs
6.8 SOI - MOSFETs
SOI-MOSFETs heat is a problem
Figure 1. Short channel SOI MOSFET created using ATHENA.

Local oxidation is used to isolate the active layer. Here
temperature distribution is shown due to self heating.

6.1 Overview



6.6 Halo MOSFETs
6.7 SOI MOSFETs


6 Future MOSFETs
6.8 Double Gate MOSFETs
Fully-depleted Double-Gate MOSFETs
Double-gate
Single-gate SOI Double-Gate, ground-plane
2 equal gates
2 different gates
Advantage: Advantage: Advantage:

- reduction of leakage current through bulk - for very thin Si-layers < 5nm the Vth roll-off - in addition to double-gate the
(fully depleted "bulk", all Si in inversion)
can be avoided down to 25nm channel length threshold voltage can be adjusted
In planar technique the fabrication of a back-gate (oxide with nm thickness and good interface quality) is not easy
from STMicroelectronics an approach "Silicon on Nothing, SON" exists

6 Future MOSFETs
Fully-depleted Double-Gate MOSFETs
Simulations indicate:
Lgate = 25nm
Tox,eq = 12Å
106 G Si Thickness [nm] G

0.0
4.0
S D
8.0
S w D 12.0
16.0
G
20.0 Wfin = 10nm
10-1 Ioff = 2.1nA/m
G
Leakage Current
Density [A/cm2]
@ Vd = 0.7 V Wfin = 20nm
Ioff = 19A/m
Leakage current is greatly reduced with thinner Si-body

6 Future MOSFETs
Scaling Performance of DG-MOSFETs
Simulations
Threshold voltage roll-off for double-gate and single –gate Threshold voltage roll-off for double-gate and ground-plate
MOSFET MOSFET is similar
Simulations Tunable threshold voltage

with ground-plate gate.
At larger VGP an additional
inversion channel is created
single-gated MOSFETs will not meet short-channel effect requirements
short channel effects are reduced in thinner silicon layers -> fully depleted
oxide thickness is not very sensitive -> overruling of scaling rules

6 Future MOSFETs
Double-Gate, Fully-depleted MOSFET Structures
Concepts
single gate

6 Future MOSFETs
Double-Gate-MOSFETs
Gate 1
poly-Si,
metal Gate
Gate fin
silicon thickness
oxide
oxide Source Drain
w silicon
Source Drain Gate 2
silicon
channel length
2 identical gates 2 independent gates
(just by etching down)
FinFET
contact
contact
fin
Channel length = LG
gate width LG
Channel width = 2*fh + fw
wG contact Gate
dielectric
fin width fw
fin f fin height
h
S
i

6 Future MOSFETs
First FinFETs
Hisamoto et al., IEDM 1998 Gate

Cross sectional SEM picture of
15-nm Si vertical fin. The height
is 50 nm.
15nm
50nm
Source 30nm Drain
50 nm
Drain current (uA)

10-4 10
Drain current (A)
Vds=0.05, 1.0 V
10-6
Vg=1.5 V
10-8 1.25 V
5 5µA with w=50nm
10-10 1.0 V
-> 100µA/µm
10-12 0.75 V Ion about factor 10

0.5 V too low
10-14 0 (for this first
-1 0 1 2 0 0.5 1 1.5 presented FinFET)
Vgs (V) Vds (V)
6 Future MOSFETs
First FinFETs
In early days several geometrical designs due to special process flow were developed and various names were proposed,
since some of the early names were protected by patent laws:
Pi - Gate Omega - Gate
one S/D body with one FIN

-> resulting in 2 sidewall gates -> double-gate
-> or in 1 top-gate and 2 sidewall gates -> Tri-gate
Multi-Transistor FinFET Multi-Transistor Multi-Gate FinFET Multi-Transistor Multi-Gate FinFET
Drain Gates
w/o connected
metal lines
Source Multi-FET
Gate Fin
multi S/D bodies with one FIN

-> resulting in 2 sidewall gates -> double-gate
-> or in 1 top-gate and 2 sidewall gates -> Tri-gate Easy design of functions like AND, XOR, SRAM INTEL, 2012

6 Future MOSFETs
First FinFETs
looking for the cross section various other names were invented:
silicon
isolator

6 Future MOSFETs
FinFET - First Companies with FinFETs
IEDM 2002 IEDM 2002
L>100nm, TSi=25nm L = 10nm shortest channel length demonstrated Vt must be adjusted

TSI = 12 nm
low leakage
Demonstration of Metal Gate

6 Future MOSFETs
FinFET - First Companies with FinFETs
INTEL, Tri-Gate (SSDM 2002) TSMC, -Gate (IEDM 2002)

6 Future MOSFETs
FinFET - Development
Single-Gate-FET
SRAM
the tri-gate architecture provides more device width for a given cell footprint compared to the standard planar transistor,
thus providing a higher read current because total current is a direct function of the total device width
Source: Technology@Intel Magazine 2006

6 Future MOSFETs
FinFET - First Circuit Results 2004

6 Future MOSFETs

6 Future MOSFETs

6 Future MOSFETs
FinFET Problems

6 Future MOSFETs
Multi-Gate FETs
2012 Node : 20 nm 2012 Node (FinFET): 20 nm
Samsung Intel
6 Future MOSFETs Fig.1
Multi-Gate FETs
Fins Gates Fig.3

cross-section of PMOS
Si3N4 ?
A1 for self-adjusting contact
metal, W ?
barrier, TiN ?
top of fin
S/D contacts,
A2 etched groove and filled
with SiGe
zoom
Fig.4
cross-section of NMOS
Dummy-Gate Dummy-Gate
at end of fin at end of fin
A1 A2
Fin etched fin (Si) Fig.2: cross section along the fin
(this cross-section is a different structure (only 5 gates) compared
Si-substrate to the top view above (Fig.1) with 6 gates
6 Future MOSFETs
Multi-Gate FETs
2015 Node: 14 nm by Samsung

Samsung 14 nm FinFET
Source: TechInsights
Gate
Drain/Source
Source: Chipworks

6 Future MOSFETs
Multi-Gate FETs
Figure 13 is a composite image of NMOS and PMOS gates so that the

differences are highlighted. The dark line surrounding the gate
structures is the Hf-based high-k, and within that are the two work-
function materials, likely TiN for PMOS and TiAlN for NMOS. (The
columnar structure of the PMOS TiN is visible in the right half of the
image.)
W
The fill has been changed from TiAl in the earlier parts to tungsten. It is
more prominent in the NMOS gates than the PMOS, because the
PMOS structure includes both work-function metals, whereas the TiN
has been etched out of the NMOS gates. At the 45-nm node Intel used
tensile tungsten in the contacts to apply channel stress – have they
TiAlN TiN transposed this to the gates in the 22-nm process?
high-k

6 Future MOSFETs
FinFET
With FinFET proper working devices with acceptable SCE and DIBL down to channel length 7 nm (year 2019) look reasonable
Technological problems will be:
gate oxide < 1nm -> high-k necessary
ultra-thin silicon < 5nm must be vertically patterned -> oxide quality on etched, vertical sidewall ?
for symmetrical Vt new gate metals must be used
Electrical problems:
parasitic tunneling currents -> high leakage current

0
10 double gate, Vd=1V, WF=4eV.
-2 double gate, Vd=1V, WF=5eV.
10 double gate, Vd=1V, WF=6eV.
1.00
-4
Electrons
Log |x|
BB Gener
Signed Log
10
20
18
Vds=1V, Vgs=0V, m=5eV, channel: p1e17 23.72
22 -6
16 20 10
Id / A/m
0.00
14 18
12 16
-8
10
Band to band tunneling 14
10
Energy (eV)
8 12
6 10
4 8 -10
Tunneling 3.448 7.171
10
-1.00
-12
Tox=3nm,
10 Drain: n1e20
20nm
-14 Channel: p1e17

Channel
Due to band to
Source
10
Drain
-2.00
band tunneling Source: n1e20

-16
0.150 0.200 0.250 0.300 0.350 10
X (microns) -2 -1 0 1 2 3
Vg / V
? Is there a design window for symmetrical Vt, Ion, Ioff, SCE and DIBL ?

6 Future MOSFETs
Outlook
Different FinFET structures which can be modeled by BSIM-CMG since 2012

6 Future MOSFETs
Nanowire-Fabrication
Bottom-up fabrication Top-down fabrication

• Material is added to the substrate in a self-organized way. • Silicon technology can be used
• Most common is the liquid growth mechanism (VLSI) • Advantages
• Material to be grown is delivered in gas phase • Well established process
• Gold particles acts as catalyst and collects the silicon • Mass production
• Because it leads to lowering of the dissociation energies of the gas • Parallel nanowires
• Advantages • Disadvantages
• Perfect geometry • Non-perfect geometry
• Different types of substrate can be used • Advanced lithography
• Complex structures without lithography • Lateral wires
• Disadvantages
• No CMOS process
• Place of nanowires is not well defined
• No mass production structuring
• Alternative
• Gold free processes developed
• Combine it with Top-down fabrication
Source: Anisotropic Nanomaterials, Preparation, Properties, and Applications, Li Q, 2015, Springer Verlag

6 Future MOSFETs
Gate-All-Around Silicon FET Fabrication
Top-down fabrication
IEEE 2009
a) Lithography Up to 12 vertically stacked nanowires

b) DRIE-etching
c) Wet oxidation
d) Lithography Vertical nanowires of 20 nm diameter
e) CMP and BHF etching Singh et all, Si, SiGe Nanowire Devices by
Top-Down Technology and their Applications,IEEE 2008
f) Nanowires
g) Oxidation to form the gateoxide Surface improvement of nanowires through oxidation and annealing
h) Depositing polysilicon
i) Patterning of the gatestack
Basic technology used in CMOS flow
6 Future MOSFETs
Lateral Gate-All-Around Silicon FET
CMOS-Inverter
IEEE 2008
LG = 350 nm
D = 3 nm
Fabrication of CMOS-circuits
Transistors show good IV-characteristic
High fluctuation of ION and VT
Reducing short channel effects
Tuning of VT
6 Future MOSFETs
Lateral Gate-All-Around Silicon FET-2016
IMEC, 2016 Symposia on VLSI Technology & Circuits
http://phys.org/news/2016-06-imec-gate-all-around-mosfets-lateral-silicon.html
• N- and P-MOSFET presented

• Vertically Stacked horizontal Si-Nanowires
• Diameter 8 nm
• Fabrication by using industry-relevant processes
• IV-characteristics for LG = 24 nm show:
• SS = 65 mV/dec
• DIBL = 42 mV/V
First time vertically stacked horizontal silicon nanowires at scaled dimensions are shown
(Lateral pitch 45 nm, 20 nm vertical separation)
Maybe paths the way for sub 10 nm
http://semiengineering.com/uncertainty-grows-for-5nm-3nm/

6 Future MOSFETs
Vertical Gate-All-Around Silicon FET
IEEE 2008
LG = 150 nm
D = 25 nm
Nanowires with diameters from 20 to 450 nm
Subthreshold Slope 75 mV/dec, DIBL 10~50 mV/V
CMOS fabrication technology was used

6 Future MOSFETs
Monolithic 3D-Integration
STMicroelectronics/IBM/Leti/Qualcomm (2008- now)
M. Vinet et all, Monolithic 3D Integration: a powerful alternative to classical 2D Scaling, IEEE 20014
• Sequentially processing transistors on top of each other

• Ultra-high 3D contact density
• Challenge is that the top layers are processed with a low thermal budget to preserve any damage to the bottom
transistor
• Process temperature for the top transistor may not be higher than 600°C
6 Future MOSFETs
Fabrication P. Batude et all, Advances in 3D CMOS Sequential Integration, IEEE 2009
1. Bottom MOSFET 2. Inter-layer-dielectric 3. Bonding
Top Wafer
Substrate Wafer
• FDSOI-MOSFET
• High-k/Metal-Gate • Low temperature
bonding
• Dielectric deposited • Initial substrate removal
• Planarization with CMP
4. Top MOSFET 5. Contact process
• FDSOI-MOSFET • 3D contact realization

• Temperature Budget • Standard CMOS
max. 650°C
• High-k/Metal-Gate

6 Future MOSFETs
• Alignment precision between the layers is

dependent on the lithography alignment
• (110) PFET on top of (100) NFET
• Independent optimization of the transistors
M. Vinet et all, Opportunities brought by sequential 3D CoolCubeTM integration, IEEE 20016
• No degradation of the bottom characteristics due to top

integration
• Shift of VT due to the increase of the gate-metal work

function through the annealing
• CMOS-Inverters and SRAM-Cells are working

P. Batude et all, Advances in 3D CMOS Sequential Integration, IEEE 2009
P. Batude et all, Advances in 3D CMOS Sequential Integration, IEEE 2009
Different channel materials for high mobility were integrated

IBM 2009
Heat difficulties in the bottom part
Implementing FinFETs started

6 Future MOSFETs
IEEE 2016
Implementation of a pFinFET in the bottom layer
Implementation of a InGaAs nFET in the top layer
No degradation of the bottom characteristics due to top integration
RF devices required for high-frequency analog or mixed signal circuits integrated on top of MOSFETs
6 Future MOSFETs
Summary
With FinFET proper working devices with acceptable SCE and DIBL down to channel length 7 nm (year 2019) look reasonable
IBM 2015
IEEE 2013
• Simulation of • Silicon Germanium

FinFET for 7 nm channel
technology node
• EUV-Lithography
• IV-characteristic on multiple levels
shows working
FinFET
Gate-All-Around FETs will come probably at 5 nm node
Fabrication of Gate-All-Around FETs expensive
M3D needs implementation of FinFET
Most promising is the lateral Gate-All-Around FET

6 Future MOSFETs
7nm FinFET
IEEE 2016
• CMOS Technology
• Replacement Gate Process
• Dual Strained channels (SiGe)
• Channel length 15 nm
• PFET SiGe channel
EUV lithography is used for some critical process steps
25% mobility increase in PFET
Volume production is scheduled to second half of 2018 (Status: September 2016)

6 Future MOSFETs
7nm FinFET
IEEE 2016
• SRAM cell of 0.027 µm

Process
• Channel strain through
Source/Drain epitaxy
• 12-level Cu/low-k
• Channel length 15 nm
Working 7nm FinFET
No details about Gate pitch and strain
Volume production is scheduled to begin by 2018 (Status: September 2016)

6.1 Overview



6.6 Halo MOSFETs
6.7 SOI MOSFETs


6 Future MOSFETs
3D-Flash-NAND Memory
End of Planartechnology ? 3d devices possible ?
https://www.micron.com/products/solid-state-storage/3d-nand-client-ssds
see details from SAMSUNG

6 Future MOSFETs
14
Planartechnology is overruled by 3D-Technology
To understand the 3D-NAND, we look first at the 2D-NAND

6 Future MOSFETs
Working principle of 2D-Flash-NAND Memory
The Flash-NAND Memory consists out of Floating-Gate MOSFETs which are linked together in a NAND circuit.
Floating-Gate MOSFET NAND-circuit
Input Output
A B
0 0 1
1 0 1
0 1 1
1 1 0
log |ID|
VT1
10-3 A/µm
VT2 To store 1 the electrons have to tunnel into the floating gate
10-6 A/µm
Stored electrons in the floating gate lead to a higher Threshold Voltage VT2
10-9 A/µm
10-12 A/µm Only when both transistors are on, the output in the NAND circuit changes
- Vgate + Vgate
6 Future MOSFETs
In the literature there is also sometimes written about multilevel cells.
http://panasonic.net/avc/sdcard/industrial_sd/img/lineup_img01.jpg
All three cells are still one Floating Gate transistor
MLC can save 2 bits in one single Floating Gate, TLC can save 3 bits in one Floating Gate
Cells more sensitive to physical degradation and has lower endurance
How does now the memory look like?

6 Future MOSFETs
Working principle with SLC 2015 15/16 nm 2D-NAND Hynix
Read the Bit in Transistor Word Line 2

• Ground Select and Bit Select Transistor switched on
• Bit Line put to a high value
• All unselected Word Lines put to such a high value that the transistors are switched
on
• Word Line 2 VT1<V<VT2
• If 0 is stored
• Transistor switches on => All transistors are on => Bit Line going down
• If 1 is stored
• Transistor is off => Bit Line stays up
2D-NAND Memories are used till today

6 Future MOSFETs
Due to stacking,
change from single
crystalline substrate
to poly crystalline
devices
3D-NAND by Toshiba/San Disk
http://www.theregister.co.uk/2013/07/23/sandisk_takes_the_bics_route_to_3d/

6 Future MOSFETs
3D-NAND by Toshiba/SanDisk 3D-NAND by Samsung
3D structure can vary from company to company

GSL: Ground Select Line
Samsung is using Si3N4 as trapping layer instead of polysilicon SSL: Source Select Line
CSL: Connected Source Line
WL: Word Line
Same working principle as the 2D-NAND
Since 2014 in production

6 Future MOSFETs
2016 Samsung SSD with 3D-V-NAND
3D-NAND (21 nm node) has a 3.5 times

higher memory density then
2D (16nm node)
Charge trap layers are used to store

electrons
Current in the polysilicon channel is decreasing

No long term scaling
6 Future MOSFETs
Resistive Random Access Memory (RRAM)
2014 SanDisk 2016 Intel
NAND is coming to an end because of reliability and degrading 128 Gbit memory
performance
All big companies see the RERAM/RRAM (resistive RAM) as

an alternative
Intel/Micron announced 2015/2016 their 3D Xpoint Technology

http://www.eetimes.com/document.asp?doc_id=1327289&page_number=2

6 Future MOSFETs
RRAM mechanism
• Two states:
• HRS high-resistance state
• LRS low-resistance state
• Set process:
Switching from HRS to LRS
• Reset process:
Switching from LRS to HRS
• Read process:
Small voltage which has no
H.-S. Philip Wong et. all, Metal–Oxide RRAM, IEEE 2012
affect on the state
• Device structure is metal insulator(i.e. HfO2) metal
• Formation process:
• High electric field: oxygen atoms drift to the anode
• Electrode/oxide interface behaves like an oxygen reservoir
• Localized deficiency of oxygen leads to a conductive filament
• LRS State
H.-S. Philip Wong et. all, Metal–Oxide RRAM, IEEE 2012

6 Future MOSFETs
RRAM mechanism called Conductive Bridging RAM (CBRAM)
• Device structure is metal insulator(i.e. SiO2) metal

• One electrode is an electrochemically active
electrode (Ag, Cu,Ni)
• Second electrode is an electrochemically inert
counter electrode (Pt, W)
• Solid electrolyte (SiO2,TiO2 and more)
A) High-resistance state (OFF-state)

• No electrodeposit on the inert electrode
B) SET-process
• Positive Voltage on the Ag electrode
• Ag+ ions drift through the thin film to the Pt-
electrode
• Electrocrystallization of Ag on the Pt
C) Electrocrystallization leads to the formation of a
metal filament
D) When the filament made a contact to the Ag, the cell
is switched on
E) RESET-process
• Cell stays on till a negative voltage is applied
Valov et. all, Electrochemical metallization memories-fundamentals, applications,
• Filament is broken prospects IOP 2011
For a new cell an electroforming process has to be made

6 Future MOSFETs
Phase Change Memory (PCM)
• Phase change between amorphous state and

crystalline state caused by Joule heating
• Change in electrical resistance
• Material: chalcogenide materials like GeSbTe
A) High-resistance state (OFF-state)

• Material is amorphous and has a high resistance
B) Set state
• Applied voltage is higher then the threshold voltage
• Electrons are injected into the material
• Electrons cause impact ionization and carrier
multiplication by colliding with defects
• Joule heating occurs M. Terao et. all, Electrical Phase-Change Memory: Fundamentals and State of the Art,
• Material reaches a temperature between 300°C and Jpn. J. Appl. Phys. 2009
400°C
• Material changes to crystalline state
• Lower resistance , higher current
C) Reset state GST = GeSbTe
• Voltage is raised BEC = Bottom Electrode
• Current gets higher BL = Bit Line
• Joule heating makes the crystal melt. WL = Word Line
• Material becomes amorphous through lowering the SL = Source Line
voltage rapidly (600°C)
Chalcogenide materials not used in CMOS until now

6 Future MOSFETs
Carbon Nanotube Random Access Memory (NRAM)
• Basically also a Resistive RAM
• Two states:
• HRS high-resistance state (“0”) https://www.theregister.co.uk/2016/08/31/nram_dev_nantero_signs_fujitsu/, 2017
• LRS low-resistance state (“1”)
• High-resistance state
• Carbon nanotubes are not in contact with each other
• Low-resistance state
• Carbon nanotubes are in contact with each other
• Non-volatil and fast as DRAM
Till today yield and reliability problems

6 Future MOSFETs
1 Transistor with one RRAM cell 1 Transistor with several RRAM cells
Low latency Cost effective, high area density
Cell size dominated by transistor Implementing a crossbar scheme
Embedded memory applications Storage devices, SSDs

Source: http://www.crossbar-inc.com/assets/resource/presentation/FMS2014-Slides-Breakthrough-3D-
Crossbar-ReRAM-Technology.pdf
6 Future MOSFETs
www.crossbar.com
Four memory
layers
Connecting
metallization
layers
CMOS controller Logic

CMOS compatible process and fast switching
RRAM is expected to replace NAND at 10nm technology node
PCM is using new materials for CMOS technology

6 Future MOSFETs
Summary
2D-Flash Memory is used in mobile applications
3D-Flash Memory, current in the polysilicon channel is decreasing
New channel materials instead of the polysilicon channel Most promising candidate is the RRAM

6 Future MOSFETs
Think positive

6.1 Overview



6.6 Halo MOSFETs
6.7 SOI MOSFETs



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Chap 6 Advanced MOSFET Development

6.2 State of the Art MOSFETs

6.3 Mobility-Enhanced MOSFETs

6.4 High-k Metal-Gate MOSFETs

6.5 Vertical MOSFETs

6.6 Halo MOSFETs

6.7 SOI MOSFETs

6.8 Double-Gate and Multi-Gate MOSFETs

6.9 Advanced Memory Devices

Advanced MOSFETs and Novel Devices Prof.Dr. W. Hansch , Dr.J.Biba

CMP + Cu + low-k SiGe + strain high-k + metal gate

EUV-lithography Vertical GAA

Advanced MOSFETs and Novel Devices Prof.Dr. W. Hansch , Dr.J.Biba

(if shrinking can be done using the same equipment.

In addition, shrinked devices offer the advantage of:

* better dynamic performance (faster, less power consumption)

MOSFETs are best suited for shrinking, because:

MOSFETs are Field-Effect devices -> easy scaling

Using this shrinking factor S = 0.7 / generation a forecast

Advanced MOSFETs and Novel Devices Prof.Dr. W. Hansch , Dr.J.Biba

historical US National Roadmaps 1992, 1994, 1997

As an indicator, whether the technology exists

existing technology, but

Advanced MOSFETs and Novel Devices Prof.Dr. W. Hansch , Dr.J.Biba

Have a look at:

"New way" Higher performance

Minimum Feature size F

Advanced MOSFETs and Novel Devices Prof.Dr. W. Hansch , Dr.J.Biba

* MOSFETs in INTEL-PIII MPU (IEDM2000)

2) Some structures cannot be scaled with F to ensure proper working,

- printed gate length

Advanced MOSFETs and Novel Devices Prof.Dr. W. Hansch , Dr.J.Biba

Starting in 2002 the terminus "node" was used

Starting in 2012 the terminus "node" was used more generalized to

Advanced MOSFETs and Novel Devices Prof.Dr. W. Hansch , Dr.J.Biba

Note the different dimensions for node, pitch, channel length

Advanced MOSFETs and Novel Devices Prof.Dr. W. Hansch , Dr.J.Biba

low power low stand-by power

DRAM: leakage current must be avoided

Logic: should be fast, leakage not so important

Source: Toshiba, IEDM 2002

Advanced MOSFETs and Novel Devices Prof.Dr. W. Hansch , Dr.J.Biba

6.2 State of the Art MOSFETs

6.3 Mobility-Enhanced MOSFETs

6.4 High-k Metal-Gate MOSFETs

6.5 Vertical MOSFETs

6.6 Halo MOSFETs

6.7 SOI MOSFETs

6.8 Double-Gate and Multi-Gate MOSFETs

6.9 Advanced Memory Devices

Advanced MOSFETs and Novel Devices Prof.Dr. W. Hansch , Dr.J.Biba

• LG =70nm defined by lithography (printed)

Typical values from INTEL, FUJITSU, Toshiba, ... :

Usually dual VT (by 2 oxide thicknesses) is used:

Source: Toshiba, IEDM 2002

Advanced MOSFETs and Novel Devices Prof.Dr. W. Hansch , Dr.J.Biba

Typical performance values from INTEL, IBM, FUJITSU, Motorola, Hitachi:

2000 Node: 130 nm 2009 Node: 32 nm

• LG =70 nm defined by lithography (printed)

Advanced MOSFETs and Novel Devices Prof.Dr. W. Hansch , Dr.J.Biba

2014 Node (FinFET): 14 nm

INTEL, IEDM 2014

Advanced MOSFETs and Novel Devices Prof.Dr. W. Hansch , Dr.J.Biba