PART TWO
SEMICONDUCTOR ELECTRONICS
1. INTRODUCTION
Semiconductor materials are distinguished by having their specific electrical conductivity somewhere
between that of good conductors (10 6(cm)1) and that of good insulators. Among those materials by
far the most important in engineering use is silicon. The other of lesser importance is Germanium
(Ge) (which is like Si an element belonging to group IV in the periodic table. Becoming more
important are the compound semiconductors usually compounded of two elements or more of Groups
III and V or II and VI of the periodic table. From this group GaAs is the most important; others are
InSb, GaP, CdS etc.
Electronic devices necessitate use of almost absolutely pure semiconductor materials in which an
extremely small quantity of foreign dopant has been included to control its electrical properties. Also
the semiconductor must normally be in the form of a single crystal throughout the device however
other forms of the semiconductors (example thin film based) have of recent found applications in
photovoltaics.
To understand the basics of the devices used in semiconductor applications, we shall explore at length
the physics of these materials from the basic scientific approach. We begin by exploring the basis of
these devices (i.e the atom) and how it is built on to give a semiconductor.
Consider an isolated hydrogen atom, which consists of a single electron circling the nucleus around a
closed orbit of radius r. From classical theory, it is postulated that the electron revolves around the
nucleus in a circular orbit and that the centripetal force (Fr) is balanced by the equal and opposite
electrostatic force (FA) of attraction between the positive charge of the proton and the negative charge
of the electron.
e
Fr
FA
p
r
The force of attraction FA between the nucleus/proton and the electron of the hydrogen atom is
where e is the electron charge and 0 is the permitivity in free space. From Newton’s 2 nd law of
motion in mechanics, the force in equation (1) is balanced by a force that holds a particle in a circular
path (i.e centripetal force)
mv 2
Fr (2)
r
where v is the velocity of the electron. Equating (1) and (2) we have
e2 mv 2
FA Fr (2a)
4 0 r 2 r
Integrating eqn 1 w.r.t r gives the potential energy of the electron at a distance r from the nucleus, i.e
r e2
V FA dr (3)
4 0 r
1 2 e2
E mv (3a)
2 4 0 r
e2
E (3b)
8 0 r
E 2 E1
(4)
h
nh
mvrn (5)
2
where n is an integer (n = 1,2,3,4,…)
e
v
4 m 0 r
Substituting v into equation (5) and solving for r we have
n 2 h 2 0
rn n 1, 2, 3,....... (6)
me 2
This is the Bohr’s radius of the nth stationary state.
13.6
eV for hydrogen atom
n2
13.6
Since E n eV n 1, 2, ......
n2
n = 2, E2 = 13.6 / 22 eV = 3.4 eV
n = 3, E3 = 1.51eV
n = 4, E4 = 0.85eV
n = 5, E5 = 0.54 eV
n = , E = 0
Equation (7) gives energy levels of a hydrogen atom. A convenient pictorial representation called
energy level diagram of a hydrogen atom is given in Figure 1.2 below
5 0.87 x 1019
excited
state 4 1.36 x 1019
3 2.42 x 1019
Ground
state 1 21.76 x 1019
Figure 1.2: Energy level diagram of a hydrogen atom
Note the gaps between different states, an electron is forbidden from having energies falling in these
gaps.
In general for an element of atomic number Z, an electron in the nth state has energy En given by
1 Z 2e4m e4m Z 2
En or
n 8 02 h 2 8 02 h 2 n
13.6Z 2
eV
n2
(8)
Electron
Energy
Band gap
As more and more atoms are brought together the discrete levels are transferred into a cluster of very
narrowly spaced levels or bands of permitted energy levels. The permitted energy bands are spaced by
band gaps in which there are no permitted states. A full band does not contribute to conduction. The top of
a conduction band is called a vacuum level. The band containing the valence electrons is called valence
band (VB) and the next band is called conduction band (CB).
The band model given in the above account explains why some materials are classified as conductors,
semiconductors or as insulators. A very poor conductor of electricity is called an insulator; an excellent
conductor is a metal; and a substance whose conductivity lies between these extremes is a semiconductor,
(Figure2.2 below).
CB
CB
CB
Eg Eg
VB
VB
Fig 2.2 VB
(a) Metal (b) Semiconductor (c) Insulator
 CB & VB overlap  Small energy band gap  Large energy band
VB partially filled (~ 1eV) gap (~ 5eV)
(b) Semiconductor
For the case of a semiconductor, the width of the forbidden energy region is relatively small (~ 1eV).
Example is graphite which is a crystalline form of carbon but having a crystal symmetry which is different
from diamond has such a small value of E g. The most important practical semiconductor materials are
germanium and silicon which have values of E g of 0.785eV and 1.21eV respectively, at 0oK. The valence
band remains full while the conduction band remains empty.
(c) Metals
A solid which contains a partly filled band structure is called a metal (Fig 2.2 a). Under the influence of
an applied electric field, the electrons may acquire additional energy and move into higher states.
Fig 2.3 Covalent bonding in (a) intrinsic Si (b) extrinsic Si with Phosphorous (c) extrinsic Si with
Aluminum.
Consider what happens if Si atom is replaced with a group III element, eg Aluminum or boron, gallium,
indium, etc, (Fig 2.3c). Aluminum has only three valence electrons; some of the covalent bond in Si will
have an electron missing. The Al impurities introduced make available positive carriers because they
create holes which can accept electrons and are called acceptor or ptype impurities. When acceptor
impurities are added to the intrinsic semiconductor material, they produce an allowable energy level
which is just above the valence band (Fig 2.4). A very small amount of energy is required for an electron
to leave the valence band and occupy the acceptor energy level. As such the holes generated in the
valence band by the electrons constitute the largest number of carriers in the semiconductor material.
CB Donor levels
VB Acceptor levels
Semiconductors in which the electrical conduction is predominantly due to free electrons are called ntype
semiconductors and those in which holes are predominant are called ptype semiconductors.
CB
Free
EC electron

ED Donor
level
Bound hole
Eg
Bound
electron
EA Acceptor
level
Ev
Free hole

VB
Figure 2.5
If p is the number of holes per unit volume or the carrier density in the valence band, we do not know
what fraction of these p holes are created by electrons going to the acceptor level and what fraction of
electrons going all the way to the conduction band. A similar statement holds for nelectrons per unit
volume in the conduction band. The problem at this point is to get the number of free electrons and free
holes available since they are important factors in determining the electrical behavior of both
semiconductors and junction devices made from them.
If nA is the no. of bound electrons per unit volume in the acceptor level and nD is the no. of bound holes
per unit volume in the donor level, then for charge neutrality
n + nA = p + nD (1)
i.e total negative charge density is equal to total positive charge density.
We shall now evaluate these four quantities. The probability that a level at energy E is occupied by an
electron is given by Fermi Dirac distribution f(E) defined by
f FD E
1
(2)
E EF
1 exp
kT
The band diagram is very important in the understanding of solidstate devices. Principles governing
construction of band diagrams are:
1. Particles tend to take up positions of minimum energy.
Potential
+ hole
energy
+V
Figure 2.6
Electrons behave like little balls, always rolling down the hill to the lowest position (seek more positive
potential); holes look like bubbles in the valence band, rising to the highest level possible (holes seek
more negative potential).
Note:
+qV = E for holes
qV = E for electrons
Consider the figure 2.7a where it is assumed that the Fermi level is not constant.
A
A B
EC V
E1 B EC
EF
E1
EF
EV
(a) EV (b)
+V
Fig 2.7 Fermi level in a semiconductor material at equilibrium
An electron will have the same probability according to the FermiDirac distribution, of occupying the
levels A and B, because both are the same height E 1 above the Fermi level. An electron at A will therefore
move to B as given by the first principle. Result, semiconductor at B becomes more negatively charged,
rising the energy of all the levels at B by the same amount (refer to eqn 46).
Electrons will continue to flow from A to B, until the probability of being in each level is the same, which
occurs when the Fermi level is same everywhere as in Figure 2.7b
It is possible to manufacture a single piece of a semiconductor material half of which is doped by ptype
impurity and the other type ntype impurity as shown in Fig 3.0 below. The joining of a ptype and ntype
materials forms a diode.
p n
+++++++      
+++++++      
++++++ +      
Fig 3.0 A pn junction diode
The plane dividing the two zones is called a junction. It has been found that three phenomena take place
when a junction is formed:
1. A thin depletion layer or region (also space charged or transition region) is established on
both sides of the junction.
2. A barrier potential or junction potential is developed across the junction.
3. Formation of junction and diffusion capacitances.
+++++++      
+++++++      
++++++ +      
(a)
Free (mobile
charges)
++++++      
 
 
++++++      
Depletion layer
with fixed ions
(b)
Fig 3.1 Pn junction at (a) initial stages showing movement of e & holes and (b) a depletion layer formed.
Eventually the formation of fixed ions on both sides inhibits the diffusion of majority carriers from their
respective regions (Fig 3.1b).
Depletion layer
VB
0
Fig 3.2 Pn junction diode with depletion layer and corresponding potential barrier profile.
VA
(a)
i
0
VB – VA
Potential barrier is
(b) reduced by VA
EC
e q(VB – VA)
EF qVA
EV
pregion nregion
(c)
Fig 3.3 a): forward biased pn junction, (b) Potential barrier diagram for forward biased pn junction (c)
corresponding energy band diagram
3.4 Forward IV characteristics.
A typical IV characteristics for a forward biased pn junction is shown in Fig 3.4
If
Vf
A B
VF
Fig 3.4 Forward IV characteristics of pn junction diodes of Ge and Si
It can be seen that forward current rises exponentially with applied forward voltage. However, at room
temperature a small pd is required before a reasonable amount of forward current starts flowing. This
voltage is known as threshold voltage or cutin or knee voltage. It is typically the same as the built in
potential/barrier potential (VB). The forward biased junction has low resistance.
VB + VA
(a) VA
VA + VB
EC
q(VA + VB)
EF
EV qVA
Figures
(c) 3.5 a): Reversed biased pn junction, b) its corresponding potential barrier diagram
c) its corresponding energy band diagram, in this case the majority carriers are held back.
Although in reversebiased case, practically there is no current due to majority carriers, there is still some
very small amount of current (a few micro amperes) due to the flow of minority carriers (thermally
generated) across the junction. Thermal energy generates some holes in the Ntype region and some
electrons in the pregion of the semiconductor. The battery drives these minority carriers across the
junction thereby producing a small current called reverse current or reverse saturation current I0 or IS. The
reverse saturation current is also referred to as leakage current of the pn junction. IV characteristics of a
reverse biased pn junction is illustrated in Fig 3.6
Forward voltage
Reverse voltage
Si I0
Ge
iD = 0, vD 0, and
vD = 0, iD > 0,
where iD is the diode current and vD is the voltage of the anode relative to the cathode. The model
equation is
iD = IS [exp(vD/(NVt)) 1],
where N is the ideality factor and Vt = kT/q is the thermal voltage. This leads to a simplified diode
current equation given by
qV
I I 0 exp A 1 Amps whose characteristics are displayed in figure 3.7.
kT
Three regions of interest in Fig 3.7 are:
kT
1. V A . In forward bias the exponential term dominates and
q
qV
I I 0 exp A Amps, which accounts for the steep rise in current
kT
2. VA = 0; I = 0 equilibrium condition is satisfied.
kT
3. V A . In reverse bias the exponential term rapidly dies away leaving
q
I I0 Amps where I0 is the reverse leakage current or reverse saturation current (IS).
Current due
I (mA) to majority
carries
Breakdown
+V
+V
Current due
to minority
carries
At low frequencies (below 1 KHz) including DC, the equivalent ideal circuit model for a diode is usually
derived from the measured current/voltage characteristics of the diode and is modeled by a piecewise
linear circuit model, with zero forward impedance and infinite reverse bias impedance. A more realistic
approximation of a diode model is represented by a nonlinear current source with a finite forward and
reverse bias, in series with a linear resistance as shown in Figure 3.8 (a), where 'A' and 'K' denote anode
and cathode of a diode, respectively.
The pn junction is represented by the realistic approximation of a diode model whose static characteristics
are modeled by the nonlinear current source ID, whose value is determined by the following equations
where VD the is voltage applied across the junction and other parameters are described in table 3.1 The
first row in the equation describes the forward characteristics, the second row describes the reverse
characteristics before diode break down, the third row describes the reverse characteristics at break down
and the last row describes the reverse characteristics after break down. All the regions of operation of a
diode are illustrated in Figure 3.8(b), where regions (1), (2),(3) and (4) correspond to row numbers of
equation 3.1. The effects of both the highlevel injection [18] and ohmic resistance are modeled by the
ohmic resistance rs. The total voltage across the diode is then given by
In addition to the nonlinear effects represented by the static model, a largesignal model takes into
consideration the chargestorage effects of a device. If these effects are not accounted for, the device
would be infinitely fast, causing the currents to change in zero time due to the lack of charge inertia. In a
junction diode there are two forms of charge storage: 1) charge storage in the depletion region due to
dopant concentrations and 2) charge storage due to the minority carriers injected into the neutral region.
Both of these charges gives rise to two capacitances: junction capacitance (Cd) and diffusion capacitance
(Cj). The total equivalent capacitance of the diode is modeled as (CD = Cj + Cd). A largesignal model of
a diode is shown in Figure 3.9, where the total equivalent capacitance (CD) can be defined equivalently by
the following capacitance relations
where the first sum terms account for the diffusion capacitance and the second for the junction
capacitance. F2 and F3 are the model constants whose values are given by the Equation 3.5 and the new
model parameters required to describe the capacitance CD of a largesignal model of a diode are given in
Table 3.2.
Doping on pside is high enough to bring the Fermi level near EV and the nside has EF inside the
conduction band. When a reverse voltage VZ is applied, valence band electrons can directly tunnel into the
empty conduction band states opposite them on the nside without first being excited into the conduction
band on the pside
Tunneling
EC
qVZ
EF
EV
++++++++++ EF
+ EC
EV
p n
Fig 3.10 Band diagram for a tunnel diode
Due to the heavy doping, a tunnel diode exhibits an unusual currentvoltage characteristic curve as
compared with that of an ordinary junction diode.
Fig 3.11:
The three most important aspects of this characteristic curve are (1) the forward current increase to a peak
(IP) with a small applied forward bias, (2) the decreasing forward current with an increasing forward bias
to a minimum valley current (IV), and (3) the normal increasing forward current with further increases in
the bias voltage. The portion of the characteristic curve between IP and IV is the region of negative
resistance.
The negative resistance region is the most important and most widely used characteristic of the tunnel
diode. A tunnel diode biased to operate in the negative resistance region can be used as either an oscillator
or an amplifier in a wide range of frequencies and applications. Very high frequency applications using
The zener diode uses a pn junction in reverse bias to make use of the zener effect, which is a breakdown
phenomenon which holds the voltage close to a constant value called the zener voltage. It is useful in
zener regulators to provide a more constant voltage, for improvement of regulated power supplies, and for
limiter applications.
Fig 3.13
Interaction between photons and semiconductor means that photons are either absorbed or emitted by the
semiconductor.
hc 1.24
E hf eV
( m)
If a photon is absorbed then the energy E = E g which gives the maximum wavelength as
1.24
max m
Eg
3.12.1Photoconductive effects
PIN diode is operated with reverse bias, smaller than the breakdown voltage, and its detection capability
stems from the sharp increase in the reverse current from I0 in the dark to I0 + Iph with light. The devise
must have a shallow junction followed by a wide depletion layer where most of the absorption and
generation should take place. The generated carriers are immediately swept apart by the high reverse field
and contribute to Iph.
Fig 3.14 PIn photodiode characteristics in dark (1) and under illumination (2)
The PIN diode in which even a small reverse voltage suffices to extend the depletion layer across the
whole intrinsic region fits the requirements very well. Carriers generated outside the depletion layer but
within a diffusion length of it have also a good chance to diffuse towards it and contribute to Iph.
The current generated by the carriers has the same direction as the leakage current (i.e. reverse direction)
so that the total diode current is
qV
I I 0 e kT 1 I ph
The characteristic is shown by line 2 in Fig 3.14
Iph I0 D V
D represents an ideal diode and Ri represents total internal resistance of regions outside the depletion
layer. The basic electrical circuit of a PIN photodetectror is shown in Fig 3.16
U
RL V0
Fig 3.16
Ip RL V
h qVA
I0 e kT
1
Fig 3.17
The cell may be used for light measurements. The IV characteristics of this photodetector is given in Fig
3.18.
Fig 3.18
Diode Circuits
The basic diode circuit (Fig 3.19), consists of the device in series with a load resistance RL and an input
signal vi.
3.14.1 Load Line
From Kirchoff’s law of voltage
v = vi  iRL
vi RL v0
i
 
A’ B’
iA’
A
iA iA B
A
vA
(i)vi 0 (ii) vi vi’
Fig 3.20 (i) Intersection of A of the load line with the diode static characteristics
(ii) Load line for dynamic curve from the loadline for static characteristics.
A shows the curve for static characteristics while b shows the dynamic characteristic curves.
In Fig 3.20a, the load line is the straight line passing through i = 0, v = vi and i = vi/RL, v = 0. That is the
intercept with the voltage axis is vi and with the current axis is vi/RL. The slope of the line is therefore
determined by RL. The point of intersection A of the load line and the static curve gives the current iA that
flows under these conditions.
Specific circuits drawn from diodes are clipping (limiting) circuits, Comparators, sampling gates rectifier
circuits, capacitor filter circuits. Others of lesser importance are peak detector and clamping circuits.
+50
50
25
50
V v0
25V
30V
30
50
50
Fig 3.21 shows a diode circuit that clips both the positive and negative voltage swings to references
voltages. A sinusoidal input and the clipped output are shown.
All this time D2 is not conducting and when the input signal switches to negative, it becomes conducting
while D1 becomes nonconducting. For the negative input, as the input increases towards –50V, the output
will be conducting and allowing in the value of input (vo = vi) until the input reaches –30V. As the input
increases from –30V towards –50V, the output gives a constant value of –30V until the input drops back
to –30V from –50V towards 0. This region again the output voltage will just be the same as the input
voltage Clipping can be achieved by use of ordinary diodes (Fig 3.22) or zener diodes.
+ +
RL
vi v0
VR
 
VR + Vγ
0
t1 t
vo
Vo
VR
0
t1 t2
t
Fig 3.24: Display of the ramp input signal vi, and the corresponding output waveform.
The circuit in Fig 3.23 above is identical to the clipping circuit but the input is taken as a ramp with the
input crossing the voltage level vi = VR + Vγ at a time t = t1. When the input vi exceeds VR, the
comparator output vo takes on a value which is very different from the magnitude of vo when vi is smaller
than VR. The output remains at vo = VR until t = t1, after which it rises with the input signal (Fig 3.24).
The device to which the comparator output is applied will respond when the comparator voltage has risen
to some level Vo above VR.
Rc
+vc
Rc vc
vs
Fig 3.25 A four diode bridge sampling gate with control vc, the signal vs and the output vo waveforms.
In this set up an external signal vs is applied and the output vo taken across the load RL and symmetrical
control voltages applied at +vc and –vc through the control resistors Rc. The rectangular shaped vc, the
sinusoidal vs and the sampled output vo are shown. Note that the period of vc need not be the same as that
of vs, although in most practical applications, the period of vc would equal or be an integral multiple of
that of vs. During the time Tc all diodes are conducting and during Tn all diodes are not conducting.
vm
RL
vi
(b)
i
(a)
(c)
Fig 3.26: (a) Basic circuit of half wave rectifier (b) Transformer sinusoidal secondary voltage v i (c) Diode
current and load current i.
Since in rectifier circuit the input vi = Vmsinωt has a peak value of Vm which is very large compared to the
cutin voltage (Vc) of the diode, it is assumed that VC = 0. With the diode idealized to be a resistance R f in
the ON state and an open circuit in the OFF state, the current I in the diode or load RL is given by
i I m sin if 0
i0 if 2
where α = ωt
and
Vm
I m
R f RL
The transformer secondary voltage is shown in Fig 3.26b and the rectified current in 3.26c.
I m RL
Vdc I dc RL
N P N P N P
E C E C
B
B
Fig 4.1 Block diagrams and equivalent circuits of (a) NPN and (b) PNP transistors.
B
B
VCC
VEE
In the figures shown above, only the result of biasing each junction separately but in practice,
both junctions are biased simultaneously by one external circuit. In figure 4.2(a), the baseemitter
junction is forward biased by source VEE. Negative terminal of VEE is connected to the nside of
In figure 4.2(b), the collectorbase is reverse biased by source VCC. Positive of VCC is connected
to Ntype collector. As a result the depletion region at the junction widens and only current that
flows from basecollector is due to minority electrons crossing the junction from ptype base.
They readily cross a reverse biased junction under the influence of the electric field, and they
constitute the flow of reverse current in the junction.
e C
E
E C
B IC
IE B IC IE
IB
IB
VEE VCC
VEE VCC
(a) (b)
Fig 4.3 Simultaneous biasing for (a) NPN and (b) PNP transistors
The figure above shows simultaneous biasing. The base is ground and is 0volts. The emitter is
negative with respect to the base and the collector is positive with respect to the base. These are
the conditions that are required to forward bias the emitterbase and reverse collectorbase. In
NPN transistor, the electron flow constitutes the dominant type current type while in PNP hole
current is the dominant type.
The total current (collector) is the sum of the injected minority carrier and the thermally
generated minority carriers. Suppose the external connections between the base and emitter are
left open, and the collectorbase has normal reverse bias (figure 4.4). The only current that flows
will be the reverse component due to thermal generation. This current is designated I CBO, the
collectorbase current with the emitter open. Hence in its normal operation with emitter circuit
connected, the total collector current is expressed as
IC(Inj) is the collector current due to carriers injected into the base.
An important parameter called alpha () is defined as the ratio of the collector current from
carrier injection to total current emitted.
IC
Generally
IE
E IE IC C C
E IE IC
 + 
+
VCB =
VBE = Output
Input IB voltage VEB VBC
Voltage
B
+  B
 +
(a) (b)
Fig 4.4: Common base connections of (a): NPN and (b) PNP transistors
VCB = 0
(IV characteristics of a
forward biased diode)
VBE (V)
Fig 4.5: CB IV input characteristics (VBE = Φ(VCB, IE))
Each curve shows how emitter current varies with BE voltage for a fixed VCB. In practice, the
effect of VCB on the input is often neglected. The same characteristics for PNP will appear but
the forward biased input voltage is +ve when measured from E to – B. Hence the +ve horizontal
scale will be labelled VEB.
Active region
saturation
IE
ICO
Cutoff
region
The external sources VBB is used to forward bias the BE and VCC to reverse bias CB. VCC must
be greater than VBB to ensure that CB is reverse biased. The emitter terminal in this case is
ground. The common emitter configuration is the most useful and most widely used transistor
configuration.
IC
IC
C
C IB B
IB B
VBB VCC
VCC E
VBB E
IE
IE
Remember that
IC = IE + ICBO
Or
But IB + IC = IE
Therefore
IC/  ICBO/ = IB + IC
And
1 I
I C 1 I B CBO
Leading to
I B I CBO
IC (a)
1 1
Using equation (a) we can obtain the expression for reverse ‘leakage’ current in the CE
configuration. From equation (a), consider the factor /(1  ) that multiplies IB, this factor is
called Beta which is also a very important transistor parameter. I.e.,
(b)
1
Beta is always greater than 1 and for typical transistors ranges from 20 to several hundred. In
terms of , equation (a) becomes
I CBO
I C I B
1
or I C I B I CEO
CE Input Characteristics
Since the input to a transistor in the CE configuration is across the BE junction, the CE input
characteristics resemble a family of forward biased diode curves.
IB (mA) VCE = 5V
VCE = 20V
VBE (V)
Fig. 4.8 CE Input characteristics
Output Characteristics
CE output characteristics show collector current IC vs collector voltage VCE, for different fixed
values of IB. These characteristics are often called collector characteristics.
IC
IB
IB = 0
VCE
Fig 4.9: CE output characteristics of a pnp transistor
Definitions:
ICBO
This is the collector current when emitter current (IE) is zero. ICBO is usually larger than
ICO because
 there is a lot of leakage current flowing around the junction (across the surfaces)
 new carriers are generated by collision in the collector junction region leading to
an avalanche
ICEO
When IB = 0, IC = ICEO given by
I
I CEO CO I E
1
That collector current when collector junction is reverse biased and base is open circuit.
Therefore cut off is a region with condition IC = ICO (reverse saturation current) and IE = 0
E
E IB B
IB B
VCC
VBB
VCC C
VBB C
IC
IC
(a) (b)
Fig 4.10 Common collector mode connection for (a) NPN and (b) PNP transistors
Therefore
But VBB is small and constant voltage across the forwardbiased BE junction (in particular 0.7V
for Si).
Thus
Therefore in order to keep the collectorbase junction reverse biased (VCB > 0), it is necessary
that VBB be larger than VCC – 0.7 (for Si).
IB VCE = VCE =
(A) 5V 10V VCE =
100 15V
80
60
40
20
0 5 10 15 20 25 VCB (V)
The characteristics are not for forward biased diode characteristics. Curves drawn at different
fixed VCE show current dropping to 0 very quickly as VCB increases slightly. This is because VBE
must remain in the neighbourhood of 0.5V to 0.7V (specifically for Si) in order for any
appreciable IB to flow.
But
Therefore if VCB increases to a point where it is near VCE, VBE approaches 0 and no IB flows.
CC Output characteristics
CC output characteristics closely resemble the CE characteristics. This is expected only that I E is
on yaxis instead of IC, and IE IC
10
IB =40A
8
4 IB = 30A
IB = 20A
2 IB = 10A
0 5 10 15 20 25 VCE (V)
IC = IB and IE = IC + IB
IE = IB + IB
and
IE = ( + 1)IB
In practical circuits, external resistors are connected in series with voltage sources VCC, VEE, etc
to control biasing.
IC
IE VBE VCB
VEE VCC
RE RC
IC
IE VEB VBC
VEE VCC
The input current and voltages and output current and voltages are still the same as for the case
of CB, but now input voltage is not equal to VEE because there is a voltage drop across RE and
output voltage is no longer same as VCC due to a voltage drop across RC. VEE and VCC are called
external supply voltages.
VCC VCB
And IC
RC RC
1 V
IC VCB CC
RC RC
The equation above is called load line for NPN common base configuration. It is the line through
all possible combinations of voltage (VCB) and IC.
IC (mA)
VCC/RC
Generally, important equations that are used to solve for all input and output currents and
voltages in NPN, Common Base are
VEE VBE
IE
RE
IC = IE
RB RB
IB
IB VCC
VCC
VBB
VBB
Fig 4.15 (a) NPN CE bias circuit (b) PNP CE bias circuit
CE bias circuit has VCC & VBB. RB and RC is chosen such that voltage drop across RB>RC, in
order to keep CE junction reverse biased.
1 V
IC VCE CC
RC RC
This is the equation for the load line of an NPN transistor in CE mode.
IC
(mA)
VCC/RC
The summary of equations for an NPN bias circuit are given below
IC = IB
CC Bias Circuit
RE
RE IE
RB
RB IB
VCC
IB
VCC VBB
VBB
Fig 4.17 (a) NPN CC bias circuit (b) PNP CC bias circuit
The load line for CC bias circuit is got from Kirchoff’s law for voltage around the output loop:
1 V
IE VCE CC
RE RE
Recall that the output characteristics for CC are, for all practical purposes, the same as those for
CE.
VCC VBE
IE
RB ( 1) RE
IC = ( + 1)IB
VCE
RC
+5V
RB
Input, 0 or +5V
Fig 4.18
In this case, the transistor is in CE mode but without bias voltage connected to the base. Instead,
a resistor RB is connected in series with the base and then directly to a square or pulsetype
waveform that serves as the inverter input. In the circuit, V CC and the ‘high’ level of the input are
both +5V and the output VCE is as usual.
When input to the inverter is high (+5V), BE junction is forward biased and current flows
through RB into the base. RB and RC are chosen so that the amount of IB is enough to saturate the
transistor. When the input to the transistor is low (0V), BE junction has no forward bias applied,
i.e. IB = 0 and consequently IC = 0. There is therefore no voltage drop across RC, and it follows
that VCE must be the same as VCC: +5V.
Transistors work effectively as switches because the ON OFF states of the transistor correspond
closely to the closing and opening of a switch connected between the collector and the emitter.
When the transistor is ON or saturated, VCE is close to zero, as it would be across a closed switch
and the current is the maximum possible, VCC/RC. When the transistor is OFF, no current flows
from the collector to the emitter and voltage is maximum, as it would be across an open switch.
This is semiconductor that depends for its operation on the control of current by an electric field.
Two types of FETs exist, i.e Junction Field Effect Transistor (JFET) and Insulated Gate FET
commonly known as MOSFET.
FET transistor differs from Bipolar Junction Transistor in the following characteristics:
1. FET operation depends upon the flow of majority carriers only, hence called unipolar
device.
2. It is simpler to fabricate and occupies less space in integrated form.
3. It exhibits high input resistance
4. It is less noisy than a bipolar transistor
5. It exhibits no offset voltage at zero drain current hence it is a good signal chopper.
ptype Gate
D
S D G
VDS G
VGS
ntype channel S
Current is caused to flow along the length of ntype bar because of the voltage supply connected
between the ends. The current consists of majority carriers which for this case are electrons.
Definitions
Source (S): Terminal through which majority carriers enter the bar. Current entering the bar at S
is IS.
Drain (D): Terminal through which majority carriers leave the bar. Current entering the bar at D
is ID.
Gate (G): On both sides of ntype bar, heavily doped (p+) regions of acceptor impurities are
formed. VGS is the voltage between source and gate.
FET Characteristics
FET in common source configuration is shown below
G IG VDD
VDS
VGG VGS IS
Fig 5.2
VGS = +0.5V
ID
VGS = 0V
VGS = 0.5V
VDS
Fig 5.4
If VGS is applied in the direction to provide additional reverse bias, the pinch off will occur for
smaller values of VDS and the maximum ID will be smaller. The maximum voltage that can be
applied between any two terminals of the FET is the lowest voltage that will cause junction
breakdown across the gate junction. From the figure above, it is seen that junction breakdown
occurs at lower VDS when the gate is reverse biased than for VGS = 0. This is because the reverse
bias gate voltage adds to the drain voltage, and hence increases the effective voltage across the
gate junction.
Generally nchannel requires zero or –ve VGG gate bias and +ve drain voltage while pchannel
requires +ve VGG gate bias and –ve drain voltage.
ON Resistance Region
In this region the JFET behaves as an ohmic resistor whose value is determined by V GS for small
VDS. The ration VDS/ID at the origin on the IV curve is called the ON drain resistance rd,ON. The
transistor is used in switching applications where FET is driven heavily ON. FET has the
advantage over BJT because it does not have an offset voltage (i.e. ID = 0 & VDS = 0).
2
b
VGS 1 VP
a
Where a – b is the penetration W(x) of the depletion region into the channel. The voltage V GS
represents the reverse bias across the gate junction and it is independent of distance along the
channel if ID = 0.
Considering a situation where an electric field x is applied along the xaxis, if a substantial ID
flows, the drain end of the gate is more reverse biased than the source end and hence the
boundaries of the depletion region are not parallel to the longitudinal axis of the channel.
Transfer Characteristics
In amplifier applications, FET is almost always used in the region beyond pinch off (also known
as current – saturation region). It has been found that the transfer characteristics giving the
relationship between IDS and VGS is approximated by
2
V
I DS I DSS 1 GS
VP
METAL OXIDE FET (MOSFET)
MOSFET has much greater commercial application than JFET. Pchannel MOSFET consists of a
lightly doped ntype substrate into two highly doped p+ regions.
S G D
Al
SiO2
p+ p+
pinduced channel
nsubstrate
Fig 5.5
I – V Characteristics
VGS = 20V
ID
(mA) VGS = 16V
VGS = 12V
VDS (V)
Fig 5.6
Threshold Voltage.
As VGS is made –ve, ID increases slowly at first then much more rapidly with increase in V GS.
The threshold voltage is the gate – source voltage (VGST) or VT at which ID approaches some
defined small value (like 10A). Manufacturers usually give the current ID,ON corresponding
approximately to the maximum value given on the drain characteristics, and VGS needed to obtain
this current.
VT for pchannel MOSFET is typically –4V and is common to use power supply of –12V for
drain supply. The large voltage is incompatible with the power supply voltage of typically +5V
used in bipolar junction transistor. Hence efforts have been made to reduce V T. This allows the
use of small power voltage, compatibility with bjt devices and smaller switching time due to the
smaller voltage swing during switching.
OR Gate
An OR gate has two or more inputs and a single output. The operation follows the definition:
‘The output of an OR assumes the state 1 if one or more inputs assume the state 1’. Input to the
logic circuit are denoted A, B, C,…., N and output Y. All the symbols assume one of the two
possible values: 0 and 1.
A INPUT OUTPUT
A B Y
B
Y 0 0 0
N
0 1 1
1 0 1
1 1 1
Standard OR symbol
Y=A+B+…+N Truth table
In diodelogic (DL) system, the logic gates are implemented by using diodes.
Rs D1
A
Rs Y
D2
B
V(0) vo
Rs R
V(1) N DN
vn
VR
Generator source resistance is designated R s. Consider a case where the supply voltage VR has a
value equal to V(0) of state 0. If all inputs are in 0 state, the voltage across each diode is V(0) –
V(0) = 0. Since in order for a diode to conduct, it must be forward biased by atleast the cutin
voltage V, none of the diodes conduct. Hence the output voltage is v o = V(0) and Y is in state 0.
If input A is in 1 state, which for negative logic is at potential V(1), less +ve than 0 state, D1
conducts.
Vo V(1) + V,
Hence the output voltage exceeds the more negative level V(1) by V .
Assumptions:
 R>>Rs
 Ideal diodes with Rf = 0, V = 0.
Under this the output, for input A excited, is v o = V(1). For the above excitation the output is at
V(1) and each diode, except D1 is back biased. Hence the presence of signal sources at B, C, ….,
N does not result in an additional load on generator A. This gate allows several independent
sources to be applied at a given node and it also minimizes the interaction of sources on one
another. If two or more inputs conduct and all other diodes remain reverse biased and the output
is V(1).
A + B + C = (A + B) + C = A + (B + C)
A+B=B+A
A+A=A
A+1=1
A+0=A
These can be verified by use of a truth table.
AND GATE
AND gate has two or more inputs and a single output. It operates according to the definition:
‘The output of an AND assumes the 1 state if and only if all the inputs assume the 1 state’.
A INPUT OUTPUT
A B Y
B
Y 0 0 0
N
0 1 0
1 0 0
1 1 1
Standard AND symbol
Y = AB … N Truth table
vn
VR
Rs D1
R
A
Rs Y
D2
B
V(1) vo
Rs
V(0) N DN
vn
Assume that all source resistance Rs are zero and the diode is ideal. If any input is at level 0
(V(0)), the diode connected to this input conducts and the output is clamped at the voltage V(0)
or Y = 0. However if all inputs are at 1 level V(1), all diodes are reverse biased and
Vo = V(1) or Y = 1.
Input output
Y=Ā A Y
A Y=Ā A Y
A 0 1
1 0
Y=Ā
When the input is at V(0), output is at V(1) and vice versa. A NOT circuit inverts a signal while
preserving its shape and the binary levels between which the signal operates.
VCC = V(1)
RC
A
V(1)
Rs
V(0) RC
VEE = V(0)
VBB
IC
+ RL
Rs
vi
VCC
The pulse makes transitions between voltage levels V 2 and V1. At V2 the transistor is at cut off
and at V1 the transistor is in saturation. The collector current i c response to input waveform and
its relationship is shown in fig (c). The current does not respond immediately to the input signal.
There is a delay and the time that develops during this delay, together with the time that is
required for the current to rise to 10% of its maximum (saturation) value
VCC
I CS is called delay time td.
RL
Definitions:
Ride time tr: The time required for the current to rise through the active region from 10% to
90% of ICS.
Storage time ts: The interval which elapses between the transition of the input waveform and the
time when ic has dropped to 90% of ic.
Fall time tf: The time required for Ic to fall from 90 to 10% of ICS
Turn off time toff: The sum of the storage and fall times
TOFF = ts + tf.
Delay time
The following factors contribute to delay time.
Storage time
The transistor responds only when the saturation charge of excess minority carriers stored in the
base are removed.
B 0 1 0 0
M Y
S 1 0 0 0
1 1 0 1
0 0 1 0
_
Y = AB … M S 0 1 1 0
1 0 1 0
1 1 1 0
Truth table
The equation is read: ‘Y equals A and B and …. and M and NOT S’. The terminal S is also
called an enable input or strobe. The enabling bit S = 0 allows the gate to perform its AND logic,
where as the inhibiting bit S = 1 causes the output to remain at Y = 0, independently of the values
of the input bits.
12V
The circuit above circuit shows a combination of AND and INVERTER circuit satisfying the
logic given in the truth table. If either A or B or both are in 0 state, V(0) = 0V, then at least one
of the diodes D1 or D2 conducts and clamps output to 0V or Y = 0.
EXCLUSIVE OR
This follows the definition:
The output of a twopoint EXCLUSIVE OR assumes the 1 state if one and only one input
assumes the 1 state.
A INPUT OUTPUT
A B Y
Y 0 0 0
B
0 1 1
1 0 1
1 1 0
Y=A+B
Truth table
This is used to check for the inequality of two bits. If bit A is not identical with bit B then the
output is obtained. Equivalently if A and B are both 1 and if A and B are both 0, then no output is
obtained and Y = 0.
INPUT OUTPUT
A B Y
A 0 0 1
0 1 1
Y
B 1 0 1
1 1 0
Truth table
Y = AB
Implemented DTL circuit for NAND positive logic is shown in the figure below.
NOR Gate
A negation following an OR is called a NOTOR or a NOR gate. A NOR circuit is implemented
by a cascade of a diode OR and a transistor INVERTER.
A INPUT OUTPUT
A B Y
Y 0 0 1
B
0 1 0
1 0 0
1 1 0
Y=A+B
Truth table
A negative NOR circuit is implemented in the figure below. Note that it is just the +ve NAND
that we discussed in the previous section.
V 2.2K
R
A Rs D1
B Rs
D2
100K
C
D
N
12V
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