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CSC 126

PART TWO
SEMICONDUCTOR ELECTRONICS

1. INTRODUCTION

Semiconductor materials are distinguished by having their specific electrical conductivity somewhere
between that of good conductors (10 6(cm)-1) and that of good insulators. Among those materials by
far the most important in engineering use is silicon. The other of lesser importance is Germanium
(Ge) (which is like Si an element belonging to group IV in the periodic table. Becoming more
important are the compound semiconductors usually compounded of two elements or more of Groups
III and V or II and VI of the periodic table. From this group GaAs is the most important; others are
InSb, GaP, CdS etc.

Electronic devices necessitate use of almost absolutely pure semiconductor materials in which an
extremely small quantity of foreign dopant has been included to control its electrical properties. Also
the semiconductor must normally be in the form of a single crystal throughout the device however
other forms of the semiconductors (example thin film based) have of recent found applications in
photovoltaics.

To understand the basics of the devices used in semiconductor applications, we shall explore at length
the physics of these materials from the basic scientific approach. We begin by exploring the basis of
these devices (i.e the atom) and how it is built on to give a semiconductor.

1.1 The Atomic Structure.

1.1.1 Rutherford’s model


The currently accepted atomic model is the Rutherford’s ‘nuclear planetary’ model, in which an atom
consists of a positively charged nucleus surrounded by a negatively charged particles (electrons) (Fig
1.1). Nearly all atomic mass is concentrated in the nucleus.

Consider an isolated hydrogen atom, which consists of a single electron circling the nucleus around a
closed orbit of radius r. From classical theory, it is postulated that the electron revolves around the
nucleus in a circular orbit and that the centripetal force (Fr) is balanced by the equal and opposite
electrostatic force (FA) of attraction between the positive charge of the proton and the negative charge
of the electron.

e-
Fr
FA
p
r

Figure 1.1: An illustration of the atomic structure.

The force of attraction FA between the nucleus/proton and the electron of the hydrogen atom is

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e2
FA  (1)
4 0 r 2

where e is the electron charge and 0 is the permitivity in free space. From Newton’s 2 nd law of
motion in mechanics, the force in equation (1) is balanced by a force that holds a particle in a circular
path (i.e centripetal force)
mv 2
Fr  (2)
r

where v is the velocity of the electron. Equating (1) and (2) we have

e2 mv 2
FA  Fr   (2a)
4 0 r 2 r

Integrating eqn 1 w.r.t r gives the potential energy of the electron at a distance r from the nucleus, i.e
r e2
V   FA dr   (3)
 4 0 r

Total energy of the electron E = k.e + p.e

1 2 e2
E mv  (3a)
2 4 0 r

e2
E (3b)
8 0 r

1.1.2 The Bohr Model

In 1913, Bohr postulated 3 fundamental laws:


1. Not all energies as given by classical mechanics eqn 3b are possible, but the atom can posses only
certain discrete energies (energy quantization). While in states corresponding to these discrete
energies, the electron does not emit radiation and the electron is said to be in a stationary or non-
radiating state.
2. In a transition from one stationary state (E 2) to another stationary state (E1), radiation will be
emitted (if E2  E1). The frequency of this radiant energy is given by

E 2  E1
 (4)
h

h is the planks constant


3. An electron in an nth stationary state has a quantized angular momentum which is an integral
multiple of h/2, given by

nh
mvrn  (5)
2
where n is an integer (n = 1,2,3,4,…)

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Combining Equation (2a) and (5), we can get the radii of the nth stationary state.
From equation 2a the velocity of the electron is given by:

e
v
4 m 0 r
Substituting v into equation (5) and solving for r we have

n 2 h 2 0
rn  n  1, 2, 3,....... (6)
me 2
This is the Bohr’s radius of the nth stationary state.

1.1.3 Atomic energy levels


The various permitted orbitals involve different electron energies. The electron energy En associated
with orbit of radius rn is given by (from equation 3b)
e2
En  
8 0 rn
n = 1, 2, 3, …. (7)
me 4  1 
  
8 02 h 2  n 2 

13.6
 eV for hydrogen atom
n2

13.6
Since E n   eV n  1, 2, ......
n2

n = 1, E1 = -13.6eV = -21.76 x 10-19 J (1eV = 1.6 X 10-19 J)

n = 2, E2 = -13.6 / 22 eV = -3.4 eV

n = 3, E3 = -1.51eV

n = 4, E4 = -0.85eV

n = 5, E5 = -0.54 eV

n =  , E = 0
Equation (7) gives energy levels of a hydrogen atom. A convenient pictorial representation called
energy level diagram of a hydrogen atom is given in Figure 1.2 below

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n Energy (J)

5 -0.87 x 10-19
excited
state 4 -1.36 x 10-19

3 -2.42 x 10-19

2 -5.43 x10 -19

Ground
state 1 -21.76 x 10-19
Figure 1.2: Energy level diagram of a hydrogen atom

Note the gaps between different states, an electron is forbidden from having energies falling in these
gaps.

In general for an element of atomic number Z, an electron in the nth state has energy En given by

1 Z 2e4m e4m Z 2
En   or 
n 8 02 h 2 8 02 h 2 n

13.6Z 2
 eV 
n2
(8)

where Z is the atomic number.

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2.0 SEMICONDUCTOR PHYSICS

2.1 Band theory of solids


Consider the situation when two hydrogen atoms are brought together. The interaction between the
electrostatic fields of the atoms split each energy level into two, giving one level slightly higher than
before and another one slightly lower as in Fig 2.1 shown below.

Electron
Energy

Band gap

One atom Two atoms Many atoms


(a) (b) (c )
Fig 2.1: Band diagram showing energy levels for one, two and many atoms.

As more and more atoms are brought together the discrete levels are transferred into a cluster of very
narrowly spaced levels or bands of permitted energy levels. The permitted energy bands are spaced by
band gaps in which there are no permitted states. A full band does not contribute to conduction. The top of
a conduction band is called a vacuum level. The band containing the valence electrons is called valence
band (VB) and the next band is called conduction band (CB).

2.1.1 Insulators, Semiconductors and Metals

The band model given in the above account explains why some materials are classified as conductors,
semiconductors or as insulators. A very poor conductor of electricity is called an insulator; an excellent
conductor is a metal; and a substance whose conductivity lies between these extremes is a semiconductor,
(Figure2.2 below).

CB
CB
CB

Eg Eg
VB
VB

Fig 2.2 VB
(a) Metal (b) Semiconductor (c) Insulator
- CB & VB overlap - Small energy band gap - Large energy band
-VB partially filled (~ 1eV) gap (~ 5eV)

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(a) Insulator
An insulator has a large forbidden band gap that separates the filled valence band from the vacant
conduction band. The energy which can be supplied to an electron from an applied field is too small to
carry the particle from the filled valence band to the conduction band. Since the electron cannot acquire
the sufficient supplied energy, conduction is impossible and hence the material is an insulator.

(b) Semiconductor
For the case of a semiconductor, the width of the forbidden energy region is relatively small (~ 1eV).
Example is graphite which is a crystalline form of carbon but having a crystal symmetry which is different
from diamond has such a small value of E g. The most important practical semiconductor materials are
germanium and silicon which have values of E g of 0.785eV and 1.21eV respectively, at 0oK. The valence
band remains full while the conduction band remains empty.

(c) Metals
A solid which contains a partly filled band structure is called a metal (Fig 2.2 a). Under the influence of
an applied electric field, the electrons may acquire additional energy and move into higher states.

2.2 The Bond Theory


Atoms join together to form solids under some conditions because each atom seeks a position of
minimum energy. For many substances, this is achieved by sharing or exchanging of valence electrons in
order to give each atom a full quota of valence electrons. Three broad types of electron sharing are
recognized:
1. Ionic bonds: Bonding is achieved by electrostatic attraction between the ions. Atoms
donate/accept electrons to become positively or negatively charged ions.
2. Covalent Bonds: Atoms are joined by sharing valence electrons.
3. Metallic bonds: These are exhibited by electrons with single valence electrons, e.g. Cu,
Na, Ag, Au. These substances find minimum energy configuration when they pool their
valence electrons. The electrons are no longer tied to specific sites (atoms) but are
unlocalised and are free to travel throughout the metal forming an electron cloud.
2.2.1 Intrinsic and Extrinsic semiconductors
Insulators with large band gaps require tremendous electric field or high temperature to excite electrons
into the conduction band. Example, gray Tin (an insulator at 0 0C) with a small band gap (≈0.1eV) or
graphite will have some of its valence electrons excited to the conduction band with application of small
heating. Hence by application of heat, the material is converted into a conductor. Such materials are
known as pure or intrinsic semiconductors.
In addition to intrinsic semiconductors, there is another class called impure/extrinsic semiconductors. To
bring out the distinction between the two classes of semiconductors, let us consider group IV elements –
carbon, silicon, germanium and gray tin semiconductors. Each of these elements has four valence
electrons. They form covalent bond crystals, where each atom is joined by four neighbors by shared
electron pair as shown in Figure2.3 below.

(a) (b) (c)

Fig 2.3 Covalent bonding in (a) intrinsic Si (b) extrinsic Si with Phosphorous (c) extrinsic Si with
Aluminum.

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If one silicon atom is replaced by a group V element (eg Phosphorous), five valence electrons of
phosphorous form covalent bonds with the four surrounding Si atoms, and then the fifth electron will be
free (Fig 2.3 b). This electron is therefore called an excess electron and can participate in conduction
process. This way silicon has been converted into a conductor. Semiconductors converted into conductors
by addition of foreign or impurity atoms are called impure or extrinsic semiconductors. An impurity like P
which donates conduction electrons is called a donor. A donor level is very close to, but is below the
conduction band.

Consider what happens if Si atom is replaced with a group III element, eg Aluminum or boron, gallium,
indium, etc, (Fig 2.3c). Aluminum has only three valence electrons; some of the covalent bond in Si will
have an electron missing. The Al impurities introduced make available positive carriers because they
create holes which can accept electrons and are called acceptor or p-type impurities. When acceptor
impurities are added to the intrinsic semiconductor material, they produce an allowable energy level
which is just above the valence band (Fig 2.4). A very small amount of energy is required for an electron
to leave the valence band and occupy the acceptor energy level. As such the holes generated in the
valence band by the electrons constitute the largest number of carriers in the semiconductor material.

CB Donor levels

VB Acceptor levels

Fig 2.4 Donor and acceptor levels in a semiconductor.

Semiconductors in which the electrical conduction is predominantly due to free electrons are called n-type
semiconductors and those in which holes are predominant are called p-type semiconductors.

2.3 Semiconductor statistics


2.3.1 Charge Densities in a Semiconductor.
Consider a semiconductor with donor and acceptor level whose energies are shown in figure 2.5 below.

CB
Free
EC electron
-
ED Donor
level
Bound hole
Eg
Bound
electron
EA Acceptor
level
Ev
Free hole
-
VB
Figure 2.5

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At very low temperatures, the electrons will posses the lowest possible energy and consequently will all
be located in the valence band and the donor level. As temperature is raised, some electrons get excited in
the acceptor level from valence band and into the conduction band from the donor level. At even higher
temperatures, electrons are able to get to the conduction band directly from the valence band. Electrons
leaving the VB to the acceptor level leave free holes and introduce bound electrons in the acceptor level.
Similarly electrons leaving donor levels to CB leave behind bound holes in donor level.

If p is the number of holes per unit volume or the carrier density in the valence band, we do not know
what fraction of these p holes are created by electrons going to the acceptor level and what fraction of
electrons going all the way to the conduction band. A similar statement holds for n-electrons per unit
volume in the conduction band. The problem at this point is to get the number of free electrons and free
holes available since they are important factors in determining the electrical behavior of both
semiconductors and junction devices made from them.

If nA is the no. of bound electrons per unit volume in the acceptor level and nD is the no. of bound holes
per unit volume in the donor level, then for charge neutrality

n + nA = p + nD (1)
i.e total negative charge density is equal to total positive charge density.
We shall now evaluate these four quantities. The probability that a level at energy E is occupied by an
electron is given by Fermi Dirac distribution f(E) defined by

f FD E  
1
(2)
 E  EF 
1  exp  
 kT 

where EF = Fermi enrgy or Fermi level


k = Boltzmann constant
T= Absolute temperature (oK)

2.5 Energy band diagrams at equilibrium

The band diagram is very important in the understanding of solid-state devices. Principles governing
construction of band diagrams are:
1. Particles tend to take up positions of minimum energy.

The figure below illustrates this principle.

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+ Electron
energy -V

Potential

+ hole
energy
+V

Figure 2.6

Electrons behave like little balls, always rolling down the hill to the lowest position (seek more positive
potential); holes look like bubbles in the valence band, rising to the highest level possible (holes seek
more negative potential).

Note:
+qV = E for holes
-qV = E for electrons

2. Constancy of the Fermi level at equilibrium (Eqn (45))

Consider the figure 2.7a where it is assumed that the Fermi level is not constant.

A
A B
EC -V
E1 B EC
EF
E1
EF

EV

(a) EV (b)
+V
Fig 2.7 Fermi level in a semiconductor material at equilibrium

An electron will have the same probability according to the Fermi-Dirac distribution, of occupying the
levels A and B, because both are the same height E 1 above the Fermi level. An electron at A will therefore
move to B as given by the first principle. Result, semiconductor at B becomes more negatively charged,
rising the energy of all the levels at B by the same amount (refer to eqn 46).

Electrons will continue to flow from A to B, until the probability of being in each level is the same, which
occurs when the Fermi level is same everywhere as in Figure 2.7b

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3.0 DIODE CIRCUITS AND CHARACTERISTICS

It is possible to manufacture a single piece of a semiconductor material half of which is doped by p-type
impurity and the other type n-type impurity as shown in Fig 3.0 below. The joining of a p-type and n-type
materials forms a diode.

p n

+++++++ - - - - - ------
+++++++ - - - - - ------
++++++ + - - - - - ------
Fig 3.0 A p-n junction diode

The plane dividing the two zones is called a junction. It has been found that three phenomena take place
when a junction is formed:

1. A thin depletion layer or region (also space charged or transition region) is established on
both sides of the junction.
2. A barrier potential or junction potential is developed across the junction.
3. Formation of junction and diffusion capacitances.

3.1 Depletion Layer


At the instant of a junction formation, there is a greater concentration of holes in the p-region and
electrons in the n-regions, than in the n- and p- regions respectively (Fig 3.1a). This concentration
difference establishes density gradient across the junction resulting in carrier diffusion. Holes diffuse from
p- to n- region and electrons from n- to p- regions and terminate their existence by recombination. The
recombination of free electrons and holes in the vicinity of the junction leaves a narrow region on either
side of the junction that contains no mobile charge. This narrow region which has been depleted of mobile
charge is called the depletion layer. It extends into both the p-type and n-type regions as shown in Figure
3.1(b). Note that the diffusion of holes from the p-type side of the depletion layer leaves behind some
uncovered fixed negative charges (the acceptor ions). Similarly, fixed positive charges (donor ions) are
uncovered on the n-type side of the depletion layer. There is then a separation of charges: negative fixed
charges on the p-type side of the depletion layer and positive fixed charges on the n-type side. This
separation of charges causes an electric field to extend across the depletion layer. A potential difference
must therefore exist across the depletion layer.

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p n

+++++++ - - - - - ------
+++++++ - - - - - ------
++++++ + - - - - - ------

(a)

Free (mobile
charges)

++++++ - - - - - -
- -

- -
++++++ - - - - - -

Depletion layer
with fixed ions
(b)
Fig 3.1 P-n junction at (a) initial stages showing movement of e- & holes and (b) a depletion layer formed.

Eventually the formation of fixed ions on both sides inhibits the diffusion of majority carriers from their
respective regions (Fig 3.1b).

3.2 Junction or barrier voltage/potential


The presence of oppositely charged fixed row of ions on both sides of the depletion layer give rise to an
electric potential difference VB across the junction even if the junction is externally isolated. It is known
as junction or barrier potential (its an inbuilt potential). It stops further flow of carriers across the junction
unless supplied by from an external source.
p n
++++++ - + - - - - - -
++++++ - + - - - - - -
++++++ - + - - - - - -

Depletion layer

VB
0

Fig 3.2 P-n junction diode with depletion layer and corresponding potential barrier profile.

3.3 Forward biased p-n junction.


If the positive of an external supply is connected to the p-side of the semiconductor and the negative to the
n-side of the semiconductor (as shown in Fig3.3a), the junction is said to be forward biased. The
application of an external potential V A takes the junction out of equilibrium and hence the Fermi level is
no longer constant across the junction. The potential barrier is reduced by V A. The result is like knocking

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several metres of the height of a reservoir dam. A large current is unleashed as the majority electrons and
holes flood down the concentration gradients.
Holes Electrons
Ih Ie
++++++ - - - - - -
++++++ - - - - - -
++++++ - - - - - -
I
p n

VA

(a)
i
0
VB – VA

Potential barrier is
(b) reduced by VA

EC
e- q(VB – VA)

EF qVA

EV

p-region n-region
(c)

Fig 3.3 a): forward biased p-n junction, (b) Potential barrier diagram for forward biased p-n junction (c)
corresponding energy band diagram
3.4 Forward I-V characteristics.

A typical I-V characteristics for a forward biased pn junction is shown in Fig 3.4

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Si
Ge
IF

If

Vf

A B

VF
Fig 3.4 Forward I-V characteristics of p-n junction diodes of Ge and Si

It can be seen that forward current rises exponentially with applied forward voltage. However, at room
temperature a small pd is required before a reasonable amount of forward current starts flowing. This
voltage is known as threshold voltage or cut-in or knee voltage. It is typically the same as the built in
potential/barrier potential (VB). The forward biased junction has low resistance.

3.5 Reverse Biased p-n junction.


If a negative terminal of the external supply is connected to the p-side of the semiconductor and the
positive terminal connected to the n-side of the semiconductor, the junction is said to be reversed biased
(Fig 2.13a). Holes are attracted by the negative terminal of the supply, similarly, electrons are also
attracted by the positive terminal.

The applied voltage increases the barrier potential to (Fig 3.5b)

VB + VA

thereby blocking the flow of carriers.

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Holes electrons Majority carriers are
pulled from the
++++++ - + - - - - - - junction area causing
++++++ - + - - - - - - the widening of the
++++++ - + - - - - - - depletion region

(a) VA

VA + VB

(b) Built in potential


increased from VB to
VA + VB

EC
q(VA + VB)
EF

EV qVA

Figures
(c) 3.5 a): Reversed biased p-n junction, b) its corresponding potential barrier diagram
c) its corresponding energy band diagram, in this case the majority carriers are held back.

3.6 Reverse I-V characteristics of a pn junction diode.

Although in reverse-biased case, practically there is no current due to majority carriers, there is still some
very small amount of current (a few micro amperes) due to the flow of minority carriers (thermally
generated) across the junction. Thermal energy generates some holes in the N-type region and some
electrons in the p-region of the semiconductor. The battery drives these minority carriers across the
junction thereby producing a small current called reverse current or reverse saturation current I0 or IS. The
reverse saturation current is also referred to as leakage current of the pn junction. I-V characteristics of a
reverse biased p-n junction is illustrated in Fig 3.6
Forward voltage
Reverse voltage

Si I0

Ge

Fig 3.6 Reverse I-V characteristics of Si and Ge p-n junction diodes

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Keeping temperature constant, as the reverse voltage is increased, I is found to increase only slightly. This
slight increase is due to the impurities on the surface of the semiconductor which behaves as a resistor of
very high resistance. A reverse biased junction is characterised by a very large resistance

3.7 Diode Law


The I-V characteristics described above are called static characteristics because they describe the d.c
behaviour of the diode. The characteristics are model as an ideal diode. The ideal diode has the properties
that

iD = 0, vD  0, and
vD = 0, iD > 0,

where iD is the diode current and vD is the voltage of the anode relative to the cathode. The model
equation is

iD = IS [exp(vD/(NVt))  1],

where N is the ideality factor and Vt = kT/q is the thermal voltage. This leads to a simplified diode
current equation given by
  qV  
I  I 0 exp  A   1 Amps whose characteristics are displayed in figure 3.7.
  kT  
Three regions of interest in Fig 3.7 are:

kT
1. V A  . In forward bias the exponential term dominates and
q

 qV 
I  I 0 exp  A  Amps, which accounts for the steep rise in current
 kT 
2. VA = 0; I = 0 equilibrium condition is satisfied.

kT
3. V A   . In reverse bias the exponential term rapidly dies away leaving
q
I  I0 Amps where I0 is the reverse leakage current or reverse saturation current (IS).

Current due
I (mA) to majority
carries
Breakdown

+V

+V
Current due
to minority
carries

Reverse characteristics Forward characteristics

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Fig 3.7 Current-voltage characteristics of a p-n junction diode

Note: VA < 0 for reverse bias


VA > 0 for forward bias

Piecewise Linear model of a diode


(a) Static Model

At low frequencies (below 1 KHz) including DC, the equivalent ideal circuit model for a diode is usually
derived from the measured current/voltage characteristics of the diode and is modeled by a piecewise
linear circuit model, with zero forward impedance and infinite reverse bias impedance. A more realistic
approximation of a diode model is represented by a non-linear current source with a finite forward and
reverse bias, in series with a linear resistance as shown in Figure 3.8 (a), where 'A' and 'K' denote anode
and cathode of a diode, respectively.

Figure 3.8: Static model of a Diode and its I-V characteristics

The pn junction is represented by the realistic approximation of a diode model whose static characteristics
are modeled by the non-linear current source ID, whose value is determined by the following equations

where VD the is voltage applied across the junction and other parameters are described in table 3.1 The
first row in the equation describes the forward characteristics, the second row describes the reverse
characteristics before diode break down, the third row describes the reverse characteristics at break down
and the last row describes the reverse characteristics after break down. All the regions of operation of a
diode are illustrated in Figure 3.8(b), where regions (1), (2),(3) and (4) correspond to row numbers of
equation 3.1. The effects of both the high-level injection [18] and ohmic resistance are modeled by the
ohmic resistance rs. The total voltage across the diode is then given by

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(b) Dynamic Model (Large Signal Model)

Fig. 3.9 Large signal model of a diode

In addition to the non-linear effects represented by the static model, a large-signal model takes into
consideration the charge-storage effects of a device. If these effects are not accounted for, the device
would be infinitely fast, causing the currents to change in zero time due to the lack of charge inertia. In a
junction diode there are two forms of charge storage: 1) charge storage in the depletion region due to
dopant concentrations and 2) charge storage due to the minority carriers injected into the neutral region.
Both of these charges gives rise to two capacitances: junction capacitance (Cd) and diffusion capacitance
(Cj). The total equivalent capacitance of the diode is modeled as (CD = Cj + Cd). A large-signal model of
a diode is shown in Figure 3.9, where the total equivalent capacitance (CD) can be defined equivalently by
the following capacitance relations

where the first sum terms account for the diffusion capacitance and the second for the junction
capacitance. F2 and F3 are the model constants whose values are given by the Equation 3.5 and the new
model parameters required to describe the capacitance CD of a large-signal model of a diode are given in
Table 3.2.

Table 3.1: Diode large-signal model parameters

3.10 Tunnel Diode Characteristics


If the doping density on both junction sides is high, tunneling occurs. The depletion layer is then too
narrow and the maximum junction field may grow to some few MV cm -1. When this combination of high

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field and narrow depletion layer occurs, electrons can then tunnel directly from VB on p-side to CB on n-
side (Fig. 3.10).

Doping on p-side is high enough to bring the Fermi level near EV and the n-side has EF inside the
conduction band. When a reverse voltage VZ is applied, valence band electrons can directly tunnel into the
empty conduction band states opposite them on the n-side without first being excited into the conduction
band on the p-side
Tunneling
EC

qVZ
EF
EV
++++++++++ EF
+ EC

EV

p n
Fig 3.10 Band diagram for a tunnel diode

Due to the heavy doping, a tunnel diode exhibits an unusual current-voltage characteristic curve as
compared with that of an ordinary junction diode.

Fig 3.11:

The three most important aspects of this characteristic curve are (1) the forward current increase to a peak
(IP) with a small applied forward bias, (2) the decreasing forward current with an increasing forward bias
to a minimum valley current (IV), and (3) the normal increasing forward current with further increases in
the bias voltage. The portion of the characteristic curve between IP and IV is the region of negative
resistance.

The negative resistance region is the most important and most widely used characteristic of the tunnel
diode. A tunnel diode biased to operate in the negative resistance region can be used as either an oscillator
or an amplifier in a wide range of frequencies and applications. Very high frequency applications using

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the tunnel diode are possible because the tunneling action occurs so rapidly that there is no transit time
effect and therefore no signal distortion. Tunnel diodes are also used extensively in high-speed switching
circuits because of the speed of the tunneling action. The tunneling phenomenon only takes place in
heavily doped diodes such as Zener diodes.

3.11 Zener Diode & breakdown


With the application of sufficient reverse voltage, a p-n junction will experience a rapid avalanche
breakdown and conduct current in the reverse direction. The energy bands of the P and N materials are
naturally at different levels, but reverse bias causes the valence band of the P material to overlap the
energy level of the conduction band in the N material. Under this condition, the valence electrons of the P
material can cross the extremely thin junction region at the overlap point without acquiring any additional
energy. When the breakdown point of the PN junction is reached, large numbers of minority carriers
"tunnel" across the junction to form the current that occurs at breakdown. The breakdown process depends
upon the applied electric field, so by changing the thickness of the layer to which the voltage is applied,
zener diodes can be formed which break down at voltages from about 4 volts to several hundred volts.

Fig 3.12 Zener diode I-V characteristics

The zener diode uses a p-n junction in reverse bias to make use of the zener effect, which is a breakdown
phenomenon which holds the voltage close to a constant value called the zener voltage. It is useful in
zener regulators to provide a more constant voltage, for improvement of regulated power supplies, and for
limiter applications.

Fig 3.13

3.12 Light – semiconductor Interaction

Interaction between photons and semiconductor means that photons are either absorbed or emitted by the
semiconductor.

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The energy e of the photon is related to the wavelength  by

hc 1.24
E  hf   eV
  ( m)
If a photon is absorbed then the energy E = E g which gives the maximum wavelength as

1.24
max  m
Eg

3.12.1Photoconductive effects

(a) PIN Photodetector


The PIN (P-Intrinsic-N) diode can be used as a detector by operating in the third quadrant as shown in Fig
3.14

PIN diode is operated with reverse bias, smaller than the breakdown voltage, and its detection capability
stems from the sharp increase in the reverse current from I0 in the dark to I0 + Iph with light. The devise
must have a shallow junction followed by a wide depletion layer where most of the absorption and
generation should take place. The generated carriers are immediately swept apart by the high reverse field
and contribute to Iph.

Fig 3.14 P-I-n photodiode characteristics in dark (1) and under illumination (2)

The PIN diode in which even a small reverse voltage suffices to extend the depletion layer across the
whole intrinsic region fits the requirements very well. Carriers generated outside the depletion layer but
within a diffusion length of it have also a good chance to diffuse towards it and contribute to Iph.
The current generated by the carriers has the same direction as the leakage current (i.e. reverse direction)
so that the total diode current is

 qV 
I  I 0  e kT  1  I ph
 
The characteristic is shown by line 2 in Fig 3.14

The equivalent circuit for PIN photodetector is given in Fig 3.15

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Ri

Iph I0 D V

Fig 3.15 Equivalent circuit for P-I-N photodetector

D represents an ideal diode and Ri represents total internal resistance of regions outside the depletion
layer. The basic electrical circuit of a PIN photodetectror is shown in Fig 3.16

U
RL V0

Fig 3.16

3.13 Photovoltaic effect


A PN junction diode can be utilized as a photodetector without any external voltage source. The basic
circuit is shown in figure below.
I
Ri

Ip RL V
 
h qVA
I0 e kT
1
 

Fig 3.17

The cell may be used for light measurements. The I-V characteristics of this photodetector is given in Fig
3.18.

Fig 3.18

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(c) Light emitting diodes (LED)
LEDs utilize the recombination of excess carriers injected in a forward-biased diode, to obtain light
emission for display purposes. Direct-band gap semiconductors have radiative recombination and hence
are used for light generation. The p-n diode in this mode is called LED though principally it is in the
infrared. The efficiency of the process of light generation increases with the injected current and with the
injected current and with a decrease in temperature. Light is concentrated near the junction because most
of the carriers are to be found within a diffusion length of the junction.

Diode Circuits
The basic diode circuit (Fig 3.19), consists of the device in series with a load resistance RL and an input
signal vi.
3.14.1 Load Line
From Kirchoff’s law of voltage

v = vi - iRL

with RL as the magnitude of the load resistance.


A K
+ +

vi RL v0
i

- -

Fig 3.19 Basic diode circuit


vi'
Load line
RL
a a
vi
vi
RL
RL
b
I’

A’ B’
iA’
A
iA iA B
A
vA
(i)vi 0 (ii) vi vi’

Fig 3.20 (i) Intersection of A of the load line with the diode static characteristics
(ii) Load line for dynamic curve from the loadline for static characteristics.
A shows the curve for static characteristics while b shows the dynamic characteristic curves.
In Fig 3.20a, the load line is the straight line passing through i = 0, v = vi and i = vi/RL, v = 0. That is the
intercept with the voltage axis is vi and with the current axis is vi/RL. The slope of the line is therefore
determined by RL. The point of intersection A of the load line and the static curve gives the current iA that
flows under these conditions.

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(i) Dynamic characteristics
If input voltage is varying then the process of finding the current at a point is to be repeated for every
value of input voltage. A plot will be obtained which is called the dynamic characteristics (plot b in Fig
3.20(ii)). This can be achieved as follows: The current IA is plotted vertically above vi at point B (Fig
3.20(ii)). As vi changes, the slope of the load line does not vary since RL is fixed. Thus when the applied
potential has the value vi’, the corresponding current is iA’. The resulting curve OBB’ that is generated as
vi varies is the dynamic characteristic.

(ii) Transfer characteristics


The curve which relates the output voltage vo to the input voltage vi of any circuit is called the transfer
characteristic curve. From figure 3.19, vo = iRL, from this particular circuit, the transfer characteristics is
just the same as the dynamic characteristics. The loadline construction allows the graphical analysis of
many circuits involving devices which are much more complicated than just a p-n diode. The external
output of almost all devices consist of a dc supply voltage V in series with a load resistance RL (as
discussed earlier). The slope of the load line is independent of the device characteristics. For the case of a
p-n junction or an avalanche diode posseses a single I-V characteristic at a given temperature. However
most other devices must be described by a family of curves (example transistor, photodiode etc) which
may have a separate curve drawn for each fixed value of example light intensity or value of input current
(for the case of a transistor).

Specific circuits drawn from diodes are clipping (limiting) circuits, Comparators, sampling gates rectifier
circuits, capacitor filter circuits. Others of lesser importance are peak detector and clamping circuits.

(a) Clipping circuits


Clipping circuits are used to select for transmission that part of an arbitrary waveform, which lies above
or below some reference level. Clipping circuits are also referred to as voltage (or current) limiters,
amplitude selectors or slicers. Example the circuit in Fig 3.19 is a clipping circuit whereby input voltages
below the cutin (Vγ) voltage are not transmitted to the output. An example of a commonly used clipping
circuit is given in Fig 3.21 below. For this case the output is clipped at +25V and –30V (which are the
reference voltages for the positive and negative, respectively). The input is at maximum 50V alternating.
D1 will be conducting when the input trace is positive upto the reference voltage (+25V) and remain
constant with the increase in the input voltage to +50V. This will remain until the input voltage drops
back to point +25V as the signal changes to negative input.

+50
50
25

50
V v0
25V
-30V
-30
-50
-50
Fig 3.21 shows a diode circuit that clips both the positive and negative voltage swings to references
voltages. A sinusoidal input and the clipped output are shown.

All this time D2 is not conducting and when the input signal switches to negative, it becomes conducting
while D1 becomes nonconducting. For the negative input, as the input increases towards –50V, the output
will be conducting and allowing in the value of input (vo = vi) until the input reaches –30V. As the input
increases from –30V towards –50V, the output gives a constant value of –30V until the input drops back
to –30V from –50V towards 0. This region again the output voltage will just be the same as the input
voltage Clipping can be achieved by use of ordinary diodes (Fig 3.22) or zener diodes.

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Fig 3.22 Clipping circuits using ordinary diodes and their corresponding traces.

(b) Comparator circuits


The circuits used for clipping can also be used to perform operations of comparison. In this case the
circuits become elements of a comparator system and are usually referred to simply as comparators. A
comparator circuit is a circuit which compares an input signal vi(t) with a reference voltage VR (Fig 3.23).
The distinction between comparator circuits and the clipping circuits is that in a comparator there is no
interest in reproducing any part of the signal waveform.

+ +

RL

vi v0
VR

- -

Fig 3.23: A diode comparator circuit

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vi

VR + Vγ

0
t1 t

vo

Vo
VR

0
t1 t2
t

Fig 3.24: Display of the ramp input signal vi, and the corresponding output waveform.

The circuit in Fig 3.23 above is identical to the clipping circuit but the input is taken as a ramp with the
input crossing the voltage level vi = VR + Vγ at a time t = t1. When the input vi exceeds VR, the
comparator output vo takes on a value which is very different from the magnitude of vo when vi is smaller
than VR. The output remains at vo = VR until t = t1, after which it rises with the input signal (Fig 3.24).
The device to which the comparator output is applied will respond when the comparator voltage has risen
to some level Vo above VR.

(c) Sampling gate circuit


An ideal sampling gate is a transmission circuit in which the output is an exact reproduction of an input
waveform during a selected time interval and is zero otherwise. The time interval for transmission is
selected by an externally expressed signal, called the control, or gating, signal and is usually rectangular
in shape. The sampling gates are also referred to as transmission gates or time selection circuits. An
example of a sampling gate circuit is shown in Fig 3.25

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RL vo

Rc

+vc
Rc -vc

vs

Fig 3.25 A four diode bridge sampling gate with control vc, the signal vs and the output vo waveforms.

In this set up an external signal vs is applied and the output vo taken across the load RL and symmetrical
control voltages applied at +vc and –vc through the control resistors Rc. The rectangular shaped vc, the
sinusoidal vs and the sampled output vo are shown. Note that the period of vc need not be the same as that
of vs, although in most practical applications, the period of vc would equal or be an integral multiple of
that of vs. During the time Tc all diodes are conducting and during Tn all diodes are not conducting.

(d) Rectifier circuits


Rectification is the conversion of alternating current into a dc. A diode can be used to convert a sinusoidal
input waveform into a unidirectional (though not constant) waveform. The basic circuit for half wave
rectification is shown in Fig 3.26.

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v vi

vm
RL
vi

(b)

i
(a)

(c)

Fig 3.26: (a) Basic circuit of half wave rectifier (b) Transformer sinusoidal secondary voltage v i (c) Diode
current and load current i.

Since in rectifier circuit the input vi = Vmsinωt has a peak value of Vm which is very large compared to the
cutin voltage (Vc) of the diode, it is assumed that VC = 0. With the diode idealized to be a resistance R f in
the ON state and an open circuit in the OFF state, the current I in the diode or load RL is given by
i  I m sin  if 0  
i0 if     2

where α = ωt

and

Vm
I m
R f  RL

The transformer secondary voltage is shown in Fig 3.26b and the rectified current in 3.26c.

The diode voltage is the dc output voltage which is

I m RL
Vdc  I dc RL 

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4.0 BIPOLAR JUNCTION TRANSISTOR
A junction transistor consists of a semiconductor material in which a layer of n-type is
sandwiched between two layers of the p-type semiconductor. Alternatively a transistor may
consist of a layer of p-type between two layers of n-type materials. The semiconductor sandwich
is extremely small. The three portions of a transistor are known as emitter, base and collector.
The arrow on the emitter lead specifies the current flow when the emitter-base junction is biased
in the forward direction. The symbols VEB, VCB and VCE are the emitter-base, collector-base and
collector-emitter voltages respectively.
P N P
N P N

N P N P N P

E C E C

B
B

Fig 4.1 Block diagrams and equivalent circuits of (a) NPN and (b) PNP transistors.

4.1 Biasing PN junctions.


To obtain normal transistor action, it is necessary to bias both PN junctions by connecting dc
voltage sources across them.
E C
E

B
B
VCC
VEE

Fig 4.2(a) Forward biasing (b) Reverse biasing


emitter-base junction collector-base junction.

In the figures shown above, only the result of biasing each junction separately but in practice,
both junctions are biased simultaneously by one external circuit. In figure 4.2(a), the base-emitter
junction is forward biased by source VEE. Negative terminal of VEE is connected to the n-side of

Justus Simiyu 28 simiyuj@uonbi.ac.ke


the n-p junction. Consequently there is a substantial flow of diffusion current across due to flow
of majority carriers (electrons) from the N-type emitter. When the electrons diffuse into the base,
they become minority carriers in that region.

In figure 4.2(b), the collector-base is reverse biased by source VCC. Positive of VCC is connected
to N-type collector. As a result the depletion region at the junction widens and only current that
flows from base-collector is due to minority electrons crossing the junction from p-type base.
They readily cross a reverse biased junction under the influence of the electric field, and they
constitute the flow of reverse current in the junction.
e- C
E
E C

B IC
IE B IC IE
IB
IB
VEE VCC
VEE VCC

(a) (b)
Fig 4.3 Simultaneous biasing for (a) NPN and (b) PNP transistors

The figure above shows simultaneous biasing. The base is ground and is 0volts. The emitter is
negative with respect to the base and the collector is positive with respect to the base. These are
the conditions that are required to forward bias the emitter-base and reverse collector-base. In
NPN transistor, the electron flow constitutes the dominant type current type while in PNP hole
current is the dominant type.

From Kirchoff’s current law,

IE = IC + IB for both PNP and NPN.

The total current (collector) is the sum of the injected minority carrier and the thermally
generated minority carriers. Suppose the external connections between the base and emitter are
left open, and the collector-base has normal reverse bias (figure 4.4). The only current that flows
will be the reverse component due to thermal generation. This current is designated I CBO, the
collector-base current with the emitter open. Hence in its normal operation with emitter circuit
connected, the total collector current is expressed as

IC = IC(Inj) + ICBO or (IC = ICBO - IE)

IC(Inj) is the collector current due to carriers injected into the base.

An important parameter called alpha () is defined as the ratio of the collector current from
carrier injection to total current emitted.

Justus Simiyu 29 simiyuj@uonbi.ac.ke


I C ( Inj )
 
IE
The greater the value of , the better is the transistor since  is the portion of the emitter current
that survives after it passes through the base to become collector current.

IC
Generally  
IE

4. 2 Common Base (CB) Connections


In common base connection, the base is the ground, i.e all voltages (C-B and E-B) are referenced
to the base. The significance of having a common point in a transistor circuit is that it gives a
reference for both input voltage to the transistor and the output voltage. In the CB configuration,
the E-B voltage is regarded as the ‘input voltage’ and the C-B as ‘output voltage’. In this set-up,
E-B voltage is same as emitter-base bias voltage VEE and output voltage (C-B) same as C-B bias
voltage (VCC).

E IE IC C C
E IE IC
- + -
+
VCB =
VBE = Output
Input IB voltage VEB VBC
Voltage
B
+ - B

- +

(a) (b)

Fig 4.4: Common base connections of (a): NPN and (b) PNP transistors

(a) CB Input Characteristics


The input I-V characteristics resemble that of a forward biased diode since the input is across the
forward-biased base –to-emitter junction. However, the shape depends on the reverse biasing
output voltage VCB, i.e, the greater the value of VCB, the more readily minority carriers in the
base are swept through the B-E junction.

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Increasing output bias

IE (mA) VCB = 25V


VCB = 10V

VCB = 0

(I-V characteristics of a
forward biased diode)

VBE (V)
Fig 4.5: CB IV input characteristics (VBE = Φ(VCB, IE))

Each curve shows how emitter current varies with B-E voltage for a fixed VCB. In practice, the
effect of VCB on the input is often neglected. The same characteristics for PNP will appear but
the forward biased input voltage is +ve when measured from E- to – B. Hence the +ve horizontal
scale will be labelled VEB.

(b) CB Output characteristics


When the collector (output) current is measured as V CB (output voltage) adjusted for fixed
settings of the emitter (input) current, we obtain the following characteristics.

Active region
saturation

IE

ICO

Cut-off
region

Fig 4.6 CB I-V characteristics (IC = Φ(VCB, IE))

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Each curve begins at IC = 0 and rises rapidly for a small +ve increase in V CB, i.e, IC increases
rapidly just as VCB begins to rise slightly beyond its –ve value.
(a). Active region
When IE = 0, IC = ICO = reverse saturation current.
When IC flows, IC = -IE (from (IC = ICBO - IE))
There is a small increase in IC with VCB and magnitude of IC is slightly less than
IE because IC = - IE and  ≈ 1
(b). Saturation
At saturation, VCB is +ve and the junction is forward biased. By definition, a transistor is said to
be saturated when both its C-B junction and E-B junction are forward biased. For CB to be
forward biased, VCB has to fall to almost 0 (VCB ≈ 0), that is it gets slightly +ve. In this region, a
small VCB leads to a large collector current (IC), in other words an exponential rise. Then the
collector current remains constant with constant IE for increase in VCB. In this region the
transistor exhibits normal properties associated wit forward biased E-B and reverse biased C-B.
Transistors are normally operated in the active region

4.3 Common Emitter (CE) Characteristics

The external sources VBB is used to forward bias the B-E and VCC to reverse bias C-B. VCC must
be greater than VBB to ensure that C-B is reverse biased. The emitter terminal in this case is
ground. The common emitter configuration is the most useful and most widely used transistor
configuration.

IC
IC

C
C IB B
IB B
VBB VCC
VCC E
VBB E
IE
IE

Fig 4.7 (a) NPN common (b) PNP common emitter


emitter configuration configuration

ICEO and Beta


To understand better the relationship between IC and ICBO, we shall derive a relationship that will
give us new parameters that are useful for predicting leakage in the CE configuration and also for
relating CE input and output currents.

Remember that

IC = IE + ICBO

Or

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IC – ICBO = IE and IC/ - ICBO/ = IE

But IB + IC = IE
Therefore
IC/ - ICBO/ = IB + IC
And
1  I
I C  1  I B  CBO
  

Leading to
I B I CBO
IC   (a)
1 1

Using equation (a) we can obtain the expression for reverse ‘leakage’ current in the CE
configuration. From equation (a), consider the factor /(1 - ) that multiplies IB, this factor is
called Beta which is also a very important transistor parameter. I.e.,

 (b)
1
Beta is always greater than 1 and for typical transistors ranges from 20 to several hundred. In
terms of , equation (a) becomes

I CBO
I C  I B 
1

or I C  I B  I CEO

CE Input Characteristics
Since the input to a transistor in the CE configuration is across the B-E junction, the C-E input
characteristics resemble a family of forward biased diode curves.

IB (mA) VCE = 5V
VCE = 20V

VBE (V)
Fig. 4.8 CE Input characteristics

Justus Simiyu 33 simiyuj@uonbi.ac.ke


When VBE = 0, IB = 0 this indicates that both emitter and collector junctions are shorted. An
increase in VCE at constant VBE causes a decrease of base width hence reducing recombination of
base current (IB)

Output Characteristics
CE output characteristics show collector current IC vs collector voltage VCE, for different fixed
values of IB. These characteristics are often called collector characteristics.

IC

IB

IB = 0

VCE
Fig 4.9: CE output characteristics of a pnp transistor

(a) Active Region


In the active region, the collector junction is reverse biased and the emitter junction is
forward biased.
(b) Cut-off region
At the cut off region, both base junction and collector junction are reverse biased (i.e I B =
0).

Definitions:
ICBO
This is the collector current when emitter current (IE) is zero. ICBO is usually larger than
ICO because
- there is a lot of leakage current flowing around the junction (across the surfaces)
- new carriers are generated by collision in the collector junction region leading to
an avalanche

ICEO
When IB = 0, IC = ICEO given by
I
I CEO  CO   I E
1
That collector current when collector junction is reverse biased and base is open circuit.
Therefore cut off is a region with condition IC = ICO (reverse saturation current) and IE = 0

Justus Simiyu 34 simiyuj@uonbi.ac.ke


(c) Saturation region
In this region, collector and emitter junctions are forward biased by at least cutin voltage.
This region is very close to V = 0 axis (all curves merge and fall drastically towards 0).
When the loadline is introduced, IC = VCC/RL

4.4 Common Collector (Cc) Characteristics


IE
IE

E
E IB B
IB B
VCC
VBB
VCC C
VBB C
IC
IC

(a) (b)

Fig 4.10 Common collector mode connection for (a) NPN and (b) PNP transistors

In this mode, the collector is ground. For the case of NPN,

VCE = VBE + VCB

Or VCB = VCE - VBE

But VCE = VCC and VCB = VBB

Therefore

VBB = VCC – VBE

But VBB is small and constant voltage across the forward-biased B-E junction (in particular 0.7V
for Si).
Thus

VBB = VCB – 0.7V

Therefore in order to keep the collector-base junction reverse biased (VCB > 0), it is necessary
that VBB be larger than VCC – 0.7 (for Si).

Justus Simiyu 35 simiyuj@uonbi.ac.ke


CC Input characteristics

VCB is input voltage and IB is input current.

IB VCE = VCE =
(A) 5V 10V VCE =
100 15V
80

60

40

20

0 5 10 15 20 25 VCB (V)

Fig.4.11 C-C IV input characteristics for pnp transistor

The characteristics are not for forward biased diode characteristics. Curves drawn at different
fixed VCE show current dropping to 0 very quickly as VCB increases slightly. This is because VBE
must remain in the neighbourhood of 0.5V to 0.7V (specifically for Si) in order for any
appreciable IB to flow.

But

VBE = VCE - VCB

Therefore if VCB increases to a point where it is near VCE, VBE approaches 0 and no IB flows.

CC Output characteristics

CC output characteristics closely resemble the CE characteristics. This is expected only that I E is
on y-axis instead of IC, and IE  IC

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IE IB = 60A
(mA)

10
IB =40A
8

4 IB = 30A

IB = 20A
2 IB = 10A

0 5 10 15 20 25 VCE (V)

Fig. 4.12 CC output I-V characteristics

Neglecting leakage current from

IC = IB and IE = IC + IB

 IE = IB + IB

and

IE = ( + 1)IB

4.5 Transistor Circuits


Bias circuits
It has been emphasised that B-E must be forward biased and C-B junction must be reverse biased
for normal transistor action. This section will extend the requirements by adjusting the value of
the bias as need be to obtain specific input and output currents and voltages.
CB Bias circuit.

In practical circuits, external resistors are connected in series with voltage sources VCC, VEE, etc
to control biasing.

Fig below shows CB biased circuits.

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RE RC

IC
IE VBE VCB

VEE VCC

Fig 4.13 (a) NPN CB bias circuit

RE RC

IC
IE VEB VBC

VEE VCC

Fig 4.13 (b) PNP CB Bias circuit

The input current and voltages and output current and voltages are still the same as for the case
of CB, but now input voltage is not equal to VEE because there is a voltage drop across RE and
output voltage is no longer same as VCC due to a voltage drop across RC. VEE and VCC are called
external supply voltages.

From Kirchoff’s law for voltage

VCC = ICRC + VCB

VCC VCB
And IC  
RC RC

1 V
IC  VCB  CC
RC RC

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IC and VCB are regarded as variables and the equation is of a straight line with slope –1/RC and y-
intercept VCC/RC.

The equation above is called load line for NPN common base configuration. It is the line through
all possible combinations of voltage (VCB) and IC.

IC (mA)

VCC/RC

0 VCC VCB (V)

Fig. 4.14 CB bias circuit output characteristics showing the loadline

Generally, important equations that are used to solve for all input and output currents and
voltages in NPN, Common Base are

VBE = 0.7V(Si), 0.3V(Ge)

VEE  VBE
IE 
RE

IC = IE

VCB = VCC - ICRC

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CE Bias Circuit
RC RC
IC

RB RB
IB
IB VCC
VCC
VBB
VBB

Fig 4.15 (a) NPN CE bias circuit (b) PNP CE bias circuit

CE bias circuit has VCC & VBB. RB and RC is chosen such that voltage drop across RB>RC, in
order to keep C-E junction reverse biased.

From Kirchoff’s law around the output loop,


VCC = ICRC + VCE
V V
I C  CC  CE
RC RC

1 V
 IC  VCE  CC
RC RC
This is the equation for the load line of an NPN transistor in CE mode.

IC
(mA)

VCC/RC

VCC VCE (V)


Fig. 4.16 Load line on CE output bias characteristics

The summary of equations for an NPN bias circuit are given below

VBE = 0.7V(Si), 0.3V(Ge)

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VCC  VBE
IE 
RB

IC = IB

VCE = VCC - ICRC

CC Bias Circuit
RE
RE IE

RB
RB IB
VCC
IB
VCC VBB
VBB

Fig 4.17 (a) NPN CC bias circuit (b) PNP CC bias circuit

The load line for CC bias circuit is got from Kirchoff’s law for voltage around the output loop:

VCC = IERE + VCE

1 V
IE  VCE  CC
RE RE

Recall that the output characteristics for CC are, for all practical purposes, the same as those for
CE.

A summary of equations for determining bias point in an NPN CC configuration are:

VBE = 0.7V (Si), 0.3V(Ge)

VCC  VBE
IE 
RB  (   1) RE

IC = ( + 1)IB

VCE = VCC – IERE

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Transistor as a switch
Transistors are used widely in digital logic circuits and switching applications. The fundamental
transistor circuit used in switching applications is called an inverter. The switching periodically
alternates between ‘low’ and ‘high’ (between 0 and +5V). The basic circuit for inverter is shown
below.

VCE

RC

+5V

RB

Input, 0 or +5V

Fig 4.18

In this case, the transistor is in CE mode but without bias voltage connected to the base. Instead,
a resistor RB is connected in series with the base and then directly to a square or pulse-type
waveform that serves as the inverter input. In the circuit, V CC and the ‘high’ level of the input are
both +5V and the output VCE is as usual.

When input to the inverter is high (+5V), B-E junction is forward biased and current flows
through RB into the base. RB and RC are chosen so that the amount of IB is enough to saturate the
transistor. When the input to the transistor is low (0V), B-E junction has no forward bias applied,
i.e. IB = 0 and consequently IC = 0. There is therefore no voltage drop across RC, and it follows
that VCE must be the same as VCC: +5V.

Transistors work effectively as switches because the ON OFF states of the transistor correspond
closely to the closing and opening of a switch connected between the collector and the emitter.
When the transistor is ON or saturated, VCE is close to zero, as it would be across a closed switch
and the current is the maximum possible, VCC/RC. When the transistor is OFF, no current flows
from the collector to the emitter and voltage is maximum, as it would be across an open switch.

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5.0 FIELD EFFECT TRANSISTOR (FET)

This is semiconductor that depends for its operation on the control of current by an electric field.
Two types of FETs exist, i.e Junction Field Effect Transistor (JFET) and Insulated Gate FET
commonly known as MOSFET.

FET transistor differs from Bipolar Junction Transistor in the following characteristics:
1. FET operation depends upon the flow of majority carriers only, hence called unipolar
device.
2. It is simpler to fabricate and occupies less space in integrated form.
3. It exhibits high input resistance
4. It is less noisy than a bipolar transistor
5. It exhibits no offset voltage at zero drain current hence it is a good signal chopper.

FETs are principally used in logic signal circuits.

p-type Gate
D
S D G

VDS G
VGS

n-type channel S

Fig.5.1(a) Basic structure of an n-channel FET (b) equivalent circuit

Current is caused to flow along the length of n-type bar because of the voltage supply connected
between the ends. The current consists of majority carriers which for this case are electrons.

Definitions
Source (S): Terminal through which majority carriers enter the bar. Current entering the bar at S
is IS.

Drain (D): Terminal through which majority carriers leave the bar. Current entering the bar at D
is ID.

Gate (G): On both sides of n-type bar, heavily doped (p+) regions of acceptor impurities are
formed. VGS is the voltage between source and gate.
FET Characteristics
FET in common source configuration is shown below

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ID

G IG VDD
VDS

VGG VGS IS

Fig 5.2

Consider case where VGS = 0 (Gate – Source is open):


For ID = 0, the channel between the gate junction is open. In response to a small V DS, n-type
channel acts as a semiconductor resistor and ID increases linearly with VDS. With increasing ID,
the voltage drop between S and voltage channel constricts. It reaches some V DS where the
channel is ‘pinched off’. This is the point where ID begins to level off and approach a constant
value (Fig below). From the figure note that each characteristic curve has an ohmic region for
small values of VDS, where ID is proportional to VDS. Each also has a constant-current region for
large values of VDS, where ID responds very slightly to VDS.

VGS = +0.5V
ID
VGS = 0V

VGS = -0.5V

VDS

Fig 5.4

If VGS is applied in the direction to provide additional reverse bias, the pinch off will occur for
smaller values of VDS and the maximum ID will be smaller. The maximum voltage that can be
applied between any two terminals of the FET is the lowest voltage that will cause junction
breakdown across the gate junction. From the figure above, it is seen that junction breakdown
occurs at lower VDS when the gate is reverse biased than for VGS = 0. This is because the reverse
bias gate voltage adds to the drain voltage, and hence increases the effective voltage across the
gate junction.
Generally n-channel requires zero or –ve VGG gate bias and +ve drain voltage while p-channel
requires +ve VGG gate bias and –ve drain voltage.

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JFET I – V CHARACTERISTICS
Assume first that a small VDS is applied between D and S, the resulting small ID has no
appreciable effect on the channel profile. Under this condition, the effective cross section of the
channel is constant throughout its length.

ON Resistance Region
In this region the JFET behaves as an ohmic resistor whose value is determined by V GS for small
VDS. The ration VDS/ID at the origin on the IV curve is called the ON drain resistance rd,ON. The
transistor is used in switching applications where FET is driven heavily ON. FET has the
advantage over BJT because it does not have an offset voltage (i.e. ID = 0 & VDS = 0).

Pinch off Region


At the pinch off point there is a gate reverse voltage that removes all the free charge from the
channel. This is the pinch off voltage (VP). This voltage is given in the expression

2
 b
VGS  1   VP
 a
Where a – b is the penetration W(x) of the depletion region into the channel. The voltage V GS
represents the reverse bias across the gate junction and it is independent of distance along the
channel if ID = 0.

Considering a situation where an electric field x is applied along the x-axis, if a substantial ID
flows, the drain end of the gate is more reverse biased than the source end and hence the
boundaries of the depletion region are not parallel to the longitudinal axis of the channel.

Transfer Characteristics
In amplifier applications, FET is almost always used in the region beyond pinch off (also known
as current – saturation region). It has been found that the transfer characteristics giving the
relationship between IDS and VGS is approximated by

2
 V 
I DS  I DSS 1  GS 
 VP 
METAL OXIDE FET (MOSFET)
MOSFET has much greater commercial application than JFET. P-channel MOSFET consists of a
lightly doped n-type substrate into two highly doped p+ regions.
S G D
Al
SiO2

p+ p+

p-induced channel
n-substrate

Fig 5.5

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If the substrate is ground and a negative voltage is applied at the gate, the electric field goes
perpendicularly through the insulating oxide. Induced +ve charge increases with increase in
applied –ve voltage and the region beneath the oxide then has p-type carriers and conductivity
increases and current flows from source to drain through the induced channel.

I – V Characteristics

VGS = -20V
ID
(mA) VGS = -16V

VGS = -12V

VDS (V)
Fig 5.6

Threshold Voltage.
As VGS is made –ve, ID increases slowly at first then much more rapidly with increase in V GS.
The threshold voltage is the gate – source voltage (VGST) or VT at which ID approaches some
defined small value (like 10A). Manufacturers usually give the current ID,ON corresponding
approximately to the maximum value given on the drain characteristics, and VGS needed to obtain
this current.

VT for p-channel MOSFET is typically –4V and is common to use power supply of –12V for
drain supply. The large voltage is incompatible with the power supply voltage of typically +5V
used in bipolar junction transistor. Hence efforts have been made to reduce V T. This allows the
use of small power voltage, compatibility with bjt devices and smaller switching time due to the
smaller voltage swing during switching.

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6.0 LOGIC CIRCUIT APPLICATIONS

OR Gate
An OR gate has two or more inputs and a single output. The operation follows the definition:
‘The output of an OR assumes the state 1 if one or more inputs assume the state 1’. Input to the
logic circuit are denoted A, B, C,…., N and output Y. All the symbols assume one of the two
possible values: 0 and 1.

A INPUT OUTPUT
A B Y
B
Y 0 0 0
N
0 1 1

1 0 1

1 1 1
Standard OR symbol
Y=A+B+…+N Truth table

In diode-logic (DL) system, the logic gates are implemented by using diodes.

Rs D1
A
Rs Y
D2
B
V(0) vo
Rs R
V(1) N DN

vn
VR

Fig. Diode OR for negative logic circuit

Generator source resistance is designated R s. Consider a case where the supply voltage VR has a
value equal to V(0) of state 0. If all inputs are in 0 state, the voltage across each diode is V(0) –
V(0) = 0. Since in order for a diode to conduct, it must be forward biased by atleast the cutin
voltage V, none of the diodes conduct. Hence the output voltage is v o = V(0) and Y is in state 0.
If input A is in 1 state, which for negative logic is at potential V(1), less +ve than 0 state, D1
conducts.

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v0  V (0)  V (0)  V (1)  V  R  RR  R
s f

Rf = diode forward resistance


Rs = diode series resistance.
R is usually chosen to be much more than Rs and Rf. Under this condition

Vo  V(1) + V,
Hence the output voltage exceeds the more negative level V(1) by V .

Assumptions:
- R>>Rs
- Ideal diodes with Rf = 0, V = 0.

Under this the output, for input A excited, is v o = V(1). For the above excitation the output is at
V(1) and each diode, except D1 is back biased. Hence the presence of signal sources at B, C, ….,
N does not result in an additional load on generator A. This gate allows several independent
sources to be applied at a given node and it also minimizes the interaction of sources on one
another. If two or more inputs conduct and all other diodes remain reverse biased and the output
is V(1).

Boolean identities for OR:

A + B + C = (A + B) + C = A + (B + C)
A+B=B+A
A+A=A
A+1=1
A+0=A
These can be verified by use of a truth table.

AND GATE

AND gate has two or more inputs and a single output. It operates according to the definition:
‘The output of an AND assumes the 1 state if and only if all the inputs assume the 1 state’.
A INPUT OUTPUT
A B Y
B
Y 0 0 0
N
0 1 0

1 0 0

1 1 1
Standard AND symbol
Y = AB … N Truth table

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Rs D1
A
Rs Y
D2
B
V(0) vo
Rs R
V(1) N DN

vn
VR

Fig (a): Negative logic AND


VR

Rs D1
R
A
Rs Y
D2
B
V(1) vo
Rs
V(0) N DN

vn

Fig (b): Positive logic AND

Assume that all source resistance Rs are zero and the diode is ideal. If any input is at level 0
(V(0)), the diode connected to this input conducts and the output is clamped at the voltage V(0)
or Y = 0. However if all inputs are at 1 level V(1), all diodes are reverse biased and
Vo = V(1) or Y = 1.

Boolean identity for AND.

ABC = (AB)C = A(BC)


AB = BA
AA = A
A1 = A
A0 = 0
A(B + C) = AB + AC

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NOT (INVERTER) CIRCUIT.
The NOT circuit has a single input and a single output and performs the operation of logic
negation according to the definition: ‘The output of a NOT circuit takes on the 1 state if and only
if the input does note take on the 1 state.

Input output
Y=Ā A Y
A Y=Ā A Y
A 0 1
1 0
Y=Ā

Equivalent circuit symbol and truth table. Y equals NOT A or Y is a complement of A.

When the input is at V(0), output is at V(1) and vice versa. A NOT circuit inverts a signal while
preserving its shape and the binary levels between which the signal operates.
VCC = V(1)

RC

A
V(1)
Rs
V(0) RC

VEE = V(0)
-VBB

Fig: Inverter for positive logic.


The transistor circuit implements an inverter for positive logic having a 0 state of V(0) = V EE and
a 1 state of V(1) = VCC. The capacitor across R1 is added to improve the transient response of the
inverter. IT aids in the removal of minority carrier charge stored in the base when the signal
changes abruptly between logic gates.
Transistor Limitations.
The following are certain transistor characteristics as well as certain circuit features which must
be taken into account when designing a transistor inverter.

1. The back-bias emitter junction voltage VEB


This voltage must not exceed the E-B breakdown voltage BVEBO specified by the
manufacturer

2. DC current gain hfE

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Since the current gain decreases with decreasing temperature, the circuit must be
designated so that at the lowest expected temperature, the transistor will remain in
saturation.

3. Reverse collector saturation current ICBO


This saturation current also depends on temperature (doubles for every 10 oC for Ge
and Si). This current is also specified with manufacturers under which the ambient
temperature (which is the maximum temperature) at which the inverter will work
satisfactorily.

Boolean identity for Inverter.




A =A
Ā+A=1
ĀA = 0
A + ĀB = A + B

TRANSITOR SWITCHING TIMES


A transistor works as a switch when a pulse is applied to the inverter. This section explores the
behaviour of a transistor as it makes a transition from one state to the other.

Consider a simple circuit below and a square pulse applied to it.

IC

+ RL
Rs
vi
VCC

Fig (a) Inverter circuit with input square pulse

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(b) Pulse waveform

(c) Collector current IC response to the driving input pulse

The pulse makes transitions between voltage levels V 2 and V1. At V2 the transistor is at cut off
and at V1 the transistor is in saturation. The collector current i c response to input waveform and
its relationship is shown in fig (c). The current does not respond immediately to the input signal.

There is a delay and the time that develops during this delay, together with the time that is
required for the current to rise to 10% of its maximum (saturation) value

VCC
I CS  is called delay time td.
RL
Definitions:

Ride time tr: The time required for the current to rise through the active region from 10% to
90% of ICS.

Turn ON time: The sum of the delay and rise time


tON = td + tr

Storage time ts: The interval which elapses between the transition of the input waveform and the
time when ic has dropped to 90% of ic.

Fall time tf: The time required for Ic to fall from 90 to 10% of ICS

Turn off time toff: The sum of the storage and fall times
TOFF = ts + tf.
Delay time
The following factors contribute to delay time.

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- When the driving signal is applied to the transistor input, a non zero time is required
to charge up the emitter junction transition capacitance so that the transistor moves
from cut off to active.
- Time interval is required before minority carriers can cross the base region to
collector junction to be recorded as Ic.
- The collector current requires some time to rise to 10% of its maximum.

Rise and Fall time


The rise and fall times arise because the transistor Ic must traverse the active region if the base
current step is used to saturate or return the transistor from saturation to cut off.

Storage time
The transistor responds only when the saturation charge of excess minority carriers stored in the
base are removed.

INHIBIT (ENABLE) OPERATION


A not circuit preceding one terminal s of an AND gate acts as an inhibitor. This modified AND
circuit implements the logical statement

If A = 1, B = 1, …., M = 1, then Y = 1 provided that S = 0. However if S = 1, then the


coincidence of A, B, ….., M is inhibited and Y = 0.
INPUT OUTPUT
A B S Y
A 0 0 0 0

B 0 1 0 0
M Y
S 1 0 0 0

1 1 0 1

0 0 1 0
_
Y = AB … M S 0 1 1 0

1 0 1 0

1 1 1 0

Truth table

The equation is read: ‘Y equals A and B and …. and M and NOT S’. The terminal S is also
called an enable input or strobe. The enabling bit S = 0 allows the gate to perform its AND logic,
where as the inhibiting bit S = 1 causes the output to remain at Y = 0, independently of the values
of the input bits.

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A Rs D1 Y
2.2K B Rs D2
Rs vo
C D
N
N
100K V
R

-12V

The circuit above circuit shows a combination of AND and INVERTER circuit satisfying the
logic given in the truth table. If either A or B or both are in 0 state, V(0) = 0V, then at least one
of the diodes D1 or D2 conducts and clamps output to 0V or Y = 0.

EXCLUSIVE OR
This follows the definition:
The output of a two-point EXCLUSIVE OR assumes the 1 state if one and only one input
assumes the 1 state.

A INPUT OUTPUT
A B Y
Y 0 0 0
B
0 1 1

1 0 1

1 1 0
Y=A+B
Truth table

If A = 1 or B = 1 but not simultaneously, then Y = 1


The Boolean notation is
_
Y = (A + B)(A B )
Another logic statement equivalent to EXCLUSIVE OR is ‘If A = 1 and B = 0, or if B = 1 and A
= 0, then Y = 1.
_
Boolean expression Y = A B + BĀ

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_ _
(a) Y = (A + B)(Ā B ) (b) Y = ( A B + B Ā)

Fig.: Two logic block diagrams for EXCLUSIVE OR gate.

An EXCLUSIVE OR is employed within the arithmetic section of a computer. Another


application is as an inequality comparator, or detector because Y = 1 only if A ≠ B.

This is used to check for the inequality of two bits. If bit A is not identical with bit B then the
output is obtained. Equivalently if A and B are both 1 and if A and B are both 0, then no output is
obtained and Y = 0.

NAND and NOR DIODE – TRANSISTOR (DTL) GATES.


A negated AND is called a NOT – AND, or a NAND gate. A NAND gate may be implemented
by placing a transistor NOT circuit after the diode logic AND. Circuits involving diodes and
transistors are called Diode – transistor Logic (DTL) gates.

INPUT OUTPUT
A B Y
A 0 0 1

0 1 1
Y
B 1 0 1

1 1 0

Truth table

Y = AB

Implemented DTL circuit for NAND positive logic is shown in the figure below.

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V 2.2K
R
A Rs D1
B Rs
D2
100K
C
D
N
-12V

Fig.: A three-input positive NAND gate.

NOR Gate
A negation following an OR is called a NOT-OR or a NOR gate. A NOR circuit is implemented
by a cascade of a diode OR and a transistor INVERTER.

A INPUT OUTPUT
A B Y
Y 0 0 1
B
0 1 0

1 0 0

1 1 0
Y=A+B
Truth table

A negative NOR circuit is implemented in the figure below. Note that it is just the +ve NAND
that we discussed in the previous section.

V 2.2K
R
A Rs D1
B Rs
D2
100K
C
D
N
-12V

Fig. Three-input negative NOR gate.


The base supply –VBB may also be used as the reference voltage VR. If all inputs are in 0 state, all
diodes conduct and the input to inverter is 0 V. If any input is in state 1, the diode connected to

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this input conducts. The voltage at diode node P is now V(1) = -12V. Hence from input to to
point P, the OR function has been satisfied. Since from P to the output we have an inverter, the
output negated what is now input to the inverter at P. With the aid of De Morgan’s laws, it can be
shown that, regardless of the hardware involved, a positive NAND is also a negative NOR,
where as a negative NAND may equally well be considered a positive NOR.

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